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H

0.5 Amp Output Current IGBT Gate Drive Optocoupler Technical Data
HCPL-3150

Features
• 0.5 A Minimum Peak Output Current • 15 kV/µs Minimum Common Mode Rejection (CMR) at VCM = 1500 V • 1.0 V Maximum Low Level Output Voltage (VOL) Eliminates Need for Negative Gate Drive • ICC = 5 mA Maximum Supply Current • Under Voltage Lock-Out Protection (UVLO) with Hysteresis • Wide Operating VCC Range: 15 to 30 Volts • 500 ns Maximum Switching Speeds • Industrial Temperature Range: -40°C to 100°C • Safety and Regulatory Approval: UL Recognized 2500 Vrms for 1 min. per UL1577 VDE 0884 Approved with VIORM = 630 Vpeak (Option 060 only) CSA Approved

Applications
• Isolated IGBT/MOSFET Gate Drive • AC and Brushless DC Motor Drives • Industrial Inverters • Switch Mode Power Supplies (SMPS)

Description
The HCPL-3150 consists of a GaAsP LED optically coupled to an integrated circuit with a power output stage. This optocoupler is

ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving IGBTs with ratings up to 1200 V/50 A. For IGBTs with higher ratings, the HCPL-3120 can be used to drive a discrete power stage which drives the IGBT gate.

Functional Diagram
N/C 1 8 VCC VO VO VEE

ANODE CATHODE N/C

2 3 4

7 6 5

SHIELD

Truth Table
VCC - VEE “Positive Going” (i.e., Turn-On) 0 - 30 V 0 - 11 V 11 - 13.5 V 13.5 - 30 V VCC - VEE “Negative-Going” (i.e., Turn-Off) 0 - 30 V 0 - 9.5 V 9.5 - 12 V 12 - 30 V

LED OFF ON ON ON

VO LOW LOW TRANSITION HIGH

A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

5965-4780E

1-197

005 LEAD COPLANARITY MAXIMUM: 0.115) MIN.778 (0.010) 9.33 (0.90 (0. Contact Hewlett-Packard sales representative or authorized distributor.025) MAX. 4.10 (0.004) 1-198 .540 (0.635 (0.381 (0. 50 per tube.070) MAX.008) 0.65 ± 0.030) 1.65 (0.047) MAX. IN VIN+ VOUT+ 7 0. 4.013) 1.xx = 0. "V" = OPTION 060.005) 0.390) 8 7 6 5 OPTION CODE* DATE CODE 6.070) 1.19 MAX.25 (0.260) 7.080 ± 0.310) 0.78 (0.28 (0.016 (0.090) 2.25 (0.070) MAX.25 (0.040) 1.635 ± 0.300 ± 0.33 (0.240) 6.350 ± 0.826 TYP. 1 PIN DIAGRAM VDD1 VDD2 8 DIMENSIONS 2 MILLIMETERS AND (INCHES).xxx = 0.047) 1. (0.92 (0. OPTION NUMBERS 300 AND 5005 Gull-Wing Surface-Mount Option 300 9. DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.635 ± 0.165) 0.194 (0. Option data sheets available.65 ± 0.25 (0. 2. 4 GND1 GND2 NOT MARKED.88 (0.130 (0.380 ± 0.010) 8 7 6 5 PAD LOCATION (FOR REFERENCE ONLY) 1.025 ± 0.40 (0.01 xx.370) 9.76 (0.185) MAX. 1.370) 9. (0.36 (0.010) 12° NOM.25 (0.025 ± 0.70 (0.015) 0.190) 6.102 (0.047) MAX. 060 = VDE 0884 VIORM = 630 Vpeak Option.19 (0. 500 = Tape and Reel Packaging Option. 50 per tube.025) 1.60 (0. 2.043 ± 0.013) 2.194 (0.51 (0.906 (0.250 ± 0. 9.290) 7. Package Outline Drawings Standard DIP Package 9. 1 2 3 4 5° TYP.Ordering Information Specify Part Number followed by Option Number (if desired) Example HCPL-3150#XXX No Option = Standard DIP package.013) HP 3150 Z YYWW PIN ONE 1.320 (0.008) 0.19 (0.20 (0.20 (0.010) 0.398 (0.780 (0.047) HP 3150 Z YYWW 4.40 (0.80 (0.020) MIN. PIN ONE 0.110) 3 V LETTER FOR 6 * MARKING CODE IN– VOUT– OPTION NUMBERS. 50 per tube. 300 = Gull Wing Surface Mount Option.390) MOLDED 1 2 3 4 1.055) 0. 1000 per reel.380 ± 0.62 ± 0.100) BSC 0.010) 7.

5 = VPR. OUTPUT Insulation Resistance at TS. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.) VDE 0884 Insulation Characteristics (Option 060 Only) Description Symbol Installation classification per DIN VDE 0110/1. File CA 88324.5°C/SEC 1 2 3 4 5 6 7 8 9 10 11 12 TIME – MINUTES MAXIMUM SOLDER REFLOW THERMAL PROFILE (NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.92 with VIORM = 630 Vpeak. INPUT Output Power PS. CSA Approved under CSA Component Acceptance Notice #5. under Product Safety Regulations section. Thermal Derating Curve. Also See Figure 37. TEMPERATURE – °C ∆T = 100°C. VPR Partial discharge < 5 pC Highest Allowable Overvoltage* VIOTM (Transient Overvoltage tini = 10 sec) Safety-Limiting Values – Maximum Values Allowed in the Event of a Failure. 0.89. Method a* VIORM x 1. 1. 100% Production Test with tm = 1 sec.875 = VPR. tm = 60 sec. VDE (Option 060 only) Approved under VDE 0884/06. Type and Sample Test. 1°C/SEC ∆T = 115°C.Reflow Temperature Profile 260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 ∆T = 145°C. Table 1 for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms Climatic Classification Pollution Degree (DIN VDE 0110/1. Case Temperature TS Input Current IS. Component Recognition Program. VPR Partial discharge < 5 pC Input to Output Test Voltage. VIO = 500 V RS Characteristic I-IV I-III 55/100/21 2 630 1181 Unit Vpeak Vpeak 945 6000 Vpeak Vpeak 175 230 600 ≥ 109 °C mA mW Ω *Refer to the front of the optocoupler section of the current Catalog.3°C/SEC Regulatory Information The HCPL-3150 has been approved by the following organizations: UL Recognized under UL 1577. (VDE 0884) for a detailed description of Method a and Method b partial discharge test profiles.89) Maximum Working Insulation Voltage VIORM Input to Output Test Voltage. File E55361. 1-199 . Method b* VIORM x 1.

1.1 mm 7. Absolute Maximum Ratings Parameter Storage Temperature Operating Temperature Average Input Current Peak Transient Input Current (<1 µs pulse width. shortest distance path along body. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110.6 mm below seating plane See Package Outline Drawings Section 2 2 3 4 Recommended Operating Conditions Parameter Power Supply Voltage Input Current (ON) Input Voltage (OFF) Operating Temperature Symbol (VCC .Insulation and Safety Related Specifications Parameter Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(101) L(102) Value Units 7. Measured from input terminals to output terminals. Through insulation distance conductor to conductor. Table 1) Option 300 .VEE) IF(ON) VF(OFF) TA Min. 1/89. 300 pps) Reverse Input Voltage “High” Peak Output Current “Low” Peak Output Current Supply Voltage Output Voltage Output Power Dissipation Total Power Dissipation Lead Solder Temperature Solder Reflow Temperature Profile Symbol TS TA IF(AVG) IF(TRAN) Min. shortest distance through air..4 0.0 -40 Max. -55 -40 Max.0 Units °C °C mA A Note 1 VR 5 Volts IOH(PEAK) 0. 15 7 -3.08 CTI 200 IIIa mm mm Volts Conditions Measured from input terminals to output terminals. 125 100 25 1.6 A (VCC .VEE) 0 35 Volts VO(PEAK) 0 VCC Volts PO 250 mW PT 295 mW 260°C for 10 sec.8 100 Units Volts mA V °C 1-200 . 30 16 0.6 A IOL(PEAK) 0.surface mount classification is Class A in accordance wtih CECC 00802.

2 5. 8 Supply Current IF = 7 to 16 mA Low Level ICCL 2.5 V) 5.5 1.2 1. 3 6. 22.0 V IO = 100 mA 4. 3.4) (VCC .0 12.6 V *All typical values at TA = 25°C and VCC . Typ.1 0.8 V Voltage High to Low Input Forward Voltage VF 1. 9. IF = 10 mA 36 VUVLO9.5 V VO > 5 V. Units Test Conditions Fig. Parameter Symbol Min.3 13.* Max. VCC = 15 to 30 V.8 V.7 5.3) V IO = -100 mA 1.0 UVLO Hysteresis UVLOHYS 1.VEE = 30 V. VF(OFF) = -3.0 mA IO = 0 mA.4 V) 2.6 mV/°C IF = 10 mA Coefficient of Forward Voltage Input Reverse BVR 5 V IR = 10 µA Breakdown Voltage Input Capacitance CIN 60 pF f = 1 MHz. Supply Current VF = -3.4 1.5 5. IF(ON) = 7 to 16 mA.8 V IF = 10 mA 16 Temperature ∆VF /∆TA -1. 7 Voltage 19 Low Level Output VOL 0.4 A VO = (VCC . 1-201 . VEE = Ground) unless otherwise specified.1 0. 15. 7.0 mA Output Open. VF = 0 V UVLO Threshold VUVLO+ 11. 6 5 Output Current 18 0.5 VO = (VCC . Current Low to High VO > 5 V 21 Threshold Input VFHL 0.0 mA Output Open.6 A VO = (VEE + 2.0 to +0.7 12.5 10.5 VO = (VEE + 15 V) 2 High Level Output VOH (VCC .8 V Threshold Input IFLH 2.15 V) 2 Low Level IOL 0. 6 Voltage 20 High Level ICCH 2. Note High Level IOH 0.0 to 0. 5 Output Current 17 0. unless otherwise noted.Electrical Specifications (DC) Over recommended operating conditions (TA = -40 to 100°C.

1 0.Output) Capacitance CI-O (Input . VCC = 15 to 30 V.” 1-202 . 11. VCC = 30 V 22 24 11. 23 Note 14 Propagation Delay tPHL 0.50 Units µs Test Conditions Rg = 47 Ω.10 Time to Low Output Level Pulse Width PWD Distortion Propagation Delay PDD -0.VEE = 30 V.* Max. IF = 10 mA TA = 25°C. Cg = 3 nF. **The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. 13 Package Characteristics Parameter Symbol Input-Output VISO Momentary Withstand Voltage** Resistance RI-O (Input . VCC = 30 V TA = 25°C. 0.27 0.Switching Specifications (AC) Over recommended operating conditions (TA = -40 to 100°C. Parameter Propagation Delay Time to High Output Level Symbol tPLH Min. For the continuous voltage rating refer to your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage. 12 30 kV/µs 11. 9 1012 0.0 to 0. VCM = 1500 V.8 V. VF(OFF) = -3.30 Max. 13 14. VF = 0 V. 12.Output) LED-to-Case θLC Thermal Resistance LED-to-Detector θLD Thermal Resistance Detector-to-Case θDC Thermal Resistance Min.8 0.6 30 µs µs µs µs kV/µs 23 VO > 5 V.1 0.50 µs 0.35 µs µs 34.* 0. Duty Cycle = 50% Fig. Note 8. VEE = Ground) unless otherwise specified.10 Typ. TA = 25°C VI-O = 500 VDC f = 1 MHz Thermocouple located at center underside of package 28 Fig.35 15 10 0. 0. IF(ON) = 7 to 16 mA. unless otherwise noted.. f = 10 kHz.6 391 439 119 Ω pF °C/W °C/W °C/W 9 *All typical values at TA = 25°C and VCC .tPLH) Any Two Parts Rise Time tr Fall Time tf UVLO Turn On tUVLO ON Delay UVLO Turn Off tUVLO OFF Delay Output High Level |CMH| 15 Common Mode Transient Immunity Output Low Level |CML| 15 Common Mode Transient Immunity 0.35 Difference Between (tPHL . 2500 Typ. Units Vrms Test Conditions RH < 50%. IF = 10 to 16 mA.3 0. t = 1 min. 10. VCM = 1500 V. IF = 10 mA VO < 5 V.

and 8 shorted together.2 0.0 VOL – OUTPUT LOW VOLTAGE – V 1.0 to 0. to assure that the output will remain in a low state (i. 13.0 to 0. Maximum pulse width = 1 ms. and 4 shorted together and pins 5. VO < 1. Temperature.35 -4 IF = 7 to 16 mA VCC = 15 to 30 V VEE = 0 V 0 0. See Applications section for additional details on limiting IOH peak. Figure 3.25 -40 -20 -5 -6 -4 -40 -20 0 20 40 60 80 100 0 20 40 60 80 100 TA – TEMPERATURE – °C TA – TEMPERATURE – °C IOH – OUTPUT HIGH CURRENT – A Figure 1. to assure that the output will remain in the high state (i.e. In this test V is measured with a dc OH load current.0 V).40 -3 -2 0. 2. Pins 1 and 4 need to be connected to LED common. Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse.5 A. VCM. Temperature.4 0.0 V).50 IF = 7 to 16 mA VOUT = VCC . Temperature. VO > 15.2%. VOL vs.0 to 0.6 0. IOH vs.VCC ) – HIGH OUTPUT VOLTAGE DROP – V 0 IOH – OUTPUT HIGH CURRENT – A (VOH .2 0. Common mode transient immunity in the high state is the maximum tolerable |dVCM /dt| of the common mode pulse. 4.0 IOL – OUTPUT LOW CURRENT – A TA – TEMPERATURE – °C TA – TEMPERATURE – °C Figure 4. In accordance with UL1577. Derate linearly above 70°C free-air temperature at a rate of 4. This value is intended to allow for component tolerances for designs with IO peak minimum = 0. The difference between tPHL and tPLH between any two HCPL-3150 parts under the same test condition. 6. 9. II-O ≤ 5 µA). IOL. maximum duty cycle = 0. Device considered a two-terminal device: pins 1.Notes: 1.0 IOL – OUTPUT LOW CURRENT – A VOL – OUTPUT LOW VOLTAGE – V 5 VF(OFF) = -3. VOH vs.5 V VCC = 15 to 30 V VEE = 0 V 0 20 40 60 80 100 2 0.8 mW/°C.6 0. Figure 5.3 mA/°C.8 V VOUT = 2. Temperature. 10. Maximum pulse width = 10 µs. if applicable.8 1...2 1 0 0 20 40 60 80 100 0 -40 -20 100 °C 25 °C -40 °C 0 0.6 0. 15. each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 Vrms for 1 second (leakage detection current limit. This load condition approximates the gate load of a 1200 V/25 A IGBT. 8. 1-203 . 1.4 VF(OFF) = -3. VOL vs. VCM. IOL vs. 5. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps. (VOH . Figure 6.VCC ) – OUTPUT HIGH VOLTAGE DROP – V -1 IF = 7 to 16 mA IOUT = -100 mA VCC = 15 to 30 V VEE = 0 V 0. Pulse Width Distortion (PWD) is defined as |tPHL-tPLH| for any given device.8 0.8 VF(OFF) = -3.8 V IOUT = 100 mA VCC = 15 to 30 V VEE = 0 V 0.4 mW/°C.4 0. 7. 3. 7. IOH.e.4 0. 14.4 V VCC = 15 to 30 V VEE = 0 V -1 100 °C 25 °C -40 °C 0.45 -2 0. This test is performed before the 100% production test for partial discharge (method b) shown in the VDE 0884 Insulation Characteristics Table. Maximum pulse width = 50 µs. maximum duty cycle = 20%.0 -3 0. 2. maximum duty cycle = 0. Derate linearly above 70°C free-air temperature at a rate of 0. Derate linearly above 70°C free-air temperature at a rate of 5. 12. Figure 2.30 0.8 1. 6. VOH vs. The maximum LED junction temperature should not exceed 125°C. 11.2 0 -40 -20 0. 3.6 0.8 V VCC = 15 to 30 V 4 VEE = 0 V 3 0.5%.

Propagation Delay vs. Transfer Characteristics. Rg. VEE = 0 V Rg = 47 Ω.5 2 2. VCC.5 ICC – SUPPLY CURRENT – mA ICC – SUPPLY CURRENT – mA 3.5 IFLH – LOW TO HIGH CURRENT THRESHOLD – mA 5 VCC = 15 TO 30 V VEE = 0 V OUTPUT = OPEN ICCH ICCL 3.0 IF = 10 mA for ICCH IF = 0 mA for ICCL TA = 25 °C VEE = 0 V 15 20 25 30 1 1.5 2. Propagation Delay vs. 1-204 .3.0 4 3 2. Propagation Delay vs. Figure 8. Figure 14. Figure 11. Figure 15. VCC. Cg. Cg = 3 nF TA = 25 °C DUTY CYCLE = 50% f = 10 kHz 400 IF(ON) = 10 mA IF(OFF) = 0 mA VCC = 30 V. Figure 9. 500 Tp – PROPAGATION DELAY – ns Tp – PROPAGATION DELAY – ns 500 VO – OUTPUT VOLTAGE – V 30 400 VCC = 30 V. VEE = 0 V Rg = 47 Ω. ICC vs. IFLH vs.5 -40 -20 1.0 VCC = 30 V VEE = 0 V IF = 10 mA for ICCH IF = 0 mA for ICCL 0 20 40 60 80 100 2. Cg = 3 nF DUTY CYCLE = 50% f = 10 kHz 300 300 300 200 200 TPLH TPHL 100 6 8 10 12 14 16 200 TPLH TPHL 100 -40 -20 0 20 40 60 80 100 100 15 20 25 30 VCC – SUPPLY VOLTAGE – V IF – FORWARD LED CURRENT – mA TA – TEMPERATURE – °C Figure 10. IF. Temperature. Figure 12. Temperature.0 ICCH ICCL 3. VEE = 0 V TA = 25 °C IF = 10 mA Cg = 3 nF DUTY CYCLE = 50% f = 10 kHz 400 VCC = 30 V. Propagation Delay vs. 500 Tp – PROPAGATION DELAY – ns Tp – PROPAGATION DELAY – ns 500 Tp – PROPAGATION DELAY – ns 500 400 IF = 10 mA TA = 25 °C Rg = 47 Ω Cg = 3 nF DUTY CYCLE = 50% f = 10 kHz TPLH TPHL 400 VCC = 30 V. VEE = 0 V TA = 25 °C IF = 10 mA Rg = 47 Ω DUTY CYCLE = 50% f = 10 kHz 25 20 15 10 5 0 300 300 200 TPLH TPHL 100 0 50 100 150 200 200 TPLH TPHL 100 0 20 40 60 80 100 0 1 2 3 4 5 Rg – SERIES LOAD RESISTANCE – Ω Cg – LOAD CAPACITANCE – nF IF – FORWARD LED CURRENT – mA Figure 13. ICC vs.5 0 -40 -20 0 20 40 60 80 100 TA – TEMPERATURE – °C VCC – SUPPLY VOLTAGE – V TA – TEMPERATURE – °C Figure 7. Propagation Delay vs. Temperature.

Figure 21. 1-205 . UVLO Test Circuit. IFLH Test Circuit.50 1.001 1. IOH Test Circuit.01 + 1 8 0. Figure 19. Forward Voltage.30 1.1 µF 100 mA 1 8 0.1 0.1000 IF – FORWARD CURRENT – mA TA = 25°C IF VF – 2 IF = 7 to 16 mA 3 6 IOH 4 5 100 10 1.1 µF VOH + VCC = 15 – to 30 V 2 7 2 IF = 7 to 16 mA 3 7 3 6 6 100 mA 4 5 4 5 Figure 18. Input Current vs.60 VF – FORWARD VOLTAGE – V Figure 16. 1 8 0.10 1.1 µF 7 + 4V – + VCC = 15 – to 30 V 0.5 V + – 1 8 0. Figure 17. IOL Test Circuit. 1 8 0.0 0.20 1.1 µF IOL + VCC = 15 – to 30 V 2. 1 8 0. VOH Test Circuit. VOL Test Circuit.40 1.1 µF 2 7 + VCC = 15 – to 30 V IF 2 7 VO > 5 V + VCC = 15 – to 30 V 3 6 VOL 3 6 4 5 4 5 Figure 20.1 µF 2 IF = 10 mA 3 7 VO > 5 V 6 + – VCC 4 5 Figure 22.

1 µF 7 Rg Q1 3 6 + – VCC = 18 V + HVDC CONTROL INPUT 74XXX OPEN COLLECTOR 3-PHASE AC 4 5 Q2 . and tf Test Circuit and Waveforms.0 V. tPLH.) HCPL-3150 8 0.1 µF 0V ∆t VOH δV δt = VCM ∆t 4 5 Figure 24. When the HCPL-3150 is in the low state. 1-206 . The HCPL-3150 realizes this very low VOL by using a DMOS transistor with 4 Ω (typical) on resistance in its pull down circuit. the HCPL-3150 has a very low maximum VOL specification of 1.1 µF VCC = 15 to 30 V IF tr tf 90% 50% VOUT 10% tPLH tPHL 500 Ω 2 7 VO + – 3 6 47 Ω 3 nF 4 5 Figure 23. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL3150 input as this can result in unwanted coupling of transient signals into the HCPL-3150 and degrade performance. CMR Test Circuit and Waveforms. (If the IGBT drain must be routed near the HCPL-3150 input. Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off. Recommended LED Drive and Application Circuit. VCM 1 IF A B 5V + – 3 6 2 7 VO + – VCC = 30 V VO SWITCH AT A: IF = 10 mA VO SWITCH AT B: IF = 0 mA + VCM = 1500 V VOL 8 0. then the LED should be reverse-biased when in the off state. tr.1 IF = 7 to 16 mA + 10 KHz – 50% DUTY CYCLE 8 0.HVDC Figure 25. +5 V 1 270 Ω 2 – the IGBT gate is shorted to the emitter by Rg + 4 Ω. to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-3150. Minimizing Rg and the lead inductance from the HCPL-3150 to the IGBT gate and emitter (possibly by mounting the HCPL-3150 on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 25. tPHL.

The HCPL-3150 total power dissipation (PT) is equal to the sum of the emitter power (PE) and the output power (PO): PT = P E + P O PE = IF • VF • Duty Cycle PO = PO(BIAS) + PO (SWITCHING) = ICC• (VCC . Step 2: Check the HCPL-3150 Power Dissipation and Increase Rg if Necessary.8 V • 0.6 A (see Figure 6). This results in lower peak currents (more margin) than predicted by this analysis. HCPL-3150 Typical Application Circuit with Negative IGBT Gate Drive.HVDC Figure 26.0 µJ• 20 kHz = 85 mW + 80 mW = 165 mW > 154 mW (PO(MAX) @ 90°C = 250 mW−20C• 4.6 A = 30. QG) • f For the circuit in Figure 26 with IF (worst case) = 16 mA.1 µF 7 Rg Q1 3 6 – + 4 5 Q2 VEE = -5 V + – VCC = 15 V + HVDC CONTROL INPUT 74XXX OPEN COLLECTOR 3-PHASE AC . Rg = 30.1.5 Ω. Step 1: Calculate Rg Minimum From the IOL Peak Specification. Max Duty Cycle = 80%.Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses. PE Parameter IF VF Duty Cycle Description LED Current LED On Voltage Maximum LED Duty Cycle PO Parameter ICC VCC VEE ESW(Rg.8 mW/C) +5 V 1 270 Ω 2 HCPL-3150 8 0.VOL) Rg ≥ ––––––––––––––– IOLPEAK (VCC – VEE .8 = 23 mW PO = 4.1. f = 20 kHz and TA max = 90°C: PE = 16 mA • 1.VEE) + ESW(RG. At lower Rg values the voltage supplied by the HCPL-3150 is not an ideal voltage step.Qg) f Description Supply Current Positive Supply Voltage Negative Supply Voltage Energy Dissipated in the HCPL-3150 for each IGBT Switching Cycle (See Figure 27) Switching Frequency 1-207 . When negative gate drive is not used VEE in the previous equation is equal to zero volts. (VCC – VEE .5 Ω The VOL value of 2 V in the previous equation is a conservative value of VOL at the peak current of 0.25 mA • 20 V + 4. Qg = 500 nC. The IGBT and Rg in Figure 26 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-3150.7 V) = –––––––––––––––– IOLPEAK (15 V + 5 V .7 V) = –––––––––––––––––– 0.

Rg must be increased to reduce the HCPL3150 power dissipation.PO(BIAS) = 154 mW . to the detector IC as Rg – GATE RESISTANCE – Ω Figure 27. all heat generated flows through θCA which raises the case temperature TC accordingly. the recommended application For example. TA = 70°C and θCA 15 kV/µs CMR while minimizing = 83°C/W: component complexity. a single HCPL3150 soldered into the center of the board and still air. For example. through the package. LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. This capacitive • (θ coupling causes perturbations in + PD DC||(θLD + θLC) + θCA) + TA the LED current during common mode transients and becomes the Inserting the values for θLC and major source of CMR failures for θDC shown in Figure 28 gives: a shielded optocoupler. given PE = 45 mW. The value of θCA = 83°C/W was obtained from thermal measurements using a 2.85 mW = 69 mW PO(SWITCHINGMAX) ESW(MAX) = ––––––––––––––– f 69 mW = ––––––– = 3. The HCPL3150 improves CMR performance by using a detector IC with an optically transparent Faraday shield. PO(SWITCHING MAX) = PO(MAX) . From the thermal mode in Figure 28 the LED and detector IC junction temperatures can be expressed as: ( ) ( ) TJE = PE• 313°C/W + PD• 132°C/W + TA = 45 mW• 313°C/W + 250 mW • 132°C/W + 70°C = 117°C TJD = PE• 132°C/W + PD• 187°C/W + TA = 45 mW• 132C/W + 250 mW • 187°C/W + 70°C = 123°C Techniques to keep the LED in the proper state are discussed in the next two sections. The value of θCA depends on the conditions of the board design and is. As shown by the model. therefore. from Figure 27. Energy Dissipated in the HCPL-3150 for Each IGBT Switching Cycle. with small traces (no ground plane).5 inch PC board. The absolute maximum power dissipation derating specifications assume a θCAvalue of 83°C/W. a value of ESW = 3.5 x 2. 1-208 .25 mA for ICC in the previous equation was obtained by derating the ICC max of 5 mA (which occurs at -40°C) to ICC max at 90°C (see Figure 7). shown in Figure 29. can achieve PO = 250 mW. How θLC • θDC + PD • –––––––––––––––– + θCA + TA ever. Esw – ENERGY PER SWITCHING CYCLE – µJ 7 6 5 4 3 2 1 0 0 20 40 60 80 100 Qg = 100 nC Qg = 250 nC Qg = 500 nC VCC = 19 V VEE = -9 V TJE and TJD should be limited to 125°C based on the board layout and part placement (θCA) specific to the application. this shield does not θLC + θDC + θLD eliminate the capacitive coupling between the LED and optocoupθLC • θDC TJD = PE ––––––––––––––– + θCA ler pins 5-8 as shown in θLC + θDC + θLD Figure 30. which diverts the capaci• (θ tively coupled current away from TJE = PE LC||(θLD + θDC) + θCA) the sensitive IC circuitry.45 µJ gives a Rg = 41 Ω. Thermal Model The steady state thermal model for the HCPL-3150 is shown in Figure 28.The value of 4. Since PO for this case is greater than PO(MAX). circuit (Figure 25). the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler. determined by the designer.45 µJ 20 kHz For Qg = 500 nC. The main design objective of a high CMR TJE = PE • (230°C/W + θCA) LED drive circuit becomes + PD• (49°C/W + θCA) + TA keeping the LED in the proper TJD = PE • (49°C/W + θCA) state (on or off) during common + PD• (104°C/W + θCA) + TA mode transients.

Figure 33 is an alternative drive circuit which. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 25) are off.<12. CMR with the LED On (CMRH) A high CMR LED drive circuit must keep the LED on during common mode transients. the optocoupler will go into the high state (assuming LED is “ON”) with a typical delay. When the HCPL-3150 output is in the high state and the supply voltage drops below the HCPL-3150 VUVLO. CMR with the LED Off (CMRL) A high CMR LED drive circuit must keep the LED off (VF ≤ VF(OFF)) during common mode transients. As long as the low state voltage developed across the logic gate is less than VF(OFF). the turn on of LED2 should be delayed (relative to the 1-209 . Thermal Model. during a -dVCM/dt transient in Figure 31.θLD = 439°C/W TJE θLC = 391°C/W TC θCA = 83°C/W* TJD θDC = 119°C/W TA TJE = LED junction temperature TJD = detector IC junction temperature TC = case temperature measured at the center of the package bottom θLC = LED-to-case thermal resistance θLD = LED-to-detector thermal resistance θDC = detector-to-case thermal resistance θCA = case-to-ambient thermal resistance ∗θCA will depend on the board design and the placement of the part. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. the LED will remain off and no common mode failure will occur.5 <VUVLO. When the HCPL-3150 output is in the low state and the supply voltage rises above the HCPL3150 VUVLO+ threshold (11. UVLO TURN On Delay. The open collector drive circuit. optocoupler output will go into the low state with a typical delay. shown in Figure 32. and it is not recommended for applications requiring ultra high CMRL performance. UVLO Turn Off Delay.8 µs. the IPM Dead Time and Propagation Delay Specifications The HCPL-3150 includes a Propagation Delay Difference (PDD) specification intended to help designers minimize “dead time” in their power inverter designs. of 0. Under Voltage Lockout Feature The HCPL-3150 contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-3150 supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. since all the current flowing through CLEDN must be supplied by the LED. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices from the highto the low-voltage motor rails.6 µs. cannot keep the LED off during a +dVCM/dt transient. does achieve ultra high CMR performance by shunting the LED in the off state. the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate.0).0 < VUVLO+ < 13. like the recommended application circuit (Figure 25). A minimum LED current of 10 mA provides adequate margin over the maximum IFLH of 5 mA to achieve 15 kV/µs CMR. Figure 28.5).threshold (9. To minimize dead time in a given design. of 0. For example.

SHIELD 5 + – VCM Figure 31.1 µF 7 ILEDP + VSAT – 2 + – VCC = 18 V 1 +5 V CLEDP 8 3 CLEDN 6 Rg 5 ••• 2 7 4 SHIELD ••• 3 Q1 4 CLEDN ILEDN 6 * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING –dVCM/dt. Equivalent Circuit for Figure 25 During Common Mode Transient. Recommended LED Drive Circuit for Ultra-High CMR. The maximum dead time for the HCPL-3150 is 700 ns (= 350 ns (-350 ns)) over an operating temperature range of -40°C to 100°C. which is specified to be 350 ns over the operating temperature range of -40°C to 100°C. turn off of LED1) so that under worst-case conditions. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero. The amount of delay necessary to achieve this conditions is equal to the maximum value of the propagation delay difference specification. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 35. Figure 32.1 CLEDP 8 1 CLEDO1 CLEDP 8 2 7 2 CLEDO2 7 3 CLEDN 6 3 CLEDN 6 4 5 4 SHIELD 5 Figure 29. as shown in Figure 34. Figure 30. Not Recommended Open Collector Drive Circuit. 1-210 . +5 V 1 CLEDP 8 0. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. transistor Q1 has just turned off when transistor Q2 turns on. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. PDDMAX. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. but it does not tell a designer what the maximum dead time will be. 1 +5 V CLEDP 8 2 7 3 CLEDN 6 4 SHIELD 5 Figure 33.

3.tPLH MAX) = PDD* MAX – PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 35. 10. Figure 37.7. Dependence of Safety Limiting Value with Case Temperature per VDE 0884.8) (10.7. Waveforms for Dead Time.tPLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. 0.1) 15 20 (12. OUTPUT POWER – PS.2) Q1 ON Q1 OFF Q2 ON VOUT2 ILED2 Q2 OFF tPHL MAX tPLH MIN PDD* MAX = (tPHL. Thermal Derating Curve. 0.3.tPLH)MAX = tPHL MAX . Figure 34. 9.Under Voltage Lock Out.tPHL MIN) + (tPLH MAX .VEE ) – SUPPLY VOLTAGE – V Figure 36. (VCC .ILED1 14 VO – OUTPUT VOLTAGE – V VOUT1 12 10 8 6 4 2 0 (10.tPLH MIN) – (tPHL MIN . INPUT CURRENT – IS 800 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 PS (mW) IS (mA) ILED1 VOUT1 Q1 ON Q1 OFF Q2 ON VOUT2 Q2 OFF ILED2 tPHL MIN tPHL MAX tPLH MIN TS – CASE TEMPERATURE – °C tPLH MAX (tPHL-tPLH) MAX = PDD* MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHL MAX . 1-211 .tPLH MIN) = (tPHL MAX . Minimum LED Skew for Zero Dead Time.1) 0 5 10 (12.

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