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VHDL PROGRAMME IN DATAFLOW

1.BAND GATE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity band is Port ( a,b,c,d : in STD_LOGIC; y : out STD_LOGIC); end band; architecture dataflow of band is begin y<=(not a)and(not b)and(not c)and(not d); end dataflow;

2.BOR GATE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bor_3 is Port ( a,b,c : in STD_LOGIC; y : out STD_LOGIC); end bor_3; architecture dataflow of bor_3 is begin y<=(not a)or(not b)or(not c); end dataflow;

3. 2 BIT COMPARATOR library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comp_2 is Port ( a,b : in STD_LOGIC; eq,less,greater : out STD_LOGIC); end comp_2; architecture dataflow of comp_2 is begin eq<=a xnor b; less<=(not a)and b; greater<=a and (not b); end dataflow; 4.BNAND GATE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity bnand is Port ( a,b,c,d,e,f,g : in STD_LOGIC; y : out STD_LOGIC); end bnand; architecture dataflow of bnand is begin y<=(((((((not a)nand(not b))nand(not c))nand(not d))nand(not e))nand(not f))nand(not g)); end dataflow;

5.BUFFER library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity buffer_1 is Port ( a : in STD_LOGIC; y : out STD_LOGIC); end buffer_1; architecture dataflow of buffer_1 is begin y<=a; end dataflow; 6.D_MUX library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity demux_18 is Port ( a : in STD_LOGIC; s : in STD_LOGIC_VECTOR (3 downto 0); y : out STD_LOGIC_VECTOR (7 downto 0)); end demux_18; architecture dataflow of demux_18 is begin y(0)<=a and(not s(2))and(not s(1))and(not s(0)); y(1)<=a and(not s(2))and(not s(1))and s(0); y(2)<=a and(not s(2))and s(1) and(not s(0)); y(3)<=a and(not s(2))and s(1)and s(0); y(4)<=a and s(2)and(not s(1))and(not s(0)); y(5)<=a and s(2)and(not s(1))and s(0); y(6)<=a and s(2)and s(1)and(not s(0)); y(7)<=a and s(2)and s(1)and s(0); end dataflow;

ALL.7. end excess_3. e(0)<=(not b0).b.b2. 8. e(1)<=((not b1)and(not b0))or(b3 and b2)or(b1 and b0). entity excess_3 is Port ( b3.b0 : in STD_LOGIC. entity fsub is Port ( a.ALL.ALL. use IEEE. use IEEE.STD_LOGIC_1164. diff.STD_LOGIC_ARITH. use IEEE. use IEEE. architecture dataflow of excess_3 is begin e(3)<=b3 or (b2 and b0)or(b2 and b1). BCD-EXCESS3 CODE CONVERTER library IEEE. .b1.STD_LOGIC_1164.ALL.STD_LOGIC_UNSIGNED. end fsub. use IEEE.ALL.c : in STD_LOGIC. borrow<=((not a)and b)or((not a)and c)or(b and c). e(2)<=(b2 and b1 and b0)or (b3 and b2)or((not b2)and b0)or((not b2)and b1). end dataflow.STD_LOGIC_ARITH. e : out STD_LOGIC_VECTOR (3 downto 0)). architecture dataflow of fsub is begin diff<=a xor b xor c. FULL SUBTRACTOR library IEEE. end dataflow.borrow : out STD_LOGIC). use IEEE.STD_LOGIC_UNSIGNED.ALL.

use IEEE.ALL. end dataflow.ALL. use IEEE. bo<=(not a)and b. end hsub. use IEEE. use IEEE.9.STD_LOGIC_UNSIGNED.STD_LOGIC_UNSIGNED. .ALL. architecture dataflow of grey is begin g(3)<=b(3). g(0)<=b(1)xor b(0).ALL. 10. g(2)<=b(3)xor b(2). end grey. g : out STD_LOGIC_VECTOR (3 downto 0)). HALF SUBTRACTOR library IEEE. end dataflow.STD_LOGIC_1164.ALL. d.ALL.STD_LOGIC_ARITH. entity hsub is Port ( a.STD_LOGIC_1164. architecture dataflow of hsub is begin d<=a xor b. g(1)<=b(2)xor b(1).bo : out STD_LOGIC). use IEEE.STD_LOGIC_ARITH.b : in STD_LOGIC. use IEEE.BINARY TO GRAY CODE CONVERTER library IEEE. entity grey is Port ( b : in STD_LOGIC_VECTOR (3 downto 0).

12. y : out STD_LOGIC).STD_LOGIC_ARITH. end inverter_1.ALL. s : in STD_LOGIC_VECTOR (1 downto 0). use IEEE.ALL.STD_LOGIC_ARITH.d : in STD_LOGIC.ALL.ALL. entity inverter_1 is Port ( a : in STD_LOGIC.MUX 4:1 library IEEE.11.b.ALL.STD_LOGIC_UNSIGNED.STD_LOGIC_UNSIGNED. use IEEE.STD_LOGIC_1164. end dataflow. end mux_4. use IEEE. architecture dataflow of inverter_1 is begin y<=not a. . use IEEE. y : out STD_LOGIC).c. use IEEE. entity mux_4 is Port ( a.STD_LOGIC_1164.ALL. end dataflow. use IEEE. INVERTER library IEEE. architecture dataflow of mux_4 is begin y<=((not s(1))and (not s(0)) and a)or((not s(1))and s(0))or( s(1)and not s(0)) or(s(1)and s(0)).

use IEEE. entity nor_2 is Port ( a. NOR GATE library IEEE.STD_LOGIC_ARITH. end nor_2. 14.STD_LOGIC_ARITH. end sr_nor.ALL.STD_LOGIC_UNSIGNED.r : in STD_LOGIC.13.STD_LOGIC_1164.STD_LOGIC_1164. architecture dataflow of nor_2 is begin y<=a nor b. RS –NOR LATCH library IEEE. use IEEE. y : out STD_LOGIC).ALL. q.ALL. use IEEE. use IEEE. end dataflow. end dataflow. use IEEE. use IEEE.nq : inout STD_LOGIC).ALL. entity sr_nor is Port ( s. architecture dataflow of sr_nor is begin q<=r nor nq.b : in STD_LOGIC. . nq<=s nor q.STD_LOGIC_UNSIGNED.ALL.ALL.

std_logic_arith.all. BINARY TO GRAY(WHEN…. end behavioural.std_logic_1164. g:out std_logic_vector(3 downto 0)).ELSE) library ieee.. --------------------------------------------------architecture behavioural of bitogr is begin g<="0000" when b="0000" else "0001" when b="0001" else "0011" when b="0010" else "0010" when b="0011" else "0110" when b="0100" else "0111" when b="0101" else "0101" when b="0110" else "0100" when b="0111" else "1100" when b="1000" else "1101" when b="1001" else "1111" when b="1010" else "1110" when b="1011" else "1010" when b="1100" else "1011" when b="1101" else "1001" when b="1110" else "ZZZZ”. use ieee. use ieee.all. --------------------------------------------------entity bitogr is port(b:in std_logic_vector(3 downto 0). end bitogr.std_logic_unsigned.all.VHDL PROGRAMME IN BEHAVIORIAL 1. . use ieee.

g<='0'.std_logic_arith.std_logic_1164.b) begin if(a=b) then e<='1'. g<='0'. use ieee. use ieee. e.l. 1 BIT COMPARATOR(IF THEN ELSIF) library ieee. end if.g:out std_logic). l<='1'. end process. elsif(a<b ) then e<='0'. . end comp_1. l<='0'. --------------------------------------------------architecture behavioural of comp_1 is begin process (a. l<='0'. --------------------------------------------------entity comp_1 is port(a. use ieee.all.b:in std_logic.2. else e<='0'. g<='1'. end behavioural.std_logic_unsigned.all.all.

4. else e<='0'. use ieee.3. --------------------------------------------------entity comp_4 is port(a.b ) begin if (a=b) then e<='1'.std_logic_arith.b:in std_logic_vector (1 downto 0).all. end behavioural.l. e. --------------------------------------------------architecture behavioural of comp_2 is begin process ( a. else l<='0'.all.b:in std_logic_vector (3 downto 0).std_logic_1164. end if.std_logic_1164. else g<='0'. end comp_4. end if. --------------------------------------------------architecture behavioural of comp_4 is . use ieee. if (a>b) then g<='1'.l.g:out std_logic). --------------------------------------------------entity comp_2 is port(a. end if.std_logic_arith.4BIT COMPARATOR ( IF …THEN…ELSE) library ieee.all. use ieee. end process. e. use ieee. end comp_2.g:out std_logic). if(a<b) then l<='1'. use ieee. use ieee.std_logic_unsigned.all. 1 BIT COMPARATOR( IF…THEN…ELSE) library ieee.all.all.std_logic_unsigned.

std_logic_1164. else if(a<b ) then e<='0'. 1 BIT COMPARATOR (IF. end process. use ieee.all. use ieee. end if..ELSE IF) library ieee.b ) begin if (a=b) then e<='1'. use ieee.l. --------------------------------------------------entity comp_12 is port(a.std_logic_arith. else e<='0'. else g<='0'. end behavioural. if(a<b) then l<='1'. g<='0'. l<='1'. l<='0'.b) begin if(a=b) then e<='1'..std_logic_unsigned.THEN.all. end if. if (a>b) then g<='1'. else if(a>b) then . --------------------------------------------------architecture behavioural of comp_12 is begin process (a. e.all. end if. 5.begin process ( a. end comp_12. else l<='0'.g:out std_logic).b:in std_logic. g<='0'.

use ieee.e<='0'. else e<='0'. end process. l<='1'. end if. 2 BIT COMPARATOR(IF THEN ELSIF) library ieee. end comp_22. .l. use ieee.g:out std_logic). l<='0'.b) begin if(a=b) then e<='1'. end if. end if. end if.std_logic_1164. 6.std_logic_unsigned. e.b:in std_logic_vector(1 downto 0).all. elsif(a<b ) then e<='0'. end process.all. use ieee.all. l<='0'. --------------------------------------------------entity comp_22 is port(a. g<='0'. g<='1'.std_logic_arith. end behavioural. l<='0'. g<='1'. g<='0'. --------------------------------------------------architecture behavioural of comp_22 is begin process (a. end behavioural.

end comp_23. y0.y1. 8.std_logic_1164.all.std_logic_1164.std_logic_arith.y4. end demux1_8 .y. use ieee.all. g<='0'. 2 BIT COMPARATOR(IF THEN ELSE IF) library ieee.std_logic_arith. D MUX (IF THEN ELSE IF ) library ieee. entity demux1_8 is port(x. . l<='1'.y7 : out std_logic).std_logic_unsigned. else if(a>b) then e<='0'.z.all.7.all. g<='1'.all. end if.i :in std_logic. e. end if.y6. --------------------------------------------------entity comp_23 is port(a. use ieee. --------------------------------------------------architecture behavioural of comp_23 is begin process (a. use ieee.y3. end if. l<='0'.b) begin if(a=b) then e<='1'. use ieee. l<='0'. use ieee. end process.y5. end behavioural. g<='0'.y2.b:in std_logic_vector(1 downto 0).l.g:out std_logic).std_logic_unsigned. use ieee. else if(a<b ) then e<='0'.all.

9. else if(x='0' and y='1'and z='1')then y0<=i.b. end if. use ieee.y.c) begin if(a='0' and b='0' and c='1')or(a='0' and b='1' and c='0')or(a='1' and b='0' and c='0')or(a='1' and b='1' and c='1') then s<='1'. end if.ca : out std_logic).std_logic_1164. else y0<=i.c :in std_logic. end fulladd .i) begin if(x='0' and y='0'and z='0')then y0<=i. else if(x='0' and y='1'and z='0')then y0<=i. use ieee.architecture behavioral of demux1_8 is begin process(x. end if.std_logic_unsigned. end if. entity fulladd is port(a. architecture behavioral of fulladd is begin process(a. end if.z.all.std_logic_arith. s. use ieee. end if. else if(x='1' and y='1'and z='0')then y0<=i. end if. else if(x='1' and y='0'and z='0')then y0<=i. . end process. end behavioral.all.b. FULL ADDER library ieee. else if(x='0' and y='0'and z='1')then y0<=i.all. else if(x='1' and y='0'and z='1')then y0<=i.

10. end if.all. entity fullsub is port(a.HALF ADDER library ieee. end if.std_logic_arith.all.std_logic_1164. FULL SUBTRACTOR library ieee.c) begin if(a='0' and b='0' and c='1')or(a='0' and b='1' and c='0')or(a='1' and b='0' and c='0')or(a='1' and b='1' and c='1') then d<='1'. .all. end behavioral.std_logic_unsigned. end if. if(a='0' and b='1' and c='1')or(a='1' and b='0' and c='1')or(a='1' and b='1' and c='0')or(a='1' and b='1' and c='1') then ca<='1'.std_logic_1164. end fullsub .all. if(a='0' and b='0' and c='1')or(a='0' and b='1' and c='0')or(a='0' and b='1' and c='1')or(a='1' and b='1' and c='1') then bo<='1'. else ca<='0'. d.all. use ieee. end process.b. use ieee. use ieee. else bo<='0'.std_logic_unsigned.b. end if. use ieee.bo : out std_logic). use ieee.std_logic_arith.else s<='0'. use ieee. 11. else d<='0'.all. end behavioral.c :in std_logic. end process. architecture behavioral of fullsub is begin process(a.

end if. end halfadd .entity halfadd is port(a.b :in std_logic. architecture behavioral of halfadd is begin process(a.all.b :in std_logic. use ieee. architecture behavioral of halfsub is begin process(a. end if. end if. else bo<='0'. if(a='0' and b='1') then bo<='1'. HALF SUBTRACTOR library ieee. end process. end behavioral. end process. end halfsub . if(a='1' and b='1') then ca<='1'. use ieee. .b) begin if(a=b) then s <= '0'. entity halfsub is port(a. end behavioral. else s<='1'.std_logic_1164.std_logic_unsigned.std_logic_arith.ca : out std_logic). use ieee. end if.all. d.all. else d<='1'. 12.b) begin if(a=b) then d <= '0'. else ca<='0'.bo : out std_logic). s.

b. elsif(a='1' and b='0' and c<='0') then y4<=i. elsif(a='1' and b='0' and c<='1') then y5<=i.c) . y0. end if.all. elsif(a='0' and b='0' and c<='1') then y1<=i. entity fullsub is port(a.std_logic_unsigned.std_logic_arith.13.all.all.FULL SUBTRACTOR library ieee. use ieee.i) begin case if(a='0' and b='0' and c<='0') then y0<=i.all.c :in std_logic. 14.bo : out std_logic). d.std_logic_arith. D MUX ( IF THEN ELSIF) library ieee. end demux_41 . end fullsub . architecture behavioral of fullsub is begin process(a. use ieee. entity demux_41 is port(a :in std_logic_vector(1 downto 0). end process.std_logic_unsigned. elsif(a='1' and b='1' and c<='0') then y6<=i. use ieee. elsif(a='0' and b='1' and c<='0') then y2<=i.y2.y1.std_logic_1164. use ieee. use ieee. i :in std_logic.b.all. elsif(a='1' and b='1' and c<='1') then y7<=i.y3 : out std_logic). architecture behavioral of demux_41 is begin process(a.all. use ieee. elsif(a='0' and b='1' and c<='1') then y3<=i. end behavioral.std_logic_1164.

end binarytoxs3 .all. end if. when "0111"=> y<="1010". use ieee. . else bo<=0. y : out std_logic_vector(3 downto 0)).std_logic_unsigned. when "0010"=> y<="0101". when "0011"=> y<="0110". use ieee. when "0100"=> y<="0111". architecture behavioral of binarytoxs3 is begin process(a) begin case a is when "0000"=> y<="0011". when "1001"=> y<="1100". when "1000"=> y<="1011".begin if(a='0' and b='0' and c='1')or(a='0' and b='1' and c='0')or(a='1' and b='0' and c='0')or(a='1' and b='1' and c='1') then d<= '1'. else d<='0'. 15. end case. if(a='0' and b='1')then bo<= '1'. end if. elsif(a='0' and b='1' and c='1')then bo<='1'.all. when "0101"=> y<="1000". elsif(a='1' and b='1' and c='1')then bo<=1. when "0001"=> y<="0100". end process. end process.std_logic_arith.all. end behavioral. end behavioral. BINARY TO EXCESS3 (CASE) library ieee.std_logic_1164. when "0110"=> y<="1001". entity binarytoxs3 is port(a :in std_logic_vector(3 downto 0). use ieee.

y4.y6. use ieee.std_logic_1164.y7 : out std_logic). y0.std_logic_unsigned. entity demux_12 is port(a. architecture behavioral of demux_81 is begin process(a.16.std_logic_1164. y0.i) begin if(a='0' and b='0' and c<='0') then y0<=i. elsif(a='1' and b='1' and c<='0') then .std_logic_arith.std_logic_unsigned. elsif(a='1' and b='0' and c<='0') then y4<=i. use ieee. elsif(a='1')then y1<=i.all. end behavioral.all.all. end process. end demux_81 .b. architecture behavioral of demux_12 is begin process(a.y3. elsif(a='1' and b='0' and c<='1') then y5<=i. end demux_12 .i :in std_logic. elsif(a='0' and b='1' and c<='0') then y2<=i.y1 : out std_logic). elsif(a='0' and b='1' and c<='1') then y3<=i. use ieee. DMUX 1:2 library ieee.y1. elsif(a='0' and b='0' and c<='1') then y1<=i.all.y2.all.c. 17.y5.i :in std_logic. use ieee.i) begin if(a='0') then y0<=i. use ieee. entity demux_81 is port(a. use ieee.all.std_logic_arith. DMUX 1:8 (IF … ELSIF) library ieee.b.c. end if.

end behavioral.i0.i2. end process.i5. end mux_81 .i5. end if.all.std_logic_1164.all. entity mux_81 is port(a.i3. y : out std_logic).i4. end mux_41 .i4.i0. use ieee. MUX 8:1 ( IF…ELSIF ) library ieee.std_logic_arith. y : out std_logic).all. end if. use ieee.i0. 19. elsif(a='1' and b='1')then y<=i3.all.b.i1. 18.b.ELSIF) library ieee.i6. architecture behavioral of mux_81 is begin process(a.i1.i0.i3 :in std_logic.i1.std_logic_unsigned.std_logic_arith.std_logic_unsigned. MUX 4:1 (IF…. elsif(a='1' and b='1' and c<='1') then y7<=i. end process.i6. elsif(a='0'and b='1')then y<=i1.b.i7 :in std_logic.b.all.i2. use ieee.i2. use ieee.i1. use ieee.c.std_logic_1164.i3.i3) begin if(a='0' and b='0') then y<=i0.i2. end behavioral. use ieee.y6<=i. elsif(a='1' and b='0')then y<=i2.i7) begin if(a='0' and b='0' and c='0') then .all. entity mux_41 is port(a. architecture behavioral of mux_41 is begin process(a.

when "100"=> a<=x xor y.x. end behavioral. use ieee. a : out std_logic).y) begin case s is when "000"=> a<=x. entity alu_1 is port(s :in std_logic_vector(2 downto 0).all.std_logic_unsigned. elsif(a='0' and b='1' and c='0') then y<=i2. architecture behavioral of alu_1 is begin process(s. end behavioral.all.y : in std_logic. elsif(a='0' and b='0' and c='1') then y<=i1. elsif(a='1' and b='1' and c='1') then y<=i7. when "111"=> a<=not(x xor y). when "110"=> a<=not(x and y). x. elsif(a='1' and b='0' and c='0') then y<=i4. when "001"=> a<=y. end alu_1 . when "010"=> a<=x or y. use ieee. end case. when "011"=> a<=x and y. elsif(a='1' and b='0' and c='1') then y<=i5.y<=i0. end process.all. elsif(a='0' and b='1' and c='1') then y<=i3. end if. 20. 1 BIT ALU library ieee.std_logic_1164.std_logic_arith. elsif(a='1' and b='1' and c='0') then y<=i6. when "101"=> a<=not(x or y). end process. . use ieee.

21. BINARY TO EXCESS3 ( CASE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity binarytoxs3 is port(a :in std_logic_vector(3 downto 0); y : out std_logic_vector(3 downto 0)); end binarytoxs3 ; architecture behavioral of binarytoxs3 is begin process(a) begin case a is when "0000"=> y<="0011"; when "0001"=> y<="0100"; when "0010"=> y<="0101"; when "0011"=> y<="0110"; when "0100"=> y<="0111"; when "0101"=> y<="1000"; when "0110"=> y<="1001"; when "0111"=> y<="1010"; when "1000"=> y<="1011"; when others=> y<="1100"; end case; end process; end behavioral; 22. DECODER 3:8 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity decoder38 is port(s :in std_logic_vector(2 downto 0); a : out std_logic_vector(7 downto 0)); end decoder38 ; architecture behavioral of decoder38 is begin process(s) begin case s is when "000"=> a<="00000001"; when "001"=> a<="00000010"; when "010"=> a<="00000100"; when "011"=> a<="00001000"; when "100"=> a<="00010000"; when "101"=> a<="00100000";

when "110"=> a<="01000000"; when "111"=> a<="10000000"; end case; end process; end behavioral; 23. DMUX 1:4 (CASE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity demux_41 is port(a :in std_logic_vector(1 downto 0); i :in std_logic; y : out std_logic_vector(3 downto 0)); end demux_41 ; architecture behavioral of demux_41 is begin process(a,i) begin case a is when "00" =>y(0)<=i; when others =>y(0)<='0'; end case; case a is when "01" =>y(1)<=i; when others =>y(1)<='0'; end case; case a is when "10" =>y(2)<=i; when others =>y(2)<='0'; end case; case a is when "11" =>y(3)<=i; when others =>y(3)<='0'; end case; end process; end behavioral; 24. QUESTION library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity desprob is port(e :in std_logic_vector(1 downto 0); c,d : in std_logic; a,b : out std_logic);

end desprob ; architecture behavioral of desprob is begin process(e) begin b<='1'; case e is when "00"=> a<=c; when "01"=> a<=d; when "10"=> a<=c or d; when others => a<='0'; end case; end process; end behavioral; 25. MUX 2:1 (CASE) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mux_21 is port(a,i0,i1 :in std_logic; y : out std_logic); end mux_21 ; architecture behavioral of mux_21 is begin process(a,i0,i1) begin case a is when '0' => y<=i0; when '1' => y<=i1; when others=>y<='Z'; end case; end process; end behavioral; 26. TRISTATE BUFFER library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity tristatebuf is port(a :in std_logic_vector(1 downto 0); y : out std_logic); end tristatebuf ; architecture behavioral of tristatebuf is begin

w. architecture dataflow of binarytogray is begin w<=a when s='0' else a . when others=> y<='Z'. use ieee. 27. end behavioral.all. end process. use ieee. when others=> y<='Z'.std_logic_arith. entity tristateinv is port(a :in std_logic_vector(1 downto 0).d. end tristateinv .std_logic_1164. TRISTATE INVERTER library ieee.std_logic_unsigned.x.process(a) begin case a is when "10"=> y<='1'.all. y<= b xor c when s='0' . y : out std_logic).b. end behavioral. use ieee.y. when "11"=> y<='1'. use ieee. end case.std_logic_unsigned. when "11"=> y<='0'. end binarytogray .z : out std_logic). BINARY TO GRAY (WHEN ELSE) library ieee.s :in std_logic. end case.c. entity binarytogray is port(a.std_logic_1164. use ieee. architecture behavioral of tristateinv is begin process(a) begin case a is when "10"=> y<='0'. use ieee.all. x<= a xor b when s='0' else a xor b .all.std_logic_arith. 28.all. end process.all.

use ieee.all. 30.std_logic_1164. end dataflow.else b xor c .all. y0. use ieee.i :in std_logic. use ieee. y1<=i when s='1' else '0'. use ieee.all.std_logic_unsigned. y : out std_logic). ALU library ieee.i2. entity demux_12 is port(s. .all.std_logic_arith. 29.all.std_logic_arith.i1. architecture dataflow of demux_12 is begin y0<=i when s='0' else '0'.i3 :in std_logic. z<= c xor d when s='0' else c xor d . use ieee.all.std_logic_unsigned.all.std_logic_1164. entity mux_41 is port(i0. use ieee. end mux_41 . architecture dataflow of mux_41 is begin y<=i0 when s="00" else i1 when s="01" else i2 when s="10" else i3.std_logic_arith. use ieee. s :in std_logic_vector(1 downto 0).all. use ieee. end demux_12 .std_logic_unsigned.all. end dataflow. 31.std_logic_1164.y1 : out std_logic). D MUX( WHEN ELSE) library ieee.MUX 4:1 ( WHEN ELSE) library ieee. end dataflow. use ieee.

s : in std_logic_vector(2 downto 0). w.std_logic_1164.all.all.z : out std_logic). y<='1' when a="0101" else '1' when a="0110" else '1' when a="1001" else '1' when a="1010" else '0' . end dataflow. architecture dataflow of selectorval is begin y<= (a and b) when s="000" else (not(a and b)) when s="001" else (a xor b) when s="010" else (a xnor b) when s="011" else (not a) when s="100" else (not b) when s="101" else 'Z'.all.std_logic_arith. use ieee.x.entity selectorval is port(a. use ieee. z<='1' when a="0100" else '1' when a="0110" else '1' when a="1000" else '1' when a="1010" else '1' when a="1100" else '0' . use ieee. 32.std_logic_unsigned.b :in std_logic.y. EXCESS3 TO BINARY library ieee. entity xs3tobinary is port(a :in std_logic_vector(3 downto 0). x<='1' when a="0111" else '1' when a="1000" else '1' when a="1001" else '1' when a="1010" else '0' . end selectorval . end xs3tobinary . y : out std_logic). . end dataflow. architecture dataflow of xs3tobinary is begin w<='1' when a="1011" else '1' when a="1100" else '0' .

entity demux_81 is port(s :in std_logic_vector(2 downto 0).y6.std_logic_unsigned.all. with s select y5<=i when "101".y2.y7 : out std_logic). end dataflow. with s select y2<=i when "010". end demux_81 . '0' when others. '0' when others. use ieee.std_logic_1164. with s select y1<=i when "001". a :out std_logic_vector(3 downto 0)).33. use ieee.all. '0' when others. i: in std_logic. with s select y7<=i when "111".all. '0' when others. use ieee. with s select y6<=i when "110".all.all. use ieee. architecture dataflow of graytobinary is .std_logic_unsigned. '0' when others.y1. '0' when others. with s select y4<=i when "100".y4.std_logic_arith.y3. '0' when others. with s select y3<=i when "011". end graytobinary . entity graytobinary is port(s :in std_logic_vector(3 downto 0). 34. '0' when others. DMUX 1:8 (WITH SELECT) library ieee.y5. architecture dataflow of demux_81 is begin with s select y0<=i when "000". use ieee.std_logic_arith. GRAY TO BINARY (WITH SELECT) library ieee. y0.std_logic_1164.all. use ieee.

std_logic_1164. "1101" when "1001".i2. "0100" when "0111". i5 when "101".all. "0011" when "0010".i1. entity mux_81 is port(s :in std_logic_vector(2 downto 0). "1001" when "1110".i7: in std_logic. use ieee. "1100" when "1000". i2 when "010".i4. i1 when "001".all. use ieee. end dataflow. "1011" when "1101".i5.std_logic_arith. "0001" when "0001". "0110" when "0100". end mux_81 . "0010" when "0011". i6 when "110". i4 when "100".i6. "0101" when "0110". 35. MUX 8:1 (WITH SELECT) library ieee.begin with s select a<="0000" when "0000". "1110" when "1011".i3. i3 when "011".std_logic_unsigned. "0111" when "0101". y : out std_logic).all. . i0. use ieee. "1111" when "1010". architecture dataflow of mux_81 is begin with s select y <=i0 when "000". "1010" when "1100". end dataflow. "1000" when others. i7 when others.

STD_LOGIC_UNSIGNED.Q2 library IEEE. use IEEE.ALL. use IEEE.ALL. use IEEE. entity task18_2 is Port ( a : in std_logic_vector(1 downto 0). end behavioral. use IEEE. architecture Behavioral of task18_2 is begin y<=i0 after 10ns when a="00" else i1 after 10ns when a="01" else i2 after 10ns when a="10" else i3 after 10ns.ALL. 38.ALL.STD_LOGIC_ARITH.STD_LOGIC_ARITH. y : out STD_LOGIC). end Behavioral.ALL. end TASK18_1. AFTER EXAMPLE library IEEE.ALL.i3 : in STD_LOGIC.STD_LOGIC_UNSIGNED. ca<=(x and y) after 30ns. use IEEE. library IEEE. i0.36.ALL.y : in STD_LOGIC.i2. s.STD_LOGIC_1164. .ca : out STD_LOGIC). end task18_2. use IEEE. use IEEE. use IEEE.ALL.STD_LOGIC_ARITH.i1.STD_LOGIC_1164.STD_LOGIC_UNSIGNED. use IEEE. entity TASK18_1 is Port ( x.STD_LOGIC_1164. architecture behavioral of TASK18_1 is begin s<=(x xor y) after 20ns.ALL. 37.

. architecture Behavioral of task18_3 is begin y1<=a. library IEEE. architecture Behavioral of task_18_4 is begin process(a. process(a. y<=a after 10ns. use IEEE.ALL. end if.b.y. end process. p. else s<='0'.'0' after 30ns. w.ALL. use IEEE. end Behavioral.c) begin if(a=b)then p<='1'.c) begin if(a='0' and b='1')or(a='1' and b='0') then s<='1'.x.b. end task_18_4.q. else p<='0'.c : in STD_LOGIC.ALL.STD_LOGIC_ARITH. end process.b. end if.STD_LOGIC_UNSIGNED. r<=a after 30 ns. q<=c after 10 ns. x<=(a and b) after 30ns. end behavioral.entity task18_3 is Port ( a.y1 : out STD_LOGIC).s : out STD_LOGIC). end task18_3.'1' after 20ns.STD_LOGIC_1164. entity task_18_4 is Port ( a. 39.b : in STD_LOGIC.r. w<=a after 10ns . use IEEE.

when "001" => y<=i(1). e : in std_logic. when "100" => y<=i(4).STD_LOGIC_1164. entity task_18_6 is Port ( din : in STD_LOGIC_vector(6 downto 0). use IEEE. use IEEE. entity task_18_5 is Port ( a : in STD_LOGIC_vector(2 downto 0). end Behavioral. use IEEE. when "111" => y<= null. architecture Behavioral of task_18_5 is begin process(a.i) begin case a is when "000" => y<=i(0). use IEEE. when "010" => y<=i(2). when "101" => y<=i(5).STD_LOGIC_UNSIGNED. NULL EXPRESSION library IEEE.ALL. end process. architecture Behavioral of task_18_6 is begin process(din.ALL.ALL. end task_18_5.ALL. library IEEE. use IEEE.ALL.STD_LOGIC_ARITH. use IEEE.STD_LOGIC_ARITH.STD_LOGIC_UNSIGNED.40. end task_18_6.ALL. 41. when "011" => y<=i(3). end case. when "110" => y<=i(6).STD_LOGIC_1164. y : out STD_LOGIC). i : in std_logic_vector(6 downto 0). dout : out STD_LOGIC_vector(6 downto 0)).e) begin .

dout(1)<=din(1). i:=0. for i in 0 to 6 loop dout(i)<=din(i). end process. dout(3)<=din(3).e. dout(6)<=din(6).ALL. use IEEE. else dout(6)<=din(0).STD_LOGIC_ARITH.STD_LOGIC_1164. dout : out STD_LOGIC_vector(6 downto 0)). dout(2)<=din(2). architecture Behavioral of task_18_7 is begin process(din. 42. use IEEE. dout(5)<=din(6). for i in 0 to 5 loop . dout(1)<=din(2). e.if(e='0') then dout(0)<=din(0). dout(3)<=din(4).i) begin if(e='0') then i:=0. end if. use IEEE. dout(4)<=din(4).ALL. FOR LOOP library IEEE. end loop.i: in std_logic.STD_LOGIC_UNSIGNED. dout(2)<=din(3). else dout(0)<=din(1). end task_18_7. entity task_18_7 is Port ( din : in STD_LOGIC_vector(6 downto 0). dout(6)<=din(0).ALL. dout(4)<=din(5). end Behavioral. dout(5)<=din(5).

D FLIPFLOP library IEEE. end if. end behavioral.ALL. end process. else q<=d. qbar<= (not d). qbar<='1'.ALL. use IEEE. use IEEE.ALL. end task19_1. end if.ALL.ALL. end process. qbar : out STD_LOGIC). use IEEE.ALL.STD_LOGIC_1164.STD_LOGIC_ARITH. end if. entity task19_1 is Port ( d. use IEEE.STD_LOGIC_UNSIGNED.rst : in STD_LOGIC. use IEEE. end Behavioral.STD_LOGIC_ARITH.clk.clk.dout(i)<=din(i+1). end loop. . architecture behavioral of task19_1 is begin process(d. T FLIP FLOP library IEEE.STD_LOGIC_1164. 43. q. use IEEE. 44.STD_LOGIC_UNSIGNED.rst) begin if(clk'event and clk='1') then if(rst<='1')then q<='0'.

rst : in STD_LOGIC. . else if(t='1') then w:=(not w).ALL.rst) variable w:std_logic.clk. use IEEE. qbar<='1'.ALL.qbar : out std_logic). entity task19_3 is Port ( j. qbar : out std_logic. q : inout std_logic). end if.k. q<=w. architecture behavioral of task19_3 is begin process(j.entity task19_2 is Port ( t.ALL. else if(j='0' and k='1') then q<='0'.clk. MASTER-SLAVE JK FLIP FLOP library IEEE. end if. end process. end task19_2. qbar<=not w. if(clk'event and clk='1') then if(rst='1')then q<='0'.STD_LOGIC_ARITH.clk.STD_LOGIC_UNSIGNED. qbar<='1'. end behavioral. begin if(clk'event and clk='1') then if(rst='1')then q<='0'. 45. use IEEE. architecture behavioral of task19_2 is begin process(t. begin w:='0'.rst) variable w:std_logic.k. use IEEE.STD_LOGIC_1164.clk. end if.rst : in STD_LOGIC. q.q. end task19_3.

mode : in STD_LOGIC. UP-DOWN COUNTER library IEEE. architecture behavioral of task19_4 is begin process(clk. qbar<='0'. end if. use IEEE. end if. count<=temp. end process.ALL. end if. use IEEE. else if(j='1' and k='1')then w:=q. w:=(not w). count : out STD_LOGIC_vector(3 downto 0)). begin if(rising_edge (clk)) then if(mode='1')then temp:=temp+1. else temp:=temp-1. end behavioral.STD_LOGIC_UNSIGNED. entity task19_4 is Port ( clk. use IEEE.ALL. end if. . q<=w.qbar<='1'. end behavioral. end task19_4. end if. qbar<=not w.ALL. end process.STD_LOGIC_1164. 46.STD_LOGIC_ARITH. end if. end if. else if(j='1' and k='0')then q<='1'.mode) variable temp:std_logic_vector(3 downto 0):="0000".

architecture data of fdiv_3 is begin . use IEEE. architecture data of base_6 is begin process(clk) variable temp: std_logic_vector(2 downto 0):=”000”.ALL. use IEEE. entity base_6 is port(clk: in std_logic.STD_LOGIC_ARITH. 48.ALL. use IEEE. end fdiv_3. entity fdiv_3 is port(clk: in std_logic.STD_LOGIC_1164. temp:=temp+1.ALL. if(temp > “101”) then temp:=”000”. BASE-6 COUNTER library IEEE.ALL. end process.47. end data.STD_LOGIC_UNSIGNED. end if.ALL. use IEEE.STD_LOGIC_UNSIGNED. FREQUENCY DIVIDER (DIVISION BY 3) library IEEE.STD_LOGIC_ARITH. use IEEE. use IEEE.ALL. end if.STD_LOGIC_1164. count: out std_logic_vector( 2 downto 0)). count: out std_logic). end base_6. begin if(clk’event and clk=’1’) then count<=temp.

process(clk) variable temp: std_logic_vector(2 downto 0):=”000”. entity task1910 is Port ( syn_clr.STD_LOGIC_1164. use IEEE.STD_LOGIC_UNSIGNED.ALL.STD_LOGIC_ARITH. end process. if (temp > “110”) then count<=’0’. architecture Behavioral of task1910 is begin process(syn_clr.ALL. end if. use IEEE. UNIVERSAL COUNTER library IEEE. end data. d:in std_logic_vector(3 downto 0). begin if(syn_clr='1')then qout<="0000". else qout<=temp.d) variable temp:std_logic_vector(3 downto 0):="0000". .load. temp:=”001”.ALL. elsif(syn_clr='0' and load='1') then qout<=d. if(temp >”011”) then count<=’1’. elsif(syn_clr='0' and load='0' and en='1' and up='1')then temp:=temp+1. end if. qout<=temp. elsif(syn_clr='0' and load='0' and en='1' and up='0')then temp:=temp-1. qout<=temp. qout : out std_logic_vector(3 downto 0)).load. end task1910.en.up : in STD_LOGIC. begin if(clk’event and clk=’1’) then temp:=temp+1. 49.up.en. end if. use IEEE.

use IEEE. sec:=sec_in.ALL.sec_in : inout integer range 0 to 59). wait for 10000 ns. architecture Behavioral of micro_wave is begin process variable hr :integer range 0 to 23. sec:=0. use IEEE.sec:integer range 0 to 59. if(hr=0)then hr:=23. entity micro_wave is Port ( hr_in : inout integer range 0 to 23. use IEEE. end process.ALL. variable min. end micro_wave.STD_LOGIC_UNSIGNED. if(hr_in=0 and min_in=0 and sec_in=0)then hr:=0. begin hr:=hr_in. min:=0. else hr:=hr-1. if(min=0)then min:=59.STD_LOGIC_ARITH. else min:=min-1. else sec:=sec-1. end if. elsif(sec=0)then sec:=59. min:=min_in. end if. end Behavioral.end if. MICROWAVE OWEN library IEEE.ALL. min_in.STD_LOGIC_1164. 50. end if. .

(“1111”.”1111”)).STD_LOGIC_UNSIGNED. begin data<= rom1 ( conv_integer (add(0 to 1)).”0000”). (“1101”.”1000”. min_in<=min.”1011”. use IEEE. end Behavioral.”0010”). add: in std_logic_vector( 3 downto 0). (“1001”. sec_in<=sec. ROM library IEEE.”1001”. constant rom1: rom_44 := ((“0001”. end data.STD_LOGIC_ARITH.conv_integer (add(2 to 3))) when (rd=’1’ and cs=’1’) else “----“.”1100”.ALL.”0010”). use IEEE. data: out std_logic_vector( 3 downto 0)). end process.ALL. .”1101”. architecture data of rom_44 is type rom_44 is array ( 0 to 3 .hr_in<=hr.”1011”. 51.STD_LOGIC_1164. “0101”.ALL.cs: in std_logic. use IEEE. 0 to 3) of std_logic_vector(3 downto 0). entity rom_44 is port ( rd.”1100”. end rom_44.

add: in std_logic_vector( 3 downto 0).”1001”. else data<= “----“.”1111”)).”0010”). entity ram_44 is port ( rd.ALL. use IEEE. use IEEE. end if. “0101”.”1100”.conv_integer (add(1 downto 0))).”1011”.ALL. architecture data of ram_44 is type ram_44 is array ( 0 to 3 . 0 to 3) of std_logic_vector(3 downto 0).”1011”.ALL.”1101”. begin if( rd=’1’ and cs=’1’) then data<= ram1 (conv_integer (add(3 downto 2)).cs: in std_logic.”1000”.STD_LOGIC_ARITH. elsif (rd=’0’ and cs=’1’ and wr=’1’) then ram1 (conv_integer (add(3 downto 2)). end ram_44.STD_LOGIC_UNSIGNED.conv_integer (add(1 downto 0))).STD_LOGIC_1164. wr: in std_logic. end process. (“1001”.”0010”). data: out std_logic_vector( 3 downto 0)). use IEEE. (“1101”. . constant ram1: ram_44 := ((“0001”.”0000”).”1100”. data<= ram1 (conv_integer (add(3 downto 2)).conv_integer (add(1 downto 0))):=data. RAM library IEEE. (“1111”.52. end data.

ALL.53.STD_LOGIC_1164. end process. use IEEE. end data. end if. end dec_cnt. begin if (clk’event and clk=’1’) then temp:=temp+1. digit : out integer range 0 to 9).STD_LOGIC_UNSIGNED.STD_LOGIC_ARITH. use IEEE. DECADE COUNTER library IEEE.ALL. . if( temp =10) then temp:=0.ALL. end if. entity dec_cnt is port (clk: in std_logic. digit <= temp. use IEEE. architecture data of dec_cnt is begin process(clk) variable temp : integer range 0 to 10.

elsif ( temp (3) =’1’ and temp /= “1111”)then temp := temp sra 1.STD_LOGIC_UNSIGNED. else temp := temp srl 1. end process. entity jo_cnt is port (clk:in std_logic. end jo_cnt.ALL. count : inout bit_vector( 3 downto 0 )). use IEEE.STD_LOGIC_1164. end if. if( clk’event and clk=’1’) then if(temp=”0000”)then temp:= “1000”.STD_LOGIC_ARITH.ALL. . architecture data of jo_cnt is begin process( clk) variable temp:bit_vector(3 downto 0):=”0000”. JHONSON COUNTER library IEEE. end if.54. use IEEE. begin count<=temp. end data. use IEEE.ALL.

use IEEE. use IEEE. entity lrsr is generic ( k: integer :=4). end lrsr.55.ALL.STD_LOGIC_UNSIGNED.rst. .ALL. end process.ALL. end reg.rst.ALL. elsif ( clk’event and clk =’1’) then for i in k downto 2 loop q(i) <= q(i – 1). end data. q : out std_logic_vector ( n. n bit register library IEEE.ALL.w) begin if(rst=’0’) then q<=(others=> ‘0’). 56. q: buffer std_logic_vector ( k downto 1)).1 downto 0)). use IEEE. port (clk. end if.STD_LOGIC_ARITH.w : in std_logic. end loop. entity reg is generic ( n: integer := 8).clk : in std_logic.ALL. use IEEE. port ( r : in std_logic_vector (n-1 downto 0). q(1) <= w. architecture data of lrsr is begin process( clk.LEFT-RIGHT SHIFT REGISTER WITH RESET library IEEE. use IEEE. rin.STD_LOGIC_1164. use IEEE.STD_LOGIC_UNSIGNED.STD_LOGIC_1164.STD_LOGIC_ARITH.

use IEEE. end loop.STD_LOGIC_1164. else for i in 0 to n-2 loop q(i)<=q(i+1).clk) begin if ( clk’event and clk=’1’) then if ( l=’1’) then q<=r.l. l.architecture data of reg is begin process ( r.w. . clk ) begin wait until clk’event and clk=’1’ . end process. port ( r : in std_logic_vector ( n-1 downto 0).ALL. end srpl. entity srpl is generic ( n : integer := 4). 57. use IEEE. if ( rin = ‘1’) then q<=r. rin.clk : in std_logic.ALL. end data. q(n-1) <= w. q : buffer std_logic_vector ( n-1 downto 0)). end if. architecture data of srpl is begin process (r. use IEEE. end if. SHIFT REGISTER PARALLEL LOAD library IEEE.w. end process.STD_LOGIC_ARITH. end data. end if.ALL.STD_LOGIC_UNSIGNED.

sum0. architecture structural of task2101 is component xor_gt is port(c.sum1).car3). end task2101.s3.sum3.STD_LOGIC_1164. u11: xor_gt port map(A2. end component.B2.s7). end component.car2). library IEEE.s4. u9:and_gt port map(car0.s3. u13:xor_gt port map(car1.s4.s12.s7. . u20: or_gt port map(s11. component and_gt is port(c.B1.A1.s2).s6.STRUCTURAL MODELING 1.ALL. u15: or_gt port map(s8.A2.B1.s1.s12.s10). use IEEE.car0. u19:and_gt port map(car2.car1.STD_LOGIC_UNSIGNED.s9.s7.sum2).s9). end structural.s11.s5.sum2.s4).s4. u12:and_gt port map(A2.s3). u2:and_gt port map(A0.s9.sum3).car2 :std_logic. u4:and_gt port map('0'.STD_LOGIC_ARITH.ALL. u3:xor_gt port map('0'. component or_gt is port(c. u5: or_gt port map(s2.sum0). u7:and_gt port map(A1. end component. signal s1.s2.s8.s12).B0.s10.B0.s11).s5).A3.car3:out std_logic). u14:and_gt port map(car1.s10. e : out std_logic).B3 : in STD_LOGIC.car0).d : in std_logic.B1.B2.sum1.d : in std_logic.car1).B3. e : out std_logic).B3. u8:xor_gt port map(car0.ALL.s1). u16: xor_gt port map(A3.d : in std_logic. u6: xor_gt port map(A1.B2.B0. u17:and_gt port map(A3. use IEEE.s7.s10.s6).s6. u10: or_gt port map(s5.s1.s8). use IEEE. e : out std_logic). u18:xor_gt port map(car2. entity task2101 is Port ( A0. begin u1: xor_gt port map(A0.

s9). end structural.i3.s9.s5.ALL.s8.STD_LOGIC_UNSIGNED. u13:or_gt port map(s7.s3.i1. end component.Y). use IEEE. e : out std_logic).y1 :std_logic. signal s1.s4).s10. component or_gt is port(c. end component.ALL.s10.se3: in STD_LOGIC. e : out std_logic). end component.s6).d : in std_logic.y0).y1). Y:out std_logic). u4:or_gt port map(s1.s6.s9.s2. entity task2102 is Port ( i0.s5). u6:not_gt port map(se1. u11:not_gt port map(s10.2.STD_LOGIC_ARITH.y0. u3:and_gt port map(s2. u12:and_gt port map(s8. u7:and_gt port map(s5.STD_LOGIC_1164.s8).se1. e : out std_logic). use IEEE.ALL. u10:and_gt port map(y1.s10).i3.d : in std_logic. library IEEE.s2). end task2102.i2. u5:and_gt port map(y0.i2. begin u1:and_gt port map(i0.s4. u8:or_gt port map(s4. architecture structural of task2102 is component and_gt is port(c.s3.se1.s6. component not_gt is port(c : in std_logic.s3). use IEEE. u9:not_gt port map(se3.s7).s1).i1.s7. u2:not_gt port map(se0. .se0.se0.

library IEEE.3. . architecture structural of task2103 is component xor_gt is port(c. e : out std_logic).s12. u8:not_gt port map(p(1).s20.s3. component and3_gt is port(c.s7. u2:not_gt port map(p(1).f : in std_logic. e : out std_logic). p:in std_logic_vector(2 downto 0).s1(2). use IEEE. begin u1:not_gt port map(p(0).STD_LOGIC_1164. e : out std_logic).s15.s9). end component.s10).d : in std_logic.s22.s10. u6:and_gt port map(s9. use IEEE.s19. e : out std_logic). e : out std_logic). component or_gt is port(c.ALL. e : out std_logic).s8:std_logic_vector(2 downto 0).d. component and_gt is port(c.s2(0)).STD_LOGIC_UNSIGNED.ALL.s11.s17. end component.s16.s5.s10. end component.s1(1)).s24:std_logic. component not_gt is port(c: in std_logic. u5:not_gt port map(A.d : in std_logic. component buffer_gt is port(c : in std_logic. u3:not_gt port map(p(2). e : out std_logic).s4. Y:out std_logic_vector(7 downto 0)).Y(0)).s2.s1(0)).s18.STD_LOGIC_ARITH.s21. u4:and3_gt port map(s1(0). u7:not_gt port map(p(0).s1(1).d : in std_logic. signal s1. signal s9.s13. entity task2103 is Port ( A. end task2103.s23. component xnor_gt is port(c. use IEEE.ALL.s2(1)). end component.B : in STD_LOGIC. end component.s14.d : in std_logic.s1(2)).s6. end component. end component.

s7(2)). u28:xnor_gt port map(A.B.Y(2)). u10:not_gt port map(B.s22.Y(6)).s5(2)).s5(1).s16).s16.s5(1)).Y(4)).s12).s3(2).s23). . end structural. u12:not_gt port map(p(0). u18:and3_gt port map(s4(0).s5(2).s2(1).s18). u36:and_gt port map(s23.s20).p(1).s14). u34:and3_gt port map(p(0).Y(1)). u35:buffer_gt port map(B.p(2).p(2).Y(5)). u19:and_gt port map(A.s20. u30:not_gt port map(p(2).s13).s24. u24:xor_gt port map(A. u16:and_gt port map(s13.s11). u14:and3_gt port map(s3(0). u15:or_gt port map(A. u25:and_gt port map(s17. u17:not_gt port map(p(0).B.s21).s3(2)).u9:and3_gt port map(s2(0).s12. u23:and3_gt port map(p(0).s24). u31:and3_gt port map(p(0). u13:not_gt port map(p(2).p(1).s15).s3(0)). u29:and_gt port map(s19.s6(1)). u26:not_gt port map(p(1).s17).s6(1).p(2). u22:not_gt port map(p(2). u27:and3_gt port map(p(0).B.s22).s14.p(2).s4(0)). u32:buffer_gt port map(A.B.Y(3)). u33:and_gt port map(s21.p(1).Y(7)).p(1).s19). u21:not_gt port map(p(1). u11:and_gt port map(s11.s7(2).s18. u20:and_gt port map(s15.

s20:std_logic.s13). u8:nand_gt port map(s7.s3).s9.s16).clk. u11:nand_gt port map(s11.s11. end task2104.s6.s14).s18. u3:nand_gt port map(s1. u6:nand_gt port map(s4.4. u9:not_gt port map(s9.STD_LOGIC_UNSIGNED.clk : in STD_LOGIC. end component.s4). u5:not_gt port map(s4. end structural. entity task2104 is Port ( A. u2:nand_gt port map(A.ALL. u12:nand_gt port map(s12.s20.s1). Y:out std_logic).s15. u4:nand_gt port map(s2.ALL.s19).clk.clk.STD_LOGIC_1164.s13.s7).s3.s5.s2. u15:nand_gt port map(s16.STD_LOGIC_ARITH.s15. use IEEE.clk. u13:not_gt port map(s14. end component. u10:nand_gt port map(s9.s5.clk. . e : out std_logic).s19.s8).s17). signal s1.clk.s9).s18). library IEEE. e : out std_logic).s17. use IEEE.s4. component not_gt is port(c : in std_logic. u16:nand_gt port map(s17.s14.s10.s6).s8.ALL.s11). u14:nand_gt port map(s14.s7.s16.s12).clk.s2). begin u1:not_gt port map(A. architecture structural of task2104 is component nand_gt is port(c. use IEEE.s12.d : in std_logic.clk.s10. u7:nand_gt port map(s1.

s0.k1). signal k1.STD_LOGIC_ARITH. end component.STD_LOGIC_1164.b0. end struct.sum1.i2.i1.b0.k2). use IEEE. u4:not_gt port map(s2. component fadder is port(a0. component not_gt is port(a:in std_logic.s2 : in STD_LOGIC.sum2. y:out std_logic). use IEEE. 4 BIT BINARAY PARALELL ADDER library IEEE.b1.ca : out std_logic).i3. library IEEE. 6.ALL. use IEEE. use IEEE. architecture struct of prgm2 is component mux2 is port(i0. entity prgm2 is Port ( i0.STD_LOGIC_UNSIGNED.STD_LOGIC_UNSIGNED.k3. ca. end component.ALL. architecture struct of prgm2 is c0:=0.ALL.sum0.y :out std_logic). u2:mux2 port map(k1.k3).5.sum3 : out STD_LOGIC).a2.ALL.STD_LOGIC_ARITH.i3. begin u1:mux2 port map(i0.y).s1.ALL. entity prgm2 is Port ( a0.c0:in std_logic. end component. .ALL. use IEEE.s0.a3.k2.a1.STD_LOGIC_1164.s1. end prgm2. sum.k3:std_logic. use IEEE. end prgm2.i1.b2.i1.b3.s0:in std_logic.i2. u3:mux2 port map(k2. y:out std_logic).c0 : in STD_LOGIC.

begin u1:dflip port map(a=>d.sum3.q=>q. u3:fadder port map(a2. architecture struct of siso is component dflip is Port ( a.k3).k4.sum0.q.ALL.b1. end struct. use IEEE.k3.qbar=>qbar).k2. qbar:inout std_logic).ALL. use IEEE.qbar=>qbar). end struct.qbar=>qbar). u4:dflip port map(a=>q. SISO library IEEE.qbar:inout std_logic).clk=>clk.STD_LOGIC_ARITH.k4). u2:dflip port map(a=>q.c0. end component.q=>q.b0.k4:std_logic.qbar=>qbar).clk : in STD_LOGIC.clk=>clk. u4:fadder port map(a3.k2). Sentity siso is Port ( d.q :inout std_logic. --signal k1. u1:fadder port map(a0.k6:std_logic.clk=>clk. use IEEE.b2.k3.clk : in STD_LOGIC.q=>q. u2:fadder port map(a1.k1. u3:dflip port map(a=>q.b3. 7.q=>q. .sum2.ALL.k5.signal k1. end siso.STD_LOGIC_1164.sum1.k1).k2.k3.k2.clk=>clk.STD_LOGIC_UNSIGNED.

s0.s0:in std_logic. signal k1.i3.i3. end component.k1).s1.k3:std_logic.ALL. end prgm2.s2 : in STD_LOGIC. architecture struct of prgm2 is component mux2 is port(i0. end component. component not_gt is port(a:in std_logic.STD_LOGIC_ARITH.i1. u2:mux2 port map(k1.i2.k2).STD_LOGIC_1164.s1.i1.ALL. .k3.s0.STD_LOGIC_UNSIGNED.8.y :out std_logic). entity prgm2 is Port ( i0.i1.ALL.y). end struct. u3:mux2 port map(k2. y:out std_logic). u4:not_gt port map(s2. y:out std_logic).k2. use IEEE.i2. use IEEE. library IEEE. begin u1:mux2 port map(i0. use IEEE.k3).

y). assign bo=(~ a)& b.i2. reg y. output y.bo).i4.c. input i0. input a.s.i1. else if(s==001) y=i1. input a.b. sum. output y. assign sum=(a^b)^c.c.VERILOG 1.i1.ca). endmodule 4.i2. assign y=a. endmodule 3.i4.diff. output bo.i6. BUFFER module buffer(a.diff.i3.b. y).i7. MUX 8:1 module mux8(i0.ca. else if(s==010) .i3. endmodule 2. FULL ADDER module fadder(a. input [2:0]s.b. output sum.b. HALF SUBTRACTOR module halfsub(a. assign ca=((a&b)|((a^b)&c)). input a.i5.i5.i7. assign diff=((a&(~b))| (b&(~a))).i6. always @(*) begin if (s==000) y=i0.

input a.b. NAND GATE module nand_gt(a. input[1:0]s.y4).y3.y3=0.s.y4=0. else if(s==101) y=i5. endmodule 6. assign y=~(a | b). end else if(s==01) begin y1=0.y2.y3.y4. else if(s==100) y=i4. NOR GATE module nor_gt(a. y).y3. output y1.y2=1. assign y=~(a & b). input i. output y. y1.y4. end else if(s==10) . else if(s==111) y=i7. else if(s==110) y=i6.y4=0. y). output y.y2. always@(*) begin if(s==00) begin y1=1.b. end endmodule 5. input a.y=i2.y3=0. D MUX 1:4 module demux4(i.b. reg y1.y2.b.y2=0. endmodule 7. else if(s==011) y=i3.

y2=0. input [2:0]s. else if (s==011) y=i(3). output [3:0]y. else if (s==001) y=i(1).y4=1. else if (s==01) y=0010. input i. MUX 1:8 module mux8(i. else if (s==10) y=0100.y3=1. reg y.s. input [7:0]i.s. end end endmodule 8.y3=0. end else if(s==11) begin y1=0.y4=0. else if (s==11) y=1000. DMUX 1:4 module dmux4(i.begin y1=0. endmodule 9. always@(*) begin if(s==000) y=i(0). . y).y2=0. else if (s==010) y=i(2). input [1:0]s. output y. always@(*) if (s==00) y=0001.y). reg y.

p. reg p.b. always@(*) begin assign s=(~d).d. assign r=((a&b)|(~(c^d))).s.q.s.q. BINARAY TO EXCESS 3 module binecxess3(a. if(c^b==1) r=1.b.r.d.q.d. if(a^b==1) q=1.b. else r=0. else if (s==111) y=i(7). always@(*) begin p=a. output p. input a.c.r. output p.q.r.r.d.s.s). reg p. input a. else if (s==101) y=i(5).c. assign p=(a|(b&d)|(b&c)). else if (s==110) y=i(6).r.s.else if (s==100) y=i(4).s).c.b.q. p. end endmodule 11. . end endmodule 10. else q=0.c. BINARY TO GRAY module bingray(a.q. assign q=((b&(~c)&(~d))|(a&d)|(a&c)|((~b)&d)|((~b)&c)).r.

endcase end endmodule 13. input [7:0]i. 3'b 110:y=8'b 10111111. input e. end endmodule 12.if(c^d==1) s=1. 3'b 100:y=8'b 11101111. MUX 8:1 module mux8(i. always @(*) begin case (s) 2'b 000:y=i(0). else s=0.s). input [2:0]i. 3'b 111:y=8'b 01111111. 3'b 010:y=8'b 11111011. y. 3'b 011:y=8'b 11110111. always@(*) begin if(e==1) y= 8'b 11111111. reg [7:0]y. output y. input [2:0]s. reg y. 3'b 101:y=8'b 11011111. y. 2'b 001:y=i(1). DECODER 3:8 module decoder(i. 3'b 001:y=8'b 11111101. else case(i) 3'b 000:y=8'b 11111110. output [7:0]y.e). .

endcase end endmodule 14.D.u. u=(A|(B&(~C))|(B&(~D))|((~C)&(~D))).r.s. output p.u.q. always@(*) begin p=(A|C|(~(B^D))). input A.s. 2'b 100:y=i(4). v=(A|(C&(~D))|(B^C)).D.r.r. 2'b 110:y=i(6).v.u.t.t.2'b 010:y=i(2).C. r=(B|D|(~C)). 2'b 011:y=i(3).q.B.q. t=(((~B)&(~D))|(C&(~D))). s=(A|((~B)&(~D))|((~B)&C)|(B&D&(~C))|(C&(~A)&(~D))).v). end endmodule . p. 2'b 101:y=i(5).C. q=((~B)|(~(C^D))).s.v.t. reg p. 2'b 111:y=i(7).B. 7 SEGMENT module segment7(A.

clk. qb<=1. output q. end else if( t==1 & clk==1) begin q<=1.d.rst. qb<=q. end else if ( t==1 & clk==0) begin q<=0. qb<=’1’. qb<=0. reg q. end else if (d) begin q<=!q. input t.qb.q.qb). always @ (posedge clk) begin if ( rst==1) begin q<=0.d.rst.qb. DFF module ( clk.q.15.qb).clk.qb. qb<=’1’. output q. input clk.rst. end endmodule . end end end endmodule 16. always @ (posedge clk) if (~ rst) begin q<=0.rst. T FLIPFLOP module tff(t.

always @ (posedge clk. output [3:0] so. LINEAR FEED-BACK SHIFT REGISTER module lfs (clk. output [3:0]q. input clk. wire w. reg [7:0] q. SISO module sisor(clk.q). end else begin q<=q-1.17. output [7:0].si. UP/DOWN COUNTER module updn ( clk.count. always @ (posedge clk) begin if(rst) begin q<=0. end else if (count) begin q<=q+1.si. input clk. reg [3:0]q.so). negedge rst) if(rst==0) q<=8’b1. always @ (posedge clk) begin so={si.so[3:1]}.count.rst. reg so. else .rst.rst.rst. assign w=!(q[7] ^ q[3]).q). end end endmodule 18. end endmodule 19. input clk.

always @ (posedge clk. reg [7:0]q. output [7:0] q. else q<={ q [6 :0]. input clk. endmodule 20.q).rst.q<={q[6:0].rst. RING COUNTER module ringc(clk. endmodule .w}. wire w. negedge rst) if(rst==0) q<=8’b1. assign w=q[7].w}.