1.

Introduction This paper is mainly about the yield of Microfabrication, we analysis it with two aspects: one is the wafer yield, and the other is chip yield (also known as die yield). Understanding yield loss is a very important issue in wafer fabrication, since high level of yield is a key factor which can significantly affect the profits of IC manufacturers. Yield loss is inevitable, and it is important to know the factors behind it. The complexity of this manufacturing process, the non-repairable defects on the wafer and the pressure of competition in the market all lead to high requirement of yield rate. 2. Major Yield Measurement The first reason that we pay so much attention to the yield rate is because the complexity of semiconductor manufacturing processes and the production of a complete package need to experience a huge complex process. During this process, any contamination from the clean room, such as dust or other debris, or Imperfections and impurities in the silicon can cause loss of yield. The second factor which keeps yields depressed is that the defects appear on wafers or chips are mostly non-repairable. In some cases, if the chips fail to meet the requirements, they can be downgrade to low-end applications. Added to these process factors is the volume nature of the business. High capital costs and high professional quality needed. This high overhead, coupled with competition that keeps downward pressure on selling prices, requires that most chip producers run a high-volume, high-yield process. Given all of these factors, the preoccupation with yield is understandable. Most suppliers of equipment and materials tout the yield improvements possible with their products. Likewise, process engineering groups have as their prime responsibility the maintenance and improvement of process yields. Yield measurement starts at the individual process level and is tracked through the entire process sequence, from incoming blank wafer to shipment of the completed circuit. There are total three measurement points we need to consider: wafer fabrication yield, wafer sort yield and packaging yield. And they can be calculated by the following equations: = Number =
Number of Wafers Out of Wafers Started

(Eq. 2-1)

Number of Functioning Die Number of Die on Wafer s

(Eq. 2-2)

= Number

Number of Packages Die Passing Final Test of Good Die Started into Packaging

(Eq. 2-3)

3. Wafer fabrication yield and its limiters Wafer fabrication yield appears at the end of wafer fabrication. It also has many other names, such as (accumulative) fabrication yield, line yield. Wafer fabrication yield can be expressed as a percentage of the wafers leaving the wafer fabrication divided by the number that entered the process. Since different product types have different components, feature sizes, and density factors, the wafer fabrication yield is calculated by product type rather than the entire fabrication line yield. Wafer fabrication yield starts by first calculating the number of wafers that leave each of the individual processes (called station yields) and dividing by the number that entered the station. The equation is as follows: = Number
Number of Wafers Leaving Station of Waf ers Entering Station

(Eq. 2-4)

The station yields are in turn multiplied together to calculate the overall wafer fabrication yield. Wafer Fabrication Yield=Y(station 1)Y(station 2)Y(Station N) (Eq. 2-5) For a single product, the wafer fabrication yield calculated from the station yields is the same as the yield calculated by dividing the number of wafers out by the number of wafers in. The accumulated yield equals the simple wafer fabrication yield calculation for this individual circuit. A modern integrated circuit will require 300 to 500 individual process steps, which represents a huge challenge to maintain profitable productivity. Successful wafer fabrication operations must achieve accumulative fabrication yields over 90 percent to stay profitable and competitive. Wafer fabrication yield limiters: 1) Number of process steps: We can get a yield rate at each process step, along with the demands of more complicated integrated circuits; the process steps will become more and more. Into 2012, the total number of major steps will reach 600. Each operation requires several steps, and each of which will include many substeps. The more complicated the circuit, with a high number of steps, the lower the expected yield. 2) Wafer break and warping During the fabrication process, the wafers are handled many times by a combination of manual and automatic machines. Each handling will bring an opportunity to break the fragile wafers. We know that a typical 300-mm diameter wafer is only about 800 m thick. So that careful wafer handling is required, and automatic handlers must be maintained to minimize breakage.

At the process of heat treatment, susceptibility of the wafers will be added to breaking. Strains are induced in crystalline materials that make them vulnerable to breaking in subsequent steps. Therefore, any breakage, no matter how small it is, will cause for rejecting the wafer from the process. 3) Process variation There are many different processes during the fabrication, such as doping, layering, and patterning. Each of them must meet incredibly stringent physical and cleanliness requirements. But even the most sophisticated processes vary from wafer-to-wafer, lot-to-lot, and day-to-day. When a process exceeds its process limits, it will cause some unwanted result on the wafer or within the chips on the wafer. The goal of process engineering is not only to keep each process operating within its control specifications but also to maintain a constant distribution of the process parameters, such as time, temperature, pressure, etc. Throughout the process, there are a number of inspections and tests designed to detect unwanted variations as well as frequent calibration of the equipment parameters to process specifications. Some of these tests are performed by production personnel and some by quality control organizations. However, even the best maintained and monitored process exhibits some variations. One of the challenges of process engineering and circuit design is to accommodate the variations and still have a functioning device. 4) Process defects Process defects are defined as isolated regions of contamination or irregularities on the wafer surface. We know that there are four total kinds of defects appear on a wafer, point defects, line defects, area defects, and volume defects. They occur randomly on the wafer surface. Some are non-fatal, and some will cause miss-function of circuits. The major sources of these defects are the various liquids, gases, room air, operators, process machines, and water used in the fabrication area. Many of these defects occur in the patterning process. We use photoresist to produce patterns, and any holes or tears in the photoresist layer from particulates will end up as tiny etched holes in the wafer surface layer. These holes are called pinholes and are a major concern of photomasking engineers. Consequently, the wafers are inspected often for contamination, usually after each major step for contamination. Wafers that exceed the established allowable density are rejected. 5) Mask defects As we mentioned above, the most possible defects appear in the process of patterning. In this process, we need photomask, and defects on the mask end up on the wafer as defects or pattern distortions. There are three common mask originated defects. First is contamination, such as dirt or stains on the clear part of the mask. In optical lithography, they can block the light and print onto the wafer as though they were an opaque part of

the pattern. Second are cracks in the quartz. They can block the patterning light and scatter the light too, causing unwanted images and distorted images. Third are pattern distortions that occur in the mask making process. These include pinholes or chrome spots, pattern extensions or missing parts, breaks in the pattern, or bridges between adjacent patterns.

4. Wafer sort yield and its limiters Wafers need to be tested after they are produced. During the test, each chip will be tested electrically for device specifications and functionality. Up to several hundred individual electrical tests may be performed on each circuit. While these tests measure the electrical performance of the devices, they indirectly measure the precision and cleanliness of the fabrication processes. Because of natural process variations and undetected defects, the wafer may have passed all the in-process checks and still have many chips that do not function. Wafer sort yield limiters: 1) Wafer diameter and edge die Nowadays, IC industry pursues larger diameter wafers, although producing larger diameter wafer will cost a lot, its benefits are apparent. Since the percentage of whole dies will increase and the percentage of edge dies or partial dies will decrease. So that larger diameter wafer can improve the wafer sort yield. 2) Die size Also, the die size is becoming larger recently, if the wafer diameter keeps the same, then the percentage of whole dies will decrease. To maintain or improve the wafer sort yield, we must increase the wafer diameter to suit the requirement of larger size of die. 3) Crystal defects, and defect density with die size and circuit density There are four main defects of crystal: point defects, line defects, area defects and volume defects. Point defects are the simplest to visualize and they play crucial roles in many aspects during fabrication process. One-dimensional defects in crystals are known as dislocations. The dislocation is a linear defect. Dislocations are active defects in crystals, that is they can move when subjected to stresses or when excess point defects are present. Also sacking faults and precipitate are common defects. The die size also affects wafer sort yield relative to the defect density on the wafer surface. The larger die size for a given defect density, the lower the yield. Due to the smaller feature size and higher density of die components, we pursue higher levels of circuit integration nowadays. The result of these trends is a higher probability that any given defect will be in an active part of the circuit, thus lowering the wafer sort yield.

4) Feature size and defect size Since the feature size is keeping shrinking, it is hard to maintain the wafer sort yield from two major factors. Firstly, its more difficult to print smaller images. Second, the smaller images are vulnerable to ever-smaller defect sizes as well as the overall defect density.

Other limiters include longer processing time and more process steps, etc. They are all factors limit the wafer sort yield.