21 views

Uploaded by Nguyen Bich Ngoc

- One Digits
- Logic-Design-part-2
- Physics Project on Logic Gates LOKESH
- cadence_tut1
- DataSheet_2803.pdf
- Life by Hoober
- vlsi_design_tutorial.pdf
- Switched Capacitor Power Amplifiers
- VLSI Technology and Design
- L6234 Three-phase motor driver
- 5614vlsi06
- Class 1
- L9
- [EE476] [lab 1] 09ece_group8
- Exclusive or Gate PDF
- 01009881
- Vlsi Design [Eee].Textmark (1)
- Data Sheet
- 74HC04.REV1
- ADP

You are on page 1of 18

10.1 Digital Circuit Design: An Overview 10. 2 Design and Performance Analysis of the CMOS Inverter 10.3 10 3 CMOS Logic-Gate Circuits Logic Gate 10.4 Pseudo-NMOS Logic Circuits 10.5 Pass Transistor Logic Circuits Pass-Transistor 10.6 Dynamic Logic Circuits

10.3.1 Basic Structure 10 3 1 B i S 10.3.2 The Two-Input NOR Gate 10.3.3 10 3 3 The Two-Input NAND Gate Two Input 10.3.4 A Complex Gate 10.3.5 Obtaining the PUN from the PDN and Vice Versa 10.3.6 The Exclusive-OR Function 10.3.7 Summary of the Synthesis Method 10.3.8 Transistor Si i 10 3 8 T i t Sizing

Basic structure of CMOS logic gate An extension of the CMOS inverter Two network - PUN : constructed of PMOS - PDN : constructed of NMOS PUN and PDN in the complementary fashion

Figure 10.8 Representation of a three-input CMOS logic gate. The PUN comprises PMOS t i transistors, and th PDN comprises NMOS t it d the i transistors. it

Implementation of Pull-Down Network (PDN )

Series

NMOS Y = f ( A, B, C )

ASIC Design Lab. http://asic.korea.ac.kr

OR AND

Parallel Se es Series

5

Implementation of Pull-Up Network (PUN )

PMOS Y = f ( A, B, C )

ASIC Design Lab. http://asic.korea.ac.kr

OR AND

Parallel Se es Series

6

A two-input CMOS NOR gate A two-input CMOS NAND gate PUN

Y = A +B

PUN

Y = A+ B = A B

Series AND Series Parallel

OR

Parallel

Parallel

PDN

Series

PDN

Y = AB

Y = A+ B OR Parallel

AND

Series

ASIC Design Lab. http://asic.korea.ac.kr

7

The implementation of output Y

Y = A( B + CD) = A + B + CD = A + BCD = A + B (C + D)

A + B = A B A B = A + B

(10.24)

10.3.5 Obtaining the PUN from the PDN and Vice Versa

The PDN and the PUN are dual networks For instance Fig. 10.14 PDN : easy to obtain

Boolean expression

Y = f ( A, B, C ) : PDN Y = f ( A, B, C ) : PUN Y = A( B + CD)

Y = A( B + CD)

CD

Series

Figure 10.14 CMOS realization of a complex gate. Fi 10 14 li i f l

The implementation of output Y

Y = AB + AB

(10.25)

Figure 10.15 (a) The PUN synthesized directly from the expression in Eq. (10.25).

10

The implementation of output Y

Y = AB + AB

(10.26)

Figure 10.15 (b) The complete XOR realization utilizing the PUN in (a) and g ( ) p g ( ) a PDN that is synthesized directly from the expression in Eq. (10.26).

11

OR AND Parallel Series

PMOS Y = f ( A, B, C )

NMOS Y = f ( A, B, C )

Parallel Series S i

12

Decide on W/L ratios for all devices Current-driving capability in both directions = that of the basic inverter Guarantee a worst-case delay equal to that of the basic inverter

=

ASIC Design Lab. http://asic.korea.ac.kr 13

Definition of the worst-case Find the input combinations that result in the lowest output current. Choose sizes that will make it equal to that of the basic inverter.

=

W/L = n W/L = n W/L = n PDN : Only one of the NMOS is conducting g

ASIC Design Lab. http://asic.korea.ac.kr 14

Determine W/L ratio

1 Based on the resistance of a MOSFET Ron W /L

Series

Rseries = rDS 1 + rDS 2 +

=

Parallel

1 R parallel = = 1 rDS1 + 1 rDS 2 +

(W / L)eq =

1 1 1 + + (W / L)1 (W / L) 2

(10.27)

(10.28)

15

Example 4 series

(W / L ) eq =

1 1 1 1 1 + + + 4p 4p 4p 4p

= p

(W/L) = p

=

(W/L) = n

Figure 10.16 Proper transistor sizing for a 10 16 four-input NOR gate. Figure 10.17 Proper transistor sizing for a four10 17 four input NAND gate.

16

Example 10.2

Provide transistor W/L ratio. ( Assume n=1.5, p=5, and L=0.25um) Consider the PDN first Find the Fi d th worst case t : when QNB is on and either QNC or QND on Two transistors in series

PDN 2n QNC : W/L= 2n = 3 = 0.75 / 0.25 QND : W/L 2 = 3 = 0 75 / 0 25 W/L= 2n 0.75 0.25 n 2n 2n QNA : W/L n = 1.5 = 0.375 / 0.25 W/L=

17

Example 10.2

PUN 3p Provide transistor W/L ratio. ( Assume n=1.5, p=5, and L=0.25um) Consider the PUN 1.5p 3p 3p The worst case : when QPA, QPC, QPD are on Three t Th transistors in series i t i i QPA : W/L= 3p = 15 = 3.75 / 0.25 QPC : W/L= 3p = 15 = 3.75 / 0.25 3 75 0 25 QPD : W/L= 3p = 15 = 3.75 / 0.25 QPB : W/L= 1.5p = 7.5 = 1.875 / 0.25

18

- One DigitsUploaded byKamal Bhakta
- Logic-Design-part-2Uploaded byPraveen Kumar
- Physics Project on Logic Gates LOKESHUploaded byLokesh Jaiswal
- cadence_tut1Uploaded byBruno Silva
- DataSheet_2803.pdfUploaded byaksj1186
- Life by HooberUploaded bybillybob123211
- vlsi_design_tutorial.pdfUploaded byManoj Venkat EMMIDISETTY
- Switched Capacitor Power AmplifiersUploaded byElectrical and Computer Engineering (ECE) at the University of Utah
- VLSI Technology and DesignUploaded bySachin Joshi
- L6234 Three-phase motor driverUploaded byHugonovich
- 5614vlsi06Uploaded byAnonymous e4UpOQEP
- Class 1Uploaded byJacky Bauery
- L9Uploaded byVô Hình
- [EE476] [lab 1] 09ece_group8Uploaded byTrung Lyam
- Exclusive or Gate PDFUploaded byVasu
- 01009881Uploaded bySathish Kumar
- Vlsi Design [Eee].Textmark (1)Uploaded bySheikh Noor Mohammad
- Data SheetUploaded byNguyen Huy Hoang
- 74HC04.REV1Uploaded byPUMASNY
- ADPUploaded bySiva Krishna
- A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique - 2015Uploaded bymtechprojects
- sample and hold.pptxUploaded bySohom Das
- THRESHOLD LOGIC (Air force Institute of Technology).pdfUploaded byojkitar
- 04397309Uploaded bysuchi87
- UntitledUploaded bylugthesavage
- Aptitude TypesUploaded byJohn Walker
- ch4iUploaded bythientuong2710
- ENGR 262 Digital Logic DesignHomework 3Uploaded byJenniferBall12
- VLSIUploaded bySam Davids
- 74HC138_74HC138S16-13_74HC138T16-13Uploaded byDistribuidorIBoolPedregalDeSantoDomingo

- Pentium E2140.pdfUploaded byMelody Cotton
- Microsoft PowerPoint - EmbeddedSystem [Compatibility Mode]Uploaded byNitesh Ch
- Socket G2 _ Socket RPGA988BUploaded byfuckyouscrbd
- Microprocessor NotesUploaded byMerin Jesuraj
- test1sUploaded bysaimanobhiram
- Instruction Set(8051)Uploaded byBhaswar Majumder
- Pipelined Processor iitkUploaded byanvinder
- MELG642hout 2 Sem 2012Uploaded byNeha Pachauri
- Processor HistoryUploaded byAman Kumar
- IEC20091118133046Uploaded bySEANM
- Microcontroller and InterfacingUploaded byAdil Ayub
- L2Uploaded byPrince Dhiman
- Instruction SetUploaded byTarun Gandhi
- Ee660 2017 Spring Materials Week 04 AssgUploaded byqaesz
- Mpmc New Manual Version 1Uploaded byBRAHMA REDDY AAKUMAIIA
- MOTHERBOARDS-SOYOUploaded byALOPECIA12
- BXXXXX EPROM Corss Reference for Car ECUUploaded byMariano Viera
- Comparison of Intel Graphics Processing Units - Wikipedia, The Free EncyclopediaUploaded by8336121
- Assembly LanguageUploaded byhippong niswantoro
- PIC Part2 ArchitectureUploaded byserjani
- Part 01Uploaded byMd Aabish
- Lecture 06_2011_12_16 Pipelining_129689311127786250Uploaded bykatsumotho
- assigment3Uploaded bymanhag
- CO SyllabusUploaded byAswathy Madhu
- SEMISECTION.pdfUploaded byeuqehtb
- czoneUploaded byRyan Tan
- Microprocessor Lesson PlanUploaded byKavitha Subramaniam
- The Sparc ArchitectureUploaded byAshwini Patil
- Program 1Uploaded bywork8
- CoprocessorsUploaded byyugii100