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Digital CMOS Logic Circuits

Chapter 10 Digital CMOS Logic Circuits


10.1 Digital Circuit Design: An Overview 10. 2 Design and Performance Analysis of the CMOS Inverter 10.3 10 3 CMOS Logic-Gate Circuits Logic Gate 10.4 Pseudo-NMOS Logic Circuits 10.5 Pass Transistor Logic Circuits Pass-Transistor 10.6 Dynamic Logic Circuits

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10.3 10 3 CMOS Logic-Gate Circuit Logic Gate


10.3.1 Basic Structure 10 3 1 B i S 10.3.2 The Two-Input NOR Gate 10.3.3 10 3 3 The Two-Input NAND Gate Two Input 10.3.4 A Complex Gate 10.3.5 Obtaining the PUN from the PDN and Vice Versa 10.3.6 The Exclusive-OR Function 10.3.7 Summary of the Synthesis Method 10.3.8 Transistor Si i 10 3 8 T i t Sizing

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10.3.1 Basic Structure


Basic structure of CMOS logic gate An extension of the CMOS inverter Two network - PUN : constructed of PMOS - PDN : constructed of NMOS PUN and PDN in the complementary fashion

No dc path between VDD and ground.

Figure 10.8 Representation of a three-input CMOS logic gate. The PUN comprises PMOS t i transistors, and th PDN comprises NMOS t it d the i transistors. it

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10.3.1 Basic Structure


Implementation of Pull-Down Network (PDN )

Series Parallel Parallel

Series

Figure 10.9 Examples of pull-down networks.

Pull Down Network ( PDN )

NMOS Y = f ( A, B, C )
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OR AND

Parallel Se es Series
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10.3.1 Basic Structure


Implementation of Pull-Up Network (PUN )

Series Parallel Series Parallel

Figure 10.10 Examples of pull-up networks.

Pull-Up Network (PUN )

PMOS Y = f ( A, B, C )
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OR AND

Parallel Se es Series
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10.3.2~3 The Two-input CMOS NOR & NAND Gate


A two-input CMOS NOR gate A two-input CMOS NAND gate PUN
Y = A +B

PUN

Y = A+ B = A B
Series AND Series Parallel

OR

Parallel

Parallel

PDN

Series

PDN
Y = AB

Y = A+ B OR Parallel

AND

Series

Figure 10.12 A two-input CMOS NOR gate.

Figure 10.13 A two-input CMOS NAND gate.

(10.21) Y = A + B = A B (10 21)


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(10.22) Y = AB = A + B (10 22)


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10.3.4 A Complex Gate


The implementation of output Y
Y = A( B + CD) = A + B + CD = A + BCD = A + B (C + D)

(10.23) DeMorgans th D M theorems


A + B = A B A B = A + B

(10.24)

Figure 10.14 CMOS realization of a complex gate.

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10.3.5 Obtaining the PUN from the PDN and Vice Versa
The PDN and the PUN are dual networks For instance Fig. 10.14 PDN : easy to obtain

Boolean expression
Y = f ( A, B, C ) : PDN Y = f ( A, B, C ) : PUN Y = A( B + CD)

Duality property Series Parallel Parallel Series

Y = A( B + CD)

Series ( B + CD) Parallel P ll l

Parallel Series Parallel

CD
Series
Figure 10.14 CMOS realization of a complex gate. Fi 10 14 li i f l

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10.3.6 The Exclusive-OR Function


The implementation of output Y
Y = AB + AB

(10.25)

Easy to synthesize the PUN

Y is not a function of the complemented variables only.

Need additional inverters Additional inverter

Figure 10.15 (a) The PUN synthesized directly from the expression in Eq. (10.25).

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10.3.6 The Exclusive-OR Function


The implementation of output Y

Y = AB + AB

(10.26)

The PDN and the PUN are not dual networks.

Duality of the PDN and the PUN is not a necessary condition.

Figure 10.15 (b) The complete XOR realization utilizing the PUN in (a) and g ( ) p g ( ) a PDN that is synthesized directly from the expression in Eq. (10.26).

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10.3.7 Summary of the Synthesis Method


OR AND Parallel Series
PMOS Y = f ( A, B, C )

Duality property Series Parallel P ll l


NMOS Y = f ( A, B, C )

Parallel Series S i

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10.3.8 Transistor Sizing


Decide on W/L ratios for all devices Current-driving capability in both directions = that of the basic inverter Guarantee a worst-case delay equal to that of the basic inverter

=
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10.3.8 Transistor Sizing


Definition of the worst-case Find the input combinations that result in the lowest output current. Choose sizes that will make it equal to that of the basic inverter.

=
W/L = n W/L = n W/L = n PDN : Only one of the NMOS is conducting g
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10.3.8 Transistor Sizing


Determine W/L ratio
1 Based on the resistance of a MOSFET Ron W /L

Series
Rseries = rDS 1 + rDS 2 +
=

Parallel
1 R parallel = = 1 rDS1 + 1 rDS 2 +

constant constant + + (W / L)1 (W / L) 2

1 1 = constant + + (W / L)1 (W / L) 2 constant = (W / L)eq

(W / L)1 (W / L) 2 + + constant constant 1 = [(W / L)1 + (W / L)2 + ] constant 1 = (W / L)eq constant t t

(W / L)eq =

1 1 1 + + (W / L)1 (W / L) 2
(10.27)

(W / L)eq = (W / L)1 + (W / L)2 +

(10.28)

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10.3.8 Transistor Sizing


Example 4 series

(W / L ) eq =

1 1 1 1 1 + + + 4p 4p 4p 4p

= p

(W/L) = p

=
(W/L) = n
Figure 10.16 Proper transistor sizing for a 10 16 four-input NOR gate. Figure 10.17 Proper transistor sizing for a four10 17 four input NAND gate.

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Example 10.2
Provide transistor W/L ratio. ( Assume n=1.5, p=5, and L=0.25um) Consider the PDN first Find the Fi d th worst case t : when QNB is on and either QNC or QND on Two transistors in series

QNB : W/L= 2n = 3 = 0.75 / 0.25


PDN 2n QNC : W/L= 2n = 3 = 0.75 / 0.25 QND : W/L 2 = 3 = 0 75 / 0 25 W/L= 2n 0.75 0.25 n 2n 2n QNA : W/L n = 1.5 = 0.375 / 0.25 W/L=

Figure 10.18 Circuit for Example 10.2.

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Example 10.2
PUN 3p Provide transistor W/L ratio. ( Assume n=1.5, p=5, and L=0.25um) Consider the PUN 1.5p 3p 3p The worst case : when QPA, QPC, QPD are on Three t Th transistors in series i t i i QPA : W/L= 3p = 15 = 3.75 / 0.25 QPC : W/L= 3p = 15 = 3.75 / 0.25 3 75 0 25 QPD : W/L= 3p = 15 = 3.75 / 0.25 QPB : W/L= 1.5p = 7.5 = 1.875 / 0.25

Figure 10.18 Circuit for Example 10.2.

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