802-1947 | Assembly Language | Command Line Interface

SPARC Assembly Language Reference Manual

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© 1995 Sun Microsystems, Inc. 2550 Garcia Avenue, Mountain View, California 94043-1100 U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® system, licensed from UNIX Systems Laboratories, Inc., a wholly owned subsidiary of Novell, Inc., and from the Berkeley 4.3 BSD system, licensed from the University of California. Third-party software, including font technology in this product, is protected by copyright and licensed from Sun’s Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, SunSoft, the SunSoft logo, Solaris, SunOS, OpenWindows, DeskSet, ONC, ONC+, and NFS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. OPEN LOOK is a registered trademark of Novell, Inc. PostScript and Display PostScript are trademarks of Adobe Systems, Inc.All SPARC trademarks are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. SPARCcenter, SPARCcluster, SPARCompiler, SPARCdesign, SPARC811, SPARCengine, SPARCprinter, SPARCserver, SPARCstation, SPARCstorage, SPARCworks, microSPARC, microSPARC-II, and UltraSPARCare licensed exclusively to Sun Microsystems, Inc. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. The OPEN LOOK® and Sun™ Graphical User Interfaces were developed by Sun Microsystems, Inc. for its users and licensees. Sun acknowledges the pioneering efforts of Xerox in researching and developing the concept of visual or graphical user interfaces for the computer industry. Sun holds a non-exclusive license from Xerox to the Xerox Graphical User Interface, which license also covers Sun’s licensees who implement OPEN LOOK GUI’s and otherwise comply with Sun’s written license agreements. X Window System is a trademark of X Consortium, Inc. THIS PUBLICATION IS PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. THIS PUBLICATION COULD INCLUDE TECHNICAL INACCURACIES OR TYPOGRAPHICAL ERRORS. CHANGES ARE PERIODICALLY ADDED TO THE INFORMATION HEREIN, THESE CHANGES WILL BE INCORPORATED IN NEW EDITIONS OF THE PUBLICATION. SUN MICROSYSTEMS, INC. MAY MAKE IMPROVEMENTS AND/OR CHANGES IN THE PRODUCT(S) AND/OR THE PROGRAMS(S) DESCRIBED IN THIS PUBLICATION AT ANY TIME.

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Contents
Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Before You Read This Book. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How This Book is Organized . . . . . . . . . . . . . . . . . . . . . . . . . . . . What Typographic Changes Mean. . . . . . . . . . . . . . . . . . . . . . . . Shell Prompts in Command Examples . . . . . . . . . . . . . . . . . . . . 1. SPARC Assembler for SunOS 5.x. . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC Assembler for SunOS 4.1 Versus SunOS 5.x . . . . . . . . . Labeling Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Object File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pseudo-Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Assembler Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Syntax Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi xii xii xiii xiv 1 1 1 2 2 2 2 2 3 3

iii

Assembler File Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lines Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Statement Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lexical Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case Distinction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Symbol Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Symbols - Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Operators and Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembler Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. Executable and Linking Format . . . . . . . . . . . . . . . . . . . . . . . . . ELF Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Predefined User Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . Predefined Non-User Sections . . . . . . . . . . . . . . . . . . . . . . . . Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relocation Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Symbol Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . String Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 4 4 4 4 5 5 5 6 6 7 9 10 11 12 14 15 19 20 21 22 22 22 24

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Assembler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section Control Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . Symbol Attribute Directives . . . . . . . . . . . . . . . . . . . . . . . . . . Assignment Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Generating Directives . . . . . . . . . . . . . . . . . . . . . . . . . . 4. Converting Files to the New Format . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. Instruction-Set Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Floating-Point Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A. Pseudo-Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alphabetized Listing with Descriptions . . . . . . . . . . . . . . . . . . . B. Examples of Pseudo-Operations. . . . . . . . . . . . . . . . . . . . . . . . . C. Using the Assembler Command Line . . . . . . . . . . . . . . . . . . . . Assembler Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembler Command Line Options . . . . . . . . . . . . . . . . . . . . . . Disassembling Object Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D. An Example Language Program . . . . . . . . . . . . . . . . . . . . . . . . . E. SPARC-V9 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24 25 25 25 25 27 27 27 28 29 30 31 39 40 41 45 45 55 59 59 60 63 65 71

Contents

v

SPARC-V9 Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Space Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC-V9 Instruction Set Changes . . . . . . . . . . . . . . . . . . . . . . .

71 72 73 73 74

Extended Instruction Definitions to Support the 64-bit Model 74 Added Instructions to Support 64 bits . . . . . . . . . . . . . . . . . ementation Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deleted Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Instruction Changes . . . . . . . . . . . . . . . . . . . . SPARC-V9 Instruction Set Mapping . . . . . . . . . . . . . . . . . . . . . . SPARC-V9 Floating-Point Instruction Set Mapping . . . . . . . . . SPARC-V9 Synthetic Instruction-Set Mapping. . . . . . . . . . . . . . SPARC-V9 Instruction Set Extensions . . . . . . . . . . . . . . . . . . . . . Graphics Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eight-bit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fixed Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SHUTDOWN Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graphics Status Register (GSR) . . . . . . . . . . . . . . . . . . . . . . . Graphics Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Access Instructions . . . . . . . . . . . . . . . . . . . . . . . . . Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 75 76 76 77 85 87 89 89 89 89 90 90 90 96 99

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. . . Predefined Non-User Sections. . . . . . . . . . . . Predefined User Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Symbol Types . . . . . . . . . . . . . . . . Floating-Point Instructions. . . . . . . . Commonly Suffixed Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Notations Used to Describe Instruction Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operators Recognized in Constant Expressions . . SPARC to Assembly Language Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Symbol Names . . . . . . . . Synthetic Instruction to Hardware Instruction Mapping . . . . . Reserved Object File Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section Attribute Flags . . . . . 6 7 9 14 16 17 19 20 23 24 30 31 32 39 41 41 vii . . . . . . . . . . Symbol Bindings . Coprocessor-Operate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section Types . . . . .Tables Table 2-1 Table 2-2 Table 2-3 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Escape Codes Recognized in Strings . . . . . . . . . . . . . . . . . . . .

. . . . . . . Extended Instruction Definitions for 64-bit Model. . . . . . . . .Table E-1 Table E-2 Table E-3 Table E-4 Table E-5 Table E-6 Table E-7 Table E-8 Table E-9 Table E-10 Table E-11 Table E-12 Table E-13 Table E-14 Table E-15 Table E-16 Table E-17 Table E-18 Table E-19 Table E-20 Table E-21 Table E-22 Table E-23 Table E-24 Table E-25 Deleted SPARC-V8 Privileged Registers . . . . . SPARC-V9 Partitioned Add/Subtract . . . . . . . . . . . . . . . . . . . . . SPARC-V9 Pixel Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers That have Been Added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC-V9 Alignment Instructions . . . . . . . . . . SPARC-V9 Registers Within a SPARC-V8 Register Field . . . SPARC-V9 Short Floating-Point Load and Store . . . . . . . . . . . . SPARC V-9 Three-Dimensional Array Addressing. . . . . . . . . . . . . . . . Added Instructions to Support 64 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC V-9 Edge Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC-V9 Floating-Point Instructions . . . . . . . . . . . SPARC-V9 to Assembly Language Mapping . . . . . . . . . . . . . . SPARC-V9 Pixel Formatting . . . . . . . . Graphics Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC-V9 Synthetic Instructions to Hardware Instruction . . . . . . . . . . . . . . . . . SPARC-V9 Atomic Quad Load. . . . . . . . . . . . SPARC-V9 SHUTDOWN Instruction . . . . . . . . . . . . . . SPARC-V9 Partial Store . . . . . . . SPARC-V9 Logical Operate Instructions . . . . . . . . . . . Miscellaneous Instruction Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 72 72 72 74 75 75 76 76 77 85 87 90 90 91 91 91 92 93 94 94 95 96 97 97 viii SPARC Assembly Language Reference Manual—November 1995 . . . . . . Added Instructions to Support High-Performance . . . Registers Widened from 32 to 64 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deleted Instructions . . . . SPARC-V9 Partitioned Multiply . . . . . . . . . . . .

98 Tables ix . . . . . . . . . . . . . . . . . .Table E-26 SPARC-V9 Block Load and Store . . . . . . .

x SPARC Assembly Language Reference Manual—November 1995 .

x macro preprocessors to achieve full macro-assembler capability. xi . Whether assembly language is chosen for the development of program modules depends on the extent to which and the ease with which the language allows the programmer to control the architectural features of the processor. The assembly language described in this manual offers full direct access to the SPARC instruction set. translates source files that are in assembly language format into object files in linking format. the assembler is a tool to use in producing program modules intended to exploit features of the SPARC architecture in ways that cannot be easily done using high level languages and their compilers. The SunOS assembler that runs on the SPARC operating environment.Preface This preface provides a brief description of the SunOS™ assembler that runs on the SPARC® operating environment and also includes a list of documents that can be used for reference. the assembler responds to directives that allow the programmer direct control over the contents of the relocatable object file. Furthermore. The assembler may also be used in connection with SunOS 5. referred to as the “SunOS SPARC” in this manual. In the program development process.

” describes the relocatable ELF files that hold code and data suitable for linking with other object files.x assembly file format.This document describes the language in which the source files must be written. cpp(1). “SPARC Assembler for SunOS 5.1 SPARC assembly files to the SunOS 5. Chapter 4.” describes how to convert existing SunOS 4.” describes the relationship between hardware instructions of the SPARC architecture and the assembly language instruction set. The nature of the machine mnemonics governs the way in which the program’s executable portion is written. ld(1). This document includes descriptions of the pseudo operations that allow control over the object file.” lists the pseudo-operations supported by the SPARC assembler.” discusses features of the SunOS 5.out(1) SPARC Architecture Manual (Version 8 and Version 9) ELF-related sections of the Programming Utilities Guide manual SPARC Applications Binary Interface (ABI) How This Book is Organized This book is organized as follows: Chapter 1. a. “Assembler Syntax. xii SPARC Assembly Language Reference Manual—November 1995 .x. “Pseudo-Operations. Chapter 5. This facilitates the development of programs that are easy to understand and maintain. “Converting Files to the New Format. dis(1). Chapter 3. Chapter 2. Before You Read This Book You should also become familiar with the following: • • • • Manual pages: as(1). Appendix A.x SPARC Assembler.” describes the syntax of the SPARC assembler that takes assembly programs and produces relocatable object files for processing by the link editor. “Instruction-Set Mapping. “Executable and Linking Format. elf(3f).

“SPARC-V9 Instruction Set. You must be root to do this. Table P-1 Typeface or Symbol AaBbCc123 Typographic Conventions Meaning The names of commands. files. AaBbCc123 AaBbCc123 AaBbCc123 Read Chapter 6 in User’s Guide. Preface xiii . “An Example Language Program. and directories. machine_name% You have mail.” describes an example C language program with comments to show correspondence between the assembly code and the C code. new words or terms. Appendix E. or words to be emphasized Example Edit your .” shows some examples of ways to use various pseudo-operations. machine_name% su Password: To delete a file. “Examples of Pseudo-Operations. on-screen computer output What you type.” describes the SPARC-V9 instruction set and the changes due to the SPARC-V9 implementation.Appendix B.login file. These are called class options.” describes the available assembler command-line options. contrasted with on-screen computer output Command-line placeholder: replace with a real name or value Book titles. type rm filename. Appendix D. What Typographic Changes Mean The following table describes the typographic changes used in this book. Appendix C. Use ls -a to list all files. “Using the Assembler Command Line.

Shell Prompts in Command Examples The following table shows the default system prompt and superuser prompt for the C shell. Table P-2 Shell C shell prompt C shell superuser prompt Bourne shell and Korn shell prompt Bourne shell and Korn shell superuser prompt Shell Prompts Prompt machine_name% machine_name# $ # xiv SPARC Assembly Language Reference Manual—November 1995 . Bourne shell. and Korn shell.

Solaris 2. 1 .x operating environment.x Introduction 1 This chapter discusses features of the SunOS 5. This document is also distributed with the on-line documentation set for the convenience of SPARCworks™ and SPARCompiler™ 4.” Operating Environment The SunOS SPARC assembler runs under the SunOS 5.x operating system or the Solaris™ 2. which is the on-line information retrieval system. This document is distributed as part of the developer documentation set with every SunOS operating system release.SPARC Assembler for SunOS 5.x SPARC assembler.0 users who have products that run on the SunOS 5. Information about Version 9 support is summarized in Appendix E. SunOS 5.2 operating environment and later releases. It is included as part of the SPARCworks/SPARCompiler Floating Point and Common Tools AnswerBook. “SPARC-V9 Instruction Set.x refers to the Solaris 2.2 operating system and later releases. This document contains information from The SPARC Architecture Manual. Version 8.x operating system.x refers to SunOS 5.

” for a detailed description of the pseudo-operations (pseudo-ops).1 Versus SunOS 5.” for a detailed description of command line options and a list of SPARC architectures. “Pseudo-Operations. Labeling Format • Symbol names beginning with a dot (.1 SPARC assembler and the SunOS 5. “Using the Assembler Command Line. These relocatable object files hold code and data suitable for linking with other object files to create an executable file or a shared object file. 2 SPARC Assembly Language Reference Manual—November 1995 . Pseudo-Operations See Appendix A.x SPARC assembler. Command Line Options See Appendix C. and are the assembler normal output. • Names beginning with an underscore (_) are reserved by ANSI C.x This section describes the differences between the SunOS 4.1 SPARC Assembler for SunOS 4.) are assumed to be local symbols. Object File Format The type of object files created by the SPARC assembler are ELF (Executable and Linking Format) files.

x SPARC link editor. Asterisks (*) indicate items to be repeated zero or more times. Wherever blanks are allowed.x SPARC assembler takes assembly language programs. and produces relocatable object files for processing by the SunOS 5. Braces ({ }) enclose alternate item choices. This chapter is organized into the following sections: Syntax Notation Assembler File Syntax Lexical Features Assembler Error Messages page 3 page 4 page 4 page 10 Syntax Notation In the descriptions of assembly language syntax in this chapter: • • • • Brackets ([ ]) enclose optional items. 3 .Assembler Syntax 2 The SunOS 5. which are separated from each other by vertical bars (|). as specified in this document. The assembly language described in this document corresponds to the SPARC instruction set defined in the SPARC Architecture Manual (Version 8 and Version 9) and is intended for use on machines that use the SPARC architecture. arbitrary numbers of blanks and horizontal tabs may be used. Newline characters are not allowed in place of blanks.

2 Assembler File Syntax The syntax of assembly language files is: [line]* Lines Syntax The syntax of assembly language lines is: [statement [ . synthetic instruction. 4 SPARC Assembly Language Reference Manual—November 1995 . Lexical Features This section describes the lexical features of the assembler syntax. or instruction. Case Distinction Uppercase and lowercase letters are distinct everywhere except in the names of special symbols. Special symbol names have no case distinction. instruction is an encoded pseudo-op. statement]*] [!comment] Statement Syntax The syntax of an assembly language statement is: [label:] [instruction] where: label is a symbol name.

normal symbolic labels may be defined only once. floating-point constants are written with 0r or 0R (where r or R means REAL) followed by a string acceptable to atof(3). The special names 0rnan and 0rinf represent the special floating-point values Not-A-Number (NaN) and INFinity. However.2 Comments A comment is preceded by an exclamation mark character (!). Labels A label is either a symbol or a single decimal digit n (0…9). and before its definition (forward reference) as nf. and octal numeric constants are recognized and are written as in the C language. Numbers Decimal. A numeric label n is referenced after its definition (backward reference) as nb. Negative Not-A-Number and Negative INFinity are specified as 0r-nan and 0r-inf. integer suffixes (such as L) are not recognized. an optional sign followed by a non-empty string of digits with optional decimal point and optional exponent. Note – The names of these floating-point constants begin with the digit zero. A label is immediately followed by a colon ( : ). C language-style comments (‘‘/*…*/’’) are also permitted and may span multiple lines. not the letter “O. For floating-point pseudo-operations. Numeric labels may be defined repeatedly in an assembly file. the exclamation mark character and all following characters up to the end of the line are ignored.” Assembler Syntax 5 . that is. hexadecimal.

An example of assembly code in the suggested style is: add %g1. are recognized in strings..’A’) --> g1 The escape codes described in Table 2-1. When used in an expression.’a’-’A’. The suggested style is to use single quote mark characters for the ASCII value of a single character. } { letter | _ | $ | .%g1 ! g1 + (’a’ . | digit }* In the above syntax: 6 SPARC Assembly Language Reference Manual—November 1995 . the numeric value of a string is the numeric value of the ASCII representation of its first character. and double quote mark characters for quoted-string operands such as used by pseudo-ops. Table 2-1 Escape Codes Recognized in Strings Escape Code \a \b \f \n \r \t \v \nnn \xnn. derived from ANSI C.. Description Alert Backspace Form feed Newline (line feed) Carriage return Horizontal tab Vertical tab Octal value nnn Hexadecimal value nn. Symbol Names The syntax for a symbol name is: { letter | _ | $ | . The sequence must not include a newline character.2 Strings A string is a sequence of characters quoted with either double-quote mark (") or single-quote mark (’) characters...

Table 2-2 lists these special symbol names. otherwise. External variable names beginning with the underscore character are reserved by the ANSI C Standard. and dot ( . The symbol dot ( . the underscore ( _ ). Table 2-2 Special Symbol Names Symbol Object General-purpose General-purpose General-purpose General-purpose General-purpose registers global registers out registers local registers in registers Name %r0 %g0 %o0 %l0 %i0 %sp %fp %f0 … %f31 %fsr %fq %c0 … %c31 %csr %cq %psr %tbr %wim %y … … … … … %r31 %g7 %o7 %l7 %i7 Comment Same Same Same Same as as as as %r0 %r8 %r16 %r24 … … … … %r7 %r15 %r23 %r31 Stack-pointer register Frame-pointer register Floating-point registers Floating-point status register Front of floating-point queue Coprocessor registers Coprocessor status register Coprocessor queue Program status register Trap vector base address register Window invalid mask Y register (%sp = %o6 = %r14) (%fp = %i6 = %r30) Assembler Syntax 7 . ) is predefined and always refers to the address of the beginning of the current assembly language statement. avoid using this type of symbol name in hand-coded assembly language routines. To simplify debugging. Do not begin these names with the underscore.Registers Special symbol names begin with a percentage sign (%) to avoid conflict with user symbols. the program will not conform to ANSI C and unpredictable behavior may result. dollar sign ($). Symbol names that begin with a dot ( . Special Symbols . ) are assumed to be local symbols. ) are treated as alphabetic characters.2 • • • • Uppercase and lowercase letters are distinct.

Used only in Sun compiler-generated code. Ancillary state registers %asr1 … %asr31 There is no case distinction in special symbols.2 Table 2-2 Special Symbol Names (Continued) Symbol Object Unary operators Name %lo %hi %r_disp32 %r_plt32 Comment Extracts least significant 10 bits Extracts most significant 22 bits Used only in Sun compiler-generated code. for example: #define psr %PSR 8 SPARC Assembly Language Reference Manual—November 1995 . for example. The lack of case distinction allows for the use of non-recursive preprocessor substitutions. %PSR is equivalent to %psr The suggested style is to use lowercase letters.

enclose operands of the %hi or %lo operators in parentheses. << Left shift %r_plt32 >> Right shift Assembler Syntax 9 . as other unary operators.2 The special symbols %hi and %lo are true unary operators which can be used in any expression and. For example: %hi(a) + b Operators and Expressions The operators described in Table 2-3 are recognized in constant expressions. Table 2-3 Operators Recognized in Constant Expressions Binary + – * / % ^ Operators Integer addition Integer subtraction Integer multiplication Integer division Modulo Exclusive OR Unary + – ~ %lo %hi %r_disp32 Operators (No effect) 2's Complement 1's Complement Extract least significant 10 bits Extract most significant 22 bits Used in Sun compiler-generated code only to instruct the assembler to generate specific relocation information for the given expression. have higher precedence than binary operations. Used in Sun compiler-generated code only to instruct the assembler to generate specific relocation information for the given expression. For example: %hi a+b %lo a+b = = (%hi a)+b (%lo a)+b To avoid ambiguity.

or %r_plt32 operators. Assembler Error Messages Messages generated by the assembler are generally self-explanatory and give sufficient information to allow correction of a problem. 10 SPARC Assembly Language Reference Manual—November 1995 .2 Table 2-3 Operators Recognized in Constant Expressions (Continued) Binary & | Operators Bitwise AND Bitwise OR Unary Operators Since these operators have the same precedence as in the C language. If you have intentionally written code this way. Certain conditions will cause the assembler to issue warnings associated with delay slots following Control Transfer Instructions (CTI). the modulo operator % must not be immediately followed by a letter or digit. These warnings are: • • • Set synthetic instructions in delay slots Labels in delay slots Segments that end in control transfer instructions These warnings point to places where a problem could exist.empty pseudo-operation in a delay slot tells the assembler that the delay slot can be empty or can contain whatever follows because you have verified that either the code is correct or the content of the delay slot does not matter.empty pseudo-operation immediately after the control transfer instruction. you can insert an . put expressions in parentheses to avoid ambiguity. To avoid confusion with register names or with the %hi. %r_disp32. The .%lo. The modulo operator is typically followed by a space or left parenthesis character.

The SPARC assembler creates a default output file when standard input or multiple files are used. This chapter is organized into the following sections: ELF Header Sections Locations Relocation Tables Symbol Tables Addresses String Tables Assembler Directives page 12 page 14 page 21 page 22 page 22 page 22 page 24 page 24 The ELF object file format consists of: • • Header Sections 11 .Executable and Linking Format 3 The type of object files created by the SPARC assembler version for SunOS 5. under the -S option) and to standard error (for example. under the -V option). These relocatable ELF files hold code and data suitable for linking with other object files to create an executable or a shared object file.x are now Executable and Linking Format (ELF) files. The assembler can also write information to standard output (for example. and are the assembler normal output.

” in the System V Application Binary Interface (SPARC™ Processor Supplement) manual. A value of 0 indicates no associated entry point. entry Virtual address at which the process is to start. 12 SPARC Assembly Language Reference Manual—November 1995 . flag Processor-specific flags associated with the file. “Object Files. A value of 2 specifies SPARC. The ELF header contains the following information: ehsize ELF header size in bytes. The initial bytes of an ELF header specify how the file is to be interpreted. see Chapter 4.3 • • • • • Locations Addresses Relocation tables Symbol tables String tables For more information. ident Marks the file as an object file and provides machine-independent data to decode and interpret the file contents. ELF Header The ELF header is always located at the beginning of the ELF file. machine Specifies the required architecture for an individual file. It describes the ELF file organization and contains the actual sizes of the object file control structures.

shoff Section header table file offset in bytes. Table 3-1 describes the reserved object file types. shentsize Size in bytes of the section header. phnum Number of entries in program header table. all entries are the same size. The value of 0 indicates no section header.3 phentsize Size in bytes of entries in the program header table. shstrndx Section header table index of the entry associated with the section name string table. A value of 0 indicates the file has no section header table. version Identifies the object file version. type Identifies the object file type. A section header is one entry in the section header table. phoff Program header table file offset in bytes. All entries are the same size. A value of 0 indicates the file has no program header table. A value of SHN_UNDEF indicates the file does not have a section name string table. shnum Number of entries in section header table. Executable and Linking Format 13 . The value of 0 indicates no program header.

of zero-length). 1. The current section is the section to which code is generated.3 Table 3-1 shows reserved object file types: Table 3-1 Type none rel exec dyn core loproc hiproc Reserved Object File Types Value 0 1 2 3 4 0xff00 0xffff Description No file type Relocatable file Executable file Shared object file Core file Processor-specific Processor-specific Sections A section is the smallest unit of an object that can be relocated. The following sections are commonly present in an ELF file: • • • • • Section header Executable text Read-only data Read-write data Read-write uninitialized data (section header only) Sections do not need to be specified in any particular order. Every section must have one section header describing the section. a section header does not need to be followed by a section. 14 SPARC Assembly Language Reference Manual—November 1995 . 2. Each section occupies one contiguous sequence of bytes within a file. However. The section may be empty (that is. These sections contain all other information in an object file and satisfy several conditions.

the entire section must be ensured double-word alignment. addralign Aligns the address if a section has an address alignment constraint. or information in the object file for debugging. Section Header The section header allows you to locate all of the file sections. An object file may have inactive space. entsize Size in bytes for entries in fixed-size tables such as the symbol table. An entry in a section header table contains information characterizing the data in a section. The contents of the data in the inactive space are unspecified. Sections can be added for multiple text or data segments. userdefined sections.3 3. Note – Not all of the sections need to be present. The section header contains the following information: addr Address at which the first byte resides if the section appears in the memory image of a process. Only 0 and positive integral powers of 2 are currently allowed. for example. Executable and Linking Format 15 . if a section contains a double-word. A value of 0 or 1 indicates no address alignment constraints. Sections in a file cannot overlap. A byte in a file can reside in only one section. shared data. the default value is 0. 4.

size Specifies the size of the section in bytes. This attribute is off if a control section does not reside in the memory image of the object file. as described in Table 3-3. Reserved for processor-specific semantics. Note – If the section type is SHT_NOBITS. Default Value 0x1 0x2 SHF_EXECINSTR SHF_MASKPROC 0x4 0xf0000000 info Extra information. The interpretation of this information depends on the section type. An index into the section header string table section specifies the location of a null-terminated string. The interpretation of this information depends on the section type. Occupies memory during process execution. Table 3-2 Flag SHF_WRITE SHF_ALLOC Section Attribute Flags Description Contains data that is writable during process execution. link Section header table index link. offset specifies the conceptual placement of the file. offset Specifies the byte offset from the beginning of the file to the first byte in the section. name Specifies the section name. Contains executable machine instructions. Table 3-2 describes the section attribute flags.3 flags One-bit descriptions of section attributes. 16 SPARC Assembly Language Reference Manual—November 1995 . as described in Table 3-3.

The section header index of the section to which the relocation applies. The section header index of the symbol table to which the hash table applies. Note: Only one section of this type is allowed in a file 0 Executable and Linking Format 17 . it may contain many unnecessary symbols. Table 3-3 Name Value Section Types Interpretation by Description info null progbits 0 1 Marks section header as inactive. Contains relocation entries with explicit addends. Contains a symbol table for link editing. This table may also be used for dynamic linking. Contains information defined explicitly by the program. however. The section header index of the associated string table. Note: Only one section of this type is allowed in a file dynamic 6 Contains dynamic linking information. 0 The section header index of the associated symbol table. the section still occupies no space in the file. A file may have multiple string table sections. type Categorizes the section contents and semantics. however. A file may have multiple relocation sections. Table 3-3 describes the section types. size may be non-zero. The section header index of the string table used by entries in the section.3 Note – If the section type is SHT_NOBITS. Note: Only one section of this type is allowed in a file Contains a string table. One greater than the symbol table index of the last local symbol. link symtab 2 strtab 3 rela 4 hash 5 Contains a symbol rehash table.

a section of this type does not occupy any space in the file. loproc hiproc louser hiuser 0x70000000 0x7fffffff 0x80000000 0xffffffff Note – Some section header table indexes are reserved and the object file will not contain sections for these special indexes. Lower and upper bound of range reserved for application programs. link nobits 8 rel 9 shlib dynsym 10 11 Reserved. however. One greater than the symbol table index of the last local symbol. The section header index of the section to which the relocation applies. The section header index of the associated symbol table. A file may have multiple relocation sections. Note: Only one section of this type is allowed in a file Lower and upper bound of range reserved for processor-specific semantics. Contains a symbol table with a minimal set of symbols for dynamic linking.3 Table 3-3 Name Value Section Types (Continued) Interpretation by Description info note 7 Contains information that marks the file. Contains information defined explicitly by the program. The section header index of the associated string table. Contains relocation entries without explicit addends. 18 SPARC Assembly Language Reference Manual—November 1995 . Note: Section types in this range may be used by an application without conflicting with system-defined section types.

Section contains runtime finalization instructions.align 4 <instructions> Code Example 3-1 Creating an .text .init sections contain codes that are to be executed before the the main program is executed. You can use the section control directives to change the user section in which code or data is generated. Section contains initialized read-write data.init" . Section contains runtime initialization instructions. Table 3-4 lists the predefined user sections that can be named in the section control directives.fini .note Section contains executable text.section ".init section in an object file. Section contains note information.line . Creating an .comment . Comment section.data & . Section Name .bss .rodata1 . Section contains debugging information.init Section in an Object File The . . To create an .init Section Executable and Linking Format 19 .data1 . use the assembler pseudo-ops shown in Code Example 3-1.init . Section contains read-only data.rodata & . Section contains line # info for symbolic debugging.debug .3 Predefined User Sections A section that can be manipulated by the section control directives is known as a user section. Table 3-4 Predefined User Sections Description Section contains uninitialized read-write data.

Section Name ".fini section.3 At link time. Do not reference or store to locations that are greater than %sp+96 in the . Creating a .init section are executed before the main program is executed.init sections in a sequence of . Note – The codes are executed inside a stack frame of 96 bytes.init section.dynamic" 20 SPARC Assembly Language Reference Manual—November 1995 .align 4 <instructions> Code Example 3-2 Creating an .fini section are executed after the main program is executed.fini section in the linker output file. The code in the . the .fini sections contain codes that are to be executed after the the main program is executed.init section in the linker output file.section ". the .o files are concatenated into a .fini Section in an Object File . Predefined Non-User Sections Table 3-5 lists sections that are predefined but cannot be named in the section control directives because they are not under user control. Note – The codes are executed inside a stack frame of 96 bytes.fini" . use the assembler pseudo-ops shown in Code Example 3-2. Table 3-5 Predefined Non-User Sections Description Section contains dynamic linking information.fini sections in a sequence of .o files are concatenated into an . To create an .fini section in an object file. Do not reference or store to locations that are greater than %sp+96 in the .fini Section At link time. . The codes in the .

strtab . ". When a section control directive (for example. that is. Section contains the procedure linking table.text".rela.plt . . A location counter tracks the current offset within each section where code or data is being generated.3 Table 3-5 Predefined Non-User Sections (Continued) Description Section contains strings needed for dynamic linking. Section contains a symbol table. Section contains the string table.section pseudo-op) is processed. but can be updated during processing of data-generating assembler directives (for example. the location information from the location counter associated with the new section is assigned to and stored with the name and value of the current location. Executable and Linking Format 21 . name is the section to which the relocations apply. the . Section Name .relname & .relaname . Section contains a symbol hash table. The current location is the location within the current section where code is generated. Section contains the dynamic linking symbol table. The current location is updated at the end of processing each statement. String table for the section header table names. Section contains the path name of a program interpreter. Section containing relocation information. Each location is identified by a section and a byte offset from the beginning of the section.text". ".shstrtab .word pseudo-op).hash .dynstr .symtab Locations A location is a specific position within a section.rel. Section contains the global offset table.interp .dynsym .got .

Relocation Tables The assembler produces a companion relocation table for each relocatable section. that is. for example. it may be an address. It makes an entry in the symbol table for each symbol that is defined or referenced in the input file and is needed during linking. The SPARC assembler creates a symbol table section for the object file. Addresses Locations represent addresses in memory if a section is allocatable. the value represents the string table index that gives the symbol name. The section header contains the symbol table index for the first non-local symbol. if more than one section is present. its contents are to be placed in memory at program runtime. otherwise.3 Note – Each section has one location counter. A value of zero indicates the symbol table entry has no name. A symbol table contains the following information: name Index into the object file symbol string table. value Value of the associated symbol. Symbol Tables A symbol table contains information to locate and relocate symbolic definitions and references. or it may be an absolute value. The table contains a list of relocations (that is. only one location can be current at any time. Symbolic references to these locations must be changed to addresses by the SPARC link editor. adjustments to data in the section) to be performed by the link editor. 22 SPARC Assembly Language Reference Manual—November 1995 . The symbol table is then used by the SPARC link editor during relocation. This value is dependent on the context.

Table 3-6 and Table 3-7 describes these values. info Specifies the symbol type and binding attributes. Current value is 0. other Undefined meaning.3 size Size of symbol. references to the symbol will continue to point to the same location because the value of the symbol will change as well. Gives the name of the source file associated with the object file. Table 3-6 Value 0 1 Type notype object Symbol Types Description Type not specified. Symbol is associated with a data object. These types of symbols are primarily used for relocation. the link editor automatically creates a procedure linkage table entry for the referenced symbol. if specified. When another object file references a function from a shared object. As a section moves during relocation. Symbol is associated with a section. 2 func 3 section 4 13 15 file loproc hiproc Executable and Linking Format 23 . shndx Contains the section header table index to another relevant section. Symbol is associated with a function or other executable code. for example. Values reserved for processor-specific semantics. a variable or an array. A value of 0 indicates that the symbol has either no size or an unknown size.

in the object file. for example. are commands to the assembler that may or may not result in the generation of code.3 Table 3-7 shows the symbol binding attributes. and unreferenced strings are allowed. or strings. Empty string table sections are permitted. A string may appear multiple times and may also be referenced multiple times. Values reserved for processor-specific semantics. Assembler Directives Assembler directives. these definitions have a lower precedence than globally defined symbols. symbol names and file names. Table 3-7 Value 0 Symbol Bindings Description Symbol is defined in the object file and not accessible in other files. Local symbols of the same name may exist in multiple files. however. Symbol is either defined externally or defined in the object file and accessible in other files. The different types of assembler directives are: • • • Section Control Directives Symbol Attribute Directives Assignment Directives 24 SPARC Assembly Language Reference Manual—November 1995 . the index referencing this section must contain zero. however. References to substrings may exist. Symbol is either defined externally or defined in the object file and accessible in other files. The strings are referenced in the section header as indexes into the string table section. Binding local 1 global 2 weak 13 15 loproc hiproc String Tables A string table is a section which contains null-terminated variable-length character sequences. or pseudo-operations (pseudo-ops). • • A string table index may refer to any byte in the section.

Symbol Attribute Directives The symbol attribute pseudo-ops declare the symbol type and size and whether it is local or global. Section Control Directives When a section is created. This directive constitutes a definition of the symbol and. You can also use the section control directives to change the user section in which code or data is generated. Data Generating Directives The data generating directives are used for allocating storage and loading values. therefore.” for a complete description of the pseudo-ops supported by the SPARC assembler. The section control pseudo-ops allow you to make entries in this table. The section control pseudo-ops cannot be used to manipulate these sections. relocation table. must be the only definition of the symbol. Note – The symbol table. Assignment Directive The assignment directive associates the value and type of expression with the symbol and creates a symbol table entry for the symbol. a section header is generated and entered in the ELF object file section header table. The section control directives also create a section symbol which is associated with the location at the beginning of each created section. and string table sections are created implicitly. The section symbol has an offset value of zero. “Pseudo-Operations.3 • • Data Generating Directives Optimizer Directives See Appendix A. Sections that can be manipulated with the section control directives are known as user sections. Executable and Linking Format 25 .

3 26 SPARC Assembly Language Reference Manual—November 1995 .

section .1 SPARC assembly files to the SunOS 5.seg to . ) so that they will not conflict with user programs’ symbol names.seg data to . “Pseudo-Operations. Prefix local symbol names with a dot (.x SPARC assembly file format.Converting Files to the New Format Introduction 4 This chapter discusses how to convert existing SunOS 4.section. • • Note – The above conversions can be automatically achieved by passing the -T option to the assembler. for example.x SPARCompilers do not prepend a leading underscore to symbol names in the users’ programs as did the SPARCompilers that ran under SunOS 4.) . change . See Appendix A.x SPARC assembly language begin with a dot (. The Solaris 2. 27 .1. Conversion Instructions • Remove the leading underscore ( _ ) from symbol names.data.” for more information. Change the usage of the pseudo-op . Local symbol names in the SunOS 5.

L16: .%lo(LF12).LE12: ret restore .%sp !#PROLOGUE# 1 .align 4 main: !#PROLOGUE# 0 sethi %hi(.x File Converted to the New Format .%lo(.optim "-O~Q~R~S" LF12 = -96 LP12 = 96 LST12 = 96 LT12 = 96 .section .text" 04 main .%g1 save %sp.ascii "hello world\n" .%o0 call printf.LF12).optim "-O~Q~R~S" .text" set .L16.%o0 call _printf.%g1 add %g1.seg "text" .proc .L14: .section .%g1.proc 04 .ascii .%g1 add %g1.%g1.1 file to the new format.LP12 = 96 .LST12 = 96 .1 nop LE12: ret restore .seg "data1" .align 4 _main: !#PROLOGUE# 0 sethi %hi(LF12).global ".1 nop .%g1 save %sp.seg "text" set L16. Example 4.LF12 = -96 .align 4 L16: .section ".align . The lines that are different in the new format are marked with change bars.4 Examples Figure 4-1 shows how to convert an existing 4.data1" 4 "hello world\n" ".LT12 = 96 Change bars Figure 4-1 Converting a 4.LF12).x File to the New Format 28 SPARC Assembly Language Reference Manual—November 1995 .global _main .%sp !#PROLOGUE# 1 L14: .

” 29 .Instruction-Set Mapping 5 The tables in this chapter describe the relationship between hardware instructions of the SPARC architecture. “SPARC-V9 Instruction Set. as defined in The SPARC Architecture Manual and the assembly language instruction set recognized by the SunOS 5.x SPARC assembler. Table Notation Integer Instructions Floating-Point Instruction Coprocessor Instructions Synthetic Instructions page 30 page 31 page 39 page 40 page 41 The SPARC-V9 instruction set is described in Appendix E.

regrs2 reg_or_imm 30 SPARC Assembly Language Reference Manual—November 1995 . %r0 %g0 %o0 %l0 %i0 .. It can be the result of the evaluation of a symbol expression.. %r7 (Globals) Same as %r8 . Source register 1. A signed or unsigned constant that can be represented in 7 bits (it is in the range -64 . A constant which fits in 22 bits. . const13 const22 creg freg imm7 reg regrd regrs1. It can be the result of the evaluation of a symbol expression... %c31 %f0 .....5 Table Notation Table 5-1 shows the table notation used in this chapter to describe the instruction set of the assembler. or an immediate constant.... %r15 (Outs) Same as %r16 . Floating-point registers.. immediate constant. %f31 Coprocessor registers. The following notations are commonly suffixed to assembler mnemonics (uppercase letters refer to SPARC architecture instruction names... const13 Value from either a single register.. regrs2. 127). %r23 (Locals) Same as %r24 .. . %r31 %g7 %o7 %l7 %i7 General purpose registers.. It can be the result of the evaluation of a symbol expression. Same as %r0 . Table 5-1 Notations address Describes regrs1 + regrs1 + regrs1 – const13 const13 regrs2 const13 const13 + regrs1 Notations Used to Describe Instruction Sets Comment Address formed from register contents.. It can be the result of the evaluation of a symbol expression.. source register 2. A signed constant which fits in 13 bits. asi Alternate address space identifier.. %c0 ... or both. %r31 (Ins) Destination register... . an unsigned 8-bit value. .

Integer Instructions The notations described in Table 5-2 are commonly suffixed to assembler mnemonics (uppercase letters for architecture instruction names).5 Table 5-1 Notations regaddr Software_trap_ number Describes regrs1 regrs1 + regrs2 regrs1 + regrs2 regrs1 + imm7 regrs1 ..127. A value formed from register contents.imm7 uimm7 imm7 + regrs1 Notations Used to Describe Instruction Sets (Continued) Comment Address formed with register contents only. The resulting value must be in the range 0. Instruction-Set Mapping 31 . immediate constant.... uimm7 An unsigned constant that can be represented in 7 bits (it is in the range 0 . 127). It can be the result of the evaluation of a symbol expression.. Table 5-2 Notation a b c d f h q sr Commonly Suffixed Notations Description Instructions that deal with alternate space Byte instructions Reference to coprocessor registers Doubleword instructions Reference to floating-point registers Halfword instructions Quadword instructions Status register Table 5-3 outlines the correspondence between SPARC hardware integer instructions and SPARC assembly language instructions.. inclusive. or both.

reg_or_imm. reg_or_imm. regrs1. Note – In Table 5-3. reg_or_imm. is always the last operand in a statement. regrs1. regrs1. • Brackets ([ ]) indicate indirection: the contents of the addressed memory location are being read from or written to. regrs1. • Braces ({ }) indicate optional arguments. reg_or_imm. regrs1. 32 SPARC Assembly Language Reference Manual—November 1995 .a" to the opcode mnemonic. All Bicc and Bfcc instructions described may indicate that the annul bit is to be set by appending ". reg_or_imm.a label" • Table 5-3 Opcode ADD ADDcc ADDX ADDXcc AND ANDcc ANDN ANDNcc Mnemonic add addcc addx addxcc and andcc andn andncc SPARC to Assembly Language Mapping Operation regrd regrd regrd regrd regrd regrd regrd regrd Add Add and modify icc Add with carry And Comments Argument List regrs1. "bgeu. “Assembler Syntax” differs from the usage of these brackets. Note that the usage of brackets described in Chapter 2. reg_or_imm.5 The syntax of individual instructions is designed so that a destination operand (if any). Braces are not literally coded. reg_or_imm. regrs1. which may be either a register or a reference to a memory location. for example. regrs1. Brackets are coded literally in the assembly language. reg_or_imm.

a} cb123{.a} bpos{.a} cb01{.a} bl{.a} cb023{.a} bcs{.a} SPARC to Assembly Language Mapping (Continued) Operation Branch on integer condition codes Comments branch never synonym: bnz synonym: bz Argument List label label label label label label label label label label label label label label label label label label label label label label label label label label label label label label label label label Call subprogram Branch on coprocessor condition codes branch never synonym: bgeu synonym: blu synonym: b Instruction-Set Mapping 33 .a} ble{.a} cb23{.a} cb1{.a} cb0{.a} cb012{.a} cb3{.a} call cbn{.a} bcc{.a} cb013{.a} bleu{.a} be{.a} bne{.a} bge{.a} ba{.a} cb2{.a} bneg{.a} bvc{.a} bgu{.5 Table 5-3 Opcode BN BNE BE BG BLE BGE BI BGU BLEU BCC BCS BPOS BNEG BVC BVS BA CALL CBccc Mnemonic bn{.a} bg{.a} cb02{.a} cb13{.eo} cb12{.a} cb03{.a} cba{.a} bvs{.

a} fbl{.a} fbule{.a} fbge{. cregrd Instruction cache flush Jump and link Load signed byte Load signed halfword Load-store unsigned byte Load unsigned byte Load unsigned halfword Load word Load double word regrd must be even synonym: fbnz synonym: fbz Load floating-point register Load double floating-point Load coprocessor Load double coprocessor fregrd must be even 34 SPARC Assembly Language Reference Manual—November 1995 . regrd [address]. cregrd [address].5 Table 5-3 Opcode FBN FBU FBG FBUG FBL FBUL FBLG FBNE FBE FBUE FBGE FBUGE FBLE FBULE FBO FBA FLUSH JMPL LDSB LDSH LDSTUB LDUB LDUH LD LDD LDF LDFSR LDDF LDC LDCSR LDDC Mnemonic fbn{.a} fbug{.a} fble{. regrd [address]. regrd [address]. %csr [address].a} flush jmpl ldsb ldsh ldstub ldub lduh ld ldd ld ld ldd ld ld ldd SPARC to Assembly Language Mapping (Continued) Operation Branch on floating-point condition codes Comments branch never Argument List label label label label label label label label label label label label label label label label address address.a} fbg{.a} fba{.a} fbu{. regrd [address]. fregrd [address].a} fbo{. regrd [address].a} fblg{. %fsr [address]. fregrd [address].a} fbne{. regrd [address].a} fbul{.a} fbuge{. regrd [address]. regrd [address].a} fbe{.a} fbue{.

regrd regrs1. [regaddr]asi. regrd %tbr. regrd regrs1. reg_or_imm. reg_or_imm. See synthetic instructions. reg rd address regrs1. regrs1. See synthetic instructions. reg_or_imm.5 Table 5-3 Opcode LDSBA LDSHA LDUBA LDUHA LDA LDDA Mnemonic ldsba ldsha lduba lduha lda ldda SPARC to Assembly Language Mapping (Continued) Operation Load signed byte from alternate space Comments Argument List [regaddr]asi. reg_or_imm. regrs1. regrd %y. regrd %wim. [regaddr]asi. SDIV SDIVcc sdiv sdivcc Instruction-Set Mapping 35 . [regaddr]asi. regrd regrs1. reg_or_imm. regrd regrs1. See synthetic instructions. regrd Signed divide Signed divide and modify icc Return from trap See synthetic instructions. regrd Multiply step (and modify icc) No operation regrs1. reg_or_imm. reg_or_imm. reg_or_imm. regrd [regaddr]asi. regrd %psr. regrd regrd regrd regrd regrd regrd must be even LDSTUBA MULScc NOP OR ORcc ORN ORNcc RDASR RDY RDPSR RDWIM RDTBR ldstuba mulscc nop or orcc orn orncc rd rd rd rd rd [regaddr]asi. regrd regrd regrd regrd Inclusive or %asrnrs1. regrs1. [regaddr]asi. See synthetic instructions. reg_or_imm. RESTORE restore RETT SAVE rett save See synthetic instructions.

reg_or_imm. [address] %cq. reg_or_imm.5 Table 5-3 Opcode SMUL SMULcc Mnemonic smul smulcc SPARC to Assembly Language Mapping (Continued) Operation Signed multiply Signed multiply and modify icc Set high 22 bits of register See synthetic instructions. [address] regrd. regrd regrs1. reg_or_imm. [address] fregrd. regrd %hi(value). Shift left logical Shift right logical Shift right arithmetic Store byte Synonyms: stub. [address] %csr. [address] %fq. [address] %fsr. [regaddr]asi regrd Must be even 36 SPARC Assembly Language Reference Manual—November 1995 . reg_or_imm. regrd const22. [regaddr]asi regrd. stsb Synonyms: stuh. stsh Comments Argument List regrs1. [address] cregrd. regrd regrs1. regrd regrs1. [address] fregrd. reg_or_imm. stsha fregrd Must be even STC STDC STCSR STDCQ st std st std STBA stba STHA STA STDA stha sta stda regrd [regaddr]asi regrd. [address] cregrd. regrd regrd. regrd regrs1. [address] regrd. [address SETHI sethi sethi SLL SRL SRA STB sll srl sra stb STH ST STD STF STDF STFSR STDFQ sth st std st std st std regrd. [address] regrd [regaddr]asi Store half-word regrd Must be even Store floating-point status register Store double floating-point queue Store coprocessor cregrd Must be even Store double coprocessor Store byte into alternate space Synonyms: stuba. stsba Synonyms: stuha.

5
Table 5-3 Opcode SUB SUBcc SUBX SUBXcc SWAP SWAPA Ticc Mnemonic sub subcc subx subxcc swap swapa tn tne SPARC to Assembly Language Mapping (Continued) Operation regrd regrd regrd regrd Subtract Subtract and modify icc Subtract with carry Swap memory word with register Trap on integer condition code Note: Trap numbers 16-31 are reserved for the user. Currentlydefined trap numbers are those defined in /usr/include/sys/trap.h Trap never Synonym: tnz Comments Argument List regrs1, regrs1, regrs1, regrs1, reg_or_imm, reg_or_imm, reg_or_imm, reg_or_imm,

[address], regrd [regaddr]asi, regrd software_trap_number software_trap_number

te tg tle tge tl tgu tleu tlu tgeu tpos tneg tvc tvs ta TADDcc TSUBcc TADDccTV taddcc tsubcc taddcctv

software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number

Synonym: tz

Synonym: tcs Synonym: tcc software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd Tagged add and modify icc

Synonym: t

Tagged add and modify icc and trap on overflow

TSUBccTV

tsubcctv

regrs1, reg_or_imm, regrd

Instruction-Set Mapping

37

5
Table 5-3 Opcode UDIV UDIVcc Mnemonic udiv udivcc SPARC to Assembly Language Mapping (Continued) Operation Unsigned divide Unsigned divide and modify icc Unsigned multiply Unsigned multiply and modify icc Illegal instruction See synthetic instructions See synthetic instructions See synthetic instructions See synthetic instructions Exclusive nor Exclusive or Comments Argument List regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd const22 reg_or_imm, %asrnrs1 regrs1, reg_or_imm, %y regrs1, reg_or_imm, %psr regrs1, reg_or_imm, %wim WRWIM WRTBR wr regrs1, reg_or_imm, %tbr wr regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd

UMUL UMULcc

umul umulcc

UNIMP WRASR WRY WRPSR

unimp wr wr wr

XNOR XNORcc XOR XORcc

xnor xnorcc xor xorcc

38

SPARC Assembly Language Reference Manual—November 1995

5
Floating-Point Instruction
Table 5-4 shows floating-point instructions. In cases where more than numeric type is involved, each instruction in a group is described; otherwise, only the first member of a group is described.
Table 5-4 SPARC FiTOs FiTOd FiTOq FsTOi FdTOi FqTOi FsTOd FsTOq FdTOs FdTOq FqTOd FqTOs FMOVs FNEGs FABSs FSQRTs FSQRTd FSQRTq FADDs FADDd FADDq Mnemonic* fitos fitod fitoq fstoi fdtoi fqtoi fstod fstoq fdtos fdtoq fqtod fqtos fmovs fnegs fabss fsqrts fsqrtd fsqrtq fadds faddd faddq Floating-Point Instructions Argument List fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs1, fregrs2, fregrd fregrs1, fregrs2, fregrd fregrs1, fregrs2, fregrd Description Convert integer to single Convert integer to double Convert integer to quad Convert single to integer Convert double to integer Convert quad to integer Convert single to double Convert single to quad Convert double to single Convert double to quad Convert quad to double Convert quad to single Move Negate Absolute value Square root

Add

* Types of Operands are denoted by the following lower-case letters: i integer s single d double q quad

Instruction-Set Mapping

39

fregrd fregrs1. fregrs2. If the EC (PSR_enable_coprocessor) field of the processor state register (PSR) is 0. Coprocessor-operate instructions are described in Table 5-5. fregrs2. fregrs2 fregrs2 fregrs2 fregrs2 Description Subtract Multiply Multiply double to quad Multiply single to double Divide Compare Compare. a cpopn instruction causes a cp_disabled trap. fregrs2. fregrd fregrs1. fregrd fregrs1. fregrd fregrs1. fregrs2. fregrd fregrs1. fregrs2. fregrs2 fregrs1. fregrd fregrs1. fregrd fregrs1. fregrs1. fregrs1. fregrs2. fregrd fregrs1. fregrs2 * Types of Operands are denoted by the following lower-case letters: i integer s single d double q quad Coprocessor Instructions All coprocessor-operate (cpopn) instructions take all operands from and return all results to coprocessor registers. fregrd fregrs1. fregrd fregrs1. or if a coprocessor is not present.5 Table 5-4 SPARC FSUBs FSUBd FSUBq FMULs FMULd FMULq FdMULq FsMULd FDIVs FDIVd FDIVq FCMPs FCMPd FCMPq FCMPEs FCMPEd FCMPEq Mnemonic* fsubs fsubd fsubq fmuls fmuld fmulq fmulq fsmuld fdivs fdivd fdivq fcmps fcmpd fcmpq fcmpes fcmped fcmpeq Floating-Point Instructions (Continued) Argument List fregrs1. fregrd fregrs1. The data types supported by the coprocessor are coprocessor-dependent. fregrs2. fregrs2. fregrs2. fregrs2. fregrs1. generate exception if not ordered fregrs1. 40 SPARC Assembly Language Reference Manual—November 1995 . fregrs2. Operand alignment is also coprocessor-dependent.

regrd regrd. const13. regrd Synthetic Instructions Table 5-6 describes the mapping of synthetic instructions to hardware instructions. reg_or_imm. regrd regrd. regrs1. Table 5-5 SPARC CPop1 CPop2 Mnemonic cpop1 cpop2 Coprocessor-Operate Instructions Name Coprocessor operation Coprocessor operation May modify ccc Comments Argument List opc.5 The conditions that cause a cp_exception trap are coprocessor-dependent. regrs1. reg_or_imm regrd [address] [address] [address] reg. regrd [address] [address] [address] Clear Clear Clear Clear (zero) register byte halfword word Comment Bit Bit Bit Bit test set clear toggle regrs1. reg_or_imm regrd const13. regrd regrd. %g0 regrd. const13. 1. regrd opc. reg_or_imm. %g0. %g0. reg_or_imm. regrd regrd const13. regrd reg_or_imm. 1. regrd regrs1 regrd regrd regrd Synthetic Instruction to Hardware Instruction Mapping Hardware Equivalent(s) andcc or andn xor jmpl or stb sth st subcc sub sub subcc subcc regrs1. Table 5-6 Synthetic Instruction btst bset bclr btog call clr clrb clrh clr cmp dec dec deccc deccc reg_or_imm. regrd Compare Decrement by 1 Decrement by const13 Decrement by 1 and set icc Decrement by const13 and set icc Instruction-Set Mapping 41 . %g0 regrd. reg_or_imm. %g0. reg_or_imm. %o7 %g0. %g0. reg_or_imm. regrd regrd. regrs2. regrs2. regrd regrd. reg_or_imm. reg_or_imm.

set set set value. regrd. regrd 42 SPARC Assembly Language Reference Manual—November 1995 . 1. regrd regrd.5 Table 5-6 Synthetic Instruction inc inc inccc inccc regrd const13.reg_or_imm. regrd %g0.regrd value. %g0 %g0. regrs2. regrd Comment Increment by 1 Increment by const13 Increment by 1 and set icc Increment by const13 and set icc jmp mov mov mov mov mov mov mov mov mov not not neg neg restore save address reg_or_imm. regrd Synthetic Instruction to Hardware Instruction Mapping (Continued) Hardware Equivalent(s) add add addcc addcc regrd. %g0. regrd regrd. 1. regrs1 %psr. regrs1 %g0. const13.reg_or_imm.%y %g0. %g0 One's complement One's complement Two's complement Two's complement Trivial restore Trivial save trivial save should only be used in supervisor code! if -4096 ≤ value ≤ 4095 if ((value & 0x3ff) == 0) otherwise Do not use the set synthetic instruction in an instruction delay slot.%wim %g0.reg_or_imm. %lo(value). regrs1 %tbr. regrd regrd regrs1. %tbr regrs1. %y reg_or_imm. regrs1 reg_or_imm. regrd regrd jmpl or rd rd rd rd wr wr wr wr xnor xnor sub sub restore save address. %wim reg_or_imm. %g0. %g0 %g0. regrd.%psr %g0. regrd %g0. regrs1 %tbr. %psr reg_or_imm. regrd %hi(value). regrd %g0.%tbr regrs1.regrd or sethi sethi or %g0. regrd. regrd %y. reg_or_imm.reg_or_imm. regrd %hi(value).regrd value. regrd regrd. value.regrd %y. const13. regrs1 %wim. regrs1 %wim. regrd regrd const13. regrs1 %psr. %g0. %g0. regrd regrd.

%g0 test tst reg orcc Instruction-Set Mapping 43 . ignores next instruction if z is not set.5 Table 5-6 Synthetic Instruction skipz skipnz Synthetic Instruction to Hardware Instruction Mapping (Continued) Hardware Equivalent(s) bnz.a .a .+8 Comment if z is set.+8 bz. %g0. ignores next instruction regrs1.

5 44 SPARC Assembly Language Reference Manual—November 1995 .

noalias pseudo-op. This pseudo-op appends a null (zero) byte to each string. . Alphabetized Listing with Descriptions . (Compiler-generated only. . .ascii string [.alias Turns off the effect of the preceding . boundary may be any power of 2. 45 . string]* Generates the given sequence(s) of ASCII characters. string"] Generates the given sequence(s) of ASCII characters.byte 8bitval [.align boundary Aligns the location counter on a boundary where ((“location counter” mod boundary)==0).) .Pseudo-Operations A The pseudo-operations listed in this appendix are supported by the SPARC assembler.asciz string [. 8bitval]* Generates (a sequence of) initialized bytes in the current segment.

the definition specifies the location of the symbol and the tentative definition is overridden. an optional sign followed by a non-empty string of digits with optional decimal point and optional exponent. the symbol is allocated in the uninitialized data section (bss).A . the SPARC link editor allocates storage for the symbol. size [.empty Suppresses assembler complaints about the next instruction presence in a delay slot when used in the delay slot of a Control Transfer Instruction (CTI). floatval is a string acceptable to atof(3). string specifies the name of the source file associated with the object file. Some instructions should not be in the delay slot of a CTI. depending on the definition of symbol_name in other files. Global is the default binding for common symbols. the symbol is allocated in sect_name and its location is optionally aligned to a multiple of alignment. (. • If the symbol is not defined in the input file and is declared to be local to the file. . Currently. If sect_name is not given. See the SPARC Architecture Manual for details.file string Creates a symbol table entry where string is the symbol name and STT_FILE is the symbol table type. Size bytes are allocated for the object represented by symbol. . 0rfloatval]* Generates (a sequence of) initialized double-precision floating-point values in the current segment.double 0rfloatval [.data is not currently supported.) • If the symbol is not defined in the input file and is declared to be global.common symbol. that is. sect_name] [. • If the symbol is defined in the input file. alignment] Provides a tentative definition of symbol.bss is supported for the section name. . only . 46 SPARC Assembly Language Reference Manual—November 1995 .

symbol]* Declares each symbol in the list to be local.pushsection . . . This operation is equivalent to: . Since local symbols are not accessible to other files. that is. symbol]* Declares each symbol in the list to be global.align 2). each symbol is either defined externally or defined in the input file and accessible in other files. an error will occur. • Multiple definitions of a defined global symbol is not allowed. default bindings for the symbol are overridden. of the specified symbol. default bindings for the symbol are overridden. Note – This pseudo-op by itself does not define the symbol.popsection .asciz string . • A global psuedo-op oes not need to occur before a definition. symbol]* . 16bitval]* Generates (a sequence of) initialized halfwords in the current segment.comment .ident string Generates the null terminated string in a comment section. local symbols of the same name may exist in multiple files. • A global symbol definition in one file will satisfy an undefined reference to the same global symbol in another file.globl symbol [. or tentative definition.local symbol [.half 16bitval [. The location counter must already be aligned on a halfword boundary (use .A . each symbol is defined in the input file and not accessible in other files.global symbol [. These symbols take precedence over weak and global symbols. that is. Pseudo-Operations 47 . If a defined global symbol has more than one definition.

) . . This new top section then becomes the current section.pushsection command allow you to switch back and forth between the named sections.pushsection sect_name [.proc n Signals the beginning of a procedure (that is. This pseudo-op and its corresponding . . This pseudo-op and its corresponding . The new section on the top of the stack becomes the current section. (Compiler-generated only.popsection Removes the top section from the section stack.volatile pseudo-op .optim string This pseudo-op changes the optimization level of a particular function. (Compiler-generated only.noalias %reg1.) .nonvolatile Defines the end of a block of instruction. %reg2 %reg1 and %reg2 will not alias each other (that is.popsection command allow you to switch back and forth between the named sections. a unit of optimization) to the peephole optimizer in the SPARC assembler. 48 SPARC Assembly Language Reference Manual—November 1995 .A Note – This pseudo-op by itself does not define the symbol. The instructions in the block may not be permuted. point to the same destination) until a .alias pseudo-op is issued. (Compilergenerated only.) . attributes] Moves the named section to the top of the section stack. This pseudo-op has no effect if: • The block of instruction has been previously terminated by a Control Transfer Instruction (CTI) or a label • There is no preceding . n specifies which registers will contain the return value upon return from the procedure.

. .align symbol: .pushsection . and reserves size bytes of space for it in the sect_name. The current section is the section that is currently on top of the stack.section section_name [. Pseudo-Operations 49 . that is. a new section with the specified name and attributes is created.A . floatval is a string acceptable to atof(3). Note – The . attributes] Makes the specified section the current section.quad 0rfloatval [.popsection sect_name alignment size If a section is not specified.skip . This pseudo-op changes the top of the section stack. size [. alignment]] Defines symbol. This operation is equivalent to: . • If section_name does not exist.reserve symbol. space is reserved in the current segment. sect_name [. an optional sign followed by a non-empty string of digits with optional decimal point and optional exponent. 0rfloatval]* Generates (a sequence of) initialized quad-precision floating-point values in the current segment. The assembler maintains a section stack which is manipulated by the section control directives.quad command currently generates quad-precision values with only double-precision significance.

Predefined user section names are changed in SunOS 5.1 SPARC assembly language programs. .section . Changes the current section to one of the predefined user sections. “Executable and Linking Format.section pseudo-op. .section . .data.seg data1.text. .A • If section_name is a non-reserved section.bss.x.seg section_name Note – This pseudo-op is currently supported for compatibility with existing SunOS 4. Attributes can be: #write | #alloc | #execinstr .single 0rfloatval [. See Table 3-2 in Chapter 3.data1.x SPARC assembly directive: . 50 SPARC Assembly Language Reference Manual—November 1995 .” for a detailed description of the section attribute flags. 0rfloatval]* Generates (a sequence of) initialized single-precision floating-point values in the current segment. See the sections “Predefined User Sections” and “Predefined Non-User Sections” in Chapter 3. “Executable and Linking Format. This pseudo-op has been replaced by the .section .seg text. . attributes must be included the first time it is specified by the . The assembler will interpret the following SunOS 4.section . Note – This operation does not align automatically. .1 SPARC assembly directive: .section directive. .” for a detailed description of the reserved sections.seg data.seg bss. to be the same as the following SunOS 5.

stabn <various parameters> The pseudo-op is used by Solaris 2. . type Declares the type of symbol.stabs <various parameters> The pseudo-op is used by Solaris 2. .skip n Increments the location counter by n. expr Declares the symbol size to be expr. Note – This operation does not align automatically. 32bitval]* Generates a (sequence of) 32-bit value(s).x SPARCompilers only to pass debugging information to the symbolic debuggers.uaword 32bitval [.type symbol. . Note – This operation does not align automatically. . which allocates n bytes of empty space in the current segment. “Executable and Linking Format. .x SPARCompilers only to pass debugging information to the symbolic debuggers.” for detailed information on symbols.A . Pseudo-Operations 51 . .uahalf 16bitval [. 16bitval]* Generates a (sequence of) 16-bit value(s). where type can be: #object #function #no_type See Table 3-6 in Chapter 3.size symbol. expr must be an absolute expression.

If string indicates a newer version of the assembler than this version of the assembler.x SPARCompilers only to pass debugging information to the symbolic debuggers. default bindings of the symbol are overridden by this directive. Note the following: • A weak symbol definition in one file will satisfy an undefined reference to a global symbol of the same name in another file.volatile Defines the beginning of a block of instruction. The block of instruction should end at a .nonvolatile pseudo-op and should not contain any Control Transfer Instructions (CTI) or labels. Note – This pseudo-op does not itself define the symbol. the link editor does not resolve these symbols.word 32bitval [. symbol] Declares each symbol in the list to be defined either externally.weak symbol [. . 52 SPARC Assembly Language Reference Manual—November 1995 . • Unresolved weak symbols have a default value of zero. 32bitval]* Generates (a sequence of) initialized words in the current segment. The instructions in the section may not be changed.A . The volatile block of instructions is terminated after the last instruction preceding a CTI or label. or in the input file and accessible to other files. . • If a weak symbol has the same name as a defined global symbol.version string Identifies the minimum assembler version necessary to assemble the input file. . a fatal error message is displayed and the SPARC assembler exits. You can use this pseudo-op to ensure assembler-compiler compatibility. Note – This operation does not align automatically. the weak symbol is ignored and no error results. .xstabs <various parameters> The pseudo-op is used by Solaris 2.

Pseudo-Operations 53 .A symbol =expr Assigns the value of expr to symbol.

A 54 SPARC Assembly Language Reference Manual—November 1995 .

static int foo4 = 2. Example 1 This example shows how to use the following pseudo-ops to specify the bindings of variables in C: common. 55 .Examples of Pseudo-Operations B This chapter shows some examples of ways to use various pseudo-ops. .global. .local.weak The following C definitions/declarations: int foo1 = 1. #pragma weak foo2 = foo1 static int foo3. .

size foo1.local .0 alpha4 12 Aug 1991" 56 SPARC Assembly Language Reference Manual—November 1995 .#object ! foo1 is of type data object.4 4 ! #pragma weak foo2 = foo1 ! static int foo3 ! static int foo4 = 2 0x2 foo4.pushsection".ident "acomp: (CDS) SPARCompilers 2.type .4 Example 2 This example shows how to use the pseudo-op . .weak foo2 foo2 = foo1 .common .#object foo4.type foo1.size .4 ! with size = 4 bytes .B can be translated into the following assembly code: Code Example B-1 .popsection foo3 foo3.globalfoo1! int foo1 = 1 .align foo4: .word0x1 .data" .word . .comment section of the object file for identification purposes.4.align4 foo1: .ident to generate a string in the .

size.#function sum.type. } can be translated into the following assembly code: . . .align sum: retl add sum 4 %o0. { return(a + b). and .align.B Example 3 The pseudo-ops shown in this example are .section ".-sum Examples of Pseudo-Operations 57 . b.%o0 ! (a + b) is done in the ! delay slot of retl ! ! ! ! ! sum is of type function size of sum is the diff of current location counter and the initial definition of sum .. The following C subroutine: int sum(a.global .text" .%o1. b) int a.type .size sum.global.

B Example 4 The pseudo-ops shown in this example are . [%o0] retl nop . .text" .global main main: save %sp.align.-96.volatile t 0x24 std %g2.L16: .volatile and .1 nop restore Example 5 This example shows how to use the .L16. . .ascii.data1" .%sp set .section.nonvolatile pseudoops to protect a section of handwritten asembly code from peephole optimization.section ".ascii "hello world\n\0" .align 4 .nonvolatile 58 SPARC Assembly Language Reference Manual—November 1995 . and .section ". The example calls the printf function to output the string "hello world".%o0 call printf.

The input file is the concatenation of all the specified files. into an executable object file. and then terminates. the SPARC assembler prints the error (including a synopsis of the command line syntax and options) to standard error output.Using the Assembler Command Line This appendix is organized into the following secitons: Assembler Command Line Assembler Command Line Options Disassembling Object Code page 59 page 60 page 63 C Assembler Command Line You invoke the assembler command line as follows: as [options] [inputfile] . The SPARC assembler recognizes the filename argument hyphen (-) as the standard input. You can use either the as or fbe command to invoke the assembler command line. It accepts more than one file name on the command line... inputfile. 59 . Note – The language drivers (such as cc and f77) invoke the assembler command line with the fbe command. The as command translates the assembly language source files. If an invalid option is given or the command line contains a syntax error. objfile.

For more information about the SPARCworks SourceBrowser. 60 SPARC Assembly Language Reference Manual—November 1995 . #include files. -Ipath When the -P option is in effect. otherwise. -K PIC This option generates position-independent code. see the Browsing Source Code manual. This option has the same functionality as the -k option under the SunOS 4.) Assembler Command Line Options -b This option generates extra symbol table information for the source code browser. the cpp preprocessor also collects browser information. and symbolic substitution through use of the C preprocessor cpp. these options are passed to the cpp preprocessor without interpretation by the as command. they are ignored. -Dname -Dname=def When the -P option is in effect. • If the as command line option -P is set. • If the as command line option -m is set. this option is ignored as the m4 macro processor does not generate browser data. The assembler invokes the preprocessor before assembly begins if it has been specified from the command line as an option. this option is passed to the cpp preprocessor without interpretation by the as command. it is ignored.C The SPARC assembler supports macros. Note – -K PIC and -K pic are equivalent. otherwise. (See the -P option.1 SPARC assembler.

on the files being assembled. -P Run cpp. so it is more useful for complex preprocessing. -o outfile Takes the next argument as the name of the output file to be produced.o suffix is appended to form the ouput file name. -Q{y|n} This option produces the “assembler version” information in the comment section of the output object file if the y option is specified. the . -S[a|C] Produces a disassembly of the emitted code to the standard output. -q This option causes the assembler to perform a quick assembly. -n Suppress all warnings while assembling. not on their concatenation.s suffix. It is recommended that you do not use this option to assemble handwritten assembly language. the information is suppressed. See the m4(1) man page for more information about the m4 macro-processor. Using the Assembler Command Line 61 . The preprocessor is run separately on each input file. if the n option is specified. -m This option runs m4 macro preprocessing on input. in the ELF symbol table. The m4 preprocessor is more powerful than the C preprocessor (invoked by the -P option). Many errorchecks are not performed when -q is specified. the C preprocessor. is removed from the input file and the . including temporary labels that are normally discarded to save space. By default.C -L Saves all symbols. The preprocessor output is passed to the assembler. if present. Note – This option disables many error checks.

otherwise. -Uname When the -P option is in effect. 62 SPARC Assembly Language Reference Manual—November 1995 . the symbol names in SunOS 4.1 assembly files to be assembled on SunOS 5.stab" sections are not stripped out by the static linker ld. -s This option places all stabs in the ". stabs are placed in "stabs. This is the default choice of the -xarch= options.1 assembly files to their corresponding SunOS 5. The resulting object code is in ELF format. this option is passed to the cpp preprocessor without interpretation by the as command. When the -s option is used. which are stripped out by the static linker ld during final execution. -V This option writes the version information on the standard error output.x versions. This option can be used in conjunction with the -S option to convert SunOS 4. By default. With this option.x symbol names. it is ignored.x systems. The resulting object code is in ELF format.1 assembly files will be interpreted as SunOS 5. -T This is a migration option for SunOS 4. stabs remain in the final executable because ".excl" sections. -xarch=v8 This option instructs the assembler to accept instructions defined in the SPARC-V8 architecture.stabs" section.C • Adding the character a to the option appends a comment line to each assembly code which indicates its relative address in its own section. -xarch=v7 This option instructs the assembler to accept instructions defined in the SPARC version 7 (V7) architecture. • Adding the character "C" to the option prevents comment lines from appearing in the output.

C -xarch=v8a This option instructs the assembler to accept instructions defined in the SPARC-V8 architecture. It will not execute on a system with a V8 processor under a Solaris operating environment. “SPARC-V9 Instruction Set. see the "UltraSPARC Programmer’s Reference Manual" and the "UltraSPARC User’s Guide." Disassembling Object Code The dis program is the object code disassembler for ELF. The resulting object code is in ELF format. plus the instructions in the Visual Instruction Set (VIS). It will execute on a system with a V9 processor under a Solaris operating environment." -xarch=v8plusa This option instructs the assembler to accept instructions defined in the SPARC-V9 architecture. less the fsmuld instruction. see the man page dis(1). It will not execute on a system with a V8 processor under a Solaris operating environment. marked to indicate that it uses V9/VIS instructions. For more information regarding SPARC-V9 instructions. see Appendix E. marked to indicate that it uses V9 instructions. For more information about VIS instructions. The resulting object code is in ELF format. It produces an assembly language listing of the object file. Using the Assembler Command Line 63 . For detailed information about this function. The resulting object code is in ELF format. -xarch=v8plus This option instructs the assembler to accept instructions defined in the SPARC-V9 architecture. It will execute on a system with a V9 processor under a Solaris operating environment.

C 64 SPARC Assembly Language Reference Manual—November 1995 .

0.An Example Language Program D The following code shows an example C language program.x operating environment. 65 . Comments have been added to the asembly code to show correspondence to the C code.2 that runs on the Solaris 2. the second example code shows the corresponding assembly code generated by SPARCompiler C 3.

} return(fib_array). } 66 SPARC Assembly Language Reference Manual—November 1995 . &n). unsigned * result. if (n >= MAX_FIB_REPRESENTABLE) { printf("Fibonacci(%d) cannot be represented in a 32 bit word\n". i <= n. i++) { fib_array[i] = prev_number + curr_number. curr_number = fib_array[i]. i. { static unsigned fib_array[MAX_FIB_REPRESENTABLE] = {0. prev_number = curr_number. i < n. int i. unsigned curr_number = 1. please enter n:\n").1}. for (i = 1. i. scanf("%d". i++) printf("Fibonacci (%d) is %u\n". *result++). n). } main() { int n. #define MAX_FIB_REPRESENTABLE 49 /* compute the first n Fibonacci numbers */ unsigned * fibonacci(n) int n. unsigned prev_number = 0. result = fibonacci(n). exit(1). printf("Fibonacci(n):.D The following C Program computes the first n Fibonacci numbers: Figure D-1 C Program Example Source /* a simple program computing the first n Fibonacci numbers */ extern unsigned * fibonacci(). } for (i = 2.

mov. C style comment strings are also permitted n >= MAX_FIB_REPRESENTABLE ? note. */ call exit.%o0 ! if branch not taken. is stored in %i0 upon entry if (n >= MAX_FIB_REPRESENTABLE) { */ cmp %i0. .D The C SPARCompiler generates the following assembler output for the Fibonacci number C source. .2 ! the ".1 mov 1.2" means there are 2 out mov %i0.ascii.%lo(. sethi.49 bl mov .-96. Figure D-2 Assembler Output From C Source ! ! ! ! ! ! ! ! ! a simple program computing the first n Fibonacci numbers.%o0 . ret . . . it's return value will be in %i0 fibonacci() can be referenced outside this file align the beginning of this section to word boundary fibonacci: save /* ! create new stack frame and register ! window for this subroutine ! ! ! ! ! ! note. cmp. bl. . ble. . save.%o0 ! set up 1st.%o1 ! registers used as arguments /* exit(1). Annotation has been added to help you understand the code. bge. 2nd argument in %o0. n). . inc.section.L20). the 1st parameter to fibonacci(). or.align.%sp ! the original source file name ! ! ! ! ! ! ! text section (executable instructions) subroutine fibonacci.word sparc instructions: add.file.global. n.%i4 ! curr_number = 1 An Example Language Program 67 . showing various pseudo-operations.proc .file .skip. i < n.section .text" 79 fibonacci 4 %sp.type. st synthetic instructions: call. %o1. or %o0. .proc. ld. . call printf.size.L77003 0. restore.global . bg.%i2 ! initialization of variable ! prev_number is executed in the ! delay slot /* printf("Fibonacci(%d) cannot be represented in a 32 bits word\n".L20).c" ". */ sethi %hi(. sparc instructions. .align "fibonacci.ident.L77003: ! initialize variables before the loop /* for (i = 2. synthetic instructions pseudo-operations: . call printf(). i++) { */ mov 1.

global main . in delay slot call scanf.%i5 .-fibonacci) ! ! ! ! i = 2 i <= n? if not. with 1st arg. to %o1. please input n:\n").%o1 /* result = fibonacci(n).%i0 bge .%i3 cmp %i3.%lo(.L33).LY1 inc 4.-104. &n). put the variables in registers /* for (i = 1.L16+8).%o0 ! call printf.2 add %fp. */ ld [%i5].i ! %i4 <-.%i2 /* curr_number = fib_array[i].result 68 SPARC Assembly Language Reference Manual—November 1995 .L16).L16).%i0 bl . repeat loop increment ptr to fib_array[] ! return fib_array in %i0 ! ! ! ! ! ! destroy stack frame and register window fibonacci() is of type function size of function: current location counter minus beginning definition of function .%o0 ! some initializations before the for! loop.%lo(.%o0 add %o0.#function fibonacci.1 ld [%fp-4].L31).-4.%lo(.align 4 main: save %sp.%o0 ! call scanf.%i4 inc %i3 cmp %i3.%i5 mov %o0.L33).%o0 /* scanf("%d".L77006: /* return(fib_array).%lo(. with 1st arg in %o0 call printf.%i5 . */ call fibonacci.1 or %o0. */ sethi %hi(.%o0 ! move 2nd arg.[%i5] /* prev_number = curr_number. */ sethi %hi(. return use %i5 to store &fib_array[i] ! loop body */ ! fib_array[i] = prev_number+curr_number ! prev_number = curr_number ! ! ! ! ! curr_number = fib_array[i] i++ i <= n? if yes.L16+8).%i4.%i4 ! %i5 <-.%i2 st %i2.%sp ! create stack frame for main() /* printf("Fibonacci(n):.L77006 sethi %hi(. */ mov %i4.D mov 2.LY1: /* fib_array[i] = prev_number + curr_number.size fibonacci. in %o0 or %o0.%i0 ret restore . i <= n.type . add %i2.(. */ sethi %hi(.proc 18 ! main program . i++) */ mov 1.%o0 add %o0.L31).

%i4 ! result++ .L16.L31: .data" ! switch to data section ! (contains initialized data) .3 mov %i2.type .%o0 ! note.%o0 ! i <= n? cmp %i5.-main) .align 4 ! ascii strings used in the printf stmts "Fibonacci(%d) cannot be represented in a 32 bit w" "ord\n\0" 4 ! align the next ascii string to word ! boundary "Fibonacci(n):.L16: /* static unsigned fib_array[MAX_FIB_REPRESENTABLE] = {0. please enter n:\n\0" 4 An Example Language Program 69 .1}.%o0 inc %i5 ! i++ ld [%fp-4].LY2: ! loop body /* printf("Fibonacci (%d) is %u\n".ascii .type main.%o2 ! call printf.%i2 ld [%fp-4].align 4 .LY2 inc 4.format string for printf add %o0.#function ! type and size of main .%o0 ! %i2 <-. i.(.#object ! storage allocation for the rest of ! fib_array[] . mov %i5.ascii .L38).align 4 ! initialization of first 2 elements .%o0 ! test if (i <= n) ? cmp %i5.align .size main.ascii .data1 section. with (*result) in %o2. format string in %o0 call printf.LE27 nop .section ".word 1 .L20: .L38).skip 188 .word 0 ! of fib_array[] .%o1 ! i in %o1.align . n is stored in [%fp-4] bg .%lo(.%o0 ble . */ ld [%i4].D sethi %hi(.align 4 .section ". */ . *result++).LE27: ret restore . #alloc: memory would be allocated for this section during run time #write: the section contains data that is writeable during process execution .data1" ! ! ! ! ! ! ! the ascii string data are entered into the .

comment section 70 SPARC Assembly Language Reference Manual—November 1995 .ascii .align .ident "%d\0" 4 "Fibonacci (%d) is %u\n\0" "acomp: (CDS) SPARCompilers 2.0 05 Jun 1991" ! an idenitfication string produced ! by the compiler to be entered into ! the .ascii .L38: .L33: .D .

expanded below: registers. 71 . Application software for the 32-bit SPARC-V8 (Version8) architecture can execute. on SPARC-V9 systems. This appendix is organized into the following sections: SPARC-V9 Changes SPARC-V9 Instruction Set Changes SPARC-V9 Instruction Set Mapping SPARC-V9 Floating-Point Instruction Set Mapping SPARC-V9 Synthetic Instruction-Set Mapping SPARC-V9 Instruction Set Extensions page 71 page 74 page 77 page 85 page 87 page 89 SPARC-V9 Changes The SPARC-V9 architecture differs from SPARC-V8 architecture in the following areas. unchanged. byte order. and instruction set.SPARC-V9 Instruction Set E This appendix describes changes made to the SPARC instruction set due to the SPARC-V9 architecture. alternate space access.

These SPARC-V9 registers are within a SPARC-V8 register field: Table E-3 SPARC-V9 Registers Within a SPARC-V8 Register Field CCR CWP PIL TBA TT[MAXTL] VER Condition Codes Register Current Window Pointer Processor Interrupt Level Trap Base Address Trap Type Version These are registers that have been added. and fcc3 (added floatingpoint condition code) bits are added and the register widened to 64-bits. and Y Note – FSR Floating-Point State Register: fcc1. nPC. Table E-4 Registers That have Been Added ASI CANRESTORE CANSAVE Address Space Identifier Restorable Windows Savable windows 72 SPARC Assembly Language Reference Manual—November 1995 .E Registers These registers have been deleted: Table E-1 Deleted SPARC-V8 Privileged Registers PSR TBR WIM Processor State Register Trap Base Register Window Invalid Mask These registers have been widened from 32 to 64 bits: Table E-2 Registers Widened from 32 to 64 bits Integer registers All state registers FSR. PC. fcc2.

f[60] The SPARC-V9. 7f16 are privileged.. FF16 are nonprivileged.CWP’s behavior in SPARC-V8. there are sixteen additional double-precision floating-point registers.E Table E-4 Registers That have Been Added (Continued) CLEANWIN FPRS OTHERWIN PSTATE TICK TL TNPC[MAXTL] TPC[MAXTL] TSTATE[MAXTL] WSTATE Clean Windows Floating-point Register State Other Windows Processor State Hardware clock tick-counter Trap Level Trap Next Program Counter Trap Program Counter Trap State Windows State Also.and store-alternate instructions to one-half of the alternate spaces can now be included in user code. This change has no effect on nonprivileged instructions. These registers overlap (and are aliased with) eight additional quadprecision floating-point registers. access to alternate address spaces is privileged. all data and instruction accesses are performed in big-endian byte order.and big-endian byte orders for data accesses only. Alternate Space Access Load.. f[62]. In SPARC-V9. f[32] . Byte Order SPARC-V9 supports both little. This is the opposite of PSR.. In SPARC-V8. CWP register is decremented during a RESTORE instruction. those to ASIs 8016 . SPARC-V9 Instruction Set 73 . and incremented during a SAVE instruction. f[32] . In SPARC-V8. instruction accesses are always performed using big-endian byte order.. loads and stores to ASIs 0016 .

only affect low-order 32 bits of FSR Same as LD. Extended Instruction Definitions to Support the 64-bit Model Table E-5 Extended Instruction Definitions for 64-bit Model FCMP.access additional registers All other arithmetic operations operate on 64-bit operands and produce 64-bit results. Shifts Tcc Split into 32-bit and 64-bit versions (was Ticc) Operates with either the 32-bit integer condition codes (icc). SLL. FCMPE LDFSR. LDA in SPARC-V8 Read/Write State Registers . SRL. STFSR LDUW. Load/Store FSR. LDUWA RDASR/WRASR SAVE/RESTORE SETHI SRA.E SPARC-V9 Instruction Set Changes Application software written for the SPARC-V8 processor runs unchanged on a SPARC-V9 processor. or the 64-bit integer condition codes (xcc) Floating-Point Compare—can set any of the four floating-point condition codes. 74 SPARC Assembly Language Reference Manual—November 1995 .

double and quad Floating-point Negate. STDF. double and quad Floating-point Absolute Value. CASXA FBPfcc FLUSHW FMOVcc FMOVr LDQF(A). STQF(A) Branch on integer condition code with prediction Branch on integer register contents with prediction Compare and Swap from an alternate space Branch on floating-point condition code with prediction Flush windows Move floating-point register if condition code is satisfied Move floating-point register if integer register satisfies condition Load/Store Quad Floating-point (in an alternate space) SPARC-V9 Instruction Set 75 . and STF Load a signed word Load a signed word from an alternate space Load an extended word Load an extended word from an alternate space Load all 64 bits of the FSR register Store an extended word Store an extended word into an alternate space Store all 64 bits if the FSR register Added Instructions to Support High-Performance System Implementation Table E-7 Added Instructions to Support High-Performance BPcc BPr CASA. STDFA. LDFA. LDF. double and quad Alternate address space forms of LDDF.E Added Instructions to Support 64 bits Table E-6 Added Instructions to Support 64 bits F[sdq]TOx FxTO[sdq] FMOV[dq] FNEG[dq] FABS[dq] LDDFA. STFA LDSW LDSWA LDX LDXA LDXFSR STX STXA STXFSR Convert floating point to 64-bit word Convert 64-bit word to floating point Floating-Point Move.

It is replaced by TBA. WIM has been replaced by several register-window registers PSR no longer exists. It has been replaced by several separate registers that are read/written with other instructions Return from trap (replace by DONE/RETRY) Store Double from Floating-point Queue (replaced by the RDPR FQ instruction Miscellaneous Instruction Changes Table E-9 Miscellaneous Instruction Changes IMPDEPn MEMBAR (Changed) Implementation-dependent instructions (replace SPARC-V8 CPop instructions) (Added) Memory barrier (memory synchronization support) 76 SPARC Assembly Language Reference Manual—November 1995 . which can be read/written with RDPR/WRPR instructions WIM no longer exists. UDIVX Move integer register if condition code is satisfied Move integer register if register contents satisfy condition Generic 64-bit multiply Population count Prefetch Data Signed and Unsigned 64-bit divide Deleted Instructions Table E-8 Deleted Instructions Coprocessor loads and stores RDTBR and WRTBR RDWIM and WRWIM REPSR and WRPSR RETT STDFQ TBR no longer exists. PREFETCHA SDIVX.E Table E-7 Added Instructions to Support High-Performance (Continued) MOVcc MOVr MULX POPC PREFETCH.

a} {.a} {.pn} bleu{. label %icc or %xcc.pt|.pn} bgu{.pt|.a} {.pn} bne{. label %icc or %xcc.pt|.pn} bcc{. label 1 0 not Z Z not (Z or (N xor V)) Z or (N xor V) not (N xor V) N xor V not (C or Z) C or Z not C C not N N not V V SPARC-V9 Instruction Set 77 .a} {.pt|.a} {.pt|. unsigned) Branch on positive Branch on negative Branch on overflow clear Branch on overflow set Comments BPA BPN BPNE BPE BPG BPLE BPGE BPL BPGU BPLEU BPCC BPCS BPPOS BPNEG BPVC BPVS ba{. Table E-10 SPARC-V9 to Assembly Language Mapping Opcode Mnemonic Argument List Operation (Branch on cc with prediction) Branch always Branch never Branch on not equal Branch on equal Branch on greater Branch on less or equal Branch on greater or equal Branch on less Branch on greater unsigned Branch on less or equal unsigned Branch on carry clear (greater than or equal.pn} bg{. label %icc or %xcc.pt|.pn} bge{.a} {.pt|. label %icc or %xcc.pt|.a} {.pn} bpos{.pt|. label %icc or %xcc.pn} bvs{. label %icc or %xcc.pt|.a} {.pt|. label %icc or %xcc.a} {.pn} bn{.pt|.pt|.pn} ble{.pn} bcs{.pn} %icc or %xcc. label %icc or %xcc.pn} bneg{.a} {. label %icc or %xcc.pt|.pn} bvc{.a} {. label %icc or %xcc.a} {. label %icc or %xcc.a} {. label %icc or %xcc. label %icc or %xcc.a} {. label %icc or %xcc. unsigned) Branch on carry set (less than.pn} be{.a} {.a} {.E SPARC-V9 Instruction Set Mapping The following tables describe the SPARC-V9 instruction-set mapping.pn} bl{.pt|.pt|. label %icc or %xcc.

a} {.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode BRZ BRLEZ BRLZ BRNZ BRGZ BRGEZ Mnemonic brz{.pn} brgz{.a} {.pt|.regrs2. label regrs1.pt|.pn} brlez{.regrd [regrs1]%asi.a} {. label regrs1.pn} brgez{. label regrs1.regrd [regrs1]%asi.pt|.pn} casa casa casxa casxa Argument List Operation Branch on register zero Branch on register less than or equal to zero Branch on register less than zero Branch on register not zero Branch on register greater than zero Branch on register greater than or equal to zero Compare and swap word from alternate space Compare and swap extended from alternate space Comments Z N or Z N not Z not (N or Z) not N regrs1. label regrs1.regrs2.a} {. label regrs1.regrs2.a} {. label CASA CASXA [regrs1]imm_asi.pt|.pn} brnz{.regrs2.pt|.regrd 78 SPARC Assembly Language Reference Manual—November 1995 .a} {.pt|.pn} brlz{.regrd [regrs1]imm_asi.

a} {.pt|. label 1 0 U G G or U L L or U L or G L or G or U E E or U E or G E or G or U E or L E or L or u E or L or G FLUSHW Flush register windows SPARC-V9 Instruction Set 79 .pt|. label %fccn. label %fccn.pn} fbuge{. label %fccn.pt|.a} {.pn} fbge{.pt|.a} {.pn} fbul{.pn} fbl{.pt|.pt|.pn} fbue{. label %fccn.pt|.a} {.a} {.a} {. label %fccn.pt|.a} {.pn} fbug{.pt|. label %fccn.pn} fbne{.pn} fbn{. label %fccn.pt|.pn} fbg{.a} {.pn} fbu{.pt|.pn} fbule{.pt|.a} {. label %fccn.pt|. label %fccn.pt|.a} {.pn} flushw %fccn.pn} fble{.a} {. label %fccn.a} {.a} {.a} {. label %fccn.pn} fblg{.a} {.pn} fbe{.a} {.pt|. label %fccn. label %fccn.pt|. label %fccn.pn} fbo{. label %fccn.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode Mnemonic Argument List Operation (Branch on cc with prediction) Branch always Branch never Branch on unordered Branch on greater Branch on unordered or greater Branch on less Branch on unordered or less Branch on less or greater Branch on not equal Branch on equal Branch on unordered or equal Branch on greater or equal Branch on unordered or greater or equal Branch on less or equal Branch on unordered or less or equal Branch on ordered Comments FBPA FBPN FBPU FBPG FBPUG FBPL FBPUL FBPLG FBPNE FBPE FBPUE FBPGE FBPUGE FBPLE FBPULE FBPO fba{.

fregrs2. fregrs2.q}ge fmov {s. q}cs fmov{s. fregrs2. fregrd %icc or %xcc.q}e fmov {s. fregrs2. fregrs2. fregrd %icc or %xcc. fregrd %icc or %xcc. fregrd %icc or %xcc. fregrs2. fregrd %icc or %xcc.d.q}g fmov {s.d.d. fregrs2. q}neg fmov{s. fregrd 1 0 not Z Z not (Z or (N xor V)) Z or (N xor V) not (N xor V) N xor V not (C or Z) C or Z not C C not N N not V V 80 SPARC Assembly Language Reference Manual—November 1995 . q}leu fmov{s.d.d.q}ne fmov {s. fregrs2. fregrd %icc or %xcc.d.d. fregrs2.d.d. fregrd %icc or %xcc. fregrd %icc or %xcc. fregrd %icc or %xcc. q}vs %icc or %xcc. fregrd %icc or %xcc. fregrs2. unsigned) Move if positive Move if negative Move if overflow clear Move if overflow set Comments FMOVA FMOVN FMOVNE FMOVE FMOVG FMOVLE FMOVGE FMOVL FMOVGU FMOVLEU FMOVCC FMOVCS FMOVPOS FMOVNEG FMOVVC FMOVVS fmov {s. q}vc fmov{s.q}gu fmov{s.d.q}l fmov {s. fregrd %icc or %xcc. fregrs2. q}cc fmov{s. q}pos fmov{s. fregrd %icc or %xcc.d.q}n fmov {s.d.q}a fmov {s. fregrs2.q}le fmov {s.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode Mnemonic Argument List Operation (Move on integer cc) Move always Move never Move if not equal Move if equal Move if greater Move if less or equal Move if greater or equal Move if less Move if greater unsigned Move if less or equal unsigned Move if carry clear (greater or equal. fregrd %icc or %xcc. fregrs2.d. fregrs2. fregrd %icc or %xcc. fregrs2.d. unsigned) Move if carry set (less than. fregrs2. fregrd %icc or %xcc.d.d.

q}lz fmovr {s.q}gz fmovr {s.d. fregrs2. fregrd SPARC-V9 Instruction Set 81 .q}gez regrs1.d.q}lz fmovr {s. fregrd regrs1. fregrs2.q}e fmovr {s. fregrs2.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode Mnemonic Argument List Operation (Move f-p register on cc) Move if register zero Move if register less than or equal zero Move if register less than zero Move if register not zero Move if register greater than zero Move if register greater than or equal to zero Comments FMOVRZ FMOVRLEZ FMOVRLZ FMOVRNZ FMOVRGZ FMOVRGEZ fmovr {s.d. fregrs2. fregrd regrs1. fregrd regrs1.q}ne fmovr {s. fregrs2. fregrd regrs1.d. fregrd regrs1.d. fregrs2.d.

fregrs2.fregrd %fccn.fregrd %fccn.fregrs2. q}n fmov{s. q}ul fmov{s. q}g fmov{s.d.d.d.fregrd %fccn.fregrs2.d.fregrs2.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode Mnemonic Argument List Operation (Move on floating-point cc) Move always Move never Move if unordered Move if greater Move if unordered or greater Move if less Move if unordered or less Move if less or greater Move if not equal Move if equal Move if unordered or equal Move if greater or equal Move if unordered or greater or equal Move if less or equal Move if unordered or less or equal Move if ordered Comments FMOVFA FMOVFN FMOVFU FMOVFG FMOVFUG FMOVFL FMOVFUL FMOVFLG FMOVFNE FMOVFE FMOVFUE FMOVFGE FMOVFUGE FMOVFLE FMOVFULE FMOVFO fmov{s.fregrs2.fregrd %fccn. q}a fmov{s. q}le fmov{s.d.d.fregrs2. q}lg fmov{s.fregrd %fccn.fregrd %fccn. q}ge fmov{s. q}uge fmov{s.fregrs2. q}ne fmov{s.fregrd %fccn. regrd Load a signed word Load signed word from alternate space 82 SPARC Assembly Language Reference Manual—November 1995 .d. regrd [regaddr] imm_asi. q}o ldsw ldsw %fccn.fregrs2.fregrs2.d.d.fregrs2. q}ue fmov{s.fregrd %fccn.d.fregrs2.fregrd 1 0 U G G or U L L or U L or G L or G or U E E or U E or G E or G or U E or L E or L or u E or L or G LDSW LDSWA [address].d. q}l fmov{s.d.d.d.fregrs2.fregrs2.fregrd %fccn. q}e fmov{s.fregrs2.fregrd %fccn.fregrd %fccn. q}ug fmov{s. q}u fmov{s.fregrs2.fregrs2.d.fregrd %fccn.d.fregrd %fccn.fregrd %fccn.fregrd %fccn. q}ule fmov{s.

reg_or_imm11. regrd %icc or %xcc. reg_or_imm11. reg_or_imm11. reg_or_imm11. regrd %icc or %xcc. unsigned) Move if positive Move if negative Move if overflow clear Move if overflow set Comments MEMBAR membar membar_mask MOVA MOVN MOVNE MOVE MOVG MOVLE MOVGE MOVL MOVGU MOVLEU MOVCC MOVCS MOVPOS MOVNEG MOVVC MOVVS mova movn movne move movg movle movge movl movgu movleu movcc movcs movpos movneg movvc movvs %icc or %xcc. regrd [address]. reg_or_imm11. regrd %icc or %xcc. regrd %icc or %xcc. regrd %icc or %xcc.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode LDX LDXA LDXFSR Mnemonic ldx ldxa ldxa ldx Argument List [address]. reg_or_imm11. reg_or_imm11. reg_or_imm11. reg_or_imm11. reg_or_imm11. regrd %icc or %xcc. regrd %icc or %xcc. %fsr Operation Load extended word Load extended word from alternate space Load floating-point state register Memory barrier (Move integer register on cc) Move always Move never Move if not equal Move if equal Move if greater Move if less or equal Move if greater or equal Move if less Move if greater unsigned Move if less or equal unsigned Move if carry clear (greater or equal. regrd 1 0 not Z Z not (Z or (N xor V)) Z or (N xor V) not (N xor V) N xor V not (C or Z) C or Z not C C not N N not V V SPARC-V9 Instruction Set 83 . regrd %icc or %xcc. reg_or_imm11. unsigned) Move if carry set (less than. regrd %icc or %xcc. regrd %icc or %xcc. reg_or_imm11. regrd %icc or %xcc. regrd %icc or %xcc. reg_or_imm11. regrd %icc or %xcc. reg_or_imm11. regrd %icc or %xcc. reg_or_imm11. regrd %icc or %xcc. regrd [reg_plus_imm] %asi. reg_or_imm11. regrd [regaddr] imm_asi.

reg_or_imm11.reg_or_imm11.reg_or_imm11.regrd %fccn.reg_or_imm11.reg_or_imm11.regrd %fccn.reg_or_imm11.regrd %fccn.reg_or_imm11.regrd %fccn. prefetch_dcn [regaddr] imm_asi.regrd G or L or L or L or G or E or E or E or G or 1 0 U G U L U G U E U G U E or L E or L or u E or L or G MOVRZ MOVRLEZ MOVRLZ MOVRNZ MOVRGZ MOVRGEZ movre movrlez movrlz movrnz movrgz movrgez regrs1.regrd regrs1.regrd reg_or_imm.regrd %fccn. prefetch_fcn See SDIVX and UDIVX 84 SPARC Assembly Language Reference Manual—November 1995 . reg_or_imm10.reg_or_imm11.reg_or_imm11.regrd %fccn.reg_or_imm11.regrd %fccn.regrd %fccn. reg_or_imm10. reg_or_imm10.reg_or_imm11.reg_or_imm11. reg_or_imm10. prefetch_fcn [reg_plus_imm] %asi.regrd regrs1. regrd [address].regrd %fccn.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode Mnemonic Argument List Operation (Move on floating-point cc) Move always Move never Move if unordered Move if greater Move if unordered or greater Move if less Move if unordered or less Move if less or greater Move if not equal Move if equal Move if unordered or equal Move if greater or equal Move if unordered or greater or equal Move if less or equal Move if unordered or less or equal Move if ordered (Move register on register cc) Move if register zero Move if register less than or equal to zero Move if register less than zero Move if register not zero Move if register greater than zero Move if register greater than or equal to zero (Generic 64-bit Multiply) Multiply (signed or unsigned) Population count Prefetch data Prefetch data from alternate space See The SPARC architecture manual.regrd regrs1. reg_or_imm10.regrd %fccn. version 9 Comments MOVFA MOVFN MOVFU MOVFG MOVFUG MOVFL MOVFUL MOVFLG MOVFNE MOVFE MOVFUE MOVFGE MOVFUGE MOVFLE MOVFULE MOVFO mova movn movu movg movug movl movul movlg movne move movue movge movuge movle movule movo %fccn.regrd %fccn.regrd regrs1.regrd Z N or Z N not Z N nor Z not N MULX POPC PREFETCH PREFETCHA mulx popc prefetch prefetcha prefetcha regrs1.reg_or_imm11.reg_or_imm11.regrd %fccn.regrd %fccn.reg_or_imm11.reg_or_imm11.regrd regrs1.regrd %fccn.regrd %fccn. reg_or_imm10. reg_or_imm.

reg_or_imm. [reg_plus_imm] %asi %fsr. fregrs2. [address] imm_asi regrd. [address] regrd. fregrs2.regrd See MULX and UDIVX STX STXA STXFSR stx stxa stxa stx regrd. fregrs2. fregrs2. [address] Store extended word Store extended word into alternate space Store floating-point register (all 64-bits) (64-bit unsigned divide) Unsigned divide UDIVX udivx regrs1. reg_or_imm.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode Mnemonic Argument List Operation (64-bit signed divide) Signed Divide Comments SDIVX sdivx regrs1. fregrs2. fregrd fregrd fregrd fregrd fregrd fregrd Description Convert floating point to 64-bit integer Convert floating-point to 32-bit integer * Types of Operands are denoted by the following lower-case letters: i 32-bit integer x 64-bit integer s single d double q quad SPARC-V9 Instruction Set 85 . regrd See MULX and SDIVX SPARC-V9 Floating-Point Instruction Set Mapping SPARC-V9 floating-point instructions are shown in Table E-11 Table E-11 SPARC-V9 Floating-Point Instructions SPARC F[sdq]TOx Mnemonic fstox fdtox fqtox fstoi fdtoi fqtoi * Argument List fregrs2.

Load quad floating-point register from alternate space Store floating-point register to alternate space Store double floating-point register to alternate space Store quad floating-point register to alternate space FNEG[dq] FABS[dq] LDFA LDDFA LDQFA STFA STDFA STQFA * Types of Operands are denoted by the following lower-case letters: i 32-bit integer x 64-bit integer s single d double q quad 86 SPARC Assembly Language Reference Manual—November 1995 . fregrd [regaddr] imm_asi. fregrd fregrd fregrd fregrd fregrd fregrd Description Convert 64-bit integer to floating point Convert 32-bit integer to floating point FMOV[dq] fregrs2. fregrd fregrs2. fregrs2. fregrd fregrs2. fregrs2. fregrs2. fregrs2. fregrs2. fregrd fregrd. fregrd [regaddr] imm_asi.E Table E-11 SPARC-V9 Floating-Point Instructions (Continued) SPARC FxTO[sdq] Mnemonic* fxtos fxtod fxtoq fitos fitod fitoq fmovd fmovq fnegd fnegq fabsd fabsq lda lda ldda ldda ldqa ldqa sta sta stda stda stqa stqa Argument List fregrs2. fregrd [reg_plus_imm] %asi. fregrd. fregrd fregrs2. fregrd [reg_plus_imm] %asi. [regaddr] imm_asi [reg_plus_imm] %asi [regaddr] imm_asi [reg_plus_imm] %asi [regaddr] imm_asi [reg_plus_imm] %asi Move double Move quad Negate double Negate quad Absolute value double Absolute value quad Load floating-point register from alternate space Load double floating-point register from alternate space. fregrd fregrs2. fregrd. fregrd fregrs2. fregrd. fregrd [reg_plus_imm] %asi. fregrd. fregrd. fregrd [regaddr] imm_asi.

%asrn %i7+8.regrd sethi or sethi or %hi(value). extended Clear extended word Copy and clear upper word Clear upper word Instruction prefetch. regrd. regrs2. regrs2. regrs2. %g0 %o7+8. %g0. regrd %g0. regrd [regrsl]ASI_P_L. regrs2. regrd %g0. regrd reg_or_imm. regrd [regrsl]ASI_P_L. regrd %asrn. regrd [regrsl]ASI_P. regrd. [address] regrs1. [regrsl]. regrd %g0. regrs2. regrd regrd regrd regrd Hardware Equivalent(s) casa casa casxa casxa [regrsl]ASI_P. regrd regrd label %y. pt rd rd wr jmpl jmpl setuw value. regrd SPARC-V9 Instruction Set 87 . %g0. regrs2. %lo(value).E SPARC-V9 Synthetic Instruction-Set Mapping Here is a mapping of synthetic instructions to hardware equivalent instructions. regrd %hi(value). regrs2. label %y. %g0 Return from subroutine Return from leaf subroutine (value & 3FF16)==0 when 0 ≤ value ≤ 4095 (otherwise) Do not use setuw in a DCTI delay slot. regrd %asrn. value. Table E-12 SPARC-V9 Synthetic Instructions to Hardware Instruction Synthetic Instruction cas casl casx casxl [regrsl]. regrd regrd. regrd %xcc. clrx clruw clruw iprefetch mov mov mov ret retl [address] regrs1. [regrsl]. Comment Compare & swap (cas) cas little-endian cas extended cas little-endian. [regrsl]. regrs2. %asrn stx srl srl bn. reg_or_imm.

regrd. Sign-extend 32-bit value to 64 bits signx signx regrsl. regrd %hi(value). regrd %hi(value). if value>=0) (otherwise. regrd regrd. %g0.regrd Hardware Equivalent(s) sethi or sethi sra sethi or sethi or sra %hi(value). %lo(value). regrd Comment value>=0 and (value & 3FF16)==0 -4096 ≤ value ≤ 4095 if (value<0) and ((value & 3FF)==0) (otherwise. %lo(value).E Table E-12 SPARC-V9 Synthetic Instructions to Hardware Instruction (Continued) Synthetic Instruction setsw value. value. %g0. regrd. regrd regrd. regrd %hi(value). regrd. regrd regrsl. %g0. regrd regrd. if value<0) Do not use setsw in a CTI delay slot. regrd regrd sra sra 88 SPARC Assembly Language Reference Manual—November 1995 . regrd %g0. regrd. %g0.

Fixed Data Formats A 64-bit word contains four 16-bit signed fixed-point values. This is the fixed 16-bit data format. This is the fixed 32bit data format. You should use floating-point data to perform complex calculations needing more precision or dynamic range. Intermediate results are 16 or 32 bits. SPARC-V9 Instruction Set 89 .E SPARC-V9 Instruction Set Extensions This section describes extensions to the SPARC-V9 instruction set. R). so the graphics instructions are optimized for short-integer arithmetic. Note – SPARC-V9 instruction set extensions used in executables may not be portable to other SPARC-V9 systems. Support is provided for band interleaved images (store color components of a point). Image components are 8 or 16 bits. Pixel multiplication is used to convert from pixel data to fixed data. Pack instructions are used to convert from fixed data to pixel data (clip and truncate to an 8-bit unsigned value). Rounding is done by adding one to the rounding bit position. The FPACKFIX instruction supports conversion from 32-bit fixed to 16-bit fixed. A 64-bit word contains two 8-bit signed fixed-point values. Enough precision and dynamic range (for filtering and simple image computations on pixel values) can be provided by an intermediate format of fixed data values. Graphics Data Formats The overhead of converting to and from floating-point arithmetic is high. The extensions support enhanced graphics functionality and improved memory access efficiency. and band sequential images (store all values of one color component). B. Eight-bit Format A 32-bit word contains pixels of four unsigned 8-bit integers. The integers represent image intensity values (α. G.

regrd regrs1. Table E-14 Graphics Status Register SPARC RDASR WRASR Mnemonic rdasr wrasr Argument List %gsr. There are 32 double-precision registers. Table E-13 SPARC-V9 SHUTDOWN Instruction SPARC SHUTDOWN Mnemonic shutdown Argument List Description shutdown to enter power down mode Graphics Status Register (GSR) You use ASR 0x13 instructions RDASR and WRASR to access the Graphics Status Register. %gsr Description read GSR write GSR Graphics Instructions Unless otherwise specified. reg_or_imm. Single-precision floatingpoint registers contain the pixel values. and double-precision floating-point registers contain the fixed values.E SHUTDOWN Instruction All outstanding transactions are completed before the SHUTDOWN instruction completes. floating-point registers contain all instruction operands. The opcode space reserved for the Implementation-Dependent Instruction1 (IMPDEP1) instructions is where the graphics instruction set is mapped. 90 SPARC Assembly Language Reference Manual—November 1995 .

fregrd fregrd fregrd fregrs2. fregrd fregrd fregrd fregrd fregrd fregrd fregrd Description 8x16-bit partition 8x16-bit upper α partition 8x16-bit lower α partition upper 8x16-bit partition lower unsigned 8x16-bit partition upper 8x16-bit partition lower unsigned 8x16-bit partition SPARC-V9 Instruction Set 91 . fregrs2. fregrs1. fregrs2. fregrs1. fregrs2. fregrs2. fregrs1. fregrs2. fregrd fregrs2. Table E-17 SPARC-V9 Partitioned Multiply SPARC FMUL8x16 FMUL8x16AU FMUL8x16AL FMUL8SUx16 FMUL8ULx16 FMULD8SUx16 FMULD8ULx16 Mnemonic fmul8x16 fmul8x16au fmul8x16al fmul8sux16 fmul8ulx16 fmuld8sux16 fmuld8ulx16 Argument List fregrs1. fregrs2.E Partitioned add/subtract instructions perform two 32-bit or four 16-bit partitioned adds or subtracts between the source operands corresponding fixed point values. fregrs1. fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd Description four 16-bit add two 16-bit add two 32-bit add one 32-bit add four 16-bit subtract two 16-bit subtract two 32-bit subtract one 32-bit subtract Pack instructions convert to a lower pixel or precision fixed format. fregrs1. fregrs2. fregrs1. fregrs1. fregrs2. fregrs1. Table E-16 SPARC-V9 Pixel Formatting SPARC FPACK16 FPACK32 FPACKFIX FEXPAND FPMERGE Mnemonic fpack16 fpack32 fpackfix fexpand fpmerge Argument List fregrs2. fregrs2. fregrd Description four 16-bit packs two 32-bit packs four 16-bit packs four 16-bit expands two 32-bit merges Partitioned multiply instructions have the following variations. fregrs1. fregrs2. fregrs2. fregrs2. fregrs2. fregrs1. fregrs1. fregrs2. fregrs1. fregrs1. Table E-15 SPARC-V9 Partitioned Add/Subtract SPARC FPADD16 FPADD16S FPADD32 FPADD32S FPSUB16 FPSUB16S FPSUB32 FPSUB32S Mnemonic fpadd16 fpadd16s fpadd32 fpadd32s fpsub16 fpsub16s fpsub32 fpsub32s Argument List fregrs1. fregrs2. fregrs2. fregrs1. fregrs2. fregrs1.

fregrd Description find misaligned data access address same as above. but little-endian do misaligned data. data alignment 92 SPARC Assembly Language Reference Manual—November 1995 . regrs2.E Alignment instructions have the following variations. regrs2. Table E-18 SPARC-V9 Alignment Instructions SPARC ALIGNADDRESS ALIGNADDRESS_ LITTLE FALIGNDATA Mnemonic alignaddr alignaddrl faligndata Argument List regrs1. fregrs2. regrd regrs1. regrd fregrs1.

fregrs1. single precision negate src1. fregrs1.E Logical operate instructions perform one of sixteen 64-bit logical operations between rs1 and rs2 (in the standard 64-bit version). single precision src1 OR negated src2 same as above. fregrs2. fregrs1. single precision negated src1 OR src2 same as above. single precision copy src1 copy src1. single precision logical XOR logical XOR. 1’s complement same as above. single precision logical AND logical AND. fregrs1. fregrs2. fregrs1. fregrs1. fregrs2. single precision negated src1 AND src2 same as above. fregrs2. fregrs1. fregrs2. fregrs1. fregrs2. single precision src1 AND negated src2 same as above. single precision fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrs2. single precision logical NAND logical NAND. fregrs2. fregrs1. fregrs1. fregrs2. fregrs2. fregrs2. single precision logical XNOR logical XNOR. 1’s complement same as above. fregrs2. fregrs2. fregrs2. fregrs2. fregrs1. fregrs2. fregrs1. fregrs1. fregrs2. fregrs2. fregrs2. fregrs1. fregrs2. Description zero fill zero fill. fregrs1. single precision copy src2 copy src2. single precision negate src2. fregrs1. fregrs2. fregrs2. single precision one fill one fill. fregrs2. fregrs1. fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd SPARC-V9 Instruction Set 93 . fregrs1. Table E-19 SPARC-V9 Logical Operate Instructions SPARC FZERO FZEROS FONE FONES FSRC1 FSRC1S FSRC2 FSRC2S FNOT1 FNOT1S FNOT2 FNOT2S FOR FORS FNOR FNORS FAND FANDS FNAND FNANDS FXOR FXORS FXNOR FXNORS FORNOT1 FORNOT1S FORNOT2 FORNOT2S FANDNOT1 FANDNOT1S FANDNOT2 FANDNOT2S Mnemonic fzero fzeros fone fones fsrc1 fsrc1s fsrc2 fsrc2s fnot1 fnot1s fnot2 fnot2s for fors fnor fnors fand fands fnand fnands fxor fxors fxnor fxnors fornot1 fornot1s fornot2 fornot2s fandnot1 fandnot1s fandnot2 fandnot2s Argument List fregrd fregrd fregrd fregrd fregrs1. fregrs1. single precision logical OR logical OR. fregrs1. fregrs2. single precision logical NOR logical NOR. fregrs1. fregrs1. fregrs1.

regrs1. fregrs2. little-endian Pixel component distance instructions are used for motion estimation in video compression algorithms. compare. SPARC-V9 Pixel Component Distance Instruction SPARC PDIST Mnemonic pdist Argument List fregrs1. compare.E Pixel compare instructions compare fixed-point values in rs1 and rs2 (two 32 bit or four 16 bit) Table E-20 SPARC-V9 Pixel Compare SPARC FCMPGT16 FCMPGT32 FCMPLE16 FCMPLE32 FCMPNE16 FCMPNE32 FCMPEQ16 FCMPEQ32 Mnemonic fcmpgt16 fcmpgt32 fcmple16 fcmple32 fcmpne16 fcmpne32 fcmpeq16 fcmpeq32 Argument List fregrs1. Table E-21 SPARC V-9 Edge Handling SPARC EDGE8 EDGE8L EDGE16 EDGE16L EDGE32 EDGE32L Mnemonic edge8 edge8l edge16 edge16l edge32 edge32l Argument List regrs1. fregrs1. compare. fregrs1. regrs2. set set set set set set set set rd rd rd rd rd rd rd rd if if if if if if if if src1>src2 src1>src2 src1≤src2 src1≤src2 src1≠src2 src1≠src2 src1=src2 src1=src2 Edge handling instructions handle the boundary conditions for parallel pixel scan line loops. compare. fregrs2. fregrs2. regrd regrd regrd regrd regrd regrd Description 8 8-bit edge boundary processing same as above. regrs2. regrd regrd regrd regrd regrd regrd regrd regrd Description 4 2 4 2 4 2 4 2 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit compare. regrs1. regrs2. fregrs1. regrs1. compare. fregrs1. regrs2. compare. fregrs2. compare. little-endian 4 16-bit edge boundary processing same as above. fregrd Description 8 8-bit components. fregrs2. regrs1. fregrs1. fregrs2. distance between 94 SPARC Assembly Language Reference Manual—November 1995 . regrs2. fregrs1. fregrs2. regrs2. little-endian 2 32-bit edge boundary processing same as above. fregrs1. fregrs2. regrs1. fregrs2.

regrs2. regrs2. regrd regrs1. Table E-22 SPARC V-9 Three-Dimensional Array Addressing SPARC ARRAY8 ARRAY16 ARRAY32 Mnemonic array8 array16 array32 Argument List regrs1. but 16-bit same as above. regrd regrs1. regrs2.The result is stored in rd. regrd Description convert 8-bit 3-D address to blocked byte address same as above. but 32-bit SPARC-V9 Instruction Set 95 .E The three-dimensional array addressing instructions convert threedimensional fixed-point addresses (in rs1) to a blocked-byte address.

Table E-23 SPARC-V9 Partial Store SPARC imm_asi Argument List Description eight 8-bit conditional stores to: primary address space secondary address space primary address space. little endian four 16-bit conditional stores to: primary address space secondary address space primary address space. [fregrs1] regmask. little endian two 32-bit conditional stores to: primary address space secondary address space primary address space. little endian secondary address space. use one of the partial store ASIs with the STDA instruction. imm_asi Note – To select a partial store instruction. little endian secondary address space. little endian STDFA STDFA STDFA STDFA STDFA STDFA STDFA STDFA STDFA STDFA STDFA STDFA ASI_PST8_P ASI_PST8_S ASI_PST8_PL ASI_PST8_SL ASI_PST16_P ASI_PST16_S ASI_PST16_PL ASI_PST16_SL ASI_PST32_P ASI_PST32_S ASI_PST32_PL ASI_PST32_SL stda fregrd.E Memory Access Instructions These memory access instructions are part of the SPARC-V9 instruction set extensions. 96 SPARC Assembly Language Reference Manual—November 1995 . little endian secondary address space.

freqrd stda [reg_plus_imm] %asi ASI_FL8_S secondary address space ASI_FL8_PL primary address space. [reg_addr] imm_asi ldda [reg_plus_imm] %asi. regrd 128-bit atomic load. regrd Description 128-bit atomic load LDDA [reg_plus_imm] %asi. little endian 16-bit load/store from/to: primary address space ASI_FL16_P ASI_FL16_S secondary address space ASI_FL16_PL primary address space. little endian ASI_FL16_SL secondary address space.E Table E-24 SPARC-V9 Short Floating-Point Load and Store SPARC imm_asi Argument List Description 8-bit load/store from/to: primary address space LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA ASI_FL8_P ldda [reg_addr] imm_asi. freqrd stda freqrd. little endian ASI_FL8_SL secondary address space. little endian SPARC-V9 Instruction Set 97 . use one of the short ASIs with the LDDA and STDA instructions Table E-25 SPARC-V9 Atomic Quad Load SPARC LDDA imm_asi ASI_NUCLEUS_ QUAD_LDD ASI_NUCLEUS_ QUAD_LDD_L Argument List [reg_addr] imm_asi. little endian Note – To select a short floating-point load and store instruction.

[reg_plus_imm] %asi ASI_BLK_AIUS secondary address space. little endian secondary address space. user privilege little endian primary address space ASI_BLK_AIUSL ASI_BLK_P ASI_BLK_S secondary address space ASI_BLK_PL primary address space. little endian ASI_BLK_COMMIT_P 64-byte block commit store to primary address space 64-byte block commit store to secondary address space ASI_BLK_COMMIT_S Note – To select a block load and store instruction. user privilege.E Table E-26 SPARC-V9 Block Load and Store SPARC imm_asi Argument List Description 64-byte block load/store from/to: primary address space. freqrd stda fregrd. user privilege. [reg_addr] imm_asi ldda [reg_plus_imm] %asi. user privilege LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA ASI_BLK_AIUP ldda [reg_addr] imm_asi. use one of the block transfer ASIs with the LDDA and STDA instructions. freqrd stda freqrd. 98 SPARC Assembly Language Reference Manual—November 1995 . little endian ASI_BLK_SL secondary address space. ASI_BLK_AIUPL primary address space.

multiple. 41 current location. 4 syntax notation. 9 . 5 hexadecimal. 27 coprocessor instruction.double. 40 cp_disabled trap. 59 assembler command line options. 22 . 25 default output file.byte. 10 converting existing object files. 5 octal numeric.Index A addresses. 11 dis program. 60 comment lines. 73 D -D option. 5 comment lines. 24 assembly language. 46 C case distinction. 40 cp_exception trap. 63 disassembling object code. 25 atof(3). 3 lines. 45 as command. 3 assignment directive. 45 assembler command line. 5. 5 floating-point. 60 assembler directives.align. 5 Control Transfer Instructions (CTI). 4 99 . 49 case distinction.common.alias. 5 decimal. 5 . 45 . 60 data generating directives. 45 byte order for V9. 8 cc language driver. 59 . in special symbols. 46. 45 . 4 statements. 46 constants.asciz. 24 types. 59 command-line options.ascii. 14 B binary operations. 63 . 21 current section.

47 M -m option. used by assembler. 4 floating-point instructions. 59 lexical features. 4 . 6 Executable and Linking Format (ELF) files. 13 . 5 invoking. 5 multiple files. 59 fbe command. 13 shentsize. 13 phoff.globl. 13 shoff. 10 error messages.empty.global. 47 instruction set changes (V9). 61 labeling format. 29 instructions assembly language. 39 floating-point pseudo-operations. 31 integer suffixes. 2 labels. 59 multiple sections. 13 shnum. 12 entry. 21 locations. 4 lines syntax.file. lexical. 61 multiple comment lines. 60 . 29 100 SPARC Assembly Language Reference Manual—November 1995 . 59 I -I option. 5 language drivers. 13 version. 59 features.ident. 46 . 89 instruction set. 46 file syntax. 10 escape codes. 13 phnum. 12 ident. 9 hardware integer assembly language instructions. 47 . 5 G . 31 hardware integer. 21 F f77 language driver. as command. 60 L -L option. in strings. 47 hardware instructions SPARC architecture. 47 location counter. 31 hyphen (-). 12 flag. 59 K -K option. 12 phentsize.local.half. 31 integer instructions.empty pseudo-operation. 4 . 74 instruction set extensions (V9). 11 expressions. 15 multiple strings in string table. 24 H . 13 type.E ELF header. on as command line. 12 to 13 ehsize. 12 machine. 13 shstrndx. 2.

60 . 7 . 61 .nonvolatile. 48 pseudo-operations. 19 . 89 instruction set mapping. 51 O -o option. 15 addralign. 55 . 89 floating-point instructions. 2 object files type. 73 fixed data formats. 61 -q option. 5 special names.skip. 48 Q -Q option. 2. 9 . 50 . 61 object file format. 15 flags.pushsection. 17 sections. 5 . 22 Index 101 . 48 numbers. 89 alternate space access. 15 entsize. 45 . 72 synthetic instruction set. 2. 16 size. 25 section control pseudo-ops. 16 name. 7 . 73 byte order. 85 graphics data formats. 16 offset.N . 51 SPARC-V9. 15 to 18 addr. 11 operators. 5 special symbols. 51 .noalias. 60 P -P option.stabs. 11 relocation tables. 49 section control directives. 49 S -S option.proc.size. 5 numeric labels.seg. 77 registers. 25 section header. 48 predefined non-user sections. 7 relocatable files. 16 info. 49 R references. 71 8-bit format. 16 type. 61 -s option. floating point values. 61 percentage sign (%). 16 link. 51 . 48 . 48 options command-line. 62 -sb option. 74 instruction set extensions. 20 predefined user sections. 89 instruction set changes.reserve. 45 pseudo-ops examples of.optim.single. 14 . 50 .noalias pseudo-op.quad.stabn. xii registers. 87 special floating-point values.section.popsection.

6 multiple in string table. 22 syntax notation.weak. 9 user sections. 24 suggested style.statement syntax.word. 6 symbol table. 51 U -U option. 4 string tables.uahalf. 23 name. 25 /usr/include/sys/trap. 22 to 23 info. 63 . 52 X -xarch=v7 option. 62 -xarch=v8a option. 30 trap numbers. 51 .h. 37 V -V option. 41 . 24 strings. 52 T -T option. 22 symbol tables. 62 -xarch=v8 option.version.xstabs. 37 . 51 unary operators. 23 size. 24 sub-strings in string table references to. 24 multiple references in string table. 52 . 25 symbol names. 53 symbol attribute directives. 6 unreferenced in string table. 62 . 23 value.type. 52 W . 52 102 SPARC Assembly Language Reference Manual—November 1995 . 23 shndx. 22 other. 24 symbol. 3 synthetic instructions. 62 .volatile.uaword. 63 -xarch=v8plus option. 62 table notation. 63 -xarch=v8plusa option. reserved.

Toutes les marques SPARC sont des marques deposées ou enregitrées de SPARC International. s’il en a. microSPARC II et UltraSPARC sont exclusivement licenciées a Sun Microsystems. Inc. Inc. CES CHANGEMENTS SERONT INCORPORES AUX NOUVELLES EDITIONS DE LA PUBLICATION. SPARCengine. UNIX est une marque enregistrée aux Etats-Unis et dans d’autres pays.227. Inc. DES GARANTIES CONCERNANT LA VALEUR MARCHANDE. par quelque moyen que ce soit sans l’autorisation préalable et écrite de Sun et de ses bailleurs de licence. L’APTITUDE DES PRODUITS A REPONDRE A UNE UTILISATION PARTICULIERE OU LE FAIT QU’ILS NE SOIENT PAS CONTREFAISANTS DE PRODUITS DE TIERS. licencié par UNIX Systems Laboratories Inc. Inc. SUN MICROSYSTEMS INC. Y COMPRIS. Sun Microsystems. Sun reconnait les efforts de pionniers de Xerox pour la recherche et le développement du concept des interfaces d’utilisation visuelle ou graphique pour l’industrie de l’informatique. et qui comprend la technologie relative aux polices de caractères. Inc. Le système X Window est un produit du X Consortium. CETTE PUBLICATION PEUT CONTENIR DES MENTIONS TECHNIQUES ERRONEES OU DES ERREURS TYPOGRAPHIQUES. est protégé par un copyright et licencié par des fourmisseurs de Sun. Aucune partie de ce produit ou de sa documentation associée ne peuvent Être reproduits sous aucune forme. et exclusivement licenciée par X/Open Company Ltd. Solaris sont des marques deposées ou enregistrées par Sun Microsystems.. la copie et la décompliation. aux Etats-Unis et dans d’autres pays. pour ses utilisateurs et licenciés. ET SANS QUE CETTE LISTE NE SOIT LIMITATIVE. Inc. SPARCdesign. SPARC811.7013 et FAR 52. filiale entierement detenue par Novell. CETTE PUBLICATION EST FOURNIE "EN L’ETAT" SANS GARANTIE D’AUCUNE SORTE. Les produits portant les marques sont basés sur une architecture développée par Sun Microsytems. Inc. Des parties de ce produit pourront etre derivees du système UNIX®. SPARCprinter. etranger(s) ou par des demandes en cours d’enregistrement. SPARCompiler. la duplication ou la divulgation par l’administation americaine sont soumises aux restrictions visées a l’alinéa (c)(1)(ii) de la clause relative aux droits des données techniques et aux logiciels informatiques du DFAR 252. SPARCstorage.227-19. Le produit décrit dans ce manuel peut Être protege par un ou plusieurs brevet(s) americain(s).. Tous droits réservés. Inc. Mountain View. SPARCworks. microSPARC. Sun détient une licence non exclusive de Xerox sur l’interface d’utilisation graphique. PostScript et Display PostScript sont des marques d’Adobe Systems. 2550 Garcia Avenue.. le logo Sun. aux EtatsUnis et dans certains autres pays.Ce produit ou document est protégé par un copyright et distribué avec des licences qui en restreignent l’utilisation. de Berkeley. SPARCcluster. . licencié par l’Université de Californie. cette licence couvrant aussi les licencies de Sun qui mettent en place OPEN LOOK GUIs et qui en outre se conforment aux licences écrites de Sun. DES CHANGEMENTS SONT PERIODIQUEMENT APPORTES AUX INFORMATIONS CONTENUES AUX PRESENTES. SPARstation. Le logiciel détenu par des tiers.Copyright 1995 Sun Microsystems. PEUT REALISER DES AMELIORATIONS ET/OU DES CHANGEMENTS DANS LE(S) PRODUIT(S) ET/OU LE(S) PROGRAMME(S) DECRITS DANS DETTE PUBLICATION A TOUS MOMENTS. SPARCserver. LEGENDE RELATIVE AUX DROITS RESTREINTS : l’utilisation. SPARCcenter. Les utilisateurs d’interfaces graphiques OPEN LOOK® et Sun™ ont été développés par Sun Microsystems. NI EXPRESSE NI IMPLICITE. Californie 94043-1100 USA.3. Inc. MARQUES Sun. ainsi que par le système 4. Inc. OPEN LOOK est une marque enregistrée de Novell.

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