SPARC Assembly Language Reference Manual

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© 1995 Sun Microsystems, Inc. 2550 Garcia Avenue, Mountain View, California 94043-1100 U.S.A. All rights reserved. This product or document is protected by copyright and distributed under licenses restricting its use, copying, distribution and decompilation. No part of this product or document may be reproduced in any form by any means without prior written authorization of Sun and its licensors, if any. Portions of this product may be derived from the UNIX® system, licensed from UNIX Systems Laboratories, Inc., a wholly owned subsidiary of Novell, Inc., and from the Berkeley 4.3 BSD system, licensed from the University of California. Third-party software, including font technology in this product, is protected by copyright and licensed from Sun’s Suppliers. RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013 and FAR 52.227-19. The product described in this manual may be protected by one or more U.S. patents, foreign patents, or pending applications. TRADEMARKS Sun, Sun Microsystems, the Sun logo, SunSoft, the SunSoft logo, Solaris, SunOS, OpenWindows, DeskSet, ONC, ONC+, and NFS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. OPEN LOOK is a registered trademark of Novell, Inc. PostScript and Display PostScript are trademarks of Adobe Systems, Inc.All SPARC trademarks are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. SPARCcenter, SPARCcluster, SPARCompiler, SPARCdesign, SPARC811, SPARCengine, SPARCprinter, SPARCserver, SPARCstation, SPARCstorage, SPARCworks, microSPARC, microSPARC-II, and UltraSPARCare licensed exclusively to Sun Microsystems, Inc. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. The OPEN LOOK® and Sun™ Graphical User Interfaces were developed by Sun Microsystems, Inc. for its users and licensees. Sun acknowledges the pioneering efforts of Xerox in researching and developing the concept of visual or graphical user interfaces for the computer industry. Sun holds a non-exclusive license from Xerox to the Xerox Graphical User Interface, which license also covers Sun’s licensees who implement OPEN LOOK GUI’s and otherwise comply with Sun’s written license agreements. X Window System is a trademark of X Consortium, Inc. THIS PUBLICATION IS PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. THIS PUBLICATION COULD INCLUDE TECHNICAL INACCURACIES OR TYPOGRAPHICAL ERRORS. CHANGES ARE PERIODICALLY ADDED TO THE INFORMATION HEREIN, THESE CHANGES WILL BE INCORPORATED IN NEW EDITIONS OF THE PUBLICATION. SUN MICROSYSTEMS, INC. MAY MAKE IMPROVEMENTS AND/OR CHANGES IN THE PRODUCT(S) AND/OR THE PROGRAMS(S) DESCRIBED IN THIS PUBLICATION AT ANY TIME.

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Contents
Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Before You Read This Book. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How This Book is Organized . . . . . . . . . . . . . . . . . . . . . . . . . . . . What Typographic Changes Mean. . . . . . . . . . . . . . . . . . . . . . . . Shell Prompts in Command Examples . . . . . . . . . . . . . . . . . . . . 1. SPARC Assembler for SunOS 5.x. . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC Assembler for SunOS 4.1 Versus SunOS 5.x . . . . . . . . . Labeling Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Object File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pseudo-Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Assembler Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Syntax Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi xii xii xiii xiv 1 1 1 2 2 2 2 2 3 3

iii

Assembler File Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lines Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Statement Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lexical Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case Distinction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Symbol Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Symbols - Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Operators and Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembler Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. Executable and Linking Format . . . . . . . . . . . . . . . . . . . . . . . . . ELF Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Predefined User Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . Predefined Non-User Sections . . . . . . . . . . . . . . . . . . . . . . . . Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relocation Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Symbol Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . String Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 4 4 4 4 5 5 5 6 6 7 9 10 11 12 14 15 19 20 21 22 22 22 24

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Assembler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Section Control Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . Symbol Attribute Directives . . . . . . . . . . . . . . . . . . . . . . . . . . Assignment Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Generating Directives . . . . . . . . . . . . . . . . . . . . . . . . . . 4. Converting Files to the New Format . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. Instruction-Set Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Floating-Point Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coprocessor Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synthetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A. Pseudo-Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alphabetized Listing with Descriptions . . . . . . . . . . . . . . . . . . . B. Examples of Pseudo-Operations. . . . . . . . . . . . . . . . . . . . . . . . . C. Using the Assembler Command Line . . . . . . . . . . . . . . . . . . . . Assembler Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assembler Command Line Options . . . . . . . . . . . . . . . . . . . . . . Disassembling Object Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D. An Example Language Program . . . . . . . . . . . . . . . . . . . . . . . . . E. SPARC-V9 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24 25 25 25 25 27 27 27 28 29 30 31 39 40 41 45 45 55 59 59 60 63 65 71

Contents

v

SPARC-V9 Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate Space Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Byte Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC-V9 Instruction Set Changes . . . . . . . . . . . . . . . . . . . . . . .

71 72 73 73 74

Extended Instruction Definitions to Support the 64-bit Model 74 Added Instructions to Support 64 bits . . . . . . . . . . . . . . . . . ementation Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deleted Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Instruction Changes . . . . . . . . . . . . . . . . . . . . SPARC-V9 Instruction Set Mapping . . . . . . . . . . . . . . . . . . . . . . SPARC-V9 Floating-Point Instruction Set Mapping . . . . . . . . . SPARC-V9 Synthetic Instruction-Set Mapping. . . . . . . . . . . . . . SPARC-V9 Instruction Set Extensions . . . . . . . . . . . . . . . . . . . . . Graphics Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eight-bit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fixed Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SHUTDOWN Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graphics Status Register (GSR) . . . . . . . . . . . . . . . . . . . . . . . Graphics Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Access Instructions . . . . . . . . . . . . . . . . . . . . . . . . . Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 75 76 76 77 85 87 89 89 89 89 90 90 90 96 99

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Predefined Non-User Sections. . . . . . . . . . . . Symbol Bindings . . . . 6 7 9 14 16 17 19 20 23 24 30 31 32 39 41 41 vii . . . . . . . . Floating-Point Instructions. . . . . . . . Operators Recognized in Constant Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commonly Suffixed Notations . . . . . . . . . . . . . . . . . . . . . . Synthetic Instruction to Hardware Instruction Mapping . . Special Symbol Names . . . . . . . . . . . . . . . . . . . . . . . . Notations Used to Describe Instruction Sets . . . . . . . . . . . Section Attribute Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tables Table 2-1 Table 2-2 Table 2-3 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Escape Codes Recognized in Strings . . . Predefined User Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC to Assembly Language Mapping . . . . . . . . Symbol Types . . . . . . . . . . . . . . . . . . . . . . . Section Types . . . . . . . . Reserved Object File Types . . . . . . . . . . . . . . Coprocessor-Operate Instructions . . .

. . . . . SPARC-V9 Pixel Formatting . . . . . . . . . . . . . . . . . SPARC-V9 Registers Within a SPARC-V8 Register Field . . SPARC-V9 Short Floating-Point Load and Store . SPARC V-9 Edge Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers That have Been Added . . . SPARC-V9 Synthetic Instructions to Hardware Instruction . . . . . . . . . . . . . . . . . . . . SPARC-V9 Partial Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC-V9 Alignment Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Instruction Definitions for 64-bit Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC-V9 Pixel Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . .Table E-1 Table E-2 Table E-3 Table E-4 Table E-5 Table E-6 Table E-7 Table E-8 Table E-9 Table E-10 Table E-11 Table E-12 Table E-13 Table E-14 Table E-15 Table E-16 Table E-17 Table E-18 Table E-19 Table E-20 Table E-21 Table E-22 Table E-23 Table E-24 Table E-25 Deleted SPARC-V8 Privileged Registers . . . . . 72 72 72 72 74 75 75 76 76 77 85 87 90 90 91 91 91 92 93 94 94 95 96 97 97 viii SPARC Assembly Language Reference Manual—November 1995 . . . . . . . . . SPARC-V9 Partitioned Add/Subtract . . . . . . Miscellaneous Instruction Changes . . . . . . . . . . . . . . SPARC-V9 Partitioned Multiply . . . . . . . . . . . . . . . . . . . . . . . . SPARC V-9 Three-Dimensional Array Addressing. . . . . . . . . . . . . . Deleted Instructions . . . . Added Instructions to Support 64 bits . . . . Graphics Status Register . . . . . . . . . . . . . . Added Instructions to Support High-Performance . . . . . . . SPARC-V9 to Assembly Language Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers Widened from 32 to 64 bits . . . . . SPARC-V9 Atomic Quad Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC-V9 Logical Operate Instructions . . . . . . . . . SPARC-V9 SHUTDOWN Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . SPARC-V9 Floating-Point Instructions . . . . . . . . . . . .

. . . . . . . . . . . . . . .Table E-26 SPARC-V9 Block Load and Store . 98 Tables ix . . . . . . . . .

x SPARC Assembly Language Reference Manual—November 1995 .

the assembler is a tool to use in producing program modules intended to exploit features of the SPARC architecture in ways that cannot be easily done using high level languages and their compilers. referred to as the “SunOS SPARC” in this manual. Furthermore.Preface This preface provides a brief description of the SunOS™ assembler that runs on the SPARC® operating environment and also includes a list of documents that can be used for reference. the assembler responds to directives that allow the programmer direct control over the contents of the relocatable object file. xi . translates source files that are in assembly language format into object files in linking format. The assembler may also be used in connection with SunOS 5. Whether assembly language is chosen for the development of program modules depends on the extent to which and the ease with which the language allows the programmer to control the architectural features of the processor. The SunOS assembler that runs on the SPARC operating environment.x macro preprocessors to achieve full macro-assembler capability. The assembly language described in this manual offers full direct access to the SPARC instruction set. In the program development process.

Chapter 4. This facilitates the development of programs that are easy to understand and maintain. The nature of the machine mnemonics governs the way in which the program’s executable portion is written. Before You Read This Book You should also become familiar with the following: • • • • Manual pages: as(1). “Assembler Syntax.x SPARC Assembler. Chapter 5.” describes the syntax of the SPARC assembler that takes assembly programs and produces relocatable object files for processing by the link editor.x.” lists the pseudo-operations supported by the SPARC assembler. “Executable and Linking Format. “Converting Files to the New Format. “Instruction-Set Mapping.” describes the relationship between hardware instructions of the SPARC architecture and the assembly language instruction set. Chapter 3. “SPARC Assembler for SunOS 5. Chapter 2.x assembly file format.1 SPARC assembly files to the SunOS 5. cpp(1). Appendix A.out(1) SPARC Architecture Manual (Version 8 and Version 9) ELF-related sections of the Programming Utilities Guide manual SPARC Applications Binary Interface (ABI) How This Book is Organized This book is organized as follows: Chapter 1. ld(1). elf(3f).” describes how to convert existing SunOS 4.This document describes the language in which the source files must be written. dis(1). xii SPARC Assembly Language Reference Manual—November 1995 .” discusses features of the SunOS 5. a. “Pseudo-Operations. This document includes descriptions of the pseudo operations that allow control over the object file.” describes the relocatable ELF files that hold code and data suitable for linking with other object files.

Appendix B. Use ls -a to list all files. type rm filename. Appendix E. contrasted with on-screen computer output Command-line placeholder: replace with a real name or value Book titles. machine_name% su Password: To delete a file. or words to be emphasized Example Edit your . Preface xiii . files. AaBbCc123 AaBbCc123 AaBbCc123 Read Chapter 6 in User’s Guide. “SPARC-V9 Instruction Set. on-screen computer output What you type. You must be root to do this. new words or terms. These are called class options. Table P-1 Typeface or Symbol AaBbCc123 Typographic Conventions Meaning The names of commands. “Using the Assembler Command Line. What Typographic Changes Mean The following table describes the typographic changes used in this book. and directories. Appendix D. Appendix C.” describes the SPARC-V9 instruction set and the changes due to the SPARC-V9 implementation.” describes an example C language program with comments to show correspondence between the assembly code and the C code.login file.” describes the available assembler command-line options.” shows some examples of ways to use various pseudo-operations. “Examples of Pseudo-Operations. “An Example Language Program. machine_name% You have mail.

Table P-2 Shell C shell prompt C shell superuser prompt Bourne shell and Korn shell prompt Bourne shell and Korn shell superuser prompt Shell Prompts Prompt machine_name% machine_name# $ # xiv SPARC Assembly Language Reference Manual—November 1995 . Bourne shell.Shell Prompts in Command Examples The following table shows the default system prompt and superuser prompt for the C shell. and Korn shell.

It is included as part of the SPARCworks/SPARCompiler Floating Point and Common Tools AnswerBook.x operating system or the Solaris™ 2. Version 8. This document contains information from The SPARC Architecture Manual.x refers to the Solaris 2. 1 . This document is distributed as part of the developer documentation set with every SunOS operating system release.0 users who have products that run on the SunOS 5.x Introduction 1 This chapter discusses features of the SunOS 5.x refers to SunOS 5.2 operating environment and later releases. “SPARC-V9 Instruction Set. SunOS 5.x operating system.x SPARC assembler.” Operating Environment The SunOS SPARC assembler runs under the SunOS 5.2 operating system and later releases. Solaris 2. Information about Version 9 support is summarized in Appendix E. This document is also distributed with the on-line documentation set for the convenience of SPARCworks™ and SPARCompiler™ 4.SPARC Assembler for SunOS 5.x operating environment. which is the on-line information retrieval system.

• Names beginning with an underscore (_) are reserved by ANSI C.x This section describes the differences between the SunOS 4.) are assumed to be local symbols. Labeling Format • Symbol names beginning with a dot (.1 Versus SunOS 5. Pseudo-Operations See Appendix A.” for a detailed description of the pseudo-operations (pseudo-ops). “Pseudo-Operations.x SPARC assembler. and are the assembler normal output. Object File Format The type of object files created by the SPARC assembler are ELF (Executable and Linking Format) files. These relocatable object files hold code and data suitable for linking with other object files to create an executable file or a shared object file. “Using the Assembler Command Line. Command Line Options See Appendix C.1 SPARC assembler and the SunOS 5. 2 SPARC Assembly Language Reference Manual—November 1995 .” for a detailed description of command line options and a list of SPARC architectures.1 SPARC Assembler for SunOS 4.

Newline characters are not allowed in place of blanks. 3 .Assembler Syntax 2 The SunOS 5.x SPARC link editor. Braces ({ }) enclose alternate item choices. The assembly language described in this document corresponds to the SPARC instruction set defined in the SPARC Architecture Manual (Version 8 and Version 9) and is intended for use on machines that use the SPARC architecture. Asterisks (*) indicate items to be repeated zero or more times. arbitrary numbers of blanks and horizontal tabs may be used. which are separated from each other by vertical bars (|). as specified in this document.x SPARC assembler takes assembly language programs. and produces relocatable object files for processing by the SunOS 5. This chapter is organized into the following sections: Syntax Notation Assembler File Syntax Lexical Features Assembler Error Messages page 3 page 4 page 4 page 10 Syntax Notation In the descriptions of assembly language syntax in this chapter: • • • • Brackets ([ ]) enclose optional items. Wherever blanks are allowed.

2 Assembler File Syntax The syntax of assembly language files is: [line]* Lines Syntax The syntax of assembly language lines is: [statement [ . statement]*] [!comment] Statement Syntax The syntax of an assembly language statement is: [label:] [instruction] where: label is a symbol name. 4 SPARC Assembly Language Reference Manual—November 1995 . synthetic instruction. or instruction. Special symbol names have no case distinction. Case Distinction Uppercase and lowercase letters are distinct everywhere except in the names of special symbols. Lexical Features This section describes the lexical features of the assembler syntax. instruction is an encoded pseudo-op.

Labels A label is either a symbol or a single decimal digit n (0…9). A label is immediately followed by a colon ( : ). Numeric labels may be defined repeatedly in an assembly file. and before its definition (forward reference) as nf. the exclamation mark character and all following characters up to the end of the line are ignored. C language-style comments (‘‘/*…*/’’) are also permitted and may span multiple lines. However. Numbers Decimal. normal symbolic labels may be defined only once.2 Comments A comment is preceded by an exclamation mark character (!). For floating-point pseudo-operations. floating-point constants are written with 0r or 0R (where r or R means REAL) followed by a string acceptable to atof(3). and octal numeric constants are recognized and are written as in the C language. Negative Not-A-Number and Negative INFinity are specified as 0r-nan and 0r-inf. Note – The names of these floating-point constants begin with the digit zero. an optional sign followed by a non-empty string of digits with optional decimal point and optional exponent. that is. The special names 0rnan and 0rinf represent the special floating-point values Not-A-Number (NaN) and INFinity.” Assembler Syntax 5 . integer suffixes (such as L) are not recognized. A numeric label n is referenced after its definition (backward reference) as nb. not the letter “O. hexadecimal.

’a’-’A’. | digit }* In the above syntax: 6 SPARC Assembly Language Reference Manual—November 1995 .. Description Alert Backspace Form feed Newline (line feed) Carriage return Horizontal tab Vertical tab Octal value nnn Hexadecimal value nn. When used in an expression. Symbol Names The syntax for a symbol name is: { letter | _ | $ | . The sequence must not include a newline character.%g1 ! g1 + (’a’ .. An example of assembly code in the suggested style is: add %g1. and double quote mark characters for quoted-string operands such as used by pseudo-ops. are recognized in strings. Table 2-1 Escape Codes Recognized in Strings Escape Code \a \b \f \n \r \t \v \nnn \xnn. derived from ANSI C.. the numeric value of a string is the numeric value of the ASCII representation of its first character.2 Strings A string is a sequence of characters quoted with either double-quote mark (") or single-quote mark (’) characters.. } { letter | _ | $ | .’A’) --> g1 The escape codes described in Table 2-1. The suggested style is to use single quote mark characters for the ASCII value of a single character.

External variable names beginning with the underscore character are reserved by the ANSI C Standard. Symbol names that begin with a dot ( . the program will not conform to ANSI C and unpredictable behavior may result. The symbol dot ( . Table 2-2 Special Symbol Names Symbol Object General-purpose General-purpose General-purpose General-purpose General-purpose registers global registers out registers local registers in registers Name %r0 %g0 %o0 %l0 %i0 %sp %fp %f0 … %f31 %fsr %fq %c0 … %c31 %csr %cq %psr %tbr %wim %y … … … … … %r31 %g7 %o7 %l7 %i7 Comment Same Same Same Same as as as as %r0 %r8 %r16 %r24 … … … … %r7 %r15 %r23 %r31 Stack-pointer register Frame-pointer register Floating-point registers Floating-point status register Front of floating-point queue Coprocessor registers Coprocessor status register Coprocessor queue Program status register Trap vector base address register Window invalid mask Y register (%sp = %o6 = %r14) (%fp = %i6 = %r30) Assembler Syntax 7 . otherwise. Do not begin these names with the underscore. Table 2-2 lists these special symbol names. the underscore ( _ ). ) are treated as alphabetic characters.2 • • • • Uppercase and lowercase letters are distinct. avoid using this type of symbol name in hand-coded assembly language routines. To simplify debugging. dollar sign ($). ) are assumed to be local symbols. and dot ( .Registers Special symbol names begin with a percentage sign (%) to avoid conflict with user symbols. ) is predefined and always refers to the address of the beginning of the current assembly language statement. Special Symbols .

The lack of case distinction allows for the use of non-recursive preprocessor substitutions.2 Table 2-2 Special Symbol Names (Continued) Symbol Object Unary operators Name %lo %hi %r_disp32 %r_plt32 Comment Extracts least significant 10 bits Extracts most significant 22 bits Used only in Sun compiler-generated code. Used only in Sun compiler-generated code. %PSR is equivalent to %psr The suggested style is to use lowercase letters. Ancillary state registers %asr1 … %asr31 There is no case distinction in special symbols. for example: #define psr %PSR 8 SPARC Assembly Language Reference Manual—November 1995 . for example.

as other unary operators. Used in Sun compiler-generated code only to instruct the assembler to generate specific relocation information for the given expression. Table 2-3 Operators Recognized in Constant Expressions Binary + – * / % ^ Operators Integer addition Integer subtraction Integer multiplication Integer division Modulo Exclusive OR Unary + – ~ %lo %hi %r_disp32 Operators (No effect) 2's Complement 1's Complement Extract least significant 10 bits Extract most significant 22 bits Used in Sun compiler-generated code only to instruct the assembler to generate specific relocation information for the given expression. << Left shift %r_plt32 >> Right shift Assembler Syntax 9 . have higher precedence than binary operations. enclose operands of the %hi or %lo operators in parentheses. For example: %hi(a) + b Operators and Expressions The operators described in Table 2-3 are recognized in constant expressions.2 The special symbols %hi and %lo are true unary operators which can be used in any expression and. For example: %hi a+b %lo a+b = = (%hi a)+b (%lo a)+b To avoid ambiguity.

10 SPARC Assembly Language Reference Manual—November 1995 . you can insert an . If you have intentionally written code this way. put expressions in parentheses to avoid ambiguity. These warnings are: • • • Set synthetic instructions in delay slots Labels in delay slots Segments that end in control transfer instructions These warnings point to places where a problem could exist.%lo. The modulo operator is typically followed by a space or left parenthesis character.empty pseudo-operation in a delay slot tells the assembler that the delay slot can be empty or can contain whatever follows because you have verified that either the code is correct or the content of the delay slot does not matter. Certain conditions will cause the assembler to issue warnings associated with delay slots following Control Transfer Instructions (CTI). The . or %r_plt32 operators.2 Table 2-3 Operators Recognized in Constant Expressions (Continued) Binary & | Operators Bitwise AND Bitwise OR Unary Operators Since these operators have the same precedence as in the C language. the modulo operator % must not be immediately followed by a letter or digit.empty pseudo-operation immediately after the control transfer instruction. %r_disp32. To avoid confusion with register names or with the %hi. Assembler Error Messages Messages generated by the assembler are generally self-explanatory and give sufficient information to allow correction of a problem.

Executable and Linking Format 3 The type of object files created by the SPARC assembler version for SunOS 5. under the -V option). This chapter is organized into the following sections: ELF Header Sections Locations Relocation Tables Symbol Tables Addresses String Tables Assembler Directives page 12 page 14 page 21 page 22 page 22 page 22 page 24 page 24 The ELF object file format consists of: • • Header Sections 11 .x are now Executable and Linking Format (ELF) files. The SPARC assembler creates a default output file when standard input or multiple files are used. and are the assembler normal output. These relocatable ELF files hold code and data suitable for linking with other object files to create an executable or a shared object file. The assembler can also write information to standard output (for example. under the -S option) and to standard error (for example.

The initial bytes of an ELF header specify how the file is to be interpreted. A value of 2 specifies SPARC. A value of 0 indicates no associated entry point. see Chapter 4. ident Marks the file as an object file and provides machine-independent data to decode and interpret the file contents. “Object Files. ELF Header The ELF header is always located at the beginning of the ELF file. entry Virtual address at which the process is to start. 12 SPARC Assembly Language Reference Manual—November 1995 .” in the System V Application Binary Interface (SPARC™ Processor Supplement) manual. flag Processor-specific flags associated with the file. machine Specifies the required architecture for an individual file. It describes the ELF file organization and contains the actual sizes of the object file control structures.3 • • • • • Locations Addresses Relocation tables Symbol tables String tables For more information. The ELF header contains the following information: ehsize ELF header size in bytes.

all entries are the same size. A value of SHN_UNDEF indicates the file does not have a section name string table. phnum Number of entries in program header table. A value of 0 indicates the file has no section header table. phoff Program header table file offset in bytes. shoff Section header table file offset in bytes. All entries are the same size. shstrndx Section header table index of the entry associated with the section name string table. A value of 0 indicates the file has no program header table. Executable and Linking Format 13 . Table 3-1 describes the reserved object file types. The value of 0 indicates no section header. A section header is one entry in the section header table. shentsize Size in bytes of the section header.3 phentsize Size in bytes of entries in the program header table. type Identifies the object file type. shnum Number of entries in section header table. version Identifies the object file version. The value of 0 indicates no program header.

a section header does not need to be followed by a section. 1. Every section must have one section header describing the section.3 Table 3-1 shows reserved object file types: Table 3-1 Type none rel exec dyn core loproc hiproc Reserved Object File Types Value 0 1 2 3 4 0xff00 0xffff Description No file type Relocatable file Executable file Shared object file Core file Processor-specific Processor-specific Sections A section is the smallest unit of an object that can be relocated. Each section occupies one contiguous sequence of bytes within a file. 14 SPARC Assembly Language Reference Manual—November 1995 . These sections contain all other information in an object file and satisfy several conditions. The following sections are commonly present in an ELF file: • • • • • Section header Executable text Read-only data Read-write data Read-write uninitialized data (section header only) Sections do not need to be specified in any particular order. However. The section may be empty (that is. 2. of zero-length). The current section is the section to which code is generated.

An entry in a section header table contains information characterizing the data in a section. shared data. Note – Not all of the sections need to be present. An object file may have inactive space. A value of 0 or 1 indicates no address alignment constraints. for example. Section Header The section header allows you to locate all of the file sections. the entire section must be ensured double-word alignment. The contents of the data in the inactive space are unspecified. The section header contains the following information: addr Address at which the first byte resides if the section appears in the memory image of a process. userdefined sections. Sections in a file cannot overlap. 4. if a section contains a double-word. A byte in a file can reside in only one section. or information in the object file for debugging. the default value is 0. Sections can be added for multiple text or data segments. addralign Aligns the address if a section has an address alignment constraint. Executable and Linking Format 15 . entsize Size in bytes for entries in fixed-size tables such as the symbol table. Only 0 and positive integral powers of 2 are currently allowed.3 3.

This attribute is off if a control section does not reside in the memory image of the object file. Default Value 0x1 0x2 SHF_EXECINSTR SHF_MASKPROC 0x4 0xf0000000 info Extra information. The interpretation of this information depends on the section type. name Specifies the section name. Occupies memory during process execution. size Specifies the size of the section in bytes. as described in Table 3-3. Table 3-2 Flag SHF_WRITE SHF_ALLOC Section Attribute Flags Description Contains data that is writable during process execution. link Section header table index link. The interpretation of this information depends on the section type. 16 SPARC Assembly Language Reference Manual—November 1995 . Table 3-2 describes the section attribute flags. as described in Table 3-3. Reserved for processor-specific semantics. An index into the section header string table section specifies the location of a null-terminated string. Note – If the section type is SHT_NOBITS.3 flags One-bit descriptions of section attributes. offset Specifies the byte offset from the beginning of the file to the first byte in the section. Contains executable machine instructions. offset specifies the conceptual placement of the file.

Contains relocation entries with explicit addends. type Categorizes the section contents and semantics. link symtab 2 strtab 3 rela 4 hash 5 Contains a symbol rehash table. it may contain many unnecessary symbols. the section still occupies no space in the file. The section header index of the section to which the relocation applies. One greater than the symbol table index of the last local symbol. 0 The section header index of the associated symbol table. A file may have multiple relocation sections. The section header index of the string table used by entries in the section. Contains information defined explicitly by the program. Contains a symbol table for link editing.3 Note – If the section type is SHT_NOBITS. Table 3-3 Name Value Section Types Interpretation by Description info null progbits 0 1 Marks section header as inactive. however. however. A file may have multiple string table sections. Note: Only one section of this type is allowed in a file dynamic 6 Contains dynamic linking information. Table 3-3 describes the section types. The section header index of the associated string table. size may be non-zero. Note: Only one section of this type is allowed in a file Contains a string table. This table may also be used for dynamic linking. Note: Only one section of this type is allowed in a file 0 Executable and Linking Format 17 . The section header index of the symbol table to which the hash table applies.

a section of this type does not occupy any space in the file. Contains information defined explicitly by the program. The section header index of the associated symbol table. One greater than the symbol table index of the last local symbol. Contains relocation entries without explicit addends. Note: Section types in this range may be used by an application without conflicting with system-defined section types.3 Table 3-3 Name Value Section Types (Continued) Interpretation by Description info note 7 Contains information that marks the file. Contains a symbol table with a minimal set of symbols for dynamic linking. The section header index of the section to which the relocation applies. however. Lower and upper bound of range reserved for application programs. loproc hiproc louser hiuser 0x70000000 0x7fffffff 0x80000000 0xffffffff Note – Some section header table indexes are reserved and the object file will not contain sections for these special indexes. Note: Only one section of this type is allowed in a file Lower and upper bound of range reserved for processor-specific semantics. The section header index of the associated string table. link nobits 8 rel 9 shlib dynsym 10 11 Reserved. 18 SPARC Assembly Language Reference Manual—November 1995 . A file may have multiple relocation sections.

Table 3-4 lists the predefined user sections that can be named in the section control directives. Section contains initialized read-write data.line .section ".fini .rodata & . Creating an .rodata1 .init" . Section contains read-only data.comment .init Section in an Object File The .text .init section in an object file.init .data & . Section contains runtime finalization instructions. Section Name . Section contains note information. To create an .3 Predefined User Sections A section that can be manipulated by the section control directives is known as a user section. Section contains line # info for symbolic debugging.data1 .init Section Executable and Linking Format 19 .bss . Table 3-4 Predefined User Sections Description Section contains uninitialized read-write data.align 4 <instructions> Code Example 3-1 Creating an . Comment section. use the assembler pseudo-ops shown in Code Example 3-1. Section contains debugging information.note Section contains executable text.init sections contain codes that are to be executed before the the main program is executed. You can use the section control directives to change the user section in which code or data is generated.debug . . Section contains runtime initialization instructions.

section ".o files are concatenated into a . the .init section. Section Name ". Do not reference or store to locations that are greater than %sp+96 in the .fini sections contain codes that are to be executed after the the main program is executed.fini Section in an Object File . Creating a .o files are concatenated into an .fini Section At link time.init section in the linker output file.dynamic" 20 SPARC Assembly Language Reference Manual—November 1995 . Note – The codes are executed inside a stack frame of 96 bytes.fini section in an object file.fini section are executed after the main program is executed.fini sections in a sequence of .init section are executed before the main program is executed. To create an . The code in the . Note – The codes are executed inside a stack frame of 96 bytes. .fini section.fini" .align 4 <instructions> Code Example 3-2 Creating an . Table 3-5 Predefined Non-User Sections Description Section contains dynamic linking information. use the assembler pseudo-ops shown in Code Example 3-2.fini section in the linker output file.3 At link time. the . The codes in the .init sections in a sequence of . Do not reference or store to locations that are greater than %sp+96 in the . Predefined Non-User Sections Table 3-5 lists sections that are predefined but cannot be named in the section control directives because they are not under user control.

Executable and Linking Format 21 .plt .text".3 Table 3-5 Predefined Non-User Sections (Continued) Description Section contains strings needed for dynamic linking. that is.interp .symtab Locations A location is a specific position within a section.relaname .shstrtab . Section contains the dynamic linking symbol table. Section containing relocation information. the .rel. Section contains a symbol table. Each location is identified by a section and a byte offset from the beginning of the section. Section contains the path name of a program interpreter. . ". Section Name . name is the section to which the relocations apply. When a section control directive (for example.got . the location information from the location counter associated with the new section is assigned to and stored with the name and value of the current location. Section contains the global offset table. Section contains a symbol hash table. ". Section contains the string table. The current location is updated at the end of processing each statement.section pseudo-op) is processed.strtab .text".hash .relname & .rela. but can be updated during processing of data-generating assembler directives (for example. The current location is the location within the current section where code is generated.dynstr .word pseudo-op).dynsym . String table for the section header table names. A location counter tracks the current offset within each section where code or data is being generated. Section contains the procedure linking table.

for example. The SPARC assembler creates a symbol table section for the object file. Symbol Tables A symbol table contains information to locate and relocate symbolic definitions and references. This value is dependent on the context. adjustments to data in the section) to be performed by the link editor. Symbolic references to these locations must be changed to addresses by the SPARC link editor. otherwise. Addresses Locations represent addresses in memory if a section is allocatable. A value of zero indicates the symbol table entry has no name. The section header contains the symbol table index for the first non-local symbol. 22 SPARC Assembly Language Reference Manual—November 1995 . Relocation Tables The assembler produces a companion relocation table for each relocatable section. the value represents the string table index that gives the symbol name. its contents are to be placed in memory at program runtime. It makes an entry in the symbol table for each symbol that is defined or referenced in the input file and is needed during linking. only one location can be current at any time. value Value of the associated symbol. The table contains a list of relocations (that is. if more than one section is present. that is. or it may be an absolute value. it may be an address. A symbol table contains the following information: name Index into the object file symbol string table.3 Note – Each section has one location counter. The symbol table is then used by the SPARC link editor during relocation.

As a section moves during relocation. Symbol is associated with a function or other executable code. info Specifies the symbol type and binding attributes. shndx Contains the section header table index to another relevant section. if specified. the link editor automatically creates a procedure linkage table entry for the referenced symbol. These types of symbols are primarily used for relocation. Table 3-6 Value 0 1 Type notype object Symbol Types Description Type not specified. other Undefined meaning. references to the symbol will continue to point to the same location because the value of the symbol will change as well. A value of 0 indicates that the symbol has either no size or an unknown size. Symbol is associated with a data object. When another object file references a function from a shared object. a variable or an array. Table 3-6 and Table 3-7 describes these values. Current value is 0. Values reserved for processor-specific semantics. Symbol is associated with a section.3 size Size of symbol. Gives the name of the source file associated with the object file. 2 func 3 section 4 13 15 file loproc hiproc Executable and Linking Format 23 . for example.

• • A string table index may refer to any byte in the section. in the object file. the index referencing this section must contain zero.3 Table 3-7 shows the symbol binding attributes. however. Assembler Directives Assembler directives. symbol names and file names. Symbol is either defined externally or defined in the object file and accessible in other files. Empty string table sections are permitted. Values reserved for processor-specific semantics. Local symbols of the same name may exist in multiple files. and unreferenced strings are allowed. Table 3-7 Value 0 Symbol Bindings Description Symbol is defined in the object file and not accessible in other files. The strings are referenced in the section header as indexes into the string table section. Binding local 1 global 2 weak 13 15 loproc hiproc String Tables A string table is a section which contains null-terminated variable-length character sequences. are commands to the assembler that may or may not result in the generation of code. these definitions have a lower precedence than globally defined symbols. however. Symbol is either defined externally or defined in the object file and accessible in other files. or strings. The different types of assembler directives are: • • • Section Control Directives Symbol Attribute Directives Assignment Directives 24 SPARC Assembly Language Reference Manual—November 1995 . for example. References to substrings may exist. A string may appear multiple times and may also be referenced multiple times. or pseudo-operations (pseudo-ops).

Symbol Attribute Directives The symbol attribute pseudo-ops declare the symbol type and size and whether it is local or global. The section control pseudo-ops allow you to make entries in this table. and string table sections are created implicitly. This directive constitutes a definition of the symbol and. Section Control Directives When a section is created. The section symbol has an offset value of zero. Data Generating Directives The data generating directives are used for allocating storage and loading values.3 • • Data Generating Directives Optimizer Directives See Appendix A. The section control pseudo-ops cannot be used to manipulate these sections. must be the only definition of the symbol. “Pseudo-Operations. Assignment Directive The assignment directive associates the value and type of expression with the symbol and creates a symbol table entry for the symbol. You can also use the section control directives to change the user section in which code or data is generated. a section header is generated and entered in the ELF object file section header table.” for a complete description of the pseudo-ops supported by the SPARC assembler. therefore. Note – The symbol table. Sections that can be manipulated with the section control directives are known as user sections. Executable and Linking Format 25 . relocation table. The section control directives also create a section symbol which is associated with the location at the beginning of each created section.

3 26 SPARC Assembly Language Reference Manual—November 1995 .

section. Conversion Instructions • Remove the leading underscore ( _ ) from symbol names.1.” for more information.x SPARC assembly language begin with a dot (. change . • • Note – The above conversions can be automatically achieved by passing the -T option to the assembler. ) so that they will not conflict with user programs’ symbol names. for example. “Pseudo-Operations.seg to .data. 27 . See Appendix A.section .Converting Files to the New Format Introduction 4 This chapter discusses how to convert existing SunOS 4. The Solaris 2. Prefix local symbol names with a dot (.1 SPARC assembly files to the SunOS 5.x SPARCompilers do not prepend a leading underscore to symbol names in the users’ programs as did the SPARCompilers that ran under SunOS 4.) .x SPARC assembly file format.seg data to . Local symbol names in the SunOS 5. Change the usage of the pseudo-op .

align .seg "text" set L16.proc 04 .seg "data1" .section ".section .%lo(LF12).align 4 _main: !#PROLOGUE# 0 sethi %hi(LF12).%o0 call _printf.LE12: ret restore .%sp !#PROLOGUE# 1 .%g1 save %sp.%lo(.L16: .LP12 = 96 .proc .global _main .ascii "hello world\n" .1 nop LE12: ret restore .text" 04 main .%g1.data1" 4 "hello world\n" ".L16.optim "-O~Q~R~S" . The lines that are different in the new format are marked with change bars.LST12 = 96 .text" set .%g1 add %g1. Example 4.%o0 call printf.section .LF12).%g1 add %g1.LT12 = 96 Change bars Figure 4-1 Converting a 4.%g1 save %sp.optim "-O~Q~R~S" LF12 = -96 LP12 = 96 LST12 = 96 LT12 = 96 .LF12).ascii .LF12 = -96 .%g1.4 Examples Figure 4-1 shows how to convert an existing 4.align 4 main: !#PROLOGUE# 0 sethi %hi(.%sp !#PROLOGUE# 1 L14: .1 nop .align 4 L16: .x File to the New Format 28 SPARC Assembly Language Reference Manual—November 1995 .seg "text" .global ".1 file to the new format.L14: .x File Converted to the New Format .

” 29 . “SPARC-V9 Instruction Set.x SPARC assembler. as defined in The SPARC Architecture Manual and the assembly language instruction set recognized by the SunOS 5. Table Notation Integer Instructions Floating-Point Instruction Coprocessor Instructions Synthetic Instructions page 30 page 31 page 39 page 40 page 41 The SPARC-V9 instruction set is described in Appendix E.Instruction-Set Mapping 5 The tables in this chapter describe the relationship between hardware instructions of the SPARC architecture.

.. The following notations are commonly suffixed to assembler mnemonics (uppercase letters refer to SPARC architecture instruction names. const13 const22 creg freg imm7 reg regrd regrs1..5 Table Notation Table 5-1 shows the table notation used in this chapter to describe the instruction set of the assembler. A constant which fits in 22 bits. an unsigned 8-bit value.. It can be the result of the evaluation of a symbol expression.. Same as %r0 . A signed or unsigned constant that can be represented in 7 bits (it is in the range -64 . asi Alternate address space identifier. source register 2. immediate constant.. It can be the result of the evaluation of a symbol expression. It can be the result of the evaluation of a symbol expression. . %c31 %f0 . . %r7 (Globals) Same as %r8 ... Source register 1. %f31 Coprocessor registers.... regrs2..... or an immediate constant.. %r23 (Locals) Same as %r24 . %r0 %g0 %o0 %l0 %i0 .. const13 Value from either a single register. It can be the result of the evaluation of a symbol expression. %r31 %g7 %o7 %l7 %i7 General purpose registers. or both. regrs2 reg_or_imm 30 SPARC Assembly Language Reference Manual—November 1995 . .. A signed constant which fits in 13 bits... %c0 .. %r31 (Ins) Destination register. 127). Floating-point registers... Table 5-1 Notations address Describes regrs1 + regrs1 + regrs1 – const13 const13 regrs2 const13 const13 + regrs1 Notations Used to Describe Instruction Sets Comment Address formed from register contents. .. %r15 (Outs) Same as %r16 .

. 127).. It can be the result of the evaluation of a symbol expression.5 Table 5-1 Notations regaddr Software_trap_ number Describes regrs1 regrs1 + regrs2 regrs1 + regrs2 regrs1 + imm7 regrs1 . Integer Instructions The notations described in Table 5-2 are commonly suffixed to assembler mnemonics (uppercase letters for architecture instruction names). uimm7 An unsigned constant that can be represented in 7 bits (it is in the range 0 ... A value formed from register contents.imm7 uimm7 imm7 + regrs1 Notations Used to Describe Instruction Sets (Continued) Comment Address formed with register contents only. inclusive. immediate constant. Table 5-2 Notation a b c d f h q sr Commonly Suffixed Notations Description Instructions that deal with alternate space Byte instructions Reference to coprocessor registers Doubleword instructions Reference to floating-point registers Halfword instructions Quadword instructions Status register Table 5-3 outlines the correspondence between SPARC hardware integer instructions and SPARC assembly language instructions. Instruction-Set Mapping 31 .127... or both. The resulting value must be in the range 0.

reg_or_imm. • Braces ({ }) indicate optional arguments. reg_or_imm. Brackets are coded literally in the assembly language.a" to the opcode mnemonic. reg_or_imm. regrs1. reg_or_imm.5 The syntax of individual instructions is designed so that a destination operand (if any).a label" • Table 5-3 Opcode ADD ADDcc ADDX ADDXcc AND ANDcc ANDN ANDNcc Mnemonic add addcc addx addxcc and andcc andn andncc SPARC to Assembly Language Mapping Operation regrd regrd regrd regrd regrd regrd regrd regrd Add Add and modify icc Add with carry And Comments Argument List regrs1. Note – In Table 5-3. “Assembler Syntax” differs from the usage of these brackets. "bgeu. • Brackets ([ ]) indicate indirection: the contents of the addressed memory location are being read from or written to. regrs1. regrs1. All Bicc and Bfcc instructions described may indicate that the annul bit is to be set by appending ". for example. reg_or_imm. reg_or_imm. which may be either a register or a reference to a memory location. Braces are not literally coded. 32 SPARC Assembly Language Reference Manual—November 1995 . reg_or_imm. regrs1. is always the last operand in a statement. reg_or_imm. regrs1. regrs1. Note that the usage of brackets described in Chapter 2. regrs1.

a} cb1{.a} cb012{.a} bl{.a} bneg{.a} cba{.a} bpos{.a} be{.a} bvs{.a} cb123{.a} cb023{.a} bg{.a} cb01{.5 Table 5-3 Opcode BN BNE BE BG BLE BGE BI BGU BLEU BCC BCS BPOS BNEG BVC BVS BA CALL CBccc Mnemonic bn{.a} cb13{.a} cb3{.a} cb013{.a} bne{.a} bvc{.a} ba{.a} bge{.a} cb23{.a} cb2{.a} cb03{.a} cb02{.eo} cb12{.a} bgu{.a} SPARC to Assembly Language Mapping (Continued) Operation Branch on integer condition codes Comments branch never synonym: bnz synonym: bz Argument List label label label label label label label label label label label label label label label label label label label label label label label label label label label label label label label label label Call subprogram Branch on coprocessor condition codes branch never synonym: bgeu synonym: blu synonym: b Instruction-Set Mapping 33 .a} cb0{.a} bleu{.a} bcs{.a} call cbn{.a} ble{.a} bcc{.

5 Table 5-3 Opcode FBN FBU FBG FBUG FBL FBUL FBLG FBNE FBE FBUE FBGE FBUGE FBLE FBULE FBO FBA FLUSH JMPL LDSB LDSH LDSTUB LDUB LDUH LD LDD LDF LDFSR LDDF LDC LDCSR LDDC Mnemonic fbn{.a} fbug{.a} fbne{.a} fba{. regrd [address]. regrd [address]. %fsr [address].a} fble{. regrd [address].a} fbge{. fregrd [address].a} fbul{. regrd [address]. cregrd [address].a} flush jmpl ldsb ldsh ldstub ldub lduh ld ldd ld ld ldd ld ld ldd SPARC to Assembly Language Mapping (Continued) Operation Branch on floating-point condition codes Comments branch never Argument List label label label label label label label label label label label label label label label label address address. regrd [address]. fregrd [address].a} fbue{. regrd [address].a} fbg{.a} fbule{.a} fbl{.a} fbe{. cregrd Instruction cache flush Jump and link Load signed byte Load signed halfword Load-store unsigned byte Load unsigned byte Load unsigned halfword Load word Load double word regrd must be even synonym: fbnz synonym: fbz Load floating-point register Load double floating-point Load coprocessor Load double coprocessor fregrd must be even 34 SPARC Assembly Language Reference Manual—November 1995 . %csr [address].a} fbu{.a} fbuge{. regrd [address]. regrd [address].a} fbo{.a} fblg{.

reg_or_imm. regrd regrd regrd regrd regrd regrd must be even LDSTUBA MULScc NOP OR ORcc ORN ORNcc RDASR RDY RDPSR RDWIM RDTBR ldstuba mulscc nop or orcc orn orncc rd rd rd rd rd [regaddr]asi. regrd Multiply step (and modify icc) No operation regrs1. reg_or_imm. reg_or_imm. [regaddr]asi. reg rd address regrs1. [regaddr]asi. See synthetic instructions. See synthetic instructions. regrd regrs1.5 Table 5-3 Opcode LDSBA LDSHA LDUBA LDUHA LDA LDDA Mnemonic ldsba ldsha lduba lduha lda ldda SPARC to Assembly Language Mapping (Continued) Operation Load signed byte from alternate space Comments Argument List [regaddr]asi. RESTORE restore RETT SAVE rett save See synthetic instructions. regrs1. regrd regrs1. See synthetic instructions. SDIV SDIVcc sdiv sdivcc Instruction-Set Mapping 35 . regrd regrs1. regrd regrd regrd regrd Inclusive or %asrnrs1. regrd %wim. reg_or_imm. regrd Signed divide Signed divide and modify icc Return from trap See synthetic instructions. reg_or_imm. See synthetic instructions. regrs1. reg_or_imm. [regaddr]asi. regrd %psr. reg_or_imm. regrd [regaddr]asi. [regaddr]asi. reg_or_imm. reg_or_imm. regrd %tbr. regrs1. regrd %y. regrd regrs1.

[address] %csr. reg_or_imm. [regaddr]asi regrd. regrd const22. [address SETHI sethi sethi SLL SRL SRA STB sll srl sra stb STH ST STD STF STDF STFSR STDFQ sth st std st std st std regrd. Shift left logical Shift right logical Shift right arithmetic Store byte Synonyms: stub. [address] %fsr. [address] regrd. regrd regrd. regrd regrs1. reg_or_imm. stsh Comments Argument List regrs1. regrd regrs1. stsb Synonyms: stuh. stsha fregrd Must be even STC STDC STCSR STDCQ st std st std STBA stba STHA STA STDA stha sta stda regrd [regaddr]asi regrd. [address] %cq. regrd regrs1. stsba Synonyms: stuha. [address] cregrd. regrd regrs1. reg_or_imm. [address] %fq. [address] fregrd. [address] regrd.5 Table 5-3 Opcode SMUL SMULcc Mnemonic smul smulcc SPARC to Assembly Language Mapping (Continued) Operation Signed multiply Signed multiply and modify icc Set high 22 bits of register See synthetic instructions. [address] regrd [regaddr]asi Store half-word regrd Must be even Store floating-point status register Store double floating-point queue Store coprocessor cregrd Must be even Store double coprocessor Store byte into alternate space Synonyms: stuba. regrd %hi(value). reg_or_imm. [address] fregrd. reg_or_imm. [regaddr]asi regrd Must be even 36 SPARC Assembly Language Reference Manual—November 1995 . [address] cregrd.

5
Table 5-3 Opcode SUB SUBcc SUBX SUBXcc SWAP SWAPA Ticc Mnemonic sub subcc subx subxcc swap swapa tn tne SPARC to Assembly Language Mapping (Continued) Operation regrd regrd regrd regrd Subtract Subtract and modify icc Subtract with carry Swap memory word with register Trap on integer condition code Note: Trap numbers 16-31 are reserved for the user. Currentlydefined trap numbers are those defined in /usr/include/sys/trap.h Trap never Synonym: tnz Comments Argument List regrs1, regrs1, regrs1, regrs1, reg_or_imm, reg_or_imm, reg_or_imm, reg_or_imm,

[address], regrd [regaddr]asi, regrd software_trap_number software_trap_number

te tg tle tge tl tgu tleu tlu tgeu tpos tneg tvc tvs ta TADDcc TSUBcc TADDccTV taddcc tsubcc taddcctv

software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number

Synonym: tz

Synonym: tcs Synonym: tcc software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number software_trap_number regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd Tagged add and modify icc

Synonym: t

Tagged add and modify icc and trap on overflow

TSUBccTV

tsubcctv

regrs1, reg_or_imm, regrd

Instruction-Set Mapping

37

5
Table 5-3 Opcode UDIV UDIVcc Mnemonic udiv udivcc SPARC to Assembly Language Mapping (Continued) Operation Unsigned divide Unsigned divide and modify icc Unsigned multiply Unsigned multiply and modify icc Illegal instruction See synthetic instructions See synthetic instructions See synthetic instructions See synthetic instructions Exclusive nor Exclusive or Comments Argument List regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd const22 reg_or_imm, %asrnrs1 regrs1, reg_or_imm, %y regrs1, reg_or_imm, %psr regrs1, reg_or_imm, %wim WRWIM WRTBR wr regrs1, reg_or_imm, %tbr wr regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd regrs1, reg_or_imm, regrd

UMUL UMULcc

umul umulcc

UNIMP WRASR WRY WRPSR

unimp wr wr wr

XNOR XNORcc XOR XORcc

xnor xnorcc xor xorcc

38

SPARC Assembly Language Reference Manual—November 1995

5
Floating-Point Instruction
Table 5-4 shows floating-point instructions. In cases where more than numeric type is involved, each instruction in a group is described; otherwise, only the first member of a group is described.
Table 5-4 SPARC FiTOs FiTOd FiTOq FsTOi FdTOi FqTOi FsTOd FsTOq FdTOs FdTOq FqTOd FqTOs FMOVs FNEGs FABSs FSQRTs FSQRTd FSQRTq FADDs FADDd FADDq Mnemonic* fitos fitod fitoq fstoi fdtoi fqtoi fstod fstoq fdtos fdtoq fqtod fqtos fmovs fnegs fabss fsqrts fsqrtd fsqrtq fadds faddd faddq Floating-Point Instructions Argument List fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs2, fregrd fregrs1, fregrs2, fregrd fregrs1, fregrs2, fregrd fregrs1, fregrs2, fregrd Description Convert integer to single Convert integer to double Convert integer to quad Convert single to integer Convert double to integer Convert quad to integer Convert single to double Convert single to quad Convert double to single Convert double to quad Convert quad to double Convert quad to single Move Negate Absolute value Square root

Add

* Types of Operands are denoted by the following lower-case letters: i integer s single d double q quad

Instruction-Set Mapping

39

Operand alignment is also coprocessor-dependent. fregrs2. fregrd fregrs1. fregrs2. fregrs2 * Types of Operands are denoted by the following lower-case letters: i integer s single d double q quad Coprocessor Instructions All coprocessor-operate (cpopn) instructions take all operands from and return all results to coprocessor registers. fregrs2. 40 SPARC Assembly Language Reference Manual—November 1995 . fregrs2 fregrs2 fregrs2 fregrs2 Description Subtract Multiply Multiply double to quad Multiply single to double Divide Compare Compare. or if a coprocessor is not present. fregrd fregrs1. a cpopn instruction causes a cp_disabled trap. fregrs1. fregrs2. fregrd fregrs1. fregrs2 fregrs1. The data types supported by the coprocessor are coprocessor-dependent. fregrd fregrs1. fregrs2. fregrd fregrs1. fregrs2. fregrs1. fregrd fregrs1. If the EC (PSR_enable_coprocessor) field of the processor state register (PSR) is 0. fregrd fregrs1. fregrs2. Coprocessor-operate instructions are described in Table 5-5. fregrs2. fregrd fregrs1.5 Table 5-4 SPARC FSUBs FSUBd FSUBq FMULs FMULd FMULq FdMULq FsMULd FDIVs FDIVd FDIVq FCMPs FCMPd FCMPq FCMPEs FCMPEd FCMPEq Mnemonic* fsubs fsubd fsubq fmuls fmuld fmulq fmulq fsmuld fdivs fdivd fdivq fcmps fcmpd fcmpq fcmpes fcmped fcmpeq Floating-Point Instructions (Continued) Argument List fregrs1. fregrd fregrs1. fregrs1. generate exception if not ordered fregrs1. fregrs2. fregrd fregrs1. fregrs2. fregrs2. fregrd fregrs1.

regrd Synthetic Instructions Table 5-6 describes the mapping of synthetic instructions to hardware instructions. regrd regrd const13. regrs2. %g0. regrd regrs1 regrd regrd regrd Synthetic Instruction to Hardware Instruction Mapping Hardware Equivalent(s) andcc or andn xor jmpl or stb sth st subcc sub sub subcc subcc regrs1. reg_or_imm. reg_or_imm. regrd regrd. regrs1. Table 5-5 SPARC CPop1 CPop2 Mnemonic cpop1 cpop2 Coprocessor-Operate Instructions Name Coprocessor operation Coprocessor operation May modify ccc Comments Argument List opc. %o7 %g0. regrd [address] [address] [address] Clear Clear Clear Clear (zero) register byte halfword word Comment Bit Bit Bit Bit test set clear toggle regrs1. regrd regrd. reg_or_imm regrd const13. regrd regrd. regrd Compare Decrement by 1 Decrement by const13 Decrement by 1 and set icc Decrement by const13 and set icc Instruction-Set Mapping 41 . %g0. regrd regrd. regrd regrd. const13. regrs1. regrd reg_or_imm. reg_or_imm. const13. %g0. %g0 regrd. 1. Table 5-6 Synthetic Instruction btst bset bclr btog call clr clrb clrh clr cmp dec dec deccc deccc reg_or_imm. reg_or_imm. regrs2. %g0. %g0 regrd. reg_or_imm regrd [address] [address] [address] reg. reg_or_imm. reg_or_imm.5 The conditions that cause a cp_exception trap are coprocessor-dependent. regrd opc. 1. reg_or_imm. reg_or_imm.

%wim reg_or_imm.regrd value. regrd Comment Increment by 1 Increment by const13 Increment by 1 and set icc Increment by const13 and set icc jmp mov mov mov mov mov mov mov mov mov not not neg neg restore save address reg_or_imm. regrd regrd. regrd. regrd %y.%tbr regrs1. %g0. regrd %g0.regrd %y. %g0.%wim %g0. %g0. regrd Synthetic Instruction to Hardware Instruction Mapping (Continued) Hardware Equivalent(s) add add addcc addcc regrd. set set set value. regrs1 %g0. regrd %hi(value). %tbr regrs1.reg_or_imm. regrs2. regrd 42 SPARC Assembly Language Reference Manual—November 1995 . regrs1 %wim. regrd regrd. reg_or_imm. regrd regrd regrs1. %y reg_or_imm.regrd value. regrd %g0.%y %g0. %psr reg_or_imm.regrd or sethi sethi or %g0. const13.reg_or_imm. %g0 One's complement One's complement Two's complement Two's complement Trivial restore Trivial save trivial save should only be used in supervisor code! if -4096 ≤ value ≤ 4095 if ((value & 0x3ff) == 0) otherwise Do not use the set synthetic instruction in an instruction delay slot. const13.%psr %g0. regrd. 1.reg_or_imm. %g0 %g0. %g0. regrd. regrs1 %tbr. regrd regrd. regrs1 %wim. %g0 %g0. regrd regrd const13. value. %lo(value). regrs1 %psr. regrd regrd.reg_or_imm. regrs1 %tbr. regrd %hi(value). 1. regrd regrd jmpl or rd rd rd rd wr wr wr wr xnor xnor sub sub restore save address. regrd %g0. regrs1 reg_or_imm.5 Table 5-6 Synthetic Instruction inc inc inccc inccc regrd const13. regrs1 %psr.

a .+8 Comment if z is set.+8 bz. ignores next instruction if z is not set.a . ignores next instruction regrs1. %g0 test tst reg orcc Instruction-Set Mapping 43 .5 Table 5-6 Synthetic Instruction skipz skipnz Synthetic Instruction to Hardware Instruction Mapping (Continued) Hardware Equivalent(s) bnz. %g0.

5 44 SPARC Assembly Language Reference Manual—November 1995 .

boundary may be any power of 2. .align boundary Aligns the location counter on a boundary where ((“location counter” mod boundary)==0). string"] Generates the given sequence(s) of ASCII characters. string]* Generates the given sequence(s) of ASCII characters.Pseudo-Operations A The pseudo-operations listed in this appendix are supported by the SPARC assembler.ascii string [. . 45 .) . Alphabetized Listing with Descriptions .alias Turns off the effect of the preceding .byte 8bitval [. 8bitval]* Generates (a sequence of) initialized bytes in the current segment.asciz string [. (Compiler-generated only. This pseudo-op appends a null (zero) byte to each string.noalias pseudo-op. .

Some instructions should not be in the delay slot of a CTI.A .file string Creates a symbol table entry where string is the symbol name and STT_FILE is the symbol table type. floatval is a string acceptable to atof(3). Size bytes are allocated for the object represented by symbol.double 0rfloatval [.empty Suppresses assembler complaints about the next instruction presence in a delay slot when used in the delay slot of a Control Transfer Instruction (CTI). Currently. . • If the symbol is not defined in the input file and is declared to be local to the file. If sect_name is not given. • If the symbol is defined in the input file. sect_name] [. Global is the default binding for common symbols. that is. alignment] Provides a tentative definition of symbol. size [. the SPARC link editor allocates storage for the symbol. an optional sign followed by a non-empty string of digits with optional decimal point and optional exponent. the symbol is allocated in the uninitialized data section (bss).common symbol. . depending on the definition of symbol_name in other files. See the SPARC Architecture Manual for details.) • If the symbol is not defined in the input file and is declared to be global. the definition specifies the location of the symbol and the tentative definition is overridden. the symbol is allocated in sect_name and its location is optionally aligned to a multiple of alignment. only . 0rfloatval]* Generates (a sequence of) initialized double-precision floating-point values in the current segment. string specifies the name of the source file associated with the object file. .bss is supported for the section name.data is not currently supported. 46 SPARC Assembly Language Reference Manual—November 1995 . (.

default bindings for the symbol are overridden. of the specified symbol. that is. • A global symbol definition in one file will satisfy an undefined reference to the same global symbol in another file. Pseudo-Operations 47 . an error will occur.pushsection .half 16bitval [. The location counter must already be aligned on a halfword boundary (use . local symbols of the same name may exist in multiple files. symbol]* . This operation is equivalent to: . that is. 16bitval]* Generates (a sequence of) initialized halfwords in the current segment. If a defined global symbol has more than one definition. • A global psuedo-op oes not need to occur before a definition. symbol]* Declares each symbol in the list to be global.global symbol [. each symbol is either defined externally or defined in the input file and accessible in other files. . . These symbols take precedence over weak and global symbols.A . Note – This pseudo-op by itself does not define the symbol.popsection .asciz string . each symbol is defined in the input file and not accessible in other files.comment . Since local symbols are not accessible to other files.ident string Generates the null terminated string in a comment section. symbol]* Declares each symbol in the list to be local. or tentative definition. • Multiple definitions of a defined global symbol is not allowed.align 2). default bindings for the symbol are overridden.globl symbol [.local symbol [.

%reg2 %reg1 and %reg2 will not alias each other (that is. This pseudo-op has no effect if: • The block of instruction has been previously terminated by a Control Transfer Instruction (CTI) or a label • There is no preceding . a unit of optimization) to the peephole optimizer in the SPARC assembler. n specifies which registers will contain the return value upon return from the procedure. (Compiler-generated only.alias pseudo-op is issued.nonvolatile Defines the end of a block of instruction. The new section on the top of the stack becomes the current section.) .A Note – This pseudo-op by itself does not define the symbol. . (Compiler-generated only.) .popsection Removes the top section from the section stack.) .pushsection sect_name [. attributes] Moves the named section to the top of the section stack. This pseudo-op and its corresponding . This new top section then becomes the current section. This pseudo-op and its corresponding .pushsection command allow you to switch back and forth between the named sections. point to the same destination) until a .proc n Signals the beginning of a procedure (that is. 48 SPARC Assembly Language Reference Manual—November 1995 .optim string This pseudo-op changes the optimization level of a particular function. (Compilergenerated only.popsection command allow you to switch back and forth between the named sections.noalias %reg1.volatile pseudo-op . . The instructions in the block may not be permuted.

This pseudo-op changes the top of the section stack. size [. space is reserved in the current segment. . and reserves size bytes of space for it in the sect_name.quad command currently generates quad-precision values with only double-precision significance. .skip . The assembler maintains a section stack which is manipulated by the section control directives.reserve symbol.pushsection . Note – The .quad 0rfloatval [.popsection sect_name alignment size If a section is not specified. The current section is the section that is currently on top of the stack. that is. floatval is a string acceptable to atof(3). Pseudo-Operations 49 . alignment]] Defines symbol.align symbol: . attributes] Makes the specified section the current section.section section_name [. sect_name [. an optional sign followed by a non-empty string of digits with optional decimal point and optional exponent.A . This operation is equivalent to: . 0rfloatval]* Generates (a sequence of) initialized quad-precision floating-point values in the current segment. • If section_name does not exist. a new section with the specified name and attributes is created.

seg data. attributes must be included the first time it is specified by the . “Executable and Linking Format. See Table 3-2 in Chapter 3. . 50 SPARC Assembly Language Reference Manual—November 1995 .A • If section_name is a non-reserved section. Note – This operation does not align automatically. This pseudo-op has been replaced by the .bss.section . .” for a detailed description of the section attribute flags. Changes the current section to one of the predefined user sections. .single 0rfloatval [. “Executable and Linking Format.section .x SPARC assembly directive: .data1. The assembler will interpret the following SunOS 4. See the sections “Predefined User Sections” and “Predefined Non-User Sections” in Chapter 3.section . .1 SPARC assembly directive: .text.x.section directive.data.seg text. to be the same as the following SunOS 5.” for a detailed description of the reserved sections.seg bss. . Attributes can be: #write | #alloc | #execinstr .section . .seg data1.seg section_name Note – This pseudo-op is currently supported for compatibility with existing SunOS 4. 0rfloatval]* Generates (a sequence of) initialized single-precision floating-point values in the current segment. . Predefined user section names are changed in SunOS 5.section pseudo-op.1 SPARC assembly language programs.

uaword 32bitval [. which allocates n bytes of empty space in the current segment. Pseudo-Operations 51 .stabn <various parameters> The pseudo-op is used by Solaris 2. expr must be an absolute expression. “Executable and Linking Format. expr Declares the symbol size to be expr. .x SPARCompilers only to pass debugging information to the symbolic debuggers.A .x SPARCompilers only to pass debugging information to the symbolic debuggers. Note – This operation does not align automatically.” for detailed information on symbols. 16bitval]* Generates a (sequence of) 16-bit value(s). 32bitval]* Generates a (sequence of) 32-bit value(s).uahalf 16bitval [.skip n Increments the location counter by n. . Note – This operation does not align automatically. . type Declares the type of symbol.type symbol.stabs <various parameters> The pseudo-op is used by Solaris 2. .size symbol. . . where type can be: #object #function #no_type See Table 3-6 in Chapter 3.

xstabs <various parameters> The pseudo-op is used by Solaris 2. Note the following: • A weak symbol definition in one file will satisfy an undefined reference to a global symbol of the same name in another file. 52 SPARC Assembly Language Reference Manual—November 1995 . 32bitval]* Generates (a sequence of) initialized words in the current segment. default bindings of the symbol are overridden by this directive.volatile Defines the beginning of a block of instruction. or in the input file and accessible to other files. . . Note – This operation does not align automatically. You can use this pseudo-op to ensure assembler-compiler compatibility. symbol] Declares each symbol in the list to be defined either externally.weak symbol [. Note – This pseudo-op does not itself define the symbol.A .x SPARCompilers only to pass debugging information to the symbolic debuggers. the link editor does not resolve these symbols. . the weak symbol is ignored and no error results. a fatal error message is displayed and the SPARC assembler exits. The instructions in the section may not be changed. The volatile block of instructions is terminated after the last instruction preceding a CTI or label. If string indicates a newer version of the assembler than this version of the assembler.word 32bitval [. • If a weak symbol has the same name as a defined global symbol. • Unresolved weak symbols have a default value of zero.nonvolatile pseudo-op and should not contain any Control Transfer Instructions (CTI) or labels. The block of instruction should end at a . .version string Identifies the minimum assembler version necessary to assemble the input file.

A symbol =expr Assigns the value of expr to symbol. Pseudo-Operations 53 .

A 54 SPARC Assembly Language Reference Manual—November 1995 .

. .weak The following C definitions/declarations: int foo1 = 1.local. #pragma weak foo2 = foo1 static int foo3.global. . 55 . static int foo4 = 2.Examples of Pseudo-Operations B This chapter shows some examples of ways to use various pseudo-ops. Example 1 This example shows how to use the following pseudo-ops to specify the bindings of variables in C: common.

ident to generate a string in the .align4 foo1: .word0x1 .word .4.common .size .comment section of the object file for identification purposes.data" .globalfoo1! int foo1 = 1 .4 ! with size = 4 bytes .pushsection".type foo1.size foo1.popsection foo3 foo3. .weak foo2 foo2 = foo1 .B can be translated into the following assembly code: Code Example B-1 .4 Example 2 This example shows how to use the pseudo-op .local .ident "acomp: (CDS) SPARCompilers 2. .type .#object ! foo1 is of type data object.align foo4: .#object foo4.0 alpha4 12 Aug 1991" 56 SPARC Assembly Language Reference Manual—November 1995 .4 4 ! #pragma weak foo2 = foo1 ! static int foo3 ! static int foo4 = 2 0x2 foo4.

size.-sum Examples of Pseudo-Operations 57 .type .align. b) int a.%o1.size sum. . .type. The following C subroutine: int sum(a.#function sum. } can be translated into the following assembly code: .B Example 3 The pseudo-ops shown in this example are . { return(a + b).align sum: retl add sum 4 %o0. b..global .global. and .%o0 ! (a + b) is done in the ! delay slot of retl ! ! ! ! ! sum is of type function size of sum is the diff of current location counter and the initial definition of sum .section ".text" .

section ".ascii "hello world\n\0" .global main main: save %sp.-96. [%o0] retl nop .data1" .ascii.section ".nonvolatile pseudoops to protect a section of handwritten asembly code from peephole optimization. .L16: .%sp set .%o0 call printf. The example calls the printf function to output the string "hello world".L16.align. .1 nop restore Example 5 This example shows how to use the . .text" .nonvolatile 58 SPARC Assembly Language Reference Manual—November 1995 .B Example 4 The pseudo-ops shown in this example are .volatile t 0x24 std %g2.section.volatile and .align 4 . and .

The SPARC assembler recognizes the filename argument hyphen (-) as the standard input.Using the Assembler Command Line This appendix is organized into the following secitons: Assembler Command Line Assembler Command Line Options Disassembling Object Code page 59 page 60 page 63 C Assembler Command Line You invoke the assembler command line as follows: as [options] [inputfile] . If an invalid option is given or the command line contains a syntax error. the SPARC assembler prints the error (including a synopsis of the command line syntax and options) to standard error output. Note – The language drivers (such as cc and f77) invoke the assembler command line with the fbe command. 59 . inputfile. and then terminates. The as command translates the assembly language source files. into an executable object file. You can use either the as or fbe command to invoke the assembler command line.. It accepts more than one file name on the command line. objfile.. The input file is the concatenation of all the specified files.

otherwise. (See the -P option. This option has the same functionality as the -k option under the SunOS 4. • If the as command line option -P is set. #include files. • If the as command line option -m is set. and symbolic substitution through use of the C preprocessor cpp. otherwise. it is ignored. these options are passed to the cpp preprocessor without interpretation by the as command. The assembler invokes the preprocessor before assembly begins if it has been specified from the command line as an option. see the Browsing Source Code manual. -K PIC This option generates position-independent code. this option is ignored as the m4 macro processor does not generate browser data.) Assembler Command Line Options -b This option generates extra symbol table information for the source code browser. this option is passed to the cpp preprocessor without interpretation by the as command. they are ignored.1 SPARC assembler. For more information about the SPARCworks SourceBrowser. the cpp preprocessor also collects browser information. -Ipath When the -P option is in effect. Note – -K PIC and -K pic are equivalent. 60 SPARC Assembly Language Reference Manual—November 1995 . -Dname -Dname=def When the -P option is in effect.C The SPARC assembler supports macros.

-P Run cpp. -o outfile Takes the next argument as the name of the output file to be produced. if present. Using the Assembler Command Line 61 .o suffix is appended to form the ouput file name. the information is suppressed. -n Suppress all warnings while assembling.s suffix. on the files being assembled. the C preprocessor. -S[a|C] Produces a disassembly of the emitted code to the standard output. including temporary labels that are normally discarded to save space. -m This option runs m4 macro preprocessing on input. The preprocessor output is passed to the assembler. not on their concatenation. By default. in the ELF symbol table. so it is more useful for complex preprocessing. It is recommended that you do not use this option to assemble handwritten assembly language. if the n option is specified. See the m4(1) man page for more information about the m4 macro-processor. The m4 preprocessor is more powerful than the C preprocessor (invoked by the -P option). -Q{y|n} This option produces the “assembler version” information in the comment section of the output object file if the y option is specified.C -L Saves all symbols. The preprocessor is run separately on each input file. Many errorchecks are not performed when -q is specified. Note – This option disables many error checks. is removed from the input file and the . the . -q This option causes the assembler to perform a quick assembly.

With this option.x symbol names. By default. -xarch=v7 This option instructs the assembler to accept instructions defined in the SPARC version 7 (V7) architecture. The resulting object code is in ELF format.C • Adding the character a to the option appends a comment line to each assembly code which indicates its relative address in its own section. stabs are placed in "stabs.stab" sections are not stripped out by the static linker ld. The resulting object code is in ELF format. This is the default choice of the -xarch= options.1 assembly files to be assembled on SunOS 5. -T This is a migration option for SunOS 4. this option is passed to the cpp preprocessor without interpretation by the as command.stabs" section.1 assembly files will be interpreted as SunOS 5.excl" sections. -V This option writes the version information on the standard error output. otherwise. stabs remain in the final executable because ". it is ignored. 62 SPARC Assembly Language Reference Manual—November 1995 . which are stripped out by the static linker ld during final execution. the symbol names in SunOS 4. -Uname When the -P option is in effect. -s This option places all stabs in the ".1 assembly files to their corresponding SunOS 5. When the -s option is used. This option can be used in conjunction with the -S option to convert SunOS 4.x systems.x versions. • Adding the character "C" to the option prevents comment lines from appearing in the output. -xarch=v8 This option instructs the assembler to accept instructions defined in the SPARC-V8 architecture.

" -xarch=v8plusa This option instructs the assembler to accept instructions defined in the SPARC-V9 architecture. It will not execute on a system with a V8 processor under a Solaris operating environment. It will not execute on a system with a V8 processor under a Solaris operating environment." Disassembling Object Code The dis program is the object code disassembler for ELF. marked to indicate that it uses V9/VIS instructions. “SPARC-V9 Instruction Set. The resulting object code is in ELF format. For detailed information about this function. The resulting object code is in ELF format. It produces an assembly language listing of the object file. plus the instructions in the Visual Instruction Set (VIS). less the fsmuld instruction. For more information about VIS instructions. It will execute on a system with a V9 processor under a Solaris operating environment. The resulting object code is in ELF format. It will execute on a system with a V9 processor under a Solaris operating environment.C -xarch=v8a This option instructs the assembler to accept instructions defined in the SPARC-V8 architecture. see the "UltraSPARC Programmer’s Reference Manual" and the "UltraSPARC User’s Guide. Using the Assembler Command Line 63 . marked to indicate that it uses V9 instructions. -xarch=v8plus This option instructs the assembler to accept instructions defined in the SPARC-V9 architecture. see Appendix E. For more information regarding SPARC-V9 instructions. see the man page dis(1).

C 64 SPARC Assembly Language Reference Manual—November 1995 .

the second example code shows the corresponding assembly code generated by SPARCompiler C 3.An Example Language Program D The following code shows an example C language program. 65 . Comments have been added to the asembly code to show correspondence to the C code.x operating environment.2 that runs on the Solaris 2.0.

printf("Fibonacci(n):. } return(fib_array). for (i = 1. unsigned prev_number = 0. n). scanf("%d". i++) printf("Fibonacci (%d) is %u\n".1}. int i. i++) { fib_array[i] = prev_number + curr_number. curr_number = fib_array[i]. i < n. i <= n. exit(1). } for (i = 2. unsigned curr_number = 1. &n). prev_number = curr_number. i. if (n >= MAX_FIB_REPRESENTABLE) { printf("Fibonacci(%d) cannot be represented in a 32 bit word\n". unsigned * result.D The following C Program computes the first n Fibonacci numbers: Figure D-1 C Program Example Source /* a simple program computing the first n Fibonacci numbers */ extern unsigned * fibonacci(). please enter n:\n"). } 66 SPARC Assembly Language Reference Manual—November 1995 . #define MAX_FIB_REPRESENTABLE 49 /* compute the first n Fibonacci numbers */ unsigned * fibonacci(n) int n. i. { static unsigned fib_array[MAX_FIB_REPRESENTABLE] = {0. *result++). } main() { int n. result = fibonacci(n).

text" 79 fibonacci 4 %sp. .%lo(.D The C SPARCompiler generates the following assembler output for the Fibonacci number C source.c" ". i < n.1 mov 1. n). showing various pseudo-operations. .global .%i4 ! curr_number = 1 An Example Language Program 67 . 2nd argument in %o0.skip. . save. */ call exit. C style comment strings are also permitted n >= MAX_FIB_REPRESENTABLE ? note. ble. Figure D-2 Assembler Output From C Source ! ! ! ! ! ! ! ! ! a simple program computing the first n Fibonacci numbers. it's return value will be in %i0 fibonacci() can be referenced outside this file align the beginning of this section to word boundary fibonacci: save /* ! create new stack frame and register ! window for this subroutine ! ! ! ! ! ! note. bl. */ sethi %hi(.%i2 ! initialization of variable ! prev_number is executed in the ! delay slot /* printf("Fibonacci(%d) cannot be represented in a 32 bits word\n". mov.L77003: ! initialize variables before the loop /* for (i = 2.%o0 . is stored in %i0 upon entry if (n >= MAX_FIB_REPRESENTABLE) { */ cmp %i0. i++) { */ mov 1.%o0 ! if branch not taken. the 1st parameter to fibonacci(). .type. %o1.align.L77003 0.global. bge. cmp.file . . sethi.L20).%o1 ! registers used as arguments /* exit(1). synthetic instructions pseudo-operations: . call printf. ret .%o0 ! set up 1st. n. Annotation has been added to help you understand the code. sparc instructions. .section.49 bl mov . call printf(). or. ld.L20).section .word sparc instructions: add. bg.align "fibonacci.%sp ! the original source file name ! ! ! ! ! ! ! text section (executable instructions) subroutine fibonacci.size.file.proc .2" means there are 2 out mov %i0. or %o0. . inc. .-96. . restore.2 ! the ".proc.ident. . st synthetic instructions: call.ascii.

%i4 inc %i3 cmp %i3.%i3 cmp %i3.%i5 mov %o0.L16+8).[%i5] /* prev_number = curr_number.-4.%lo(. in %o0 or %o0.2 add %fp.%sp ! create stack frame for main() /* printf("Fibonacci(n):.L31).%i2 st %i2. repeat loop increment ptr to fib_array[] ! return fib_array in %i0 ! ! ! ! ! ! destroy stack frame and register window fibonacci() is of type function size of function: current location counter minus beginning definition of function .%i0 bge .global main .LY1 inc 4. please input n:\n").%lo(.L16). return use %i5 to store &fib_array[i] ! loop body */ ! fib_array[i] = prev_number+curr_number ! prev_number = curr_number ! ! ! ! ! curr_number = fib_array[i] i++ i <= n? if yes. with 1st arg in %o0 call printf.proc 18 ! main program .-104.type .%i2 /* curr_number = fib_array[i]. */ sethi %hi(.%i4.%lo(.L77006 sethi %hi(. &n). */ mov %i4.1 ld [%fp-4].L31).%o0 add %o0.L33).%o0 ! call scanf.%lo(.align 4 main: save %sp.(.%o1 /* result = fibonacci(n). i++) */ mov 1. add %i2. i <= n. */ sethi %hi(. with 1st arg.size fibonacci. in delay slot call scanf.#function fibonacci.LY1: /* fib_array[i] = prev_number + curr_number.%i0 bl .%o0 ! call printf. */ ld [%i5]. */ call fibonacci.L16+8).%i5 .%o0 ! some initializations before the for! loop.D mov 2. */ sethi %hi(.%i5 .1 or %o0.%o0 /* scanf("%d".%o0 add %o0.%i0 ret restore .L33).L77006: /* return(fib_array).%i4 ! %i5 <-.L16).-fibonacci) ! ! ! ! i = 2 i <= n? if not. put the variables in registers /* for (i = 1.result 68 SPARC Assembly Language Reference Manual—November 1995 .%o0 ! move 2nd arg.i ! %i4 <-. to %o1.

L16.LE27: ret restore .ascii .section ".%o1 ! i in %o1. */ ld [%i4]. n is stored in [%fp-4] bg .section ".%o0 ! %i2 <-.#function ! type and size of main .%o0 inc %i5 ! i++ ld [%fp-4].L20: .%o0 ! i <= n? cmp %i5.LY2: ! loop body /* printf("Fibonacci (%d) is %u\n".data1 section.word 0 ! of fib_array[] .-main) . *result++).align 4 ! initialization of first 2 elements .type .align 4 . i.data1" ! ! ! ! ! ! ! the ascii string data are entered into the . with (*result) in %o2.#object ! storage allocation for the rest of ! fib_array[] . please enter n:\n\0" 4 An Example Language Program 69 .%o0 ble .type main.1}.L16: /* static unsigned fib_array[MAX_FIB_REPRESENTABLE] = {0.LE27 nop .word 1 .skip 188 .align .L31: .ascii .%o0 ! note. #alloc: memory would be allocated for this section during run time #write: the section contains data that is writeable during process execution .size main.L38).format string for printf add %o0.ascii .%i4 ! result++ .D sethi %hi(.L38).(.%lo(.align 4 .data" ! switch to data section ! (contains initialized data) .%i2 ld [%fp-4].%o2 ! call printf.align .LY2 inc 4.%o0 ! test if (i <= n) ? cmp %i5.3 mov %i2. format string in %o0 call printf.align 4 ! ascii strings used in the printf stmts "Fibonacci(%d) cannot be represented in a 32 bit w" "ord\n\0" 4 ! align the next ascii string to word ! boundary "Fibonacci(n):. */ . mov %i5.

D .comment section 70 SPARC Assembly Language Reference Manual—November 1995 .0 05 Jun 1991" ! an idenitfication string produced ! by the compiler to be entered into ! the .ident "%d\0" 4 "Fibonacci (%d) is %u\n\0" "acomp: (CDS) SPARCompilers 2.ascii .L33: .L38: .ascii .align .

expanded below: registers.SPARC-V9 Instruction Set E This appendix describes changes made to the SPARC instruction set due to the SPARC-V9 architecture. unchanged. on SPARC-V9 systems. byte order. alternate space access. 71 . Application software for the 32-bit SPARC-V8 (Version8) architecture can execute. and instruction set. This appendix is organized into the following sections: SPARC-V9 Changes SPARC-V9 Instruction Set Changes SPARC-V9 Instruction Set Mapping SPARC-V9 Floating-Point Instruction Set Mapping SPARC-V9 Synthetic Instruction-Set Mapping SPARC-V9 Instruction Set Extensions page 71 page 74 page 77 page 85 page 87 page 89 SPARC-V9 Changes The SPARC-V9 architecture differs from SPARC-V8 architecture in the following areas.

fcc2. These SPARC-V9 registers are within a SPARC-V8 register field: Table E-3 SPARC-V9 Registers Within a SPARC-V8 Register Field CCR CWP PIL TBA TT[MAXTL] VER Condition Codes Register Current Window Pointer Processor Interrupt Level Trap Base Address Trap Type Version These are registers that have been added. nPC. and fcc3 (added floatingpoint condition code) bits are added and the register widened to 64-bits.E Registers These registers have been deleted: Table E-1 Deleted SPARC-V8 Privileged Registers PSR TBR WIM Processor State Register Trap Base Register Window Invalid Mask These registers have been widened from 32 to 64 bits: Table E-2 Registers Widened from 32 to 64 bits Integer registers All state registers FSR. Table E-4 Registers That have Been Added ASI CANRESTORE CANSAVE Address Space Identifier Restorable Windows Savable windows 72 SPARC Assembly Language Reference Manual—November 1995 . and Y Note – FSR Floating-Point State Register: fcc1. PC.

7f16 are privileged. f[32] . f[32] .. access to alternate address spaces is privileged. instruction accesses are always performed using big-endian byte order. and incremented during a SAVE instruction. f[62].. all data and instruction accesses are performed in big-endian byte order. This is the opposite of PSR. loads and stores to ASIs 0016 . Byte Order SPARC-V9 supports both little. FF16 are nonprivileged. This change has no effect on nonprivileged instructions. Alternate Space Access Load. In SPARC-V8. SPARC-V9 Instruction Set 73 . These registers overlap (and are aliased with) eight additional quadprecision floating-point registers..CWP’s behavior in SPARC-V8. In SPARC-V8.E Table E-4 Registers That have Been Added (Continued) CLEANWIN FPRS OTHERWIN PSTATE TICK TL TNPC[MAXTL] TPC[MAXTL] TSTATE[MAXTL] WSTATE Clean Windows Floating-point Register State Other Windows Processor State Hardware clock tick-counter Trap Level Trap Next Program Counter Trap Program Counter Trap State Windows State Also. there are sixteen additional double-precision floating-point registers.and big-endian byte orders for data accesses only. In SPARC-V9.and store-alternate instructions to one-half of the alternate spaces can now be included in user code. f[60] The SPARC-V9.. those to ASIs 8016 . CWP register is decremented during a RESTORE instruction.

Load/Store FSR. FCMPE LDFSR. Extended Instruction Definitions to Support the 64-bit Model Table E-5 Extended Instruction Definitions for 64-bit Model FCMP. STFSR LDUW. 74 SPARC Assembly Language Reference Manual—November 1995 . LDUWA RDASR/WRASR SAVE/RESTORE SETHI SRA. SLL. LDA in SPARC-V8 Read/Write State Registers .only affect low-order 32 bits of FSR Same as LD. Shifts Tcc Split into 32-bit and 64-bit versions (was Ticc) Operates with either the 32-bit integer condition codes (icc).E SPARC-V9 Instruction Set Changes Application software written for the SPARC-V8 processor runs unchanged on a SPARC-V9 processor. SRL.access additional registers All other arithmetic operations operate on 64-bit operands and produce 64-bit results. or the 64-bit integer condition codes (xcc) Floating-Point Compare—can set any of the four floating-point condition codes.

STDFA. LDF. LDFA.E Added Instructions to Support 64 bits Table E-6 Added Instructions to Support 64 bits F[sdq]TOx FxTO[sdq] FMOV[dq] FNEG[dq] FABS[dq] LDDFA. double and quad Floating-point Absolute Value. STDF. double and quad Alternate address space forms of LDDF. STFA LDSW LDSWA LDX LDXA LDXFSR STX STXA STXFSR Convert floating point to 64-bit word Convert 64-bit word to floating point Floating-Point Move. STQF(A) Branch on integer condition code with prediction Branch on integer register contents with prediction Compare and Swap from an alternate space Branch on floating-point condition code with prediction Flush windows Move floating-point register if condition code is satisfied Move floating-point register if integer register satisfies condition Load/Store Quad Floating-point (in an alternate space) SPARC-V9 Instruction Set 75 . double and quad Floating-point Negate. CASXA FBPfcc FLUSHW FMOVcc FMOVr LDQF(A). and STF Load a signed word Load a signed word from an alternate space Load an extended word Load an extended word from an alternate space Load all 64 bits of the FSR register Store an extended word Store an extended word into an alternate space Store all 64 bits if the FSR register Added Instructions to Support High-Performance System Implementation Table E-7 Added Instructions to Support High-Performance BPcc BPr CASA.

UDIVX Move integer register if condition code is satisfied Move integer register if register contents satisfy condition Generic 64-bit multiply Population count Prefetch Data Signed and Unsigned 64-bit divide Deleted Instructions Table E-8 Deleted Instructions Coprocessor loads and stores RDTBR and WRTBR RDWIM and WRWIM REPSR and WRPSR RETT STDFQ TBR no longer exists. which can be read/written with RDPR/WRPR instructions WIM no longer exists. It is replaced by TBA. PREFETCHA SDIVX. It has been replaced by several separate registers that are read/written with other instructions Return from trap (replace by DONE/RETRY) Store Double from Floating-point Queue (replaced by the RDPR FQ instruction Miscellaneous Instruction Changes Table E-9 Miscellaneous Instruction Changes IMPDEPn MEMBAR (Changed) Implementation-dependent instructions (replace SPARC-V8 CPop instructions) (Added) Memory barrier (memory synchronization support) 76 SPARC Assembly Language Reference Manual—November 1995 .E Table E-7 Added Instructions to Support High-Performance (Continued) MOVcc MOVr MULX POPC PREFETCH. WIM has been replaced by several register-window registers PSR no longer exists.

pn} bcs{.a} {. label %icc or %xcc.pn} bleu{.pn} bvs{.a} {. label %icc or %xcc. Table E-10 SPARC-V9 to Assembly Language Mapping Opcode Mnemonic Argument List Operation (Branch on cc with prediction) Branch always Branch never Branch on not equal Branch on equal Branch on greater Branch on less or equal Branch on greater or equal Branch on less Branch on greater unsigned Branch on less or equal unsigned Branch on carry clear (greater than or equal.a} {.pt|. label %icc or %xcc.a} {. label %icc or %xcc.a} {.pt|. label %icc or %xcc.pn} bne{. label %icc or %xcc. label %icc or %xcc.pt|. label %icc or %xcc.a} {.a} {.a} {.pt|.pn} bgu{.pn} bneg{.a} {.pn} bcc{.pn} %icc or %xcc. unsigned) Branch on positive Branch on negative Branch on overflow clear Branch on overflow set Comments BPA BPN BPNE BPE BPG BPLE BPGE BPL BPGU BPLEU BPCC BPCS BPPOS BPNEG BPVC BPVS ba{.a} {.pt|.a} {.pn} be{.pn} bvc{. label %icc or %xcc.pt|.pn} bge{.pt|. label %icc or %xcc.a} {. unsigned) Branch on carry set (less than.pt|.pn} ble{. label %icc or %xcc. label %icc or %xcc.pt|.a} {. label %icc or %xcc. label %icc or %xcc.pt|.pt|.pt|. label %icc or %xcc.a} {.a} {.pt|.pt|.pt|.pn} bn{.pt|.a} {.E SPARC-V9 Instruction Set Mapping The following tables describe the SPARC-V9 instruction-set mapping.pn} bg{.pn} bl{.pn} bpos{. label 1 0 not Z Z not (Z or (N xor V)) Z or (N xor V) not (N xor V) N xor V not (C or Z) C or Z not C C not N N not V V SPARC-V9 Instruction Set 77 .

pn} brlez{.regrs2. label regrs1.pt|.a} {.pt|.regrd [regrs1]%asi.a} {.regrs2.regrs2.pn} brgz{.pn} brlz{.a} {. label CASA CASXA [regrs1]imm_asi.pn} brgez{.regrs2.pt|.pn} brnz{.regrd [regrs1]imm_asi. label regrs1. label regrs1.a} {.regrd 78 SPARC Assembly Language Reference Manual—November 1995 .regrd [regrs1]%asi.pt|.a} {.pt|.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode BRZ BRLEZ BRLZ BRNZ BRGZ BRGEZ Mnemonic brz{.a} {. label regrs1. label regrs1.pt|.pn} casa casa casxa casxa Argument List Operation Branch on register zero Branch on register less than or equal to zero Branch on register less than zero Branch on register not zero Branch on register greater than zero Branch on register greater than or equal to zero Compare and swap word from alternate space Compare and swap extended from alternate space Comments Z N or Z N not Z not (N or Z) not N regrs1.

pt|.pt|.pt|.pt|.a} {.pn} fbu{.pn} fbo{. label %fccn.pn} fbne{.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode Mnemonic Argument List Operation (Branch on cc with prediction) Branch always Branch never Branch on unordered Branch on greater Branch on unordered or greater Branch on less Branch on unordered or less Branch on less or greater Branch on not equal Branch on equal Branch on unordered or equal Branch on greater or equal Branch on unordered or greater or equal Branch on less or equal Branch on unordered or less or equal Branch on ordered Comments FBPA FBPN FBPU FBPG FBPUG FBPL FBPUL FBPLG FBPNE FBPE FBPUE FBPGE FBPUGE FBPLE FBPULE FBPO fba{.pt|. label %fccn.pn} fbul{. label %fccn.a} {. label %fccn. label %fccn.a} {.pn} fbg{.pn} fble{. label %fccn.a} {.a} {.pt|.pt|. label 1 0 U G G or U L L or U L or G L or G or U E E or U E or G E or G or U E or L E or L or u E or L or G FLUSHW Flush register windows SPARC-V9 Instruction Set 79 .a} {.pn} fbge{.a} {.a} {. label %fccn.a} {.pn} flushw %fccn.pt|.a} {. label %fccn.a} {. label %fccn. label %fccn.pt|.pn} fblg{. label %fccn.pt|.pn} fbe{.pt|.pt|.pt|.pn} fbl{.pn} fbuge{.pn} fbn{.a} {.pt|. label %fccn.a} {.a} {.pn} fbule{.pn} fbug{.pt|. label %fccn.a} {.a} {.pn} fbue{.pt|. label %fccn. label %fccn.

q}cc fmov{s. q}vc fmov{s. fregrs2.d. fregrs2.d.d. fregrs2.q}gu fmov{s.d.d.d.d. fregrd %icc or %xcc.q}l fmov {s.q}e fmov {s. fregrd %icc or %xcc. fregrd %icc or %xcc. q}cs fmov{s. fregrs2. fregrd %icc or %xcc.d.q}n fmov {s. fregrd %icc or %xcc. fregrs2. fregrs2. q}vs %icc or %xcc. fregrd %icc or %xcc. fregrs2.d.d. fregrs2.d. fregrs2. fregrd %icc or %xcc. q}leu fmov{s.d.d.d.d. fregrs2.q}ne fmov {s. fregrd %icc or %xcc. fregrd %icc or %xcc.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode Mnemonic Argument List Operation (Move on integer cc) Move always Move never Move if not equal Move if equal Move if greater Move if less or equal Move if greater or equal Move if less Move if greater unsigned Move if less or equal unsigned Move if carry clear (greater or equal. q}pos fmov{s. q}neg fmov{s. fregrs2. fregrs2. fregrd %icc or %xcc. fregrs2.q}g fmov {s. fregrs2. fregrd %icc or %xcc. fregrd %icc or %xcc.d.q}a fmov {s. fregrs2. unsigned) Move if carry set (less than. fregrs2. fregrd %icc or %xcc. fregrd %icc or %xcc. fregrd 1 0 not Z Z not (Z or (N xor V)) Z or (N xor V) not (N xor V) N xor V not (C or Z) C or Z not C C not N N not V V 80 SPARC Assembly Language Reference Manual—November 1995 .q}le fmov {s. unsigned) Move if positive Move if negative Move if overflow clear Move if overflow set Comments FMOVA FMOVN FMOVNE FMOVE FMOVG FMOVLE FMOVGE FMOVL FMOVGU FMOVLEU FMOVCC FMOVCS FMOVPOS FMOVNEG FMOVVC FMOVVS fmov {s.q}ge fmov {s. fregrd %icc or %xcc.

fregrs2. fregrd SPARC-V9 Instruction Set 81 . fregrs2. fregrd regrs1. fregrd regrs1. fregrs2.q}lz fmovr {s. fregrs2.q}ne fmovr {s.d.d.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode Mnemonic Argument List Operation (Move f-p register on cc) Move if register zero Move if register less than or equal zero Move if register less than zero Move if register not zero Move if register greater than zero Move if register greater than or equal to zero Comments FMOVRZ FMOVRLEZ FMOVRLZ FMOVRNZ FMOVRGZ FMOVRGEZ fmovr {s. fregrs2. fregrs2. fregrd regrs1.d.q}gez regrs1. fregrd regrs1.q}lz fmovr {s.d.d. fregrd regrs1.q}gz fmovr {s.d.q}e fmovr {s.

d.fregrs2.fregrd %fccn.fregrd %fccn.d.fregrd %fccn.fregrs2. q}ge fmov{s.fregrs2.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode Mnemonic Argument List Operation (Move on floating-point cc) Move always Move never Move if unordered Move if greater Move if unordered or greater Move if less Move if unordered or less Move if less or greater Move if not equal Move if equal Move if unordered or equal Move if greater or equal Move if unordered or greater or equal Move if less or equal Move if unordered or less or equal Move if ordered Comments FMOVFA FMOVFN FMOVFU FMOVFG FMOVFUG FMOVFL FMOVFUL FMOVFLG FMOVFNE FMOVFE FMOVFUE FMOVFGE FMOVFUGE FMOVFLE FMOVFULE FMOVFO fmov{s.fregrd %fccn. q}u fmov{s. q}l fmov{s.d.fregrd %fccn.fregrd 1 0 U G G or U L L or U L or G L or G or U E E or U E or G E or G or U E or L E or L or u E or L or G LDSW LDSWA [address].fregrs2. q}o ldsw ldsw %fccn.fregrd %fccn.fregrs2. q}ule fmov{s. q}uge fmov{s.fregrs2.fregrd %fccn.d.d.d.fregrd %fccn. q}ul fmov{s.fregrd %fccn.fregrd %fccn.fregrs2.fregrs2.d. q}g fmov{s.fregrd %fccn. q}e fmov{s.d.fregrs2.fregrs2.fregrs2.d.fregrs2.d. regrd Load a signed word Load signed word from alternate space 82 SPARC Assembly Language Reference Manual—November 1995 .d.fregrd %fccn.fregrd %fccn.fregrs2.fregrs2.fregrd %fccn.d.d.d.fregrd %fccn. q}lg fmov{s.fregrs2. q}ug fmov{s.fregrs2. q}ne fmov{s.d. q}a fmov{s.d. q}le fmov{s. q}ue fmov{s. q}n fmov{s. regrd [regaddr] imm_asi.

reg_or_imm11. regrd [regaddr] imm_asi. reg_or_imm11. reg_or_imm11. regrd %icc or %xcc. reg_or_imm11. regrd %icc or %xcc. regrd %icc or %xcc. reg_or_imm11. regrd %icc or %xcc. regrd %icc or %xcc. regrd %icc or %xcc. reg_or_imm11. reg_or_imm11. reg_or_imm11. unsigned) Move if carry set (less than. regrd %icc or %xcc. reg_or_imm11. regrd %icc or %xcc. reg_or_imm11. regrd %icc or %xcc. reg_or_imm11. regrd %icc or %xcc. regrd [reg_plus_imm] %asi. reg_or_imm11. regrd 1 0 not Z Z not (Z or (N xor V)) Z or (N xor V) not (N xor V) N xor V not (C or Z) C or Z not C C not N N not V V SPARC-V9 Instruction Set 83 . regrd %icc or %xcc. reg_or_imm11. regrd %icc or %xcc. regrd [address]. reg_or_imm11. regrd %icc or %xcc. %fsr Operation Load extended word Load extended word from alternate space Load floating-point state register Memory barrier (Move integer register on cc) Move always Move never Move if not equal Move if equal Move if greater Move if less or equal Move if greater or equal Move if less Move if greater unsigned Move if less or equal unsigned Move if carry clear (greater or equal. reg_or_imm11. unsigned) Move if positive Move if negative Move if overflow clear Move if overflow set Comments MEMBAR membar membar_mask MOVA MOVN MOVNE MOVE MOVG MOVLE MOVGE MOVL MOVGU MOVLEU MOVCC MOVCS MOVPOS MOVNEG MOVVC MOVVS mova movn movne move movg movle movge movl movgu movleu movcc movcs movpos movneg movvc movvs %icc or %xcc. regrd %icc or %xcc.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode LDX LDXA LDXFSR Mnemonic ldx ldxa ldxa ldx Argument List [address]. regrd %icc or %xcc. reg_or_imm11.

reg_or_imm11.regrd %fccn.regrd %fccn.regrd %fccn.reg_or_imm11.reg_or_imm11.regrd reg_or_imm. regrd [address].regrd %fccn.reg_or_imm11.reg_or_imm11.regrd %fccn.reg_or_imm11.regrd regrs1.reg_or_imm11.regrd %fccn.regrd %fccn.regrd regrs1.regrd G or L or L or L or G or E or E or E or G or 1 0 U G U L U G U E U G U E or L E or L or u E or L or G MOVRZ MOVRLEZ MOVRLZ MOVRNZ MOVRGZ MOVRGEZ movre movrlez movrlz movrnz movrgz movrgez regrs1.regrd %fccn.reg_or_imm11. prefetch_fcn [reg_plus_imm] %asi.reg_or_imm11. version 9 Comments MOVFA MOVFN MOVFU MOVFG MOVFUG MOVFL MOVFUL MOVFLG MOVFNE MOVFE MOVFUE MOVFGE MOVFUGE MOVFLE MOVFULE MOVFO mova movn movu movg movug movl movul movlg movne move movue movge movuge movle movule movo %fccn. prefetch_dcn [regaddr] imm_asi. reg_or_imm.regrd %fccn.reg_or_imm11.reg_or_imm11.reg_or_imm11.reg_or_imm11.regrd %fccn.regrd %fccn. reg_or_imm10. reg_or_imm10. reg_or_imm10. reg_or_imm10.reg_or_imm11. reg_or_imm10.regrd %fccn.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode Mnemonic Argument List Operation (Move on floating-point cc) Move always Move never Move if unordered Move if greater Move if unordered or greater Move if less Move if unordered or less Move if less or greater Move if not equal Move if equal Move if unordered or equal Move if greater or equal Move if unordered or greater or equal Move if less or equal Move if unordered or less or equal Move if ordered (Move register on register cc) Move if register zero Move if register less than or equal to zero Move if register less than zero Move if register not zero Move if register greater than zero Move if register greater than or equal to zero (Generic 64-bit Multiply) Multiply (signed or unsigned) Population count Prefetch data Prefetch data from alternate space See The SPARC architecture manual.regrd %fccn.regrd %fccn. reg_or_imm10.regrd Z N or Z N not Z N nor Z not N MULX POPC PREFETCH PREFETCHA mulx popc prefetch prefetcha prefetcha regrs1.regrd regrs1.reg_or_imm11. prefetch_fcn See SDIVX and UDIVX 84 SPARC Assembly Language Reference Manual—November 1995 .reg_or_imm11.regrd regrs1.regrd regrs1.regrd %fccn.

[reg_plus_imm] %asi %fsr. reg_or_imm. fregrs2. reg_or_imm. fregrs2. fregrs2. regrd See MULX and SDIVX SPARC-V9 Floating-Point Instruction Set Mapping SPARC-V9 floating-point instructions are shown in Table E-11 Table E-11 SPARC-V9 Floating-Point Instructions SPARC F[sdq]TOx Mnemonic fstox fdtox fqtox fstoi fdtoi fqtoi * Argument List fregrs2. [address] regrd.E Table E-10 SPARC-V9 to Assembly Language Mapping (Continued) Opcode Mnemonic Argument List Operation (64-bit signed divide) Signed Divide Comments SDIVX sdivx regrs1. fregrs2. [address] imm_asi regrd.regrd See MULX and UDIVX STX STXA STXFSR stx stxa stxa stx regrd. [address] Store extended word Store extended word into alternate space Store floating-point register (all 64-bits) (64-bit unsigned divide) Unsigned divide UDIVX udivx regrs1. fregrd fregrd fregrd fregrd fregrd fregrd Description Convert floating point to 64-bit integer Convert floating-point to 32-bit integer * Types of Operands are denoted by the following lower-case letters: i 32-bit integer x 64-bit integer s single d double q quad SPARC-V9 Instruction Set 85 . fregrs2.

Load quad floating-point register from alternate space Store floating-point register to alternate space Store double floating-point register to alternate space Store quad floating-point register to alternate space FNEG[dq] FABS[dq] LDFA LDDFA LDQFA STFA STDFA STQFA * Types of Operands are denoted by the following lower-case letters: i 32-bit integer x 64-bit integer s single d double q quad 86 SPARC Assembly Language Reference Manual—November 1995 . fregrs2. fregrd [reg_plus_imm] %asi. fregrd [reg_plus_imm] %asi. fregrs2. fregrd fregrd. fregrd fregrs2. fregrd [regaddr] imm_asi.E Table E-11 SPARC-V9 Floating-Point Instructions (Continued) SPARC FxTO[sdq] Mnemonic* fxtos fxtod fxtoq fitos fitod fitoq fmovd fmovq fnegd fnegq fabsd fabsq lda lda ldda ldda ldqa ldqa sta sta stda stda stqa stqa Argument List fregrs2. fregrd fregrd fregrd fregrd fregrd fregrd Description Convert 64-bit integer to floating point Convert 32-bit integer to floating point FMOV[dq] fregrs2. fregrd. fregrd fregrs2. fregrd fregrs2. fregrd [reg_plus_imm] %asi. fregrd [regaddr] imm_asi. fregrd fregrs2. fregrd. fregrd. fregrd. fregrs2. fregrd fregrs2. fregrd [regaddr] imm_asi. [regaddr] imm_asi [reg_plus_imm] %asi [regaddr] imm_asi [reg_plus_imm] %asi [regaddr] imm_asi [reg_plus_imm] %asi Move double Move quad Negate double Negate quad Absolute value double Absolute value quad Load floating-point register from alternate space Load double floating-point register from alternate space. fregrd. fregrs2. fregrs2.

%lo(value). [regrsl]. regrd regrd. %g0. %g0 Return from subroutine Return from leaf subroutine (value & 3FF16)==0 when 0 ≤ value ≤ 4095 (otherwise) Do not use setuw in a DCTI delay slot. label %y. regrs2. regrd %g0. regrs2. clrx clruw clruw iprefetch mov mov mov ret retl [address] regrs1. [regrsl]. regrd [regrsl]ASI_P_L. regrs2. regrs2. regrd %g0. regrd %g0. regrs2. regrd %hi(value). regrd [regrsl]ASI_P. regrs2. regrd. regrd %asrn. regrs2. regrd regrd regrd regrd Hardware Equivalent(s) casa casa casxa casxa [regrsl]ASI_P. reg_or_imm. [address] regrs1. %asrn stx srl srl bn. regrd regrd label %y. pt rd rd wr jmpl jmpl setuw value.E SPARC-V9 Synthetic Instruction-Set Mapping Here is a mapping of synthetic instructions to hardware equivalent instructions. regrs2. value. %g0 %o7+8. regrd %xcc. regrd [regrsl]ASI_P_L. %g0. regrd reg_or_imm. regrd SPARC-V9 Instruction Set 87 . regrd.regrd sethi or sethi or %hi(value). %asrn %i7+8. extended Clear extended word Copy and clear upper word Clear upper word Instruction prefetch. Table E-12 SPARC-V9 Synthetic Instructions to Hardware Instruction Synthetic Instruction cas casl casx casxl [regrsl]. regrd %asrn. Comment Compare & swap (cas) cas little-endian cas extended cas little-endian. [regrsl].

regrd %g0. if value<0) Do not use setsw in a CTI delay slot. %lo(value).regrd Hardware Equivalent(s) sethi or sethi sra sethi or sethi or sra %hi(value). regrd. regrd %hi(value). regrd regrd. %g0. %lo(value). regrd. regrd %hi(value). value. regrd regrd sra sra 88 SPARC Assembly Language Reference Manual—November 1995 . regrd regrsl. if value>=0) (otherwise. Sign-extend 32-bit value to 64 bits signx signx regrsl. regrd Comment value>=0 and (value & 3FF16)==0 -4096 ≤ value ≤ 4095 if (value<0) and ((value & 3FF)==0) (otherwise. %g0. regrd. regrd regrd. %g0. regrd regrd. %g0. regrd.E Table E-12 SPARC-V9 Synthetic Instructions to Hardware Instruction (Continued) Synthetic Instruction setsw value. regrd %hi(value).

Eight-bit Format A 32-bit word contains pixels of four unsigned 8-bit integers. Image components are 8 or 16 bits. The FPACKFIX instruction supports conversion from 32-bit fixed to 16-bit fixed. The integers represent image intensity values (α. Note – SPARC-V9 instruction set extensions used in executables may not be portable to other SPARC-V9 systems. Pixel multiplication is used to convert from pixel data to fixed data. Pack instructions are used to convert from fixed data to pixel data (clip and truncate to an 8-bit unsigned value). Graphics Data Formats The overhead of converting to and from floating-point arithmetic is high. so the graphics instructions are optimized for short-integer arithmetic. Rounding is done by adding one to the rounding bit position. Intermediate results are 16 or 32 bits. A 64-bit word contains two 8-bit signed fixed-point values. You should use floating-point data to perform complex calculations needing more precision or dynamic range.E SPARC-V9 Instruction Set Extensions This section describes extensions to the SPARC-V9 instruction set. R). G. Support is provided for band interleaved images (store color components of a point). This is the fixed 16-bit data format. Enough precision and dynamic range (for filtering and simple image computations on pixel values) can be provided by an intermediate format of fixed data values. The extensions support enhanced graphics functionality and improved memory access efficiency. and band sequential images (store all values of one color component). B. This is the fixed 32bit data format. SPARC-V9 Instruction Set 89 . Fixed Data Formats A 64-bit word contains four 16-bit signed fixed-point values.

and double-precision floating-point registers contain the fixed values. 90 SPARC Assembly Language Reference Manual—November 1995 . Single-precision floatingpoint registers contain the pixel values. regrd regrs1. %gsr Description read GSR write GSR Graphics Instructions Unless otherwise specified. The opcode space reserved for the Implementation-Dependent Instruction1 (IMPDEP1) instructions is where the graphics instruction set is mapped.E SHUTDOWN Instruction All outstanding transactions are completed before the SHUTDOWN instruction completes. Table E-14 Graphics Status Register SPARC RDASR WRASR Mnemonic rdasr wrasr Argument List %gsr. There are 32 double-precision registers. floating-point registers contain all instruction operands. Table E-13 SPARC-V9 SHUTDOWN Instruction SPARC SHUTDOWN Mnemonic shutdown Argument List Description shutdown to enter power down mode Graphics Status Register (GSR) You use ASR 0x13 instructions RDASR and WRASR to access the Graphics Status Register. reg_or_imm.

fregrs1. fregrs2. fregrs2. fregrs1. fregrd fregrd fregrd fregrd fregrd fregrd fregrd Description 8x16-bit partition 8x16-bit upper α partition 8x16-bit lower α partition upper 8x16-bit partition lower unsigned 8x16-bit partition upper 8x16-bit partition lower unsigned 8x16-bit partition SPARC-V9 Instruction Set 91 . Table E-15 SPARC-V9 Partitioned Add/Subtract SPARC FPADD16 FPADD16S FPADD32 FPADD32S FPSUB16 FPSUB16S FPSUB32 FPSUB32S Mnemonic fpadd16 fpadd16s fpadd32 fpadd32s fpsub16 fpsub16s fpsub32 fpsub32s Argument List fregrs1. fregrs2. fregrs2. fregrs2. Table E-16 SPARC-V9 Pixel Formatting SPARC FPACK16 FPACK32 FPACKFIX FEXPAND FPMERGE Mnemonic fpack16 fpack32 fpackfix fexpand fpmerge Argument List fregrs2. fregrs2. fregrs1. fregrs1. fregrs1. fregrs2. fregrd fregrd fregrd fregrs2. fregrs1. fregrs2.E Partitioned add/subtract instructions perform two 32-bit or four 16-bit partitioned adds or subtracts between the source operands corresponding fixed point values. fregrs2. fregrs1. fregrs1. fregrs2. fregrs2. fregrs2. fregrs2. fregrs2. fregrs1. fregrs1. fregrs2. Table E-17 SPARC-V9 Partitioned Multiply SPARC FMUL8x16 FMUL8x16AU FMUL8x16AL FMUL8SUx16 FMUL8ULx16 FMULD8SUx16 FMULD8ULx16 Mnemonic fmul8x16 fmul8x16au fmul8x16al fmul8sux16 fmul8ulx16 fmuld8sux16 fmuld8ulx16 Argument List fregrs1. fregrs1. fregrs2. fregrs1. fregrs2. fregrs1. fregrs1. fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd Description four 16-bit add two 16-bit add two 32-bit add one 32-bit add four 16-bit subtract two 16-bit subtract two 32-bit subtract one 32-bit subtract Pack instructions convert to a lower pixel or precision fixed format. fregrs1. fregrd fregrs2. fregrd Description four 16-bit packs two 32-bit packs four 16-bit packs four 16-bit expands two 32-bit merges Partitioned multiply instructions have the following variations.

fregrd Description find misaligned data access address same as above. regrd fregrs1. Table E-18 SPARC-V9 Alignment Instructions SPARC ALIGNADDRESS ALIGNADDRESS_ LITTLE FALIGNDATA Mnemonic alignaddr alignaddrl faligndata Argument List regrs1.E Alignment instructions have the following variations. data alignment 92 SPARC Assembly Language Reference Manual—November 1995 . regrs2. fregrs2. but little-endian do misaligned data. regrs2. regrd regrs1.

1’s complement same as above. fregrs2. fregrs2. fregrs2. fregrs2. fregrs1. fregrs1. fregrs1. fregrs1. fregrs1. fregrs1. fregrs2. fregrs1. fregrs1. single precision logical OR logical OR. single precision negated src1 OR src2 same as above. fregrs1. fregrs2. fregrs1. fregrs2. fregrs1. fregrs2. single precision negated src1 AND src2 same as above. fregrs1. fregrs1. single precision logical NOR logical NOR. fregrs2. fregrs1. Description zero fill zero fill. fregrs1. single precision src1 OR negated src2 same as above. single precision logical XOR logical XOR. fregrs2. fregrs2. fregrs1. fregrs2. fregrs2. Table E-19 SPARC-V9 Logical Operate Instructions SPARC FZERO FZEROS FONE FONES FSRC1 FSRC1S FSRC2 FSRC2S FNOT1 FNOT1S FNOT2 FNOT2S FOR FORS FNOR FNORS FAND FANDS FNAND FNANDS FXOR FXORS FXNOR FXNORS FORNOT1 FORNOT1S FORNOT2 FORNOT2S FANDNOT1 FANDNOT1S FANDNOT2 FANDNOT2S Mnemonic fzero fzeros fone fones fsrc1 fsrc1s fsrc2 fsrc2s fnot1 fnot1s fnot2 fnot2s for fors fnor fnors fand fands fnand fnands fxor fxors fxnor fxnors fornot1 fornot1s fornot2 fornot2s fandnot1 fandnot1s fandnot2 fandnot2s Argument List fregrd fregrd fregrd fregrd fregrs1. fregrs1. fregrs2. fregrs1. single precision copy src1 copy src1. single precision fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrs2. fregrs2. fregrs2. fregrs2. single precision one fill one fill. single precision logical NAND logical NAND. single precision negate src1.E Logical operate instructions perform one of sixteen 64-bit logical operations between rs1 and rs2 (in the standard 64-bit version). 1’s complement same as above. fregrs2. fregrs2. fregrs2. fregrs1. fregrs2. fregrs1. single precision copy src2 copy src2. single precision negate src2. fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd fregrd SPARC-V9 Instruction Set 93 . single precision logical AND logical AND. fregrs1. fregrs1. fregrs1. single precision logical XNOR logical XNOR. single precision src1 AND negated src2 same as above. fregrs2. fregrs2.

fregrs2. compare. compare. SPARC-V9 Pixel Component Distance Instruction SPARC PDIST Mnemonic pdist Argument List fregrs1. compare. fregrs1. little-endian Pixel component distance instructions are used for motion estimation in video compression algorithms. fregrs1. regrd regrd regrd regrd regrd regrd regrd regrd Description 4 2 4 2 4 2 4 2 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit compare. fregrs2. fregrs2. regrs1. regrs1. compare. regrs2. fregrs2. regrs2. fregrs2. regrs2. distance between 94 SPARC Assembly Language Reference Manual—November 1995 . fregrs2.E Pixel compare instructions compare fixed-point values in rs1 and rs2 (two 32 bit or four 16 bit) Table E-20 SPARC-V9 Pixel Compare SPARC FCMPGT16 FCMPGT32 FCMPLE16 FCMPLE32 FCMPNE16 FCMPNE32 FCMPEQ16 FCMPEQ32 Mnemonic fcmpgt16 fcmpgt32 fcmple16 fcmple32 fcmpne16 fcmpne32 fcmpeq16 fcmpeq32 Argument List fregrs1. fregrs1. set set set set set set set set rd rd rd rd rd rd rd rd if if if if if if if if src1>src2 src1>src2 src1≤src2 src1≤src2 src1≠src2 src1≠src2 src1=src2 src1=src2 Edge handling instructions handle the boundary conditions for parallel pixel scan line loops. regrs2. little-endian 4 16-bit edge boundary processing same as above. regrd regrd regrd regrd regrd regrd Description 8 8-bit edge boundary processing same as above. compare. compare. compare. regrs1. regrs2. fregrs2. regrs2. fregrs2. Table E-21 SPARC V-9 Edge Handling SPARC EDGE8 EDGE8L EDGE16 EDGE16L EDGE32 EDGE32L Mnemonic edge8 edge8l edge16 edge16l edge32 edge32l Argument List regrs1. fregrs1. fregrd Description 8 8-bit components. little-endian 2 32-bit edge boundary processing same as above. regrs1. fregrs1. regrs1. fregrs2. fregrs1. fregrs1.

regrd regrs1.E The three-dimensional array addressing instructions convert threedimensional fixed-point addresses (in rs1) to a blocked-byte address. Table E-22 SPARC V-9 Three-Dimensional Array Addressing SPARC ARRAY8 ARRAY16 ARRAY32 Mnemonic array8 array16 array32 Argument List regrs1. regrs2. regrs2.The result is stored in rd. but 16-bit same as above. regrd regrs1. regrs2. regrd Description convert 8-bit 3-D address to blocked byte address same as above. but 32-bit SPARC-V9 Instruction Set 95 .

little endian four 16-bit conditional stores to: primary address space secondary address space primary address space. imm_asi Note – To select a partial store instruction. Table E-23 SPARC-V9 Partial Store SPARC imm_asi Argument List Description eight 8-bit conditional stores to: primary address space secondary address space primary address space. little endian STDFA STDFA STDFA STDFA STDFA STDFA STDFA STDFA STDFA STDFA STDFA STDFA ASI_PST8_P ASI_PST8_S ASI_PST8_PL ASI_PST8_SL ASI_PST16_P ASI_PST16_S ASI_PST16_PL ASI_PST16_SL ASI_PST32_P ASI_PST32_S ASI_PST32_PL ASI_PST32_SL stda fregrd. little endian two 32-bit conditional stores to: primary address space secondary address space primary address space. [fregrs1] regmask. 96 SPARC Assembly Language Reference Manual—November 1995 .E Memory Access Instructions These memory access instructions are part of the SPARC-V9 instruction set extensions. use one of the partial store ASIs with the STDA instruction. little endian secondary address space. little endian secondary address space. little endian secondary address space.

[reg_addr] imm_asi ldda [reg_plus_imm] %asi. little endian Note – To select a short floating-point load and store instruction. regrd Description 128-bit atomic load LDDA [reg_plus_imm] %asi.E Table E-24 SPARC-V9 Short Floating-Point Load and Store SPARC imm_asi Argument List Description 8-bit load/store from/to: primary address space LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA ASI_FL8_P ldda [reg_addr] imm_asi. little endian ASI_FL8_SL secondary address space. use one of the short ASIs with the LDDA and STDA instructions Table E-25 SPARC-V9 Atomic Quad Load SPARC LDDA imm_asi ASI_NUCLEUS_ QUAD_LDD ASI_NUCLEUS_ QUAD_LDD_L Argument List [reg_addr] imm_asi. freqrd stda [reg_plus_imm] %asi ASI_FL8_S secondary address space ASI_FL8_PL primary address space. freqrd stda freqrd. regrd 128-bit atomic load. little endian SPARC-V9 Instruction Set 97 . little endian ASI_FL16_SL secondary address space. little endian 16-bit load/store from/to: primary address space ASI_FL16_P ASI_FL16_S secondary address space ASI_FL16_PL primary address space.

ASI_BLK_AIUPL primary address space. little endian ASI_BLK_COMMIT_P 64-byte block commit store to primary address space 64-byte block commit store to secondary address space ASI_BLK_COMMIT_S Note – To select a block load and store instruction. user privilege. [reg_plus_imm] %asi ASI_BLK_AIUS secondary address space. freqrd stda fregrd. [reg_addr] imm_asi ldda [reg_plus_imm] %asi. 98 SPARC Assembly Language Reference Manual—November 1995 . little endian secondary address space. use one of the block transfer ASIs with the LDDA and STDA instructions. user privilege little endian primary address space ASI_BLK_AIUSL ASI_BLK_P ASI_BLK_S secondary address space ASI_BLK_PL primary address space. user privilege LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA LDDFA STDFA ASI_BLK_AIUP ldda [reg_addr] imm_asi. freqrd stda freqrd. little endian ASI_BLK_SL secondary address space.E Table E-26 SPARC-V9 Block Load and Store SPARC imm_asi Argument List Description 64-byte block load/store from/to: primary address space. user privilege.

4 syntax notation. 10 converting existing object files. 40 cp_disabled trap.double. 60 data generating directives. 3 lines. 24 types. 3 assignment directive. 73 D -D option. 21 current section. 25 atof(3). 5 hexadecimal. 11 dis program. 45 . 45 . 5 comment lines. 25 default output file. 24 assembly language. 45 as command.align. 41 current location. 63 disassembling object code. 27 coprocessor instruction. 46. in special symbols. 5 Control Transfer Instructions (CTI). 59 . 4 99 . 59 assembler command line options.Index A addresses. 5 floating-point. 46 C case distinction. 49 case distinction. 45 byte order for V9. 5 . 4 statements. 60 assembler directives. 59 command-line options. 5 decimal. 14 B binary operations. 60 comment lines.common. 5 octal numeric. 45 assembler command line. 46 constants.byte.ascii.asciz. 8 cc language driver.alias. 9 . 40 cp_exception trap. 63 . multiple. 22 . 5.

12 flag. 5 G . 47 hardware instructions SPARC architecture. 12 ident. 61 multiple comment lines. 10 escape codes. 9 hardware integer assembly language instructions. 4 . 15 multiple strings in string table. 59 multiple sections. 13 type. 89 instruction set. 12 entry.empty. in strings. 29 instructions assembly language. 12 machine. 13 shoff. 13 shentsize. 46 file syntax. 13 shstrndx. 60 . as command. 31 hyphen (-). 5 invoking. 59 lexical features. on as command line. 12 to 13 ehsize. 31 hardware integer. 6 Executable and Linking Format (ELF) files. 39 floating-point pseudo-operations. 47 M -m option. 2.file. 13 phnum. 59 features. 31 integer suffixes. 13 . 5 language drivers. 12 phentsize.half. 61 labeling format. 11 expressions. 47 . 4 lines syntax. used by assembler.empty pseudo-operation. 4 . 10 error messages. 13 shnum. 59 I -I option. 24 H . 13 version. 46 . 21 locations. 31 integer instructions.E ELF header. 59 K -K option. 5 multiple files. 29 100 SPARC Assembly Language Reference Manual—November 1995 . 2 labels.global.local. 60 L -L option.globl. 47 location counter. 13 phoff. 74 instruction set extensions (V9). 59 fbe command. 21 F f77 language driver. 47 instruction set changes (V9). 4 floating-point instructions. lexical.ident.

16 info.reserve.nonvolatile. 17 sections. 60 P -P option.single. 22 Index 101 .skip.quad. 48 Q -Q option. 89 alternate space access.noalias. 51 . 7 . 60 . 16 link. 87 special floating-point values. 16 type. 15 entsize. 20 predefined user sections. 61 . 45 pseudo-ops examples of. 5 special names.section. 14 . 7 . 48 options command-line. 49 section control directives.seg. 89 instruction set mapping. 25 section header. 2 object files type. 51 SPARC-V9. 5 numeric labels. 51 O -o option. 15 to 18 addr. 49 S -S option. 2. 25 section control pseudo-ops. 15 flags. 5 . 45 . 16 size.optim. 48 . 2. 61 percentage sign (%). 61 object file format. 61 -q option. 48 numbers. 50 . 48 predefined non-user sections. 71 8-bit format. 55 . 62 -sb option. 72 synthetic instruction set. 9 . floating point values.pushsection. 89 floating-point instructions.N . 61 -s option.stabn. 50 .noalias pseudo-op. 73 fixed data formats. 74 instruction set extensions. 73 byte order. 15 addralign.stabs.size. 77 registers. 5 special symbols. 7 relocatable files. 48 pseudo-operations. 51 . 49 R references. 89 instruction set changes. xii registers.popsection. 16 offset. 19 . 11 relocation tables. 16 name. 85 graphics data formats.proc. 11 operators.

24 multiple references in string table. 51 unary operators. 22 other.weak. 52 . 24 symbol. 25 /usr/include/sys/trap.uahalf. 22 symbol tables. 22 to 23 info. 6 unreferenced in string table. 22 syntax notation. 24 strings. 23 size. 63 -xarch=v8plus option.version. 52 W .word. 23 value.volatile. 24 sub-strings in string table references to. 62 table notation.h. 63 .xstabs. 4 string tables. 41 . 3 synthetic instructions. 52 102 SPARC Assembly Language Reference Manual—November 1995 . 52 T -T option. 53 symbol attribute directives. 52 X -xarch=v7 option. 62 -xarch=v8 option. 25 symbol names. 51 . 6 multiple in string table. 23 shndx. reserved. 9 user sections. 37 V -V option. 23 name. 24 suggested style. 63 -xarch=v8plusa option. 51 U -U option. 62 .uaword. 62 -xarch=v8a option. 6 symbol table. 62 .statement syntax.type. 30 trap numbers. 37 .

Inc. SPARCstorage. Inc. le logo Sun. microSPARC. Sun reconnait les efforts de pionniers de Xerox pour la recherche et le développement du concept des interfaces d’utilisation visuelle ou graphique pour l’industrie de l’informatique. SPARCompiler. pour ses utilisateurs et licenciés.. ET SANS QUE CETTE LISTE NE SOIT LIMITATIVE. CES CHANGEMENTS SERONT INCORPORES AUX NOUVELLES EDITIONS DE LA PUBLICATION.7013 et FAR 52. Inc. et exclusivement licenciée par X/Open Company Ltd. CETTE PUBLICATION EST FOURNIE "EN L’ETAT" SANS GARANTIE D’AUCUNE SORTE. la duplication ou la divulgation par l’administation americaine sont soumises aux restrictions visées a l’alinéa (c)(1)(ii) de la clause relative aux droits des données techniques et aux logiciels informatiques du DFAR 252. SPARCdesign. Inc. Les utilisateurs d’interfaces graphiques OPEN LOOK® et Sun™ ont été développés par Sun Microsystems. L’APTITUDE DES PRODUITS A REPONDRE A UNE UTILISATION PARTICULIERE OU LE FAIT QU’ILS NE SOIENT PAS CONTREFAISANTS DE PRODUITS DE TIERS. licencié par l’Université de Californie. Le produit décrit dans ce manuel peut Être protege par un ou plusieurs brevet(s) americain(s).. microSPARC II et UltraSPARC sont exclusivement licenciées a Sun Microsystems. aux Etats-Unis et dans d’autres pays.Copyright 1995 Sun Microsystems. LEGENDE RELATIVE AUX DROITS RESTREINTS : l’utilisation. la copie et la décompliation. de Berkeley. Solaris sont des marques deposées ou enregistrées par Sun Microsystems. Tous droits réservés.227-19. par quelque moyen que ce soit sans l’autorisation préalable et écrite de Sun et de ses bailleurs de licence. filiale entierement detenue par Novell. Inc. Toutes les marques SPARC sont des marques deposées ou enregitrées de SPARC International. Le système X Window est un produit du X Consortium. SPARC811. SPARCworks. Inc. licencié par UNIX Systems Laboratories Inc. DES CHANGEMENTS SONT PERIODIQUEMENT APPORTES AUX INFORMATIONS CONTENUES AUX PRESENTES. Californie 94043-1100 USA. SPARCcluster. ainsi que par le système 4. cette licence couvrant aussi les licencies de Sun qui mettent en place OPEN LOOK GUIs et qui en outre se conforment aux licences écrites de Sun. UNIX est une marque enregistrée aux Etats-Unis et dans d’autres pays. Mountain View. SPARstation. 2550 Garcia Avenue.Ce produit ou document est protégé par un copyright et distribué avec des licences qui en restreignent l’utilisation. etranger(s) ou par des demandes en cours d’enregistrement. Les produits portant les marques sont basés sur une architecture développée par Sun Microsytems. PostScript et Display PostScript sont des marques d’Adobe Systems. SPARCprinter.227. s’il en a. et qui comprend la technologie relative aux polices de caractères. CETTE PUBLICATION PEUT CONTENIR DES MENTIONS TECHNIQUES ERRONEES OU DES ERREURS TYPOGRAPHIQUES. Des parties de ce produit pourront etre derivees du système UNIX®. SPARCengine. Sun détient une licence non exclusive de Xerox sur l’interface d’utilisation graphique. MARQUES Sun. Le logiciel détenu par des tiers.. Inc. Inc. Aucune partie de ce produit ou de sa documentation associée ne peuvent Être reproduits sous aucune forme. . SPARCcenter. est protégé par un copyright et licencié par des fourmisseurs de Sun. Inc. aux EtatsUnis et dans certains autres pays. Sun Microsystems. NI EXPRESSE NI IMPLICITE. SPARCserver. Y COMPRIS. Inc. PEUT REALISER DES AMELIORATIONS ET/OU DES CHANGEMENTS DANS LE(S) PRODUIT(S) ET/OU LE(S) PROGRAMME(S) DECRITS DANS DETTE PUBLICATION A TOUS MOMENTS. DES GARANTIES CONCERNANT LA VALEUR MARCHANDE. SUN MICROSYSTEMS INC.3. OPEN LOOK est une marque enregistrée de Novell.