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(EC 05574) VLSI DESIGN [3/2 ECE R-05 Regulation

]

UNIT 1: INTRODUCTION: Introduction to IC Technology - MOS, PMOS, NMOS, CMOS & BiCMOS
technologies- Oxidation, Lithography, Diffusion, Ion implantation, Metallisation, Encapsulation, Probe
testing, Integrated Resistors and Capacitors.

UNIT 2 (BASIC ELECTRICAL PROPERTIES): Basic Electrical Properties of MOS and BiCMOS
Circuits: Ids-Vds relationships, MOS transistor threshold Voltage, gm, gds, figure of merit ωo; Pass
transistor, NMOS Inverter, Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters.

UNIT 3 (VLSI CIRCUIT DESIGN PROCESSES): VLSI Design Flow, MOS Layers, Stick Diagrams,
Design Rules and Layout, 2 µm CMOS Design rules for wires, Contacts and Transistors Layout Diagrams
for NMOS and CMOS Inverters and Gates, Scaling of MOS circuits, Limitations of Scaling.

UNIT 4 (GATE LEVEL DESIGN) : Logic Gates and Other complex gates, Switch logic, Alternate gate
circuits, Basic circuit concepts, Sheet Resistance RS and its concept to MOS, Area Capacitance Units,
Calculations - τ - Delays, Driving large Capacitive Loads, Wiring Capacitances, Fan-in and fan-out, Choice
of layers

UNIT 5 (SUBSYSTEM DESIGN): Subsystem Design, Shifters, Adders, ALUs, Multipliers, Parity
generators, Comparators, Zero/One Detectors, Counters, High Density Memory Elements.

UNIT 6 (SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN): PLAs, FPGAs, CPLDs, Standard
Cells, Programmable Array Logic, Design Approach.

UNIT 7 (VHDL SYNTHESIS) : VHDL Synthesis, Circuit Design Flow, Circuit Synthesis, Simulation,
Layout, Design capture tools, Design Verification Tools, Test Principles.

UNIT 8 (CMOS TESTING): CMOS Testing, Need for testing, Test Principles, Design Strategies for test,
Chip-level Test Techniques, System-level Test Techniques, Layout Design for improved Testability.

TEXTBOOKS :
1. Essentials of VLSI circuits and systems - Kamran Eshraghian, Eshraghian Dougles and A. Pucknell,
PHI, 2005 Edition.
2. Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education, 1999.

REFERENCES :
1. Chip Design for Submicron VLSI: CMOS Layout & Simulation, - John P. Uyemura, Thomson
Learning.
2. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003.
3. Digital Integrated Circuits - John M. Rabaey, PHI, EEE, 1997.
4. Modern VLSI Design - Wayne Wolf, Pearson Education, 3rd Edition, 1997.

gm. NMOS. Driving large Capacitive Loads. Contacts and Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates. CPLDs. Limitations of Scaling UNIT 4 (GATE LEVEL DESIGN) : Logic Gates and Other complex gates.Adders. UNIT 3 (VLSI CIRCUIT DESIGN PROCESSES): VLSI Design Flow. Area Capacitance Units. High Density Memory Elements. Scaling of MOS circuits. Various pull ups. Counters. MOS Layers. Alternate gate circuits. Metallisation. Programmable Array Logic. Switch logic. CMOS & BiCMOS technologies- Oxidation. Standard Cells. Parity generators. Probe testing. Syllabus in detailed: UNIT 1: INTRODUCTION: Introduction to IC Technology – MOS. Basic circuit concepts. Fan-in and fan-out. Choice of layers UNIT 5 (SUBSYSTEM DESIGN): Subsystem Design. Sheet Resistance RS and its concept to MOS. Design Approach. Ion implantation. Zero/One Detectors. Shifters. ALUs. MOS transistor threshold Voltage. Multipliers. Diffusion.τ . Stick Diagrams. Bi-CMOS Inverters. Calculations .Delays. gds. FPGAs. figure of merit (ωo). 2 µm CMOS Design rules for wires. UNIT 6 (SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN): PLAs. Integrated Resistors and Capacitors UNIT 2 (BASIC ELECTRICAL PROPERTIES): Basic Electrical Properties of MOS and BiCMOS Circuits: Ids-Vds relationships. . Wiring Capacitances. Pass transistor. PMOS. Design Rules and Layout. Encapsulation. NMOS Inverter. Comparators. CMOS Inverter analysis and design. Lithography.

Design Strategies for test. UNIT 8 (CMOS TESTING): CMOS Testing. Chip-level Test Techniques. TTR/ .UNIT 7 (VHDL SYNTHESIS) : VHDL Synthesis. Circuit Synthesis. Note: I thought there will be some text book kind “contents” can be generated from VLSI syllabus. Design capture tools. Need for testing. But only 1 layer is possible. Test Principles. Layout Design for improved Testability. Design Verification Tools. So I think page no. Circuit Design Flow. Test Principles. Simulation.1 of this file alone sufficient for the VLSI syllabus!. System-level Test Techniques. Layout.