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Power Architecture Conference

Design, Verification and Implementation of Power Architecture based products Presenter Wolfgang Stronski Date May 27, 2008

The Power Architecture and word marks and the Power and logos and related marks are trademarks and service marks licensed by

Cadence Design Systems
MISSION To be and be recognized as the indispensable partner to the electronics industry
Wireless handsets

Gaming and home entertainment

Computing, storage, and networking

Automotive 1

Cadence Design Systems

Global leader of design automation solutions

Market Cap: $3.0B* 2007 Revenue: $1.6B WW offices: 60 Employees: 5300

2007 9% revenue growth 25% non-GAAP EPS growth 30% non-GAAP operating margin $402 million operating cash flow
*February 2008

NOTE: Revenue and Regional Mix are for the four quarters ended December 29, 2007.


Global reach Europe 18% North America 49% Asia 12% Japan 21% 3 .

Cadence Design Systems » Putting customers first » Cadence customers • Systems companies • Semiconductor companies • Design/supply chain partners » Electronic systems and Integrated Circuits (IC’s) development 4 .

Cadence Design Systems Enabling companies to play in trillion dollar markets… MISSION To be and be recognized as the indispensable partner to the electronics industry COMPUTING COMMS CONSUMER AUTOMOTIVE INDUSTRIAL GOV/MIL 5 .

Computing.Semiconductor consumption driven by 3 ‘Cs’ Consumer. Communications. IC Insights COMPUTING COMMS CONSUMER AUTOMOTIVE INDUSTRIAL GOV/MIL 6 . 2004-2009 Total IC Market by System Type ($B) Source: SIA.

3 ‘Cs’ Common characteristics Design requirements User Long power life Low battery Small form factor (consumer) SoC. SiP. PCB Feature-rich Large scale integration Seamless connectivity Advanced RF technology High quality audio Analog/mixed-signal Multimedia High-performance digital HW/SW verification Applications 7 .

low power PCB design Miniature. memory. system. digital. highspeed Block. SW 8 . analog. library Package design High-pin count.3 ‘Cs’ Design capability requirements Verification Digital design High speed. chip. Low power Custom design RF. high complexity.

Cadence Design Systems Holistic solutions for product development Services PCB design D es ha ign in n ig es in D ha C Package design Custom design Verification 9 gn si in e D ha C Digital design C D e C s ha ign in .

and networking Automotive 10 .Cadence Design Systems WE’RE INSIDE THE THINGS YOU CAN’T DO WITHOUT Wireless handsets Gaming and home entertainment Computing. storage.

Cadence Support for Power Architecture .

ibm. Voltage Storm. Diagnostics. Assura. Ultrasim.nsf/techdocs/9B8CB5AE8A767C0D87257012006F61B2 12 . VirtuosoXL Layout and Schematic Editor Palladium Purpose RTL Synthesis and Low Power Simulation. Logic Verification Equivalence/Model/Constraint Checking SoC Physical Implementation DFT Test Gen. Yield Automated Custom / Analog Design and Layout Implementation Emulation/Acceleration Cadence design flow and SOC infrastructure for Power Architecture found at: http://www-306. VAVO. Tool Encounter Front End Designer Incisive Encounter Conformal SOC Encounter Encounter Test Architect SW Tools Enabled to Support Embedded Power Architecture » Silicon proven design flow for Power Architecture based designs using the latest Cadence technology tuned for performance optimization and smallest silicon area. Verilog A.

in execution or near start: – 440 core implemented in 2 different Asian Foundries at 130nm – 440 core implemented in an Asian Foundry 65nm process – 440 core implementation in progress in an Asian Foundry at 45nm – SOC referencing e500 core (FSL) implementation at 90nm – 440. 440FPU and 405 core model definition for Palladium 13 .ORG » Firm Core and Hard Core Process Ports • Core Hardening and SOC Activities include: – Porting the 440/460 cores into non-IBM process nodes – Support of Validation of the hardened 440/460 cores in silicon – Implementing 440/460 and e500 (FSL) based SOC designs – Emulation model development and verification services support • Customer engagements either completed.Cadence Support for Power Architecture » Cadence is Founding Member of POWER.

Cadence Support for Power Architecture » System Design and Verification • Palladium Emulation model development and verification services support – 440. 440FPU and 405 core models for Palladium • Verification IP for Accelerating Chip Level Design and Verification » System on Chip (SoC) Integration • Implemented 440 and e500 (Freescale) based Power Architecture SOC designs • Optimized for Power Management with Cadence SoC Encounter and Cadence Front End Designer 14 .

» Emulation support services for integrated Power Architecture models into SOC 15 .System Design and Verification : Emulation with Palladium » RTL equivalent Palladium models of the Power Architecture 440G5V3. 440G5V4 and 405 cores. » Model are non-RTL. » Models derived from Power Architecture RTL with memory elements such as the Icache and Dcache mapped to Palladium memory modeling elements. compiled Palladium Library elements with the top level I/O compatible with Power Architecture SMART model.

with associated memory models for SRAM and Flash.System Design and Verification – Verification IP » Cadence has an Ecosystem License to access IBM’s Enablement for Power Architecture 405 and 440 Series Cores • Examples: SystemC models. Peripheral models (Arbiters. etc) » Cadence is able to use IBM’s Verification IP and Enablement in Customer Engagements under specific Terms and Conditions » Examples for Interactions: • Cadence has created SystemC model for PCI interface into verification environment for Power Architecture SOC test chip. RTL models: CoreConnect Bus Models. • Based on a Verilog platform and transactors. 16 .

Accelerated Verification of Power Architecture Embedded SoCs » How do you? • Accelerate Power Architecture based SoC integration and verification • Ease the development and verification of IP cores into new applications • Support Virtual Prototyping benefits for Power Architecture core based designs 17 .

L3 Verification Result with Palladium Palladium emulator » Cadence Reference Design • 1.2 Mhz • Entire Design in 2 Domains » L3 Design • >500Khz • Critical Path in DSP Logic » Power Architecture440G5V3 • Optimized for Palladium • 700K gates per instance » Multi-User mode running multiple testbenches » High reliability • Emulator uptime in months 18 .

X Bridge Controller Logic DDR Controller L2 cache Controller Ethernet Custom MAC Logic AMBA AHB AHB to APB Bridge AMBA APB APIC UART GPIO RTC PWM WDT TTC 19 .Power Architecture SoC in Cadence Incisive emulation verification environment Code Symphony Debugger Cadence Power Architecture SoC platform UIC DMA Power Architecture440 Controller CoreConnect Palladium Runtime control and debug environment Reference Design PLB PLB/OPB Bridge PLB To AMBA Bridge OPB Core OPB OPB Core Custom SRAM PCI .

Why accelerated verification of L3 Power Architecture SoC matters? » Finds bugs using Palladium in an accelerated verification environment that cannot be found with other means » Allows for application software to be developed and verified before silicon • High Software Quality with Initial Silicon » Verifies architectural assumptions before tapeout » Ensures high level of functionality with first silicon • Software Quality was ahead of development curve • Adequately validated all Signal Processing functionality –Basic Functionality = Seconds of Realtime –Enabled Completion of Functional Verification Plan 20 .

– The physical design completed and verified via 3D parasitic extraction and physical DRC and LVS verification • Verification Silicon Implementation – Worked with custom to implement Power Architecture macro in a FPGA fabric which was fabricated by Customer. Cadence performed this port in a 4 step process: • Custom Block Port – Redesigned all custom blocks for Asian process including CAMRAMs. • Device Test. Many customer corner and margin requirements limiting performance to maximize yield for high volume production. LOD. and high subthreshold device leakage. Size: 4. – Design has met all performance targets and is now going into production. and register files to accommodate local on chip variation.77 mm2 Typical/Worst Performance: 700/400 MHz 21 . • Power Architecture 440 Core Hardening – Synthesized the IBM RTL code to a Asian process compatible netlist. Characterization and Production – FPGA fabric was packaged and Cadence and Customer worked together to validate the Power Architecture in Silicon was first pass functional. – Included industry standard scan and BIST methodologies. SRAMs. N-well proximity effects.Power Architecture 440 65nm “Firm” Implementation » Power Architecture 440 core hardened to Asian Foundry 65nm LV process including custom block redesign to deal with new technology device effects. then floor-planned which includes implementing clock insertion. BIST and scan insertion.

29 bit comparator sum addressed CAMRAM’s » 64 entry.40% faster) vs. 88 bit CAMRAM » 4:2 Standard Cell/Custom 1 bit Compressor » Custom memories as required » Custom muxes and clock circuits 22 . a fully synthesized solution: » 256 x 303 CAMRAM » 256 x 266 CAMRAM » 32 x 32 GPR » 8 entry.Power Architecture 440/460 Custom Blocks » Power Architecture critical paths were identified to determine the circuit blocks that must be completely custom designed to achieve optimum processor performance » As a result of this analysis the following Power Architecture blocks are typically implemented by Cadence as customized circuits and provide a differentiated offering in terms of size (40% smaller) and performance (20%.

Verification and Implementation .Solutions for Design.

Comprehensive verification Solutions for the enterprise Incisive® functional verification platform Incisive removes risks and improves quality and predictability Hardware Software – – – Streamlined. comprehensive verification from block chip system A Plan to closure methodology to manage cross team verification activities Comprehensive verification IP (VIP) for standards compliance Process automation and management Automated test bench With Plan-to-closure Methodology Acceleration Emulation 24 .

Advanced low power design solutions Systems perspective. and area objectives • Automation to complete designs within schedule with complex power domain structures • Verification to reduce silicon failures when using advanced power reduction techniques 25 Leakage Dynamic Power domain infrastructure Low power verification and test Advanced Leakage Optimization Power Integrity . integrated approach Incisive® functional verification platform Encounter® digital IC design platform » Encounter and Incisive deliver highest power optimization • Design and implementation to support multiple advanced power reduction techniques concurrently with timing. yield.

high performance chips Cadence® Logic Design Team Solution Encounter® digital IC design platform Encounter and Incisive deliver • Integrated design and verification • Superior chip planning and prototyping • High capacity QoS closure • Complexity management • Integrated yield optimization in the flow d Spee Power Yield Design with. physical Full chip planning and prototyping Mfg-aware implementation Sign-off STA 26 . test..High-end digital design solutions Big. verification. power. complex.

Connecting semi companies to system customers Incisive® Palladium® acceleration/emulation Incisive enables companies to perform • Pre-silicon software development • Comprehensive verification with ‘live’ data Pe ce rman rfo HW/SW Capac ity Simulation acceleration and in-circuit emulation High throughput for HW/SW co-verification High debug productivity Correlation Data 27 .

count. high digital. analog. High speed. chip. complexity.RF.Collaborating with the Ecosystem Packaging EMS Independent SW Providers Incisive® Encounter® Virtuoso® Cadence SiP® Allegro® System Enterprise Digital Custom Package PCB Verification design design design design Block. low power. memory. speed SW Low power library low cost Design chain enabled Cadence® Services Semiconductor IP Equipment Manufacturing Foundries 28 . highsystem. High-pin Miniature.

org .Getting Started with Advanced Low-Power: A Practical Guide to Low-Power Design » Captures collective efforts of the 28 Power Forward Initiative members » Details low-power design & user experiences • • • • • • • Introduction to Low Power Verification of low-power Intent Front-end Design Low-Power Implementation Low-Power Test CPF User Experiences CPF Terminology Glossary » User experience chapters by ARC.powerforward. demonstrate expertise 29 » Free download from www. ARM. NXP and TSMC » PFI Members use guide to educate their customers. Freescale. NEC. Fujitsu.

org » Cadence has broad solutions for enabling Power Architecture based designs • through tools and design services • for design and verification of SoC based on Power Architecture • for enabling HW/SW co-design of Power Architecture based systems 30 .Summary » Cadence is founder of power.

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