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Slack is defined as the difference between the reqd_arrival time of a signal & it's actual arrival time.

It is also defined as the difference between the clock period and the total path delay from one flop to other flop which includes the clock to q delay of source flop, total combinational delay between flops and set up time of the destination flop. VHDL Sequential Statements: These statements are for use in Processes, Procedures and Functions. Sequential Statements: wait statement, assertion statement, report statement, signal assignment, statement, variable assignment statement, procedure call statement, if statement, case statement, loop statement, next statement, exit statement, return statement, null statement VHDL Concurrent Statements: These statements are for use in Architectures. Concurrent Statements, block statement, process statement, concurrent procedure call statement, concurrent assertion statement, concurrent signal assignment statement, conditional signal assignment statement, selected signal assignment statement, component instantiation statement, generate statement Difference between blocking and non-blocking? The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking. The two are distinguished by the = and <= assignment operators. The blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement. The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit. FPGA: a) SRAM based technology. b)Segmented connection between elements. c) Usually used for complex logic circuits. d) Must be reprogrammed once the power is off. e) Costly CPLD: a) Flash or EPROM based technology. b) Continuous connection between elements. c) Usually used for simpler or moderately complex logic circuits. d) Need not be reprogrammed once the power is off. e) Cheaper The main distinction between FPGA and CPLD device architectures is that FPGAs are internally based on Look-up tables (LUTs) while CPLDs form the logic functions with sea-of-gates (e.g. sum of products). The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. CLB are configurable logic blocks and can be configured to combo,ram or rom depending on coding style CLB consist of slices and each slice consist of -input LUT (look up table) F-LUT and G-LUT.Each Virtex-6 FPGA slice contains four LUTs and eight
flip-flops, only some slices can use their LUTs as distributed RAM or SRLs.

What is the difference between a LATCH and a FLIP-FLOP? Latch is a level sensitive device while flip-flop is an edge sensitive device. Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches. Latches take fewer gates (also less power) to implement than flip-flops. Latches are faster than flip-flops. Latch does not have clock signal whereas flip flop does. Flip flop has two values while latch has only one value.
What is the difference between Behavior modeling and RTL MODELING? Behavior modeling is easier to write than RTL modeling (assuming structural) Fewer lines of codes in Behavior than RTL. What is the benefit of using Behavior modeling style over RTL modeling? Not easily synthesizable, RTL is easily synthesizable