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Performance analysis of a Digital Phase-Locked Loop with a Hyperbolic Nonlinearity

Sithamparanathan Kandeepan Wireless Signal Processing Group National ICT Australia RSISE, Australian National University
Sam Reisenfeld CRC for Satellite Systems Faculty of Engineering University of Technology Sydney


Abstract - the treatment of phase locked loops (PLL) has been heavily looked into over the past several decades on its performances and analysis, and is a very old topic. However the usage of it has never been reduced with the rapid evolvement of various open loop and closed loop systems. In this paper we analyse the performance of an arctan based digital phase locked loop (DPLL) with a hyperbolic nonlinearity for single-tone carrier tracking. We purposely introduce the nonlinearity for improved performance of the closed loop system. We look at the acquisition performance of the DPLL by considering the phase plane portrait and the lockin range of the loop. The steady state (SS) performance of the loop is analysed by considering the open loop SS statistical distribution of the phase noise. Index Terms- Digital phase-locked loop (DPLL), PLL, arctan, hyperbolic, phase plane (PP) portrait, steady state (SS)

flexibility to incorporate basically any type of signal processing functionalities within the loop due to its reprogrammable nature. In our research we implement a software based DPLL with an arctan based phase detector (PD) using digital signal processors. The equivalent model of this during the analog era was the tan-locked loop [9,10]. In our loop model we also incorporate a nonlinear signal processing element, which is a hypobilc function, in addition to the arctan PD to improve the performance. We introduce to the loop model of the DPLL initially and then analyse the performance of the loop during the acquisition mode and the SS mode.
II. LooP MODEL The loop model considered is given in Figure-1. It consists of an error detector or a PD, a loop filter and a numerically controlled oscillator (NCO). The NCO is equivalent to the voltage controlled oscillator (VCO) of its analog counterpart.
I/P signal

phase locked loops are widely used in many applications such as communications, controls, radar, sonar and electrical engineering systems. In communications, radar and sonar, carrier tracking is a common problem and phase locked loops are the simplest solution. The advantage of it is that it does not require a tunable band pass filter to track high frequency carrier signals. The treatment of the analysis of a PLL began in the mid 20th century. Viterbi [4] and Gardner [1] looked into the performance analysis of an analog phase locked loop for carrier tracking. The acquisition performance is well treated by Viterbi in [4], where as the SS performance is well treated by Gardner in [1]. During the evolution of the digital era came the concept of digital phase locked loops. A similar performance analysis of the DPLL to the analog PLL was performed by Lindsey and Chie [2] and subsequently by many others [58]. Currently, with the advancement in digital signal processing techniques and advanced digital signal processing hardware, software implemented PLL are common in use. Similar to the analog and the digital PLL, software implemented PLL are analysed on its acquisition and SS performances and appears to be the same. The software implemented PLL are basically carrier-locking loops running on digital signal processors where the processing is done on sampled signals. They have the
0-7803-9282-5/05/$20.00 2005 IEEE


Figure- 1, Digital phase locked loop model

Depending on the type of filter, whether it's a perfect integrator or an imperfect integrator, the loop is said to be a perfect loop or an imperfect loop. Further, if the loop filter is a single pole filter then the loop is said to be a 2nd order loop, in general if the loop filter has got N poles then the loop is said to be an (N+1)t order loop. The input to the DPLL is a complex signal, which has the Inphase and the Quadrature inputs. The PD is a four-quadrant arctan PD that maps the input arguments to its corresponding four quadrant phase plane, which is followed by a hyperbolic function. The block diagram of the PD model is shown in Figure-2. The input signal r, which is a complex single-sinusoid signal corrupted with AWGN is given by,

r[n]=Aexp{2zjfTfn- jf}- q

ICICS 2005


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NCO is given by,

where, A, f and are all deterministic constants, Ts is the sampling period of the discrete signal, and ri is the complex Gaussian noise process given by, (2) q=n c - jn s where, nc and n, are two independent zero mean Gaussian random processes of 2 variance with a double sided power spectral density of No W/Hz. The output signal x from the


Let us consider the input signal r without the additive noise component. The input-output characteristics curve of the PD model for the noiseless case is shown in Figure-3. The characteristic curve shows the nonlinear nature of the PD. For the liner loop (equation (6)), the expected characteristic curve is a straight line with a unity gradient passing through the origin.

x[n] = exp{-j 6[n] } (3) The multiplier in Figure-2 is a complex multiplier. The output of the multiplier is fed into the arctan function, and the resulting phase is passed through a hyperbolic function
In (4), is given by,


and n.
/. o. /.








(pe= g(-) = sinh(F-)

-6 -8

= arctan{u,v} (5) where, u and v are the real and imaginary components of the output of the complex multiplier.



Figure-3, Ideal characteristic curves of the nonlinear hyperbolic PD model




Figure-2, Nonlinear phase detector model

The mathematical model of the loop without the nonlinear hyperbolic g(.) function is given by, D (z)V (z) (6) H (z)

D (z)V (z)

Analysis show, from sections to follow, that the characteristic curve of the hyperbolic PD model changes when the input noise is considered. We see that the actual characteristics depend upon the input signal to noise ratio (SNR) for the hyperbolic PD model. A. Steady-State Phase Error The SS phase error is the value of the phase error signal at the output of the PD during SS. For a linear system the SS phase error may be found by using the final value theorem. The final value theorem for the discrete system is given by,
ls =lim

where, D(z) and V(z) are the discrete transfer functions of the loop filter and the NCO respectively, given by, az D (z ) =(7)

where, O0(z) is the Z-transform of the input phase, given by,

f9(7= ? i Ui k ) /-, ILJ I



(1- a)]


V (z)





In equations (7) and (8), a is the filter co-efficient and k is the NCO parameter that controls the loop. We note here that the loop filter is an imperfect single pole filter, and hence the corresponding loop given by (6) is a second order imperfect loop. We also define the closed loop bandwidth for the discrete linear system defined in (6) as [2],


The SS phase error of the linear systems in (6) is found using (11), and is given by, (12) (I,ss= 27ff,/k Then, the SS phase error of the hyperbolic nonlinear loop is found using (12) and (4), which is given by, (h-ss

ln{(2iCfTs /k) + I((2irfTs /k) 2 + 1)}


H(z)H(1 lz*)z dz (9) 2 c where, B, is the input signal bandwidth to the DPLL. It should be noted here that the above linear system analysis is no longer valid when the nonlinear function g(.) is considered within the loop, however the linear system performance is used as a reference to compare the performance of the nonlinear loop. 2BL



The differences between the SS phase errors for the linear case and the nonlinear case are depicted in Figure-4. From the figure, we see that due to the nonlinear characteristics of the hyperbolic PD, the SS phase error is reduced depending on the value of k for a given f and Ts.

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65 60 55

50 _


40 30


50 45


10 _


35 30


-40 _














Time sample

Phase Error - degree

Figure-4, SS-phase error, imperfect 2nd order loop, k= 1, f= 560Hz, f= 5kHz

Figure-5, PP portrait of the linear loop described in equation (6), BL 22.5Hz

1500 1000

This in particular has an advantage in terms of the lock-in range ofthe loop, which we discuss in the next section. B. Lock-in Range The lock-in range of the loop is the amount of frequency drift, offset from the center frequency (in our case zero frequency), that the loop can pull-in. For a given loop, the pull-in process, which is the same as the acquisition process, depends on the frequency offset to be pulled-in and the loop transfer function. For the case of an imperfect loop, the pullin process is successful up to a SS phase error of 180 degrees, and for higher frequency offsets the pull-in is unsuccessful as the loop starts to cycle-slip and keeps on slipping forever. On the other hand, perfect loops eventually lock in even after cycle-slips, and theoretically perfect loops are said to have an infinite lock-in range. From (13), we can determine the pull-in range of the hyperbolic loop model, which is given by, (e -e )fs k fh (14) L 4n whereas, for the linear case the lock-in range is given by, fL= fsk/2. Therefore, we see that the hyperbolic loop model gives a pull-in range that is 3.6761 times greater than the linear model. In the following section we see how the frequency is pulled-in by looking at the phase plane (PP) trajectories ofthe loop. C. Phase Plane Portrait The dynamical nature of the system, during the acquisition process, is best described by the PP analysis. The PP portrait is the plot of trajectories of the difference equation describing the loop for various initial conditions. The x-axis of the plot represents the phase difference and the y-axis represents the frequency difference between the received and the locally generated signals. Firgue-5 and Figure-6 show the PP portraits of the linear loop and the hyperbolic loop respectively. From the figures we see how the hyperbolic loop achieves a wider lock-in range compared to the linear loop. The hyperbolic loop compresses the phase error signal, which allows it to acquire a wider range of


-500 -1000 -1 500











Phase error - degrees

Figure-6, PP portrait of the hyperbolic nonlinear loop

IV. PERFORMANCE ANALYSIS WITH NOISE The noiseless analysis performed so far was mainly for the acquisition of the DPLL. Though acquisition analysis of the loop for the noisy conditions is not treated, it is generally known that a PLL or a DPLL pulls-in the signal frequency almost equivalently to the noiseless case for intermediate and high levels of SNR. However, the SS tracking performance of the loop is no longer the same even at high SNR. Due to the input noise, the loop will experience jitter in its SS operation, and such jitter is known as the phase noise. We now consider the loop's SS performance when the input signal is corrupted by AWGN as given in (1).

A. Statistical Distribution of the SS Open Loop Phase Noise The SS open loop phase noise distribution is the statistical distribution of the noise within the loop during SS assuming the loop is open. In the following analysis, two main assumptions are made, which are valid for intermediate and high levels of SNR. The first assumption is that the loop has attained lock, and the second assumption is that the loop SNR is high. The loop SNR is defined by, SNRL= P, / NOBL (15) where, P, is the input signal power. The loop SNR can be increased either by increasing the input SNR or by narrowing BL. When the above two assumptions are satisfied, the loop is successfully opened for analysis,

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assuming there is negligible correlation in the loop noise due to its feedback path.

Hyp-offset = O \ linear-offset = Odeg

snr = 10dB

linear-offset = 40deg

Hyp-offset =46deg

symmetrical nature for non-zero SS phase offsets and the skew-index of the curve increases with increasing phase error offsets at SS. B. Noisy Characteristics In section III, the characteristics curve of the hyperbolic PD was given for the case without noise. Here, we study the nature ofthe same, when there is additive noise at the input.


Hyp-offset = 115deg linear-offset = 80deg

{ { \ Hyp-offset 202deg




snr =

snr =0OdB -5dB


linear offset

1 10deg


1OdB Inr --20dB

rA -100












(Pe - degrees Figure-7, Open Loop SS Phase Error distribution for the hyperbolic PD model





When the input noise is considered, the loop given in equation (6) is no longer linear. This is due to the nonlinear operation of the arctan function in the PD. For the hyperbolic PD we can determine the open loop SS phase error distribution using transformation of random variables, which is given by, (16) fe ((qe)= cosh( Ve ) Z0 (a) where, a =sinh-'(Pe) and Z,(u) is given by equation (17). The function in (17) is the result of the existence of the arctan function within the PD [11,12]. The probability density function of the phase error process for the hyperbolic PD model is shown in Figure-7 for different SS phase offsets. The phase noise distribution shows a nonF


-150 -100







C - radians Figure-8, Noisy characteristics of the hyperbolic PD

The characteristics curve of the hyperbolic PD is the expected value of its output for different inputs at a particular SNR. Trajectories of such curves are shown in Figue-8 for different input SNR. We see that the PD performance degrades with decreasing SNR, which is not the result that we rather prefer.

exp(-p / 2)


2)LT+ F2






foriT2 < a.<z


r for-zr 2<a.CT 2
F)i2 zrT2 F




2 F




C 2

[tan(fz + a)y1 +

i+a 2

072[I + tan2((z + a)]


[tan(-z + a),u + P2



-x2ff X-

fexp( -u /2).du with





oh s)

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C. Phase Detector Gain The PD gain is unity when there is no noise at the input. This can be proved by considering the Taylor series expansion of the hyperbolic function in (4). However, when there is noise at the input, the PD gain is no longer unity rather depends on the input SNR. The PD gain is given by the first derivative of the characteristics curve at the origin. Since the characteristics curve changes with the input SNR the PD gain also changes. Mathematically, PD gain is expressed as,

Figure-i 0 depicts the PJ experienced by the hyperbolic loop model in log-scale. The performance of the hyperbolic loop is a bit poorer than the arctan model in terms ofthe SS phase noise, and gets worse at very low SNR levels. It also reaches the threshold point, where the jitter increases rapidly, well before the arctan reaches its threshold [11,12]. Therefore, the overall SS jitter performance is not appreciable for the hyperbolic model when compared to the arctan model.

=V() dQ pd v d(O)



where, v(.) is the characteristic function ofthe PD.


0.4 8

A hyperbolic PD based DPLL was treated in this paper. The hyperbolic loop was anlysed in terms of both acquisition and tracking performances for a single-tone complex input signal. We compared the performance of the nonlinear hyperbolic loop with the linear loop for the noiseless case and with the arctan based loop for the noisy case. The hyperbolic loop shows improved acquisition performance, where the lock-in range of the loop is widened, but on the other hand the tracking performance in terms of SS phase jitter shows poorer performance than the arctan model. The PD was also analysed in terms of its gain, characteristic function, and the open loop SS phase noise distribution.




Figure-9, PD gain variation with input signal to noise ratio

SNRi.- dB




The PD gain as a variation of the input SNR is shown in Figure-9. The PD gain is not unity for SNR levels below 12dB. It is important for the designer to note the variation of the PD gain at different SNR, which changes the loop characteristics by changing the overall loop gain. This might even drive the loop out of a stable position in some cases. D. Steady State Phase Jitter The SS phase jitter (PJ) is caused due to the additive noise at the input. It is important for us to know how much jitter is expected for a given loop design at a particular SNR level.

The authors would like to thank the Research School of Information Science and Engineering (RSISE) at the Australian National University (ANU). Dr. Kandeeapn is an adjunct academic with the RSISE at ANU. National ICT Australia is funded through the Australian Government's backing Australia's ability initiative, in part through the Australian Research Council.
[1] F.M.Gardner, "Phase Lock Techniques", NY, Willey, 1979. [2] W.C.Lindsey and C.M.Chie, "A Survey of DPLL ", Proceedings of the IEEE, pp296-317 April 1981. [3] H. Meyer, G Ascheid, "Synchronisation in Digital Communications", vol-1, John Willey & Sons, 1990 [4] A.J. Viterbi, "Principles of Coherent Comms" McGraw-Hill, 1966 [5] M.P.Fitz and W.C.Lindsey, "Decision-Directed Burst-Mode Carrier Synchronisation Techniques," IEEE Trans on Comms, vol. 40 No.10, pp. 1644-1653, Oct 1992 [6] M. P. Fitz and R. J.-M. Cramer, "A Performance Analysis of a Digital PLL Based MPSK Demodulator," IEEE Trans on Comms, vol. 43 No.2/3/4, pp. 1192-1201, Feb/Mar/Apr 1995. [7] J.V.Lorenzo-Ginori and J. A. Naranjo-Bouzas, "All-Digital PLL with Extended Tracking Capabilities," in Electronics Letters, vol. 33 No.18, Aug 1997, pp. 1519-1521. [8] R.C.Tausworthe,"A Second/Third-Order Hybrid Phase Locked receiver for Tracking Doppler Rates",JPL Tech Rep 32-1526,vol.1,pp 42-45 [9] J.C.Lee and C.K.Un, "Performance Analysis of Digital Tanlock Loop," IEEE Trans on Comms, vol. 30, pp. 2398-2411, 1982. [10] C.A.Pomalaza-Raez, "Noise Analysis of a Digital Tanlock Loop," IEEE Trans on Aerospace and Elect Sys, vol. 24, pp. 713-718, 1988. [11] S.Kandeepan, S.Reisenfeld, "Frequency Tracking and Acquisition with a Four-Quadrant arctan-Based Digital Phase-Locked Loop", ICICSPCM 2003 proceedings of,Vol.l,pp 401-405,15-18 Dec 2003, Singapore. [12] S.Kandeepan, "Synchronisation Techniques for Digital Receivers", PhD Thesis, University of Technology Sydney, 2003


P/Nn Figure-1O, Steady state phase jitter ofthe hyperbolic loop








For the traditional analog and digital PLLs, with multiplier based PD, the PJ is inversely proportional to the loop SNR. Similar theory applies here as well. We can reduce the PJ either by increasing the input SNR or by narrowing BL.

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