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Rick Walker Hewlett-Packard Company Palo Alto, California
Serial data transmission sends binary bits of track drifting txas a seriesprop delayor electrical identify bits information clock and of optical variation + pulses:
The transmission channel (coax, radio, ﬁber) generally distorts the signal in various ways:
From this signal we must recover both clock and data 5
Use a precise clock to chop the received data into periods Overlay each of the periods onto one plot symbol cell Y
Y amplitude distribution at Y-Y 7
Eye diagram construction random data TX link synth trigger RX scope 6 .
Deﬁnition of Jitter unit interval -3T -2T -T 0 T 2T 3T 4T Impulses spaced equally in time (jitter free signal) time -3T -2T -T 0 T 2T 3T 4T Impulses spaced irregularly in time (jittered signal) Errors treated as discrete samples of continuous time jitter After Trischitta and Varma: “Jitter in Digital Transmission Systems” 20 .
Analytic Treatment of Jitter Perfect Clock: x ( t ) = A cos ω c t Jittered Clock: x ( t ) = A cos [ ω c t + φ ( t ) ] φ ( t ) is then treated as a continuous time signal After Behzad Razavi: “Monolithic Phase-Locked Loops. ISSCC96 Tutorial” 29 .
Data Recovery with simple PLL Jittered Data Signal D Q Retimed Data Phase Detector PLL Low-pass Loop Filter Voltage Controlled Oscillator 28 .
for good introduction to PLL theory 30 . John Wiley and Sons. Gardner.Model of Loop Phase Detector Loop Filter VCO Kφ 1 β + -----------------( 1 + sτ ) Kv 1 -s Warning: Extra Integration in loop makes for tricky design! See Floyd M. “Phaselock Techniques”.
Loop Frequency Response a (input data jitter) 80dB 40dB 0dB -40dB -80dB 1k 10k 100k 1M 10M 100M 1G 10G Kφ 1 β + -----------------( 1 + sτ ) Kv -----s c b (vco phase noise) open loop gain c/a c/b 31 .
but the techniques are useful and relevant for datacom applications also.Jitter Measurements • SONET has most complete set of jitter measurement standards. • • • Jitter Tolerance Jitter Transfer Jitter Generation 46 .
the sinewave modulation amplitude is increased until the BER penalty is equal to that caused by 1dB optical attentuation 47 After Trischitta and Varma: “Jitter in Digital Transmission Systems” .Jitter Tolerance Test Setup laser transmitter data generator optical attenuator optical receiver xamp + limiter decision circuit retiming circuit bit error rate tester FM modulated clock sine wave generator At each frequency.
Sept.5 25 100 400 ft [kHz] 65 250 1000 4000 from SONET SPEC: TA-NWT-000253 Issue 6. ﬁg 5-13 48 . 1990.SONET Jitter Tolerance Mask 15 UI 1.5 UI 0.488 Gb 10 Gb acceptable range f1 f0 [Hz] 10 10 10 ? f2 f1 [Hz] 30 30 600 ? f3 f2 [Hz] 300 300 6000 ? ft f3 [kHz] 6.15 UI f0 Data Rate 155 Mb 622 Mb 2.
T.U.Jitter Transfer Measurement data generator decision circuit clock retiming circuit D. ϕ Phase detector Signal Generator Phase modulator [TrV89] [RaO91] IN OUT network analyzer 49 .
Jitter Transfer Analysis sideband clock amplitude ∆Θ Assuming small angles (i. plotted as a function of jitter frequency.e. ?? .: only one dominant sideband on recovered clock): ulta nt V sideband Jitter pp ( rads ) = 2∆Θ ≅ 2 atan ------------------------.U.T input. V clock res Jitter transfer is deﬁned as the jitter at the clock output divided by the jitter at the D.
Jitter Transfer Speciﬁcation P[dB] acceptable range slope = -20 dB/decade fc Data Rate 155 Mb 622 Mb 2.488 Gb fc[kHz] 130 500 2000 P[dB] 0.1 This speciﬁcation is intended to control jitter peaking in long repeater chains 50 .1 0.1 0.
Some Signal Degradation Mechanisms • • • • • • • Multiplex Jitter AC Coupling Optical Pulse Dispersion Skin Loss Random Noise E+O Crosstalk Intersymbol Interference 8 .
bit stufﬁng events high speed data sub-rate data phase error [in UI] time Multiplex jitter is not a problem on the high rate channel itself - it only occurs on non-synchronous, lower speed tributaries that have been sent over the high-speed channel (e.g.: DS3 over SONET OC-48). 9
Voltage and Time aberrations caused by AC-coupling
V Vt t=0 t=t1
t1 V – Vt AC coupled pulses droop as P ≡ --------------- × 100 ≈ ------- × 100 . V RC
Jitter is introduced by ﬁnite slope of pulse rise/fall time:
tr t1 ∆t = --------------( 2RC )
retiming circuit S.U.T.
Jitter Generation (cont.488 Gb/s SONET) speciﬁes 12 kHz hipass ﬁlter.01 UI RMS integrated jitter. V clock sideband ∆Θ 2) Multiply Jitter components by Filter Mask 3) RMS sum total noise voltages over band 4) Convert RMS noise voltage to RMS jitter OC-48 (2. and maximum 0. 52 res ulta nt .) 1) Measure Jitter Sidebands around Clock clock amplitude V sideband Jitter pp ( rads ) = 2∆Θ ≅ 2 atan ------------------------.
Decision Circuit • • • • Quantizes amplitude at precise sample instant Typically uses positive feedback to resolve small input signals A master/slave D-ﬂip-ﬂop carefully optimized for input sensitivity and clock phase margin is a common choice Latches input data on rising edge of clock signal simpliﬁed schematic symbol: D Q clock 39 .
e.: 8B10B of FibreChannel 16 After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”.Nlow in past transmitted signal +5 0 -5 encoded data signal signal disparity • • In an unbalanced code the disparity can grow without limit. e.g.g. (see bibliography for full citation) .Code Disparity Disparity is deﬁned as Nhigh . the disparity is limited to a ﬁnite worst case value.: 4B5B code of FDDI In a balanced code.
: SAW ﬁlter bandpass ﬁlter LC tank Recovered Clock Output NRZ Data Input non-linear element delay (this last circuit can be thought of as an NRZ-RZ converter) 25 .g.Filter Method Examples d ⁄ dt X 2 bandpass ﬁlter e.
Spectrum of NRZ data variations due to DC balance strategy power in dB sin ( 2πfT ) -----------------------2π fT missing clock frequency f = 0 1 ⁄ 2T 1⁄T 3 ⁄ 2T 2⁄T 22 .
NRZ and RZ signalling NRZ = “non return to zero” data + + + + + neither clock nor data frequency in spectrum data frequency clock frequency RZ = “return to zero” data + + + + + clock. 21 . but no data frequency in spectrum T NRZ signalling is almost universally used.
± ∆ k ± Θ k 2 k 23 .A detailed look at the spectrum of differentiated NRZ missing clock frequency power in dB ±∆k f = 0 fc ⁄ 2 fc fc ∑ A k sin 2π ----.
g.± ∆ ± Θ ∑ A k sin 2k k k • • Mix data signal with itself (e.cos ( α – β ) – cos ( α + β ) 2 All the symmetric sidebands mix pairwise to coherently create a carrier frequency component: direct implementation of this principle is “Filter Method” 24 .: square law): 1 sin α sin β = -.Reconstructing the Clock • Start with symmetric sideband pairs about fc/2: fc 2π ----.
Example Bipolar Decision Circuit master latch slave latch gnd data in data out clock in Vbias -5V • many clever optimizations are possible 40 .
Summary of Filter Method Jittered NRZ Data Signal D Q bandpass ﬁlter/limiter Con: Retimed Data d ⁄ dt X 2 Pro: Very simple to implement Temperature and frequency variation of ﬁlter group delay makes sampling Can be built with time difﬁcult to control microwave “tinkertoys” using coax to very high frequencies Narrow pulses imply high fT Hi-Q ﬁlter difﬁcult to integrate 26 .
Example MOS Decision Circuit master latch data in clock slave latch clock decision circuits can be implemented in NMOS technology up to Gb/s speeds 41 .
the decision threshold X-X must centered in the signal swing. Two common ways of automatically generating threshold voltage are: • Peak detection of signal extremes.Decision Threshold Generation • To minimize bit-error rate. limited run-length required positive peak detector negative peak detector Decision Threshold Signal • Decision threshold = signal average. balanced signal required Low-Pass Filter Decision Threshold 15 Signal After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”. (see bibliography for full citation) .
Quantized Feedback AC-Coupled Transmission Link TX H (ω) RX Feedback voltage models missing DC information 1 – H (ω) D Q clock Output Data (models ideal TX waveform) 11 .
the proper frequency look locked. or VCO at 2x. 90° 270° 180° Data at 1/2.Phasor Diagram • • • Graph of relative phase between clock and data Each complete rotation is 1 unit interval of phase slip Rotations/second = frequency error (in Hz) 0° Plot of data transitions versus VCO clock phase. = missing transitions = actual transitions 43 . This puts a limit on VCO tolerance to prevent false locking.
5] ideal data eye 270° 90° noisy data eye 180° clock a.b D data Q D Q Raw out-of lock indication 44 .Example Lock Detector 0° [FP15.
ISSCC96 Tutorial” .Aided Acquistion • Tricky task due to Nyquist sampling constraints caused by stuttering data transitions PD Input Data VCO FD loop ﬁlter 2 loop ﬁlter 1 • Still subject to false lock if VCO range is too wide 42 After Behzad Razavi: “Monolithic Phase-Locked Loops.
(see bibliography for full citation) .Phase Detectors • • Phase detectors generate a DC component proportional to deviation of the sampling point from center of bit-cell Phase detectors are: Continuous 90° – 180 ° – 90 ° 0° 180° Binary Quantized • Binary quantized phase detectors are also called “Bangbang” phase detectors 32 After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”.
(Figure from paper FP15. avoiding false locking problems.Training Loops retimed data bang-bang drive Input PDET charge pump Clock VCO Data select dlock dtrans ﬂock Reference Clock 2. This allows the VCO process-variation to be dynamically trimmed out. 1997 ISSCC) 45 .488GHz/256 FDET Clock/256 State Machine LOS 1/256 divider An increasingly common technique is to provide a reference clock to the CDR circuit.5.
Coding for Desirable Properties • • • • • DC balance. low disparity Bounded run length High Coding Efﬁciency Spectral Properties (decrease HF and/or DC component) Many Variations are Possible! • • • • Manchester [San82] mB/nB [Gri69][Rou76][WiF83] [YKI84] [Pet88] Scrambling [CCI90] CIMT [WHY91] 17 .
SyncB(even). SyncA(odd).Simple 3B/4B code example 4B Output Data 3B Input Data Even Words 000 001 010 011 100 101 110 111 SyncA SyncB 0100 0010 0111 1000 Odd Words 0011 0101 0110 1001 1010 1100 1011 1101 1110 0001 Maximum Runlength is 6 Coding Efﬁciency is 4/3 Sending Sync Sequence: SyncA(even). SyncB(odd) allows the unambiguous alignment of 4-bit frame 18 .
(see bibliography for full citation) 1 2 j n 19 .Scrambling • Uses a feedback shift register to randomize data reversing process at receiver restores original data Scrambled Data Data Output Data Input XOR Shift Register n j 2 1 Clk PRBS Generators Caveat: Only guarantees balance and runlength under very speciﬁc data conditions! After Tom Hornak: “Interface Electronics for Fiber Optic Computer Links”.
Lam93. WKG94] After Todd Weigandt. Varactor) Narrow/Slow Good Poor Excellent Tunability Stability Wide/Fast Poor (needs acquisition aid) Multi-Phase Clocks Other • [Cor79. Ena87. CMOS 1-2 GHz Good Poor (L. “Timing Jitter Analysis for High-Frequency CMOS Ring Oscillators”. DeV91.VCO alternatives LC Oscillator Speed Phase Noise Integration Multivibrator Ring Oscillator Technology Dependent 1-10’s of GHz. Wal89. Kim. B. March 10. P. 1994 36 .Gray.
Grebene. 1972. pp 313-315 37 . and so is limited to moderate frequencies.Multivibrator VCO Capacitor is alternately charged and discharged by constant current Tuned by varying Itune in current source Diode clamps keep output voltage constant independent of frequency Relies on non-linear switching for oscillation behavior. “Analog Integrated Circuit Design”. Itune I tune Frequency = ---------------4CV be After Alan B. Van Nostrand Reinhold.
Example Ring Oscillator VCO Input 1 Output Tune Input 2 Input 1 Output [SyA86] [EnA87] [Wal89] Inpu Input 1 Tune Input 2 Output t2 38 .
Loop Filters • • may be analog (integrator) or digital (up-down counter) should have provision for holding value constant (tristating) under long run-length conditions [Den88] [Dev91] [LaW91] [WuW92] VOUT UP 0 0 DOWN 0 1 0 1 VOUT tristate ramp DOWN ramp UP tristate UP DOWN 1 1 35 .
001 k=.Skin Loss • Nearly all cables can be modeled by the Skin Loss Equation with various k factors: T ( f ) = 10 1.0 linear amplitude k=.00001 R3 R2 ( –k ) f .0 1k freq (log scale) 10G [YFW82] Three-element equivalent circuit of a conductor with skin loss 12 . Ring 3 Ring 2 Ring 1 L3 L2 R1 0.0001 k=.
1. usable signal See Paper: FP15.Skin Loss Equalization at Transmitter boost the ﬁrst pulse after every transition Error at sampling pt. 1997 ISSCC before after 14 .
4 3dB boost 1.5 0.0 0 1 equalized pure skin loss 1k freq (log) 10G 2x improvement in maximum usable bit-rate [WWS92] 13 .0 0.Skin Loss Equalization at Receiver transmission (linear scale) 1.
Agenda • • • • • • Overview of Serial Data Communications Signal Degradation Mechanisms Data Coding Techniques Clock Recovery Methods Components Used in Clock/Data Recovery Jitter Measurements 2 .
488Gb/s SONET CDR ~$500 (telecom application) 3 .25Gb/s Gigabit Ethernet Transceiver <$10 in volume (datacom application) 1cm 2. long-haul telecom applications Many different trade-offs are made to tailor each circuit to the target application area • 1. low cost datacom applications to very high precision.Diversity of CDR applications • Clock and Data Recovery (CDR) applications span the range from ultra-high-volume.
1.0/sqrt(e) Q also equals the center frequency of a ﬁlter divided by the full-width of the resonance measured at the half power points: Fcenter/ amplitude Q/2*PI cycles Fcenter High-Q ﬁlter can be emulated by PLL with low loop B. 27 .W.0 1.Q-Factor in resonant circuits Voltage envelope of ringing circuit falls to 1/sqrt(e) in Q radians.
Bit Error Rate (BER) Testing • • • • Pseudo-Random-Bit-Sequence (PRBS) is used to simulate random data for transmission across the link PRBS pattern 2N-1 Bits long contains all N-bit patterns Number of errored-bits divided by total bits = BER. Typical links are designed for BERs better than 10-12 PRBS data generator clock in TX link synth RX PRBS data receiver clock in 4 .
Drawbacks of Simple PLL 1) timing pulses 2) transfer function (linear vs BB). 3) quadratic. BB 4) critical problem is the stuttering data ?? .
... 7 = 3xor 5 (DOWN) D Q D Q DOWN Data See FA9.... 3 = 1 retimed......... 5 = 3 retimed...... 2= Clock (Early)......... 6 = 1 xor 3 (UP). 1997 ISSCC [Hog85][Shi87] 33 ............“Self-Correcting Phase Detector” UP Data Clock 1 = Data..6....... 4 = Clock..............
Binary Quantized Phase Detector • • NRZ data is sampled at each bit cell and near the transitions of each bit cell The sign of the transition sample is compared with the preceeding and following bit cell sample to deduce the phase error B A T B Output DQ DQ A 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 tristate vco fast ? vco slow vco slow ? vco fast tristate Data DQ Clock DQ T A T B [Ale75][WHY91] [LaW91][ReG73] 34 .
CDR Design Checklist 1) Eye Margin • • • • how much noise can be added to the input signal while maintaining target BER? (voltage margin) How far can clock phase alignment be varied while maintaining target BER? phase margin) how much does the static phase error vary versus frequency. noise and offset sufﬁcient? . temperature and process variation? Is input ampliﬁer gain.
etc) what is the jitter transfer function? (peaking and bandwidth)what is the jitter tracking tolerance versus frequency? .CDR Design Checklist (cont) 2) Jitter Characteristics • • what is the jitter generation? (VCO phase noise.
jitter. and stability change versus transition density? 4) Acquisition Time what is the initial.CDR Design Checklist (cont) 3) Pattern Dependency • • • • • • how do long runlengths affect system performance? is bandwidth sufﬁcient for individual isolated bit pulses? are there other problematic data patterns? (resonances) does PLL bandwidth. power-on lock time? what is the phase-lock aquisition time when input source is changed? .
CDR Design Checklist (cont) 5) How is precision achieved? are laser-trimming or highly precise IC processes required? 6) Input/output impedance • • • • • • are external capacitors. inductors needed? does the CDR need an external reference frequency? Is S11/S22 (input/output impedance) maintained across the frequency band? are reﬂection large enough to lead to eye closure and pattern dependency? is t >15 dB return loss maintained across the band? .
CDR Design Checklist (cont) 7) Power Supply • • • • • does the CDR create power supply noise? how sensitive is the CDR to supply noise? Is the VCO self-modulated through its own supply noise? (can be “deadly”) what is the total static power dissipation? what is the die temperature under worse case conditions? .
CDR Design Checklist (cont) 8) False lock susceptibility • • • • can false lock occur? are false lock conditions be detected and eliminated? can the VCO run faster than the phase/frequency detector can operate? (another “killer”) have all latchup/deadly embrace conditions been considered and eliminated? .
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