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2, MARCH 2007

Numerical Optimization of an Active Voltage

Controller for High-Power IGBT Converters
Angus T. Bryant, Member, IEEE, Yalan Wang, Student Member, IEEE, Stephen J. Finney, Tee Chong Lim, and
Patrick R. Palmer, Member, IEEE

Abstract—Feedback control of insulated gate bipolar transistors

(IGBTs) in the active region can be used to regulate the device
switching trajectory. This facilitates series connection of devices
without the use of external snubber networks. Control must be
achieved across the full active region of the IGBT and must balance
a number of conflicting system goals including diode recovery. To
date, the choice of control parameters has been a largely empir-
ical process. This paper uses accurate device models and formal-
ized optimization procedures to evaluate IGBT active voltage con-
trollers. A detailed optimization for the control of IGBT turn-on is Fig. 1. Reference waveform V used to control the collector voltage V .
presented in this paper.
Index Terms—Active voltage control (AVC), optimization, power
semiconductor device modeling, series insulated gate bipolar tran- profile is optimized to balance the conflicting objectives of re-
sistors (IGBTs). ducing the switching losses and minimizing the diode over-
voltage during reverse recovery.
CTIVE voltage control (AVC) has been shown to provide
A an effective solution to the series connection of insulated
gate bipolar transistors (IGBTs). A high speed feedback loop is
The active voltage controller (AVC) works by comparing the
collector voltage with a reference voltage
trol the IGBT during switching.
to con-
is generated in the AVC
used to force the collector-emitter voltage to follow a predefined gate drive, and has specific characteristics tailored for controlled
reference. By this means voltage sharing and control are switching of IGBTs [1]–[5]. The form of is shown in
achieved without the need for bulky snubber networks [1]–[3]. Fig. 1.
Investigations have shown that a complex series of trade-offs The turn-off phase is characterized by an initial precondi-
are implicit in the design of the IGBT controller [4]. Increased tioning step, , necessary to allow the device sufficient time
feedback loop gain and reduced gate resistance improve refer- to reach the active region where its voltage may be controlled
ence tracking but can result in oscillations and loss of voltage easily. The main ramp then follows, during which the voltage is
sharing. Diode power loss and over-voltage associated with controlled until it reaches the supply voltage and the free-
IGBT turn-on can be reduced by slowing the switching refer- wheel diode can turn on. is the maximum IGBT voltage
ence, at the cost of increased IGBT switching losses. This last desired, and must be greater than to ensure the device re-
issue is particularly important for bridge leg applications where mains fully off. also serves to clamp the voltage overshoot
complementary IGBT voltage sharing must be maintained [5]. and should accommodate ringing that may occur around .
Design of AVC by means of small signal models and con- The turn-on phase is characterized by an initial slowly-de-
trol theory is limited by the fact that most linearized IGBT pa- creasing ramp, which allows the diode to begin to recover, and
rameters strongly depend on the operating point. In this paper the voltage is supported by the stray inductance. A steeper ramp
these issues are addressed through the use of an optimization then follows to allow rapid completion of switching, to avoid ex-
approach that uses full nonlinear models and balances the con- cessive turn-on energy losses. Rapid turn-off of the diode may
flicting system requirements. In particular, the IGBT switching be accompanied by a high voltage overshoot.
The need to maintain low losses is important since the turn-on
Manuscript received November 16, 2005; revised June 13, 2006. This work of the IGBT may incur large losses. The requirement to reduce
was supported by the U.S. Office of Naval Research under Grant N00014-00-1- the diode peak recovery voltage is necessary to reduce the ten-
0131 and the Schiff Foundation, Cambridge University. Recommended for pub- dency for the freewheel diode to “snap” during turn-off; indeed
lication by Associate Editor Y. C. Liang.
A. T. Bryant is with the School of Engineering, University of Warwick, it has been found experimentally [5] that using a slow
Coventry CV4 7AL, U.K. (e-mail: ramp during IGBT turn-on reduces the diode peak recovery
Y. Wang and P. R. Palmer are with the Center for Advanced Photonics and voltage.
Electronics, Department of Engineering, University of Cambridge, Cambridge
CB3 0FA, U.K. (e-mail:;
S. J. Finney and T. C. Lim are with the Institute for Energy and Environment, III. CIRCUIT AND DEVICE MODELLING
Department of Electronic and Electrical Engineering, University of Strathclyde,
Glasgow G1 1XW, U.K. A chopper cell is used in order to evaluate the AVC per-
Digital Object Identifier 10.1109/TPEL.2006.889895 formance, shown in Fig. 2. The control loop is formed by the
0885-8993/$25.00 © 2007 IEEE

Fig. 3. IGBT carrier distribution for on-state and turn-off operation, showing
the depletion layer sweeping out the stored charge as the voltage increases
during turn-off. The boundary currents I 0 I are also indicated.

Fig. 2. Chopper cell circuit used in simulation, showing the AVC control
model. a current buffer stage [10]. This has a cutoff frequency of
and a dc gain of . A Simulink “viscous friction” block is
incorporated to account for the large-signal behaviour of the
feedback block and the amplifier block . Stray induc- amplifier.
tances have also been included. A gate resistor is added for
A. Device Models The gate drive optimization concentrates on optimizing the
reference voltage turn-on profile and gate resistance ,
The IGBT and diode models are based on those developed both to reduce the switching losses and to minimize the peak
using a Fourier-series-based solution of the ambipolar diffusion diode recovery voltage overshoot . This is achieved using a
equation (ADE) [6], [7]. These compact, physics-based models formal numerical optimization algorithm [7], [11]. Such an al-
offer an accurate solution of the device physics. They have been gorithm finds the optimum design by varying system parameters
developed for use in both PSpice and MATLAB/Simulink. Here, (e.g., component values, controller gains, or reference wave-
MATLAB is used as a convenient environment for the optimiza- form characteristics) and evaluating the system performance. In
tion algorithm, requiring the Simulink model implementation addition to the optimization algorithm, a suitable function must
[7]. be found to quantify the performance of the system to allow the
The carrier dynamics of the carrier storage region (CSR) are evaluation to proceed automatically. Since the evaluation relies
governed by the ambipolar diffusion equation (ADE) describing on simulation of the system, this function must process the sim-
the behaviour of the excess carrier density. In the Fourier-based ulation results to obtain the performance metric.
solution the excess carrier density is expressed as a Fourier se-
ries in space, which transforms the ADE into a set of ODEs A. Optimization Algorithm
[6]. The boundary conditions of the CSR—necessary to solve Optimization techniques rely on finding the minimum of
the ADE—are the hole and electron currents at each end. The an objective (or cost) function. This is specific to a particular
moving boundary at the gate side of the region determines the problem, and must depend on the system parameters. The
switching characteristics of the IGBT. The interaction of the de- optimum set of parameter values will give the minimum objec-
pletion layer formed during turn-off and the remaining stored tive function (e.g., finding the minimum power dissipation by
charge defines the gate input capacitance and output capacitance varying circuit parameters).
[8], [9]. The formulation used for the gate-collector capacitance The objective function typically embodies good engineering
is given in Appendix I. This is solved in relation to the ADE in a practice. In optimization of the AVC gate drive, the device
continuous manner as part of the model. The output capacitance power dissipation and the diode overshoot voltage cannot be
is implicitly modelled by the movement of the depletion layer expressed as analytic functions of the parameters (gate resis-
boundary as it sweeps out the stored charge, Fig. 3. A simplified tance, feedback gain, etc.). Therefore direct search algorithms
block diagram of the Simulink IGBT model is shown in Fig. 4. must be used to locate the minimum [12], [13]. This involves
Further details are given in [6], [7]. the objective function being evaluated at points surrounding the
current position in the parameter space, and an advantageous
B. AVC Model move being made.
The feedback circuit in Fig. 2 is a potential divider which According to the Hooke and Jeeves Search [13], shown in
reduces the large collector voltage to a suitable level for use in Fig. 5, after a move in a particular direction is made, the search
the control circuit. A single pole with a cutoff frequency of algorithm then tests to see if further movement in the same di-
and a dc gain of is assumed. The amplifier is realized rection would give another reduction in the objective function.
in the gate drive with a wide-bandwidth op-amp, LM7171, and This is known as a pattern move. The search is terminated when

Fig. 4. Simulink IGBT model, with labels showing the functions of the various blocks.

Here, the waveforms are processed to give the diode and

IGBT power dissipation and the peak diode voltage overshoot.
The results are combined and weighted as required to form the
objective function.

B. Implementation
The optimization algorithm is implemented in MATLAB.
The objective function evaluation consists of running the
simulation in Simulink (using a MATLAB function call) and
analyzing the data within MATLAB. Simulation runs which
take longer than a set time are ignored as they generally involve
a lack of convergence, such that the particular simulation is
unlikely to produce a result.
While the reduction in switching losses is the main desired
objective, evaluating this from switching waveforms may be dif-
Fig. 5. Example of the Hook and Jeeves direct search with two variables. ficult to achieve. Therefore the total average power loss over
one complete switching cycle is taken instead. The diode peak
recovery voltage overshoot is simply found by searching for
there is no further improvement in objective function by moving the most negative diode voltage during the IGBT turn-on/diode
in any direction. turn-off switching event. The objectives may be combined into

Fig. 6. Boost converter used as a clamped inductive load test circuit.


one using a weighted sum. The average total power dissipation

is close to 1 kW, and the peak recovery voltage is one to two
times the supply voltage. Hence, to reasonably balance the ef- Fig. 7. Experimental (dotted) and simulated (solid) waveforms for turn-on with
the original profile (P1) at 113 A.
fects, the objective for the optimizations is equal to a simple sum
of the average power dissipation in kW and the relative peak re-
covery voltage
and the device models have been proven to predict the device
(1) operation accurately [11]. Therefore in this paper the optimiza-
tion technique is investigated using laboratory-scale conditions
for demonstration.
V. RESULTS Figs. 7 and 8 show experimental waveforms from the AVC
gate drive and corresponding simulation waveforms. The con-
A. Experimental Setup and Model Validation troller used the original profile P1, given in Table II. These
waveforms exhibit the expected characteristics of the AVC gate
The experimental circuit is based on a boost converter, Fig. 6. drive, including the preconditioning step and good voltage fol-
The switching voltage may be set by varying the supply lowing during switching. The simulated gate waveforms also
voltage , the load resistance and the charging period of demonstrate that the model correctly captured the controller ac-
the supply inductance . The acquisition of the waveforms tion of the AVC method. The switching energies at turn-on and
is carried out using a LeCroy Waverunner LT344L digital os- turn-off are compared in Table IV, showing close agreement.
cilloscope, from which the waveforms can be extracted using
MATLAB. The measured waveforms are as follows.
B. Optimization of the AVC Method
The output voltage of the gate drive, measured at the
gate drive side of the gate resistor . The profile P1 and the gate resistance were then opti-
The gate-emitter voltage of the IGBT, measured at mized [optimization (1)] to minimize the power dissipation over
the IGBT side of the gate resistor . the whole switching cycle, giving profile P2. Fig. 9 shows the
IGBT collector-emitter voltage. simulation waveforms for profiles P1 and P2. The optimiza-
tion has effectively caused the devices to operate under hard
IGBT collector current.
switching. This gives an increased reverse recovery current and
The AVC reference voltage, scaled to match the diode overshoot voltage. The power dissipation values
collector voltage demand. before and after optimization are given in Table III, showing a
The devices under test are from a Semikron IGBT/diode pair, reduction in power dissipation.
SKM400GA173D, rated at 1700 V/400 A and previously pa- Profile P2 was then optimized further [optimization (2)]
rameterized using methods described in [11]. The switching by minimizing the weighted sum of the power dissipation
voltage is set to 300 V and the load current to two values: and the diode peak reverse recovery voltage . The
113 A and 50 A. The system parameters are given in Table I. The simulation waveforms for the resulting profile, P3, are shown
AVC technique has been proven previously at high voltage [1], in Fig. 10, compared with those for P2. Values for and

Fig. 9. Optimization (1): simulation waveforms for optimized and original pro-
files (P2, solid, and P1, dotted, respectively).

Fig. 8. Experimental (dotted) and simulated (solid) waveforms for turn-off

with the original profile (P1) at 113 A. TABLE III


3: Objective function consists of value shown in bold.

place during the collector current fall. As the rate of current fall
depends on the small difference between the device voltage and
are given in Table III, showing that the overshoot the supply, the error in tracking the reference results in an error
in the diode reverse recovery voltage, , has been eliminated in the current fall. However, Table IV shows a close agreement
at the expense of a small increase in losses. between the simulated and experimental switching energies at
The effect of reducing the load current to 50 A is shown in the two current levels, showing that the improvement expected
Fig. 11 for profiles P1 and P3. The diode recovery occurred be- is obtained experimentally.
fore the second ramp in both cases. The optimization continued The practical effect of adopting a fixed profile for a range of
(index 3, Table III), at 50 A, giving profile P4, and a low diode load currents is illustrated in Figs. 17 and 18. Fig. 17 shows
overvoltage was maintained, Fig. 12. turn-on at a load current of 113 A, using profile P4. The second
ramp occurred before the completion of the diode recovery, ac-
C. Experimental Validation of Optimization Trends companied by an increased diode overshoot voltage. Fig. 18
Experimental and simulation waveforms for turn-on and shows turn-on at a load current of 50 A, using profile P3. The
turn-off are shown in Figs. 13 and 14, respectively, for a load diode recovery occurred during the first ramp, leading to in-
current of 113 A, using the optimized profile P3. Similar creased losses, Table IV.
waveforms are shown, in Figs. 15 and 16, for the reduced load
current of 50 A, using the optimized profile P4. The simu- VI. DISCUSSION
lated waveforms contain similar features to the experimental The results in Section V show that the simulation captures
waveforms. The tracking of the reference in the experimental the behaviour of the AVC gate drive sufficiently accurately to
results is not as close as that predicted by the simulation. The be used in formal optimization. In particular, the switching en-
experimental results in Fig. 14 show a small oscillation in the ergy predictions in Table IV are close to the experimental values.
rising collector voltage not contained in the simulation. In Some of the errors between the simulation and experimental
Figs. 8 and 14 active clamping of the collector voltage is taking waveforms may be accounted for by the models used in the

Fig. 10. Optimization (2): simulation waveforms for the optimized profile P3 Fig. 12. Optimization (3): simulation waveforms at reduced current (50 A),
(solid), compared with those for profile P2 (dashed). with the profile optimized for 50 A (P4, solid) and that for 113 A (P3, dotted).

Fig. 11. Simulation waveforms for reduced current operation (50 A), with the Fig. 13. Experimental (dotted) and simulated (solid) waveforms for turn-on
original profile P1 (dotted) and the profile optimized for 113 A (P3, solid). with the optimized profile (P3) at 113 A.

simulation of the gate drive. The two-stage turn-on profile al- reverse recovery voltage becomes large in magnitude, as is ev-
lows the diode to recover before the IGBT collector voltage has ident from Fig. 9. This shows that the optimization correctly
reached its on-state value, although successfully achieving this determines that hard switching results in the minimum IGBT
depends on the choice of the profile. Clearly this may be ex- losses, Table IV. The reintroduction of a large diode peak re-
pected to increase the turn-on switching losses. Consequently, verse recovery voltage is unattractive, and the loss of control
optimization (1) effectively removes active control of the gate, over the IGBT is unacceptable when switching series-connected
forcing the IGBT into hard switching. However, the peak diode devices.

Fig. 14. Experimental (dotted) and simulated (solid) waveforms for turn-off Fig. 16. Experimental (dotted) and simulated (solid) waveforms for turn-off
with the optimized profile (P3) at 113 A. with the optimized profile (P4) at 50 A.


3: All switching energies, E , E , refer to IGBT losses and are in mJ.

Optimized profiles are given in bold. Energies for Figs. 17 and 18 are given
in (parentheses), referring to load currents inappropriate for the profile used.
y: Type refers to waveforms used to evaluate energies; exp: experimental,
sim: simulation.

slope also acts to turn on the IGBT quickly to maintain low

switching losses.
Retaining the power dissipation in the objective function in
optimization (2) means that the gains made in optimization
(1) are not lost. Although the values in Table III how that the
Fig. 15. Experimental (dotted) and simulated (solid) waveforms for turn-on power dissipation increases from 1.20 to 1.38 kW, the total
with the optimized profile (P4) at 50 A. objective function value decreases from 2.85 to 2.38. The
values in Table IV show that the energy losses increase from
6.1 to 14.3 mJ, but both are significantly smaller than the initial
Optimization (2) reduces the diode peak reverse recovery value of 35.9 mJ. Clearly a small sacrifice in power dissipa-
voltage, shown in Fig. 10. This is achieved by delaying the tion is beneficial in improving the apparent overall system
second, steeper slope until the diode reverse recovery current performance. However, it should be stressed that the choice of
is near to its peak. Then, the development of the diode reverse weighting between power dissipation and diode peak reverse
recovery voltage is closely tracked by the reducing IGBT col- recovery voltage depends ultimately on the application. Dif-
lector voltage. The diode reverse recovery overshoot voltage is ferent weightings would give rise to correspondingly different
very small as if it were switching at a low voltage. This second optimum profiles.

the device, contributing significantly to the power dissipation.

Delaying the step in with larger values of therefore re-
duces . Alternatively the time may be shortened. An
increased value of also improves stability. These waveforms
may be considered ideal.
With a smaller current, switching occurs more quickly.
Therefore the diode recovers before the IGBT collector voltage
reaches its on-state value, Fig. 11. The switching loss is not
optimized but the reference tracking is maintained. Although
the switching losses become suboptimal, the reduced current
means that the absolute switching loss decreases. Despite being
suboptimal in this condition, P3 is an improvement on the
original profile P1.
Reoptimization, Fig. 12, improves the combined objective of
power dissipation and diode peak reverse recovery voltage at
50 A by making the profile steeper. In addition to the profile
becoming steeper, the duration of the first slope is also
reduced, so that, as with optimization (2), the diode recovers
just as the reference voltage is falling. Undoubtedly this syn-
chronization is very attractive.
Inevitably, without adaptive control of the reference wave-
form, the switching will often be suboptimal as the load current
varies during operation. A higher load current, Fig. 17, results in
Fig. 17. Experimental waveforms for turn-on with the profile optimized for
50 A (P4) at 113 A.
a late diode recovery and an increased overshoot voltage. This
represents harder switching and the switching losses are reduced
( decreases from 14.7 mJ to 11.5 mJ, Table IV). A smaller
load current, Fig. 18, results in early diode recovery. While this
guarantees that there is no diode overvoltage, it results in greater
switching losses than are necessary ( increases from 6.3 mJ
to 9.5 mJ, Table IV). Clearly, delaying the onset of the second
ramp as much as possible is attractive if eliminating diode over-
voltage is essential.
Thus, the main compromise necessary is in the timing of the
second ramp, if one profile is required to operate at all load
currents. At high currents, minimizing the losses is essential,
and extra diode overshoot voltage may be acceptable because
diodes are less likely to “snap” at high currents [14]. There-
fore, using a profile optimized for an intermediate current level
would be most attractive. At low currents, this will result in
the diode recovering before the second ramp. Thus, snap in the
diode voltage recovery is likely to be contained within the de-
vice voltage rating. The small additional losses incurred are a
necessary consequence of controlling the diode recovery in an
robust manner.
The AVC optimization would benefit greatly from the use
of a multiple-objective optimization algorithm, e.g., [15]. This
would avoid the need for a weighting, generating trade-off
curves from which the designer could judge quickly the op-
Fig. 18. Experimental waveforms for turn-on with the profile optimized for timum trade-off. Optimization across multiple conditions [16],
113 A (P3) at 50 A. particularly the load current and temperature, would also be
useful in ensuring a robust controller design.
In practical systems, there may be a string of series-connected
It should be noted from Table II that the gate resistance IGBTs. Since there will always be an inherent variation in IGBT
also increased from 3.9 to 10.9 in the optimizations. This is parameters, such as leakage current and threshold voltage, the
contrary to usual practice but it is clear the tracking remains ability of a gate drive to maintain control of the device may vary
good. The principal effect of this is to delay the onset of turn-off across the string. Simulation of a whole series string and the
during the preconditioning step, Figs. 14 and 16 compared to subsequent application of robust optimization methods would
Fig. 8. During this period the collector voltage is in the range of be a valuable asset in determining the reliability of the system
at least tens of volts, with the full load current flowing through performance.

and the gate around the edge of the cell, Fig. 19. It has been
observed from detailed device simulations that during turn-off,
the gate depletion layer expands from the edge of the intercell
region under the gate, and moves towards the P-well as the ac-
cumulation layer under the gate is removed. It is also assumed
that the depletion layer extends the same distance laterally as it
does vertically, and that the width of this depletion layer, ,
is set by the difference between the MOS channel voltage
and the gate voltage


where is the permittivity of silicon, is the unit electron charge

and is the base (drift region) doping concentration.
The gate capacitance therefore consists of two separate ca-
pacitances: the depleted capacitance, , and the remaining
accumulation layer capacitance, . has a capacitance
per unit area consisting of the series combination of the oxide
capacitance per unit area, , and the depletion layer depth,
, where is the radius. has a capacitance per unit area
equal to that of the oxide capacitance . In order to calculate
these capacitances, the lateral depletion layer width, , must
be correctly limited to the intercell half-width,
if .

The radius of the cell, , is also defined by the intercell area

Fig. 19. Arrangement of the gate accumulation and depletion layers during
IGBT turn-off. Dimensions for calculating the gate capacitance are shown
ratio, , and the intercell half-width,

VII. CONCLUSION The depth of the depletion layer is also given by

The numerical optimization method outlined in this paper (5)

has been shown to be an effective method of improving the
performance of the AVC gate drive. It is clear that MATLAB/ The accumulation and depletion capacitances are therefore
Simulink is a suitable environment for optimization of AVC per- calculated by integrating the capacitances across the appropriate
formance. Accurate compact diode and IGBT models were used areas, giving
to achieve close matching between experimental and simulated
The strategy described in this paper is appropriate for control-
ling single IGBTs where the diode overvoltage needs to be lim-
ited. A compromise between switching losses and diode over- (6)
shoot voltage may be obtained for different load currents using
AVC. The designer may select the weightings used in the objec- (7)
tive and the load current at which the optimization is performed.
The optimization has indicated that the main fall of the IGBT (8)
collector voltage should be delayed until the diode recovers. The
study has also highlighted that a single-point optimization can
be chosen which is appropriate for the range of load currents REFERENCES
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[4] P. Palmer, Y. Wang, M. Abu-Khaizaran, and S. Finney, “Design of Yalan Wang (S’05) received the B.S. degree in
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Aachen, Germany, Jun. 2004, pp. 3248–3254. sity, Xi’an, China, in 2000 and is currently pursuing
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Electron., vol. 5, no. 4, pp. 459–468, Oct. 1990. borough University of Technology, Loughborough,
[9] P. Palmer and J. Joyce, “Circuit analysis of active mode parasitic os- U.K., in 1988 and the Ph.D. degree from Heriot-Watt
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pp. 85–91, Apr. 2003. He worked for the Electricity Council Research
[10] Y. Wang, A. Bryant, P. Palmer, S. Finney, M. Abu-Khaizaran, and G. Center before joining the Power Electronics Re-
Li, “An analysis of high power IGBT switching under cascade active search Group, Heriot-Watt University in 1990.
voltage control,” in Proc. Ind. Appl. Soc. Conf., Hong Kong, Oct. 2005, From 1994 to 2005, he was a member of academic
pp. 806–812. staff at Heriot-Watt University and is currently a
[11] A. Bryant, X. Kang, E. Santi, P. Palmer, and J. Hudgins, “Two-step Senior Lecturer with the Institute of Energy and
parameter extraction procedure with formal optimization for physics- Environment, University of Strathclyde, Glasgow, U.K., specializing in power
based circuit simulator IGBT and PIN diode models,” IEEE Trans. electronic systems. He has published over 20 articles in IEEE and IEE journals.
Power Electron., vol. 21, no. 2, pp. 295–309, Mar. 2006. His research interests include the power electronics for high power applications
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of fast power diodes,” in Proc. EPE Conf., Seville, Spain, 1995, vol. 1, He is currently a Research Fellow with Strathclyde
pp. 577–582. University, Glasgow, U.K. His research activity in-
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Parallel Problem Solving Nature, Birmingham, U.K., Sep. 2004, pp. verter drives.
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erating conditions on multi-objective optimization of power electronic
devices and circuits,” in Proc. IEEE 40th Annu. Ind. Appl. Soc. Conf.,
Kowloon, Hong Kong, Oct. 2005, pp. 1449–1456.

Patrick R. Palmer (M’87) received the B.Sc.

and Ph.D. degrees in electrical engineering from
the Imperial College of Science and Technology,
University of London, London, U.K., in 1982 and
1985, respectively.
He joined the faculty at the Department of Engi-
neering, University of Cambridge, Cambridge, U.K.,
Angus T. Bryant (S’02–M’06) received the M.Eng. in 1985 and St. Catharine’s College, Cambridge,
degree in electrical and information sciences and in 1987. He became an Associate Professor in
the Ph.D. degree in power electronics from Queens’ the Department of Electrical and Computer Engi-
College, Cambridge University, Cambridge, U.K., in neering, University of British Columbia, Vancouver
2001 and 2005, respectively. BC, Canada, in 2004 and Reader in Electrical Engineering, University of
In 2005, he became a Research Fellow at the Uni- Cambridge, in 2005. He has extensive publications in his areas of interest
versity of Warwick, Warwick, U.K. His main inter- and is the inventor on two patents. His research is mainly concerned with
ests are semiconductor device modelling, simulation the characterization and application of high-power semiconductor devices,
and characterization of power electronic systems, and computer analysis, simulation and design of power devices and circuits and he
optimization and testing of power electronic systems has further interests in fuel cells.
under realistic loading conditions. Dr. Palmer is a Chartered Engineer in the U.K.