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ECE4514 Fall 2011 Homework 7: A Static RAM Controller

Assignment posted on 13 October 8AM Solutions due on 20 October 8AM Asynchronous Static RAM memory modules are commonly used for off-chip bulk storage. Accessing data in an SRAM requires the user to provide address- and data-signals with a timing according the specification provided by the SRAM manufacturer. In this homework, you will study the data sheet of the static RAM module present on your DE2-115 board, and you will develop a controller for it. The controller is a module that can translate a generic digital memory interface (used by on-chip components) into an interface that follows the specifications of the static RAM manufacturer. You will receive a simple testbench that enables you to verify the correct operation of the SRAM controller. However, the design of the SRAM controller is entirely up to you; only the input/output specification is a given. The result of this homework will the Verilog file that you have developed for this SRAM controller. It is not allowed to use any external code for this assignment. You cannot make use of IP modules, code provided through the Altera toolkit, and so forth. Every single line of Verilog must be your own.

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You’ll need to use the datasheet to understand the operation of this component. you have to specificy the read-access and write-access in terms of clock cycles. and a second table which shows what will happen when your interface performs a write-access. You will also need to determine the timing of a read operation and a write operation. there is a subdirectory called DE2 115 datasheets. you need to create two tables: one which shows what will happen when your interface performs a read-access. Look at the component on the board to identify the exact speed grade for your case. Once you have studied the SRAM datasheet. input wire sram_oe_n. • There are several different timing diagrams present. corresponding to different use cases of the SRAM. and a read-access operation for this component. Choose the use case that fits most closely to your particular board configuration. input wire sram_ub_n.Section 1: Study the SRAM datasheet The objective of this section is to learn enough about the SRAM on your DE2-115 board so that you are able to write Verilog code for the following SRAM interface. 2 . input wire sram_lb_n. To describe the behavior of the SRAM controller. this particular SRAM comes in three different speed grades. A few crucial remarks are as follows. // // // // // // // SRAM SRAM SRAM SRAM SRAM SRAM SRAM address bidirectional data upper byte control lower byte control chip enable output enable write enable On your DE2-115 CDROM. module sram( input wire [19:0] sram_addr. Find the datasheet for the SRAM component on your board. input wire sram_ce_n. input wire sram_we_n ). inout wire [15:0] sram_dq. Since we will be developing a synchronous SRAM controller. • According to the datasheet. you have to define a write-access operation.

describe the communication between the SRAM chip and your SRAM controller. For SRAM inputs. as an input our as an output. assume the value of the address is ADDRESS. the important point is that your SRAM controller will be able to follow the constraints of the timing diagram. For the write operation. The SRAM input/output sram dq is special: it can be either an SRAM input or an SRAM output. in each cycle. For this section. Your SRAM interface will need to treat this bus as a tri-state bus. In your tables.. For SRAM outputs. indicate if sram dq is used. assume the value of the address is ADDRESS. you need to turn in a PDF which shows both tables (one for read access and one for write access) to the SRAM. In the cells of the table.. 3 . Note that this section does not specify the amount of clock cycles you need for the SRAM access. You can assume that the controller will operate at 50MHz. For the read operation. express the logic values of signals which your SRAM controller will receive from the SRAM. You can extend each table with as many columns (clock cycles) you need to implement a write-access and a read-access to the SRAM. and the data read from ram is READDATA. and the data written into ram is WRITEDATA.cycle 1 sram sram sram sram sram sram sram addr dq ub n lb n ce n oe n we n cycle 2 cycle 3 cycle . express the logic values of the signals which your SRAM controller will provide.

and should be 1 when the user wants to initiate a RAM-access operation. • frwn is a RAM-read/write control signal. you have studied the SRAM. frnw. wire sram_lb_n. and should be 1 for a read operation. fready. 4 clk. and write into this asynchronous SRAM. the ports starting with f are for the SRAM user. wire sram_we_n . The outline for this SRAM controller looks as follows.Section 2: Design the SRAM controller In Section 1. wire [15:0] sram_dq. The signal is 1 to indicate that the current clock edge terminates a RAM-access operation. module sramctl( input wire input wire input wire input wire output wire input wire input wire output reg output inout output output output output output ). and you developed a high-level model of a synchronous controller that can read from. • faccess is a RAM-access control signal. Now. The ports starting with sram are connected to the SRAM. [15:0] fwdata. and they have the following meaning. and 0 for a write operation. wire sram_oe_n. • fready is a RAM-access status signal. • frdata holds the data going from the RAM to the user. wire sram_ub_n. you need to develop an implementation for the controller. • faddr holds the RAM address. [15:0] frdata. faccess. wire sram_ce_n. • fwdata holds the data going from the user to the RAM. // // // // // // // // // // // // // fpga fpga fpga fpga fpga fpga SRAM SRAM SRAM SRAM SRAM SRAM SRAM address write-data read-data memory access read/not-write control ready signal address bidirectional data upper byte control lower byte control chip enable output enable write enable wire [19:0] sram_addr. rst. [19:0] faddr. These latter ports are asserted at the upgoing clock edge.

It’s up to you to decide how to handle this. then the RAM controller should put the fready signal low at the next clock edge. you only have the SRAM datasheet.An example of the operation of this interface is illustrated in the timing diagram above. single fready is high at that clock edge. A single-cycle write operation is illustrated at clock edge 5. fwdata=d3. An important challenge is that you don’t have a behavioral model of the SRAM. At clock edge 3. Your task is to develop this SRAM controller as a synthesizable Verilog program. a read-access operation is started by providing (faddr=ad1. For example. In this case. or you could try to implement your design and instrument it with a SignalTap-II logic analyzer. the data is then returned to the user. A single-cycle read operation is illustrated at clock edge 3 (faddr=ad2. you could try to build a behavioral SRAM model for debugging purposes. the user needs to provide an address as well as data (faddr=a3. Note that the access cycle time for the RAM is determined by the timing specification of the SRAM according to the data sheet. Assume that read operations into the SRAM would take two clock cycles. faccess=1. The data from RAM is valid at clock edge 4. faccess=1. frnw=1). 5 . frnw=0). At clock edge 1. frnw=1). faccess=1.

The SRAM controller needs to work properly with the provided test bench. • By pressing push button 0. you can control your design by means of the buttons and the slider switches.To help you test the SRAM controller on the DE2-115 board. • By pressing push button 1. 6 . The address used for the write operation is given by the bit pattern of slider switches 0 to 15. this simple test bench enables you to read and write values into the SRAM. The testbench works as follows. you will reset the design. you will write the value from the data register into the SRAM.v. The data stored at that location will be displayed on red led 0 to 15. For this section. After downloading your design to the FPGA. The upper 4 bits of the SRAM address are held at 0. you will read the value from the SRAM at the address given by the bit pattern on the slider switches. you need to turn in a Verilog description of the SRAM controller. Thus. you will program the bit pattern of slider switches 0 to 15 into a data register. sramctl. • By pressing push button 2. a test bench is provided on Scholar. • By pressing push button 3.

2. 1. For Section 1.v and call the top-level module of the controller sramctl.What to turn in Turn in the following data on the scholar website. 7 . a Verilog design of the SRAM controller. For Section 2. a PDF file with the two tables describing a synchronous read operations and a synchronous write operation into the SRAM. Call this file sramctl.