# Static Timing Analysis Overview

Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations. PrimeTime checks for violations in the same way that you would do it manually, but with much greater speed and accuracy. To check a design for violations, PrimeTime breaks the design down into a set of timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface. Another way to perform timing analysis is to use dynamic simulation, which determines the full behavior of the circuit for a given set of input stimulus vectors. Compared with dynamic simulation, static timing analysis is much faster because it is not necessary to simulate the logical operation of the circuit. It is also more thorough because it checks all timing paths, not just the logical conditions that are sensitized by a particular set of test vectors. However, static timing analysis can only check the timing, not the functionality, of a circuit design.

Timing Paths
The first step performed by PrimeTime for timing analysis is to break the design down into a set of timing paths. Each path has a startpoint and an endpoint. The startpoint is a place in the design where data is launched by a clock edge. The data is propagated through combinational logic in the path and then captured at the endpoint by another clock edge. The startpoint of a path is a clock pin of a sequential element, or possibly an input port of the design (because the input data can be launched from some external source). The endpoint of a path is a data input pin of a sequential element, or possibly an output port of the design (because the output data can be captured by some external sink). Figure 1-4 shows an example of a simple design and the data paths contained in that design. Figure 1-4 Timing Paths

and ends at a data capture point: Path 1 starts at an input port and ends at the data input of a sequential element. Path 2 starts at the clock pin of a sequential element and ends at the data input of a sequential element.In this figure. as illustrated in Figure 1-5. PrimeTime considers other types of paths for timing analysis. such as the following: Clock path (a path from a clock input port or cell pin. Each path starts at a data launch point. A combinational logic cloud might contain multiple paths. Figure 1-5 Multiple Paths Through Combinational Logic In addition to the data paths just described. each logic cloud represents a combinational logic network. through one or more buffers or inverters. PrimeTime uses the longest path to calculate a maximum delay or the shortest path to calculate a minimum delay. passes through some combinational logic. to the clock pin of a sequential element) for data setup and hold checks Clock-gating path (a path from an input port to a clock-gating element) for clock-gating setup and hold checks Asynchronous path (a path from an input port to an asynchronous set or clear pin of a sequential element) for recovery and removal checks Figure 1-6 shows some examples of these types of paths. . Path 3 starts at the clock pin of a sequential element and ends at an output port. Path 4 starts at an input port and ends at an output port.

Net Delay . Based on these table entries. the chip topography is unknown. Cell Delay Cell delay is the amount of delay from input to output of a logic gate in a path. PrimeTime calculates the cell delay from delay tables provided in the technology library for the cell. PrimeTime can read the SDF file and back-annotate the design with the delay information for layout-accurate timing analysis. The total delay of a path is the sum of all cell and net delays in the path. PrimeTime uses interpolation or extrapolation of table values to obtain a delay value for the current conditions specified for the design. When necessary. an external tool can accurately determine the delays and write them to a Standard Delay Format (SDF) file. PrimeTime calculates each cell delay. After layout. In the absence of back-annotated delay information from an SDF file. a delay table lists the amount of delay as a function of one or more variables. Typically.Figure 1-6 Path Types Delay Calculation After breaking down a design into a set of timing paths. Before layout. so PrimeTime must estimate the net delays using wire load models. PrimeTime can also accept a detailed description of parasitic capacitors and resistors in the interconnection network. such as input transition time and output load capacitance. and then accurately calculate net delays based on that information. PrimeTime calculates the delay along each path. The method of delay calculation depends on whether chip layout has been completed.

PrimeTime can also check recovery/removal constraints. data-to-data constraints. if a signal must reach a cell input at no later than 8 ns and is determined to arrive at 5 ns. A setup constraint specifies how much time is necessary for data to be available at the input of a sequential device before the clock edge that captures the data in the device. combined with net resistance and the limited drive strength of the cell driving the net. A hold constraint specifies how much time is necessary for data to be stable at the input of a sequential device after the clock edge that captures the data in the device. In addition to setup and hold constraints. This constraint enforces a minimum delay on the data path relative to the clock path. The amount of time by which a violation is avoided is called the slack. The technology library provides statistical wire load models for estimating parasitic resistance and capacitance based on the number of fanout pins on each net. PrimeTime can calculate net delays by the following methods: By using specific time values back-annotated from an SDF file By using detailed parasitic resistance and capacitance data back-annotated from file in RSPF. Constraint Checking After PrimeTime determines the timing paths and calculates the path delays. For example. SPEF. A negative slack indicates a timing violation. Setup and Hold Checking for Flip-Flops Figure 1-7 shows how PrimeTime checks setup and hold constraints for a flip-flop in the absence of timing exceptions that apply to the data path. and minimum pulse width for clock signals. This delay is caused by the parasitic capacitance of the interconnection between the two cells. A slack of 0 means that the constraint is just barely satisfied. it can check for violations of timing constraints. or SBPF format By estimating delays from a wire load model A wire load model attempts to predict the capacitance and resistance of nets in the absence of back-annotated delay information or parasitic data. the slack is 3 ns. . for a setup constraint.Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path. such as setup and hold constraints. clock-gating setup/hold constraints. This constraint enforces a maximum delay on the data path relative to the clock path.

For this hold check. see Chapter 9. For this setup check. PrimeTime considers the longest possible delay along the data path and the shortest possible delay along the clock path between FF1 and FF2. it is reported as a timing violation. it verifies that the data path delay is small enough so that the data launched from FF1 reaches FF2 within one clock cycle. PrimeTime assumes that signals are to be propagated through each data path in one clock cycle.0 time units. Therefore. is specified in the technology library. This check ensures that the data already existing at the input of FF2 remains stable long enough after the clock edge that captures data for the previous cycle. The clock period is defined in PrimeTime to be 10 time units. (The time unit size. and arrives at least 1.) By default. it verifies that the data launched from FF1 reaches FF2 no sooner than the capture clock edge for the previous clock cycle.0 time units and a minimum hold time of 0.0 time unit before the data gets captured by the next clock edge at FF2.Figure 1-7 Setup and Hold Checks For this example. Note: For more examples of setup and hold calculations. assume that the flip-flops are defined in the technology library to have a minimum setup time of 1.” . PrimeTime considers the shortest possible delay along the data path and the longest possible delay along the clock path between FF1 and FF2. “Timing Exceptions. such as ns or ps. A hold violation can occur if the clock path has a long delay. If the data path delay is too long. including paths that use different clocks at the path startpoint and endpoint. when PrimeTime performs a setup check. When PrimeTime performs a hold check.

the rising edge of PH1 launches the data. All three latches are level-sensitive. For this example. For the path from L1 to L2. PrimeTime can use time borrowing to lessen the constraints on successive paths. and L2 is controlled by PH2. A rising edge launches data from the latch output. In these cases. nonoverlapping clocks to control successive registers in a data path. Figure 1-8 Latch-Based Paths Figure 1-9 shows how PrimeTime performs setup checks between these latches. consider the two-phase. latch-based path shown in Figure 1-8. This timing requirement is labeled Setup 1. consider the latch setup and delay times to be zero. Figure 1-9 Time Borrowing in Latch-Based Paths . For example. the data might arrive either before or after the opening edge of PH2 (at time=10).Setup and Hold Checking for Latches Latch-based designs typically use two-phase. The data must arrive at L2 before the closing edge of PH2 at time=20. as indicated by the dashed-line arrows in the timing diagram. and a falling edge captures data at the latch input. with the gate active when the G input is high. Arrival after time=20 would be a timing violation. L1 and L3 are controlled by PH1. Depending on the amount of delay between L1 and L2.

Otherwise. the path originates at the D pin rather than the G pin of L2. When borrowing occurs. In that case. PrimeTime lets you specify the following types of timing exceptions: False path – A path that is never sensitized due to the logic configuration. the first path (from L1 to L2) borrows time from the second path (from L2 to L3). To perform hold checking. Figure 1-10 Hold Checks in Latch-Based Paths Timing Exceptions When certain paths are not intended to operate according to the default setup/hold behavior assumed by PrimeTime. expected data sequence. the launch of data for the second path occurs not at the opening edge. If the data arrives after the opening edge of PH2. For the first path (from L1 to L2). or negative (a violation) if the data arrives after the closing edge at time=20. the data for the next path from L2 to L3 gets launched by the opening edge of PH2 at time=10. at some time between the opening and closing edges of PH2. This timing requirement is labeled Setup 2b. PrimeTime reports the setup slack as zero if borrowing occurs. you should specify those paths as timing exceptions.If the data arrives at L2 before the opening edge of PH2 at time=10. or operating mode. PrimeTime considers the launch and capture edges relative to the setup check. Minimum/maximum delay path – A path that must meet a delay constraint that you specify explicitly as a time value. This is depicted in Figure 1-10. PrimeTime might incorrectly report those paths as having timing violations. just as a synchronous flip-flop would operate. but at the data arrival time at L2. This timing requirement is labeled Setup 2a. The slack is positive if the data arrives before the opening edge at time=10. Learning to Use PrimeTime . thereby ensuring that data launched in the previous cycle is latched and not overwritten by the new data. It verifies that data launched at the startpoint does not reach the endpoint too quickly. Multicycle path – A path designed to take more than one clock cycle from launch to capture.

If you need help while using PrimeTime. and by searching through the Web-based SolvNet article database.For a basic introduction to using PrimeTime. see “PrimeTime Documentation and Online Help”. . information is readily available by using the help and man commands. by consulting the PrimeTime manuals. read this chapter and the next chapter of this manual. For more information about getting help.