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D Support Mixed-Mode Signal Operation (5-V D Bus Hold on Data Inputs Eliminates the
Input and Output Voltages With 3.3-V VCC) Need for External Pullup/Pulldown
D Typical VOLP (Output Ground Bounce) Resistors
<0.8 V at VCC = 3.3 V, TA = 25°C D Latch-Up Performance Exceeds 500 mA Per
D Support Unregulated Battery Operation JESD 17
Down to 2.7 V D ESD Protection Exceeds JESD 22
D Ioff and Power-Up 3-State Support Hot – 2000-V Human-Body Model (A114-A)
Insertion – 200-V Machine Model (A115-A)
1OE
VCC
1OE
2OE
VCC
2Y4
1A1
(TOP VIEW)
1OE VCC 1 20
1 20 3 2 1 20 19
1A1 2 19 2OE 1A1 2 19 2OE 1A2 4 18 1Y1
2Y4 1Y1 2Y4 3 18 1Y1 2Y3 5 17 2A4
3 18
1A2 2A4 1A2 4 17 2A4 1A3 6 16 1Y2
4 17
2Y3 5 16 1Y2 2Y3 5 16 1Y2 2Y2 7 15 2A3
1A3 6 15 2A3 1A3 6 15 2A3 1A4 8 14 1Y3
2Y2 7 14 1Y3 9 10 11 12 13
2Y2 7 14 1Y3
1A4 2A2 1A4 8 13 2A2
2Y1
2A1
1Y4
2A2
GND
8 13
2Y1 9 12 1Y4 2Y1 9 12 1Y4
GND 10 11 2A1 10 11
2A1
GND
description/ordering information
These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
ORDERING INFORMATION
ORDERABLE
TA PACKAGE† TOP-SIDE MARKING
PART NUMBER
QFN – RGY Tape and reel SN74LVTH244ARGYR LXH244A
Tube SN74LVTH244ADW
SOIC – DW LVTH244A
Tape and reel SN74LVTH244ADWR
–40°C to 85°C SOP – NS Tape and reel SN74LVTH244ANSR LVTH244A
SSOP – DB Tape and reel SN74LVTH244ADBR LXH244A
TSSOP – PW Tape and reel SN74LVTH244APWR LXH244A
VFBGA – GQN Tape and reel SN74LVTH244AGQNR LXH244A
CDIP – J Tube SNJ54LVTH244AJ SNJ54LVTH244AJ
–55°C to 125°C CFP – W Tube SNJ54LVTH244AW SNJ54LVTH244AW
LCCC – FK Tube SNJ54LVTH244AFK SNJ54LVTH244AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 2002, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.
FUNCTION TABLE
(each buffer)
INPUTS OUTPUT
OE A Y
L H H
L L L
H X Z
2 18 11 9
1A1 1Y1 2A1 2Y1
4 16 13 7
1A2 1Y2 2A2 2Y2
6 14 15 5
1A3 1Y3 2A3 2Y3
8 12 17 3
1A4 1Y4 2A4 2Y4
Pin numbers shown are for the DB, DW, FK, J, NS, PW, RGY, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Current into any output in the low state, IO: SN54LVTH244A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVTH244A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVTH244A . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVTH244A . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): GQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
2.7 V
LOAD CIRCUIT Timing Input 1.5 V
0V
tw
tsu th
2.7 V
2.7 V
Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V
0V 0V
2.7 V 2.7 V
Output 1.5 V 1.5 V
Input 1.5 V 1.5 V
Control
0V 0V
VOH Output 3V
1.5 V 1.5 V Waveform 1 1.5 V
Output VOL + 0.3 V
S1 at 6 V VOL
VOL
(see Note B)
tPHL tPLH tPZH tPHZ
Output VOH
VOH
Waveform 2 VOH – 0.3 V
1.5 V 1.5 V 1.5 V
Output S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING
PINS **
14 16 20
DIM
0.100 (2,54)
0.020 (0,51) MIN A
0.070 (1,78)
0.023 (0,58)
0.015 (0,38) 0°–15°
4040083/E 03/99
0.006 (0,15)
0.100 (2,54) 0.004 (0,10)
0.045 (1,14)
0.320 (8,13) MAX
1 20 0.019 (0,48)
0.015 (0,38)
0.050 (1,27)
0.540 (13,72)
0.490 (12,45)
10 11
4040180-4 / C 02/02
NO. OF A B
18 17 16 15 14 13 12
TERMINALS
** MIN MAX MIN MAX
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
4040140 / D 10/96
1,95 TYP
3,10 0,65
2,90
0,325
0,65
D
4,10 2,60
C
3,90
B
1 2 3 4
A1 Corner
Bottom View
1,00 MAX
0,08
Seating Plane
0,45 0,25
20× 0,15
0,35
0,05 M
4200704/D 07/2002
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
3,65
3,35
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
ÏÏÏÏÏÏ
Pin 1 Index Area
Top and Bottom
0,20 Nominal
1,00 Lead Frame
0,80
Seating Plane
0,08 C
0,05 C
0,00
Seating Height
3,50
0,50 0,50
20X
2 9 0,30
Pin 1 Identifier
1
10
11
20
D 19 12
20X 0,23 +0,07
–0,05
3,15 MAX 0,10 M C A B
0,05 M C
0.020 (0,51)
0.050 (1,27) 0.010 (0,25)
0.014 (0,35)
16 9
0.419 (10,65)
0.400 (10,15)
0.299 (7,59) 0.010 (0,25) NOM
0.291 (7,39)
Gage Plane
0.010 (0,25)
1 8
0°– 8° 0.050 (1,27)
A 0.016 (0,40)
Seating Plane
0.012 (0,30)
0.104 (2,65) MAX 0.004 (0,10)
0.004 (0,10)
PINS **
16 18 20 24 28
DIM
4040000/E 08/01
0,51
1,27 0,25 M
0,35
14 8
0,15 NOM
5,60 8,20
5,00 7,40
Gage Plane
1 7 0,25
Seating Plane
PINS **
14 16 20 24
DIM
4040062 / B 02/95
0,38
0,65 0,15 M
0,22
28 15
0,25
0,09
5,60 8,20
5,00 7,40
Gage Plane
1 14 0,25
A 0°–ā8° 0,95
0,55
Seating Plane
PINS **
14 16 20 24 28 30 38
DIM
4040065 /E 12/01
0,30
0,65 0,10 M
0,19
14 8
0,15 NOM
4,50 6,60
4,30 6,20
Gage Plane
0,25
1 7
0°– 8°
A 0,75
0,50
Seating Plane
PINS **
8 14 16 20 24 28
DIM
4040064/F 01/97
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