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UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering And Computer Sciences


Eddie Ng Mounir Bohsali Professor Bernhard Boser

The main objective of this project is to build a system capable of measuring cell impedance which can be modeled as a parallel RC equivalent network. In order to alleviate the required precision, the channel/cell block is configured in a feedback network whose output signal is compared to the calibrated reference signal. The resulting cell impedance value is passed through ten pairs of I/Q mixers in parallel. After the signal is low pass filtered, it is digitized and fed into a DSP to calculate the end result. Since calibration is done in an early stage in the system, only the first amplifier with the channel/cell feedback configuration requires high precision (0.01%). The simulated system shows that the final results are accurate within 0.01% after modeling the critical non-idealities of all different blocks such as equivalent input referred and quantization noise, finite open loop gain, finite amplifier bandwidth, DC offset, INL, and DNL.

Hierarchical Design Description:

Fig. 1 shows a block level simulation diagram of the entire system. To first order, the system was initially simulated with ideal components. As a second step, critical non-idealities of each building block based on actual commercial products were added, and the system was re-simulated and the results were verified to meet the specs. Feedback amplifier: The channel/cell is placed in a negative feedback configuration around the amplifier. The resulting transfer function is Rf Rf H(s)_ideal = = s Rf (Ccell + Cchannel) Zcell Rcell + Rchannel where Rcell + Rchannel Zcell = 1 + s (Rcell + Rchannel) (Ccell + Cchannel) Refer to Figures 4 and 5 for Simulink block level implementations for the above two transfer functions.

In order to measure the cell impedance, ten input sine waves at logarithmically spaced frequencies (f1, f2, f10) with amplitudes as shown in table 1 are applied to the channel containing both the cell and the solution (See Fig. 3). The input amplitudes are chosen as such to prevent output saturation. In that order, the table below (Table 1) showing minimum and maximum gains at each frequency was generated. The supply voltage (+/-15V) of the chosen commercial op-amp sets a upper limit on the input voltage given by Vsupply Vin_max min [ , Vcc] gain_max The integrated output noise sets a lower limit on the input voltage. Since ten sine waves are applied simultaneously to the amplifier, each signal amplitude could add up in phase. In order to prevent saturation, an n factor is used to scale each input. Simulation showed that an n factor of 8 is sufficient to limit the output swing to +/- 12.5V (maximum output voltage swing of commercial amplifier used in the design).

Frequency 100KHz 2.15KHz 4.64KHz 1MHz 2.15MHz 4.64MHz 10MHz 21.5MHz 46.4MHz 100MHz

Minimum Gain (Cch=50pF, Rch=250)

0.200025 0.200114 0.20053 0.20245 0.211087 0.247442 0.372285 0.704102 1.470623 3.146363

Maximum Gain (Cch=1nF, Rch=500)

0.4049 0.422173 0.494883 0.74457 1.408205 2.941246 6.292726 13.50792 29.14195 62.80127

Maximum Input Amplitude Vo-p

12.5 / n 12.5 / n 12.5 / n 12.5 / n 8.9 / n 4.2 / n 2.0 / n 0.93 / n 0.43 / n 0.2 / n

Table 1. Summary of maximum input amplitudes allowed before output clipping. Simulation suggest usage of n=8, To further refine the model, non-idealities such as finite open-loop gain, offset, finite bandwidth, input-referred noise are added to the Simulink models. Finite open loop gain: The finite open loop gain results in a gain error in the above ideal transfer function as follows: 1 , where a = finite amplifier gain H(s) = H(s)_ideal 1 Rf 1 + (1 + ) a Z Refer to Figure 5 for a Simulink implementation of the above transfer function. Finite amplifier bandwidth: The finite amplifier bandwidth is modeled as follows: ao a= where ao = low frequency gain jwo 1+ w _ 3dB
DC offset and input referred noise: DC offset is modeled in Simulink as a constant block, and input referred noise is modeled using a random signal generator. The THS4021 op-amp from TI, inc. with specifications that meet the above constraints is used in the design The following are the key specs of the above op-amp: Vsupply: +/-15V Output voltage range: +/- 12.5V Input voltage range: +/- 15V Open loop gain: 60V/mV Vos: 0.5mV Gain Bandwidth: 350MHz Input referred noise: 1.5nV/sqrt(Hz)


Calibration is performed in an early stage of the system. A dedicated path for calibration containing a channel without cells is placed in parallel with the path containing channel with cells. A differential topology is used to subtract the measured analog voltage signal from the calibrated channel only analog voltage signal. This is done directly after the first stage analog amplifier. The transfer function of the resulting network is: - Rf Zcell H(s) = Zchannel(Zchannel + Zcell) Since calibration is being done in an early stage of the system, all the analog components following the fist stage amplifier only need to carry approximately a 1% accuracy. Refer to Figures 7 and 8 for measurement calibrated values of Rchannel and Cchannel.
Mixers: In order to separate the outputs at the different frequencies of interest, the signal is fed into twenty analog mixers separated into ten pairs. Each pair is tuned to one input frequency (i.e. f1, f2, ,f10). Within each pair of mixers, the two local oscillator frequencies are 90o out of phase producing the real and the imaginary parts of the output signal. The commercial AD831 mixer from Analog Devices is used in this system. The mixer specifications as summarized as follows: Vsupply = +/-5V 1dB compression point = 10dBm IP3 = 24dBm LO drive = -10dBm Bandwidth = 500MHz for both RF and LO SSB NF = 10.3dB

The mixers are implemented in Simulink. Since the NF of the mixer is critical in this application, it is modeled in Simulink as a random signal generator added with the input of the mixer.
Low Pass Filters: Following the mixers, low pass filters are used to attenuate the high frequency unwanted signals that result from the mixing operation and keeping only the DC signal of interest. In Simulink, the low pass filters are implemented as a sixth order Bessel low pass filters with fpass=1/10 of input frequency. We chose a sixth order filter because it can give a good attenuation at the frequency of interest and is easily implemented with biquads with acceptable sensitivity of component variations at the same time. A Bessel filter is used to provide good step response and further reduce the settling time. As shown later, these filters also provide an anti-aliasing function for the ADC. A gain stage is added after the low pass filters in order to present a high level signal for the ADC to take advantage of its full scale range.

ADC: The down-conversion of the amplifier output signal from a high frequency to DC relaxes considerably the speed specification of the ADC. However, note that this translation to DC is accompanied by several potential problems as DC offset generated by the amplifiers, noise, and harmonic distortion. A differential topology is used to fix the DC offset problem. Moreover, noise is modeled by a random signal generator whose output is added to the ADC input. The noise variance is calculated using the SNR of the actual ADC used. An ENOB of 14-bit resolution ADC is chosen with a sampling frequency of 40kHz. The commercial ADS7807 16-bit ADC from TI, inc. is used in this system. The following are the critical specifications of the used ADC: Vsupply: +/-5V DNL_max: 16-bits, no missing code INL_max: +/- 1.5LSB SINAD with 1kHz input: 86dB SINAD=SNDR SINAD + 1.76 = 14.6 > 14 required resolution ENOB = 6.02 INL and DNL distortion is modeled in Simulink by representing the input as a 3rd order power series. Vin = Vin + a2*Vin2 + a3*Vin3 Thermal noise is modeled by a random signal generator whose output is added to the ADC input. The noise variance is calculated using the SNR of the actual ADC used. Refer to Figure 6 for the ADC Simulink model. DSP: Following the analog to digital conversion, the signal is processed by a Digital Signal Processor (DSP) for back-end calculation of Zcell using the following two equations: 2 vout Rchannel 2 gain Rcell = 2 Rchannel vout Vin Rf gain 2 vout Ccell = 2 f Rf vi gain where vout is the output voltage of the entire system gain is the overall cascaded gain of the entire system To cancel the factor of produced from mixing two sinusoidal waveforms, a factor of 2 is multiplied to vout. The commercial SMJ320F240 DPS from TI, inc. is used in this system.

10 Input Sinewaves Transfer function Impedance measurement System Display

See Fig. 3

See Fig. 5

See Fig. 2 (dashed circle only)

Figure 1. Simulink block level simulation diagram of complete system

Mixer LPF ZOH Quantizer Gain Display

See Fig. 3

See Fig. 5

See Fig. 6

Figure 2. Simulink block level simulation diagram of the impedance measurement system

f1=100k f2=215k f3=464k f4=1M f5=2.15M f6=4.64M f7=10M f8=21.5M f9=46.4M f10=100M

s Rf Ccell

Rf Rcell

Figure 4. Simulink block level simulation diagram of ideal feedback amplifier transfer function
H( s ) Rf Zcell Rf Rcell s Rf Ccell

Figure 3. Simulink block level simulation diagram of input block

Figure 5. Simulink block level simulation diagram of feedback amplifier transfer function (including finite open loop gain and bandwidth) 1 H(s) = H(s)_ideal 1 Rf 1 + (1 + ) a Z

Figure 6. Simulink block level simulation digram of ADC (non-idealities modeling include thermal noise, INL, DNL, ENOB)

Simulation Results and Verification:

Since calibration is used, the resistance R and the capacitance C of the cell model need to be measured to 1% accuracy in less than 1ms. The following tables summarize the above measurement values and show that all accuracy specifications are met:
Measured Values Ccell (max) Ccell (min) 1.004458E-11 5.030458E-13 1.00911E-11 4.96136E-13

Frequency 1.000000E+05 1.00000E+08

Rcell (max) 4.971222E+00 4.95762E+00

Rcell (min) 2.499606E+00 2.47567E+00

Ccell (max) =1% of 1nF =.01nF, Rcell (max) =1% of 500 =5 Ccell (min) =1% of 50pF =.5pF, Rcell (min) =1% of 250 =2.5 Table 2. Measured values of maximum and minimum Rcell and Ccell over extreme frequency range.
Frequency 1.000000E+05 1.00000E+08 error (%)=abs(measured-actual)/(actual)*100 (<1%) Ccell (max) Ccell (min) Rcell (max) Rcell (min) 4.458366E-01* 6.091612E-01 -5.755533E-01 -1.575827E-02 9.11141E-01 -7.72849E-01 -8.47633E-01 -9.73285E-01

* example calculation: (1.004458e-11-1e-11)/1e-11*100=.4458% Table 3. Calculated error of maximum and minimum Rcell and Ccell over extreme frequency range.
Frequency 1.000000E+05 1.00000E+08 overall error (%)=(measured/(channel+cell))*100-1 (<.01%) Ccell (max) Ccell (min) Rcell (max) Rcell (min) 4.458366E-03* 6.091612E-03 -5.755533E-03 -1.575827E-04 9.11141E-03 -7.72849E-03 -8.47633E-03 -9.73285E-03

* example calculation: 1.004458e-11/(1e-9)*100-1=.004458% Table 4. Calculated overall error of maximum and minimum Rcell and Ccell over extreme frequency range.

The simulation results below show that these specifications are met. For better illustration purposes, the resistor transconductance g is ploted instead of its resistance R. The graphs in Figures 7 and 8 show the output results of the calibration procedure for the conductance and capacitance where the exact values of R and C are 250 and 50pF respectively.
Conductance (S) v/s time (sec)

4.0001 mS

Figure 7. Measured conductance of calibration solution (exact R = 250 = mS)

Capacitance (F) v/s time (sec) 50.096 pF

Figure 8. Measured capacitance of calibration solution (exact C = 50 pF)

Resistance () v/s time (sec)

Rcell= 2.49

Figure 9. Results of the measured Rcell of 2.5 Capacitance (F) v/s time (sec)


Figure 10. Results of the measured Ccell of 0.01nF

Figures 11 and 12 below show the output results of the error in Rcell and Ccell . The graphs show an accuracy greater than 1%. These graphs are generated for resistance and capacitance of 2.5 and .01nF respectively.

Error in R in % vs time in
0.2 % < 1% required accuracy

Figure 11. Error for Rcell = 2.5

Error in C in % v/s time i

0.18% < 1% required accuracy

Figure 12. Error for Ccell = 0.01nF The above simulations show that all specifications requirements (accuracy, settling time) are met at the extreme cases of the cell impedances and frequencies.

In this project, the hierarchical design of a cell impedance measurement system is demonstrated through the use of ideal simulation building blocks as a first step, then through the refinement of the simulations by adding relevant non-idealities to each block based on actual commercial components. Simulations performed on extreme cases of cell impedance values and frequencies are shown to meet the project specifications. The main features of the design are the implementation of the calibration at a very early stage in the system to alleviate the accuracy requirements on all subsequent stage, especially the ADC, as well as the calculation of impedance at different frequencies in parallel. Simulations with non-idealities added to the blocks show that the system is robust and is insensitivity to second order effects. A main improvement that could be done in this design is the calculation of the impedance at the ten different frequencies in a serial instead of the parallel implemented fashion which will considerably reduce the hardware complexity. However, this will make the speed requirements of the circuit much more constrained. Moreover, the choice of the intermediate frequency could be more carefully chosen in such a way to reduce the complexity of the DSP. We have learned how to design an impedance measurement system and select the appropriate components necessary to build such a system. We also gained knowledge of modeling second order effects in Simulink. In addition, we learned how to scale voltage swing at each stage, making use of the full-scale voltage to achieve highest accuracy.