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4

Hybridization of CMOS and SET


4.1 Motivation for CMOS-SET Hybridization
From the discussions of the last three chapters, we can observe that the SET has attracted attention as a candidate for future VLSI mainly due to its three virtues: nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics. In spite of such interesting properties, the practical implementation of the SET is questionable because of its low current drive and lack of mature room temperature operable technology. A comparison between the advantages and limitations of CMOS and SET technologies is presented in Table 4.1. From this table it can be inferred that, despite its attractive features, it would be very difficult for SET (as well as for any new nanotechnology) to compete head to head with CMOSs large-scale infrastructure, proven design methodologies, and economic predictability. Even if a stable, unified technology for SET fabrication is available in the near future, the digital applications of SET are not appealing due to its nano-Ampere current drive capability and lack of adapted interconnects. However, Table 4.1 also suggests that CMOS and SET are rather complementary. SET advocates low power consumption and new functionality (related to the Coulomb blockade oscillations), while CMOS has advantages such as high-speed driving and voltage gain that can compensate for the intrinsic drawbacks of SET. Therefore, although a complete replacement of CMOS by single electronics is unlikely in the near future, it is also true that by combining SET and CMOS, we can bring out new functionalities, which are unmirrored in pure CMOS technology. Such a cointegration approach also smoothes out the abrupt change of technology from CMOS to SET [1, 2].

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Table 4.1 Comparison Between Advantages and Limitations of SET and CMOS Technologies SET Advantages Nanoscale feature size Unique Coulomb blockade oscillation characteristics Ultralow power dissipation Limitations Low current drive Lack of room temperature operable technology Background charge effect CMOS High gain and current drive High speed Very matured fabrication technology Sub-10-nm physical limits Power density

The concept of hybrid CMOS-SET architectures has already captivated much consideration both in industry and academia. Toshiba has recently demonstrated the performance of a hybrid MOS-SET inverter (see Figure 4.1) on a SOI wafer [3, 4]. Although this architecture improves the gain at the logic transition region of a normal SET inverter, the current drive is still very low. In fact, it is very difficult to improve all the limitations of SET logic (e.g., gain, current

1.44V

Gate voltage of SET (V) 2.0 1.8 1.6 (a) 1.4 1.2 Output of SET-pMOS circuit (V) 0.045 (b) 0.040 0.035 Output of CMOS inverter (V) Inital 0.75 (c) 0.70 0.65 0.60 0 20

T = 300K

Initial (converter)

After writing (inverter) After writing

SET-pMOS inverter

CMOS inverter

40 60 Time (s)

80

100

Figure 4.1 Schematic of the hybrid inverter proposed by Uchida et al. [3, 4] and its measured characteristics at room temperature. It is worth noting that the SET used here is the programmable one, as explained in the previous chapter. The CMOS inverter is used to amplify the current drive and output voltage level of the hybrid inverter. (Reproduced with permission from [4]. 2003 IEEE.)

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drive, output voltage range) by introducing hybrid architectures. However, in order to optimize the total die area and power dissipation of a digital system, we may design specific modules with SET logic, which does not require high-speed operation. To a certain extent, the analog applications of the pure SET and hybrid CMOS-SET circuits appear more compelling. The unique periodic Coulomb blockade oscillation feature of the SET can be exploited to engender several novel analog functionalities, which are very difficult to realize in a pure CMOS approach. For example, the single-electron random number generator demonstrated by Toshiba (see Table 4.2) consists of only a single SET and a MOS current source. However the same circuit demands a noise source, an amplifier and a comparator for pure CMOS technology implementation. We will see later that the CMOS-SET hybrid circuit has a wide spectrum of applications, especially in neural network and multiple valued (MV) logic systems. In this chapter we will first talk about different issues of CMOS-SET hybridization. After that, we will discuss a CAD framework for CMOS-SET cosimulation. This chapter will be concluded with the case studies of different hybrid CMOS-SET architectures, along with a recently reported SETMOS device. It should be noted that here the term CMOS conveys the CMOS technology, not the circuit (i.e., both the n-MOS and p-MOS may not be present in a hybrid architecture with SET).

4.2 Challenges for CMOS-SET Hybridization


Although the concept of CMOS-SET hybridization is quite fascinating, the following challenges should be taken into consideration for its realization.
Table 4.2 Comparison Between CMOS and SET Random Number Generators (RNG) Schematic Noise source Noise (VRMS) Size Operating temperature SET RNG Single-electron capture/emission ~0.1V On chip (ultrasmall, ultralow-power dissipation) CMOS RNG Thermal/shot noise ~1 V On board (10100 cm2)

Room temperature operation Room temperature operation (randomness increases with increasing temperature)

Adapted by the authors with permission from [5]. 2002 IEEE.

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Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

4.2.1

CAD Framework for CMOS-SET Cosimulation and Codesign

We have discussed before that the CAD and simulation of electron devices and circuits (using tools like SPICE) are key factors contributing to the success of the CMOS technology. Therefore, a successful implementation of the SET as a candidate for hybrid CMOS-nano VLSI also demands accurate modeling and simulation of CMOS-SET devices and circuits. Hence, a suitable simulation framework for exploration of hybrid CMOS-SET circuit architectures is highly desirable. Some works have addressed the hybrid SET-CMOS simulation based on background MC or ME simulation of SET devices combined with conventional analytical models based on SPICE simulation for MOSFETs [6]. However, the major disadvantages of these approaches are time-consuming computation (especially for the calculation of transient response, current sources, and resistances) and concrete limitations for more complex circuits. Apart from the MC and ME methods, the macromodeling technique [7] has also been employed to simulate SET devices and circuits. Although this technique is SPICE compatible and useful for cosimulation with MOSFET, its nonphysical (or empirical) nature makes it an inconvenient tool for practical SET-CMOS hybrid IC design. In this chapter, we introduce a new CAD framework for cosimulation of hybrid CMOS-SET circuits. This new CAD framework is developed by implementing the MIB model by the analog hardware description language (AHDL) in a professional circuit simulator.
4.2.2 Design Rules for Hybrid CMOS-SET Circuit Design

We have to understand that the characteristics of SET are quite different from MOSFET, and hence the analog CMOS architectures cannot be mimicked in SET or hybrid CMOS-SET circuits. Moreover, the drain current in a SET is much lower, and SET is operated under much smaller drain voltages (V DS <1.5e/C ) than MOSFET devices. Therefore, some design rules should be obeyed for practical hybrid CMOS-SET circuit design. Some examples of such design rules are listed later. Figure 4.2 demonstrates the relationship between the bias current and the output voltage (VDS) of a constant current biased SET. As the bias current increases, (a) VDS,MAX increases, (b) the dynamic range of the VDS variation decreases, and (c) influence of the temperature on the output voltage decreases. Therefore, for analog SET/ hybrid CMOS-SET IC design, in order to optimize the tradeoff between the VDS,MAX and the dynamic range of the VDS variation, the bias current should be less than 0.5IBIAS /{e/4CRT )}. Some architectures commonly used in CMOS technology might be prohibited in SET circuits. One such example is the CMOS differential pair amplifier architecture, as shown Figure 4.3(a). A similar SET prototypesee Figure 4.3(b)may create instability in the circuit (and convergence problems in

Hybridization of CMOS and SET


3.5 3.0 10 8 = 20 2.0 4 1.5 1.0 0.5 0.1 = 20 1 IBIAS /{e/(4CRT)} = 40 2 0 6

87

VDS, MAX /(e/C)

Figure 4.2 Effect of the bias current (IBIAS) on the current-based SET, where the symbols denote the MC simulation and solid line represents the MIB model simulation and = (e 2 /C )/kB T .

ID IBIAS

VDS, MAX /VDS, MIN


MOSFET

2.5

IBIAS
(a)

VGS

ID IBIAS
SET

IBIAS
(b)

VGS

Figure 4.3 (a) MOSFET differential pair amplifier and the corresponding single operating/ stability point. (b) SET differential pair amplifier and the corresponding multiple operating/stability points (represented by the circles).

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simulation) as the periodic ID -VGS characteristics of a SET offer several possible values of VGS for a certain value of IBIAS. However, this multiple-stability-points property of SET circuits can be exploited for other applications (e.g., MV logic systems, which will be explained in the next chapter). The operating temperature should be chosen carefully, as in the present available technology the SETs are operated at a much lower temperature than CMOS. A subambient temperature (150C to 50C) operation appears to be a possible compromise, as SET could be operated in this temperature regime with some realistic device parameters, and MOSFET also exhibits superior performance in terms of leakage power and subthreshold slope in subambient temperature. We will again discuss the subambient operation of hybrid circuits later in this chapter.
4.2.3 Technology for CMOS-SET Cofabrication

Availability of a stable technology for CMOS-SET cofabrication is probably the biggest challenge for the realization of the CMOS-SET hybridization concept. Although SET can be also fabricated by using metals and III-V materials, for its hybridization with CMOS, a silicon-based CMOS-compatible fabrication process is most demanding. Some CMOS-compatible SET fabrication technologies have already been reported by Toshiba, Inc. [4] and NTT research laboratory [8, 9]. We will discuss more in detail about CMOS-SET cofabrication in Chapter 6.

4.3 CMOS-SET Cosimulation and Codesign


4.3.1 Verilog-A Language

The Verilog-A hardware description language (HDL) is a behavioral language for analog and mixed signal systems. It is derived from the IEEE 1364 Verilog HDL specification. Compiled or interpreted Verilog-A language combined with SmartSpice (a circuit simulator developed by Silvaco International [10]) provides designers with an easy-to-use, comprehensive environment for the design and verification of complex analog and mixed-signal circuits. It provides an executable specification for design integrity and powerful optimization capabilities for achieving those specificationson schedule. One of the key features of Verilog-A is that it enables compact model engineers to easily develop proprietary models for specific semiconductor device behavior (e.g., Coulomb blockade oscillations). Like the digital Verilog systems, the basic component of a Verilog-A analog system is a module. The module defines the behavior of an analog component but also allows a structural description of a system. The Smartspice

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Verilog-A simulation flow is demonstrated in Figure 4.4. The main stages of the simulation flow are:

Verilog-A SET module

SPICE netlist SOURCE

VerilogA compiler

C file RUN C-compiler

.so file

SMARTSPICE

(a)

VerilogA SET module module set (drain, gate1, gate2, source); inout drain, gate1, gate2, source; electrical drain, gate1, gate2, source; // Default value of the model parameters parameter real CTS = 1e-18, CTD = 1e-18 parameter real CG = 2e-18, CG2 = 0; parameter real RTD = 1e6, RTS = 1e6; parameter real XI = 0; analog begin ::::::::::::::::::::::::::::::MIB Subroutine I(drain, source) = . end endmodule

Standard SPICE netlist .verilog "set.va" // Includes the SET module M1 2 2 4 4 MOD1 L = 0.5U W = 0.8U M2 3 2 4 4 MOD1 L = 0.5U W = 0.8U ::::::::::::::::::::::::::::::::: VDD 1 0 4.635 VSS 4 0 5 ::::::::::::::::::::::::::::::::: YVLGmyset 1 3 6 7 0 set CG 1=2e-18 // Instantiate SET ::::::::::::::::::::::::::::::::::: .dc VIN 0.00 0.04 0.0008 .end

(b)

Figure 4.4 (a) Simulation flow in Verilog-A Smartspice environment; (b) Verilog-A SET module and typical SPICE netlist.

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Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

A compilation phase: During the sourcing of a Smartspice netlist,

Verilog-A files referred by the .verilog command cards are compiled by the Verilog-A SILVACO compiler. As the result of the compilation, a C file is produced for each module parsed.
A linkage phase: The generated C files are then automatically parsed by

the SILVACO C interpreter and transformed into an optimized pseudocode that will be executed during the simulation. If the C files are compiled by gcc or the native C compiler, a dynamically linkable library (a .so file) is produced. This library is then linked to the Smartspice executable.
A simulation phase: Once all Verilog-A modules have been incorpo-

rated, the simulation in Smartspice is done as usual. The compilation and the linkage are in fact transparent to the user. Simulating a netlist with Verilog-A modules is still done the same way with a traditional netlist: first the netlist is sourced, then a simulation is run, and the results are output. Though the Verilog-A approach allows quick validation of advanced models and their portability to many simulators, the final implementation should be in C code for efficiency and speed optimization.
4.3.2 Implementation of MIB Model in Smartspice

The MIB model is implemented in Smartspice through its Verilog-A interface, which essentially embeds the SET model as a separate module in the circuit simulator without actually having to rigorously solve the SET characteristic equations along with other nonlinear elements in the hybrid circuit [11, 12]. As shown in Figure 4.4, a module for SET is first created with four ports (two gates, one drain, and one source). Inside the module, the drain current is calculated by the MIB model, which assigns it as a current from the drain port to the source portFigure 4.4(b). We can now instantiate this SET model in a traditional SPICE netlist in order to cosimulate the MIB model, along with other MOSFET device models (e.g., BSIM [13] and EKV [14]). In fact it is also possible to use different levels of the MIB model (i.e., analog model and digital model) for different types of circuit simulation, as is done for BSIM models.

4.4 Case Studies of Different Hybrid CMOS-SET Architectures


In this section, we will discuss some interesting CMOS-SET hybrid architectures and analyze their characteristics by the MIB-Smartspice simulator.

Hybridization of CMOS and SET 4.4.1 Neural Network

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Neural networks are very sophisticated nonlinear modeling techniques capable of modeling extremely complex functions. They also keep in check the curse of dimensionality problem that bedevils attempts to model nonlinear functions with large numbers of variables [15, 16]. Neural networks grew out of research in artificial intelligencespecifically, attempts to mimic the fault tolerance and capacity to learn of biological neural systems by modeling the low-level structure of the brain. The brain is principally composed of a very large number (circa 1010) of neurons, massively interconnected (with an average of several thousand interconnects per neuron, although this varies enormously). Each neuron is a specialized cell, which can propagate an electrochemical signal. The neuron has a branching input structure (the dendrites), a cell body, and a branching output structure (the axon). The axons of one cell connect to the dendrites of another via a synapse. When a neuron is activated, it fires an electrochemical signal along the axon. This signal crosses the synapses to other neurons, which may in turn fire. A neuron fires only if the total signal received at the cell body from the dendrites exceeds a certain level (the firing threshold). Thus, from a very large number of extremely simple processing units (each performing a weighted sum of its inputs and then firing a binary signal if the total input exceeds a certain level), the brain manages to perform extremely complex tasks. Of course, there is a great deal of complexity in the brain that has not been discussed here, but it is interesting that artificial neural networks can achieve some remarkable results using a model not much more complex than this. Neural networks are applicable in virtually every situation in which a relationship between the predictor variables (independent inputs) and predicted variables (dependent outputs) exists, even when that relationship is very complex and difficult to articulate in the usual terms of correlations or differences between groups. A few representative examples of problems to which neural network analysis has been applied successfully are:
Detection of medical phenomena; Stock market prediction; Credit assignment in banking; Monitoring of the condition of machinery; Engine management.

The model of an artificial neuron is shown in Figure 4.5. The neuron can be divided into three parts: (a) input (dendrites), (b) summation and activation function blocks (cell body), and (c) output (axon). Since a powerful signal

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Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

Nucleus Cell body

Dendrites

VIN1 VIN2 VINk

Figure 4.5 (a) Schematic of a neuron cell and (b) its electrical model.

processor demands a large number of neurons, due to the power dissipation and size of the neural chip, it is difficult to design an efficient neural network by CMOS technology. However, we can exploit the ultralow power dissipation and nano feature size of SET devices to realize a compact neural device. A SET-based neural network scheme (composed of two cascaded currentbiased SETs), as proposed by Goossens [17], is depicted in Figure 4.6(a). For the proper operation of the circuit, the drain and source tunnel capacitances of the SETs have to be equal (CTD = CTS), and the gate capacitances have to be twice that of (CG = CG2 = 2CTD). It is worth noting that in order to drive currents on the order of nanoamperes through the SET, we have to bias the MOS transistors in a subthreshold (weak inversion) region. Using Smartspice, the static characteristics of the activation function of the neuron cell have been simulated accurately and good agreement with MC simulation is observedsee Figure 4.6(b). For MC simulation, the pMOSFET current sources have been replaced with ideal current sources. It should be noted that the digital MIB model (which is limited to V DS < e /C ) shows discrepancies with its analog counterpart in some regions of the neuron characteristics. The spice netlist for the simulation of neuron cell is available in Eldo\set_ neuron.cir file and in Smartspice\set_neurone.in file in the associated CD-ROM.

n De dr ite s
(a) Activation function Adder Axon

VOUT V
Axon Cell body (b)

Hybridization of CMOS and SET

93

(a)

(b)
Figure 4.6 (a) Schematic and (b) characteristics of the activation function of the neuron cell (with CG = CG2 = 0.04 aF, CTD = CTS = 0.02 aF, RTD = RTS = 1 M) as predicted by SIMON (symbol) and Smartspice (solid and dotted lines). It should be noted that IBIAS is taken to be 50 nA for SIMON simulation, and for Smartspice simulation the MOS current source is designed in such a way that it can drive the same bias current through the SET. Here the pMOSFET parameters are L = 0.5 m, W = 0.8 m, tOX = 9.74 nm, VTH (MOSFET threshold voltage) = 0.55V, and the EKV MOSFET model is used. The dotted line represents the MIB model without the VDS > e/C extension.

4.4.2

NDR and Hysteresis Architecture

A negative differential resistance (NDR) is a resourceful element with a wide variety of circuit applications, such as oscillators, amplifiers, logic cells, and memory. One of the first single-electron device-based NDR circuits, proposed by Heij et al. [18], is founded on a single-electron box (SEB), which is

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Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

capacitively coupled to a SETsee Figure 2.4(c). With the increase of input voltage, when the SEB becomes able to trap an electron, it drives the SET into a Coulomb blockade state that results in a sudden decrease of the current through the circuit (NDR characteristics). Here we introduce another SET-based NDR architecture, which, instead of using the electron trapping mechanism, uses the typical oscillations in ID -VGS characteristics [19, 20]. The architecture of the NDR device, which is composed of two crossconnected SETs (T1 and T 2) and one current source (CMOS mirror), is depicted in Figure 4.7(a). As explained in Figure 4.7(b), the bias current source and the first SET (T1) create a feedback loop that helps to decrease the gate-to-source voltage (VGS) of the second SET (T 2) for a certain range of increasing input voltage (VIN), and that follows a decrease in the drain current (or the input current, IIN) of T 2see the qualitative evolution of operating points on T 1 and T 2 characteristics as depicted in Figure 4.7(b). As a result, NDR characteristics are obtained. This architecture requires CG > CT for T 1, in order to achieve its inverting gain greater than unitysee (2.31)as it is the primary condition for obtaining the NDR effect. If the T 2 transistor is biased with a current sourcesee Figure 4.8(a) the inherited NDR property can be exploited in order to obtain hysteresis characteristics. If we vary the input current (IIN) from zero to any positive higher value, VIN becomes a hysteretic function of IIN, as explained in Figure 4.8(b). Such a current biased cross-connected SET architecture could be a commendable candidate for a highly dense capacitorless static random access memory (SRAM) application. Figure 4.9(a) shows the characteristics of the NDR device for different values of the bias current, and Figure 4.9(b) exhibits the complementary hysteresis characteristics. (Please note how the NDR and hysteresis behavior get modulated for different bias currents). Such a tunable hysteresis loop device can find applications as a Schmitt Trigger for a noise eliminating comparator (to restore signal integrity), where there is always a tradeoff between the width of the hysteresis loop and the speed of the operation. Another application for such an architecture could be a clock generator with variable frequency or pulse width. Please note that Figure 4.9(a) also shows the discrepancies between analog and digital MIB models for certain regions of the NDR characteristics. Figures 4.10(a) and (b) demonstrate the effects of temperature variation on the NDR and the hysteresis behavior of the proposed architecture. As temperature increases, the SET subthreshold slope increases, and consequently the NDR and hysteresis characteristics deteriorate. Figures 4.11(a) and (b) show the background charge effects on the NDR and the hysteresis behavior, which is quite complex, as the background charge changes the characteristics of both devices.

Hybridization of CMOS and SET

95

VDS1

(1)

I D1

IBIAS

VIN IBIAS IIN VGS1 = VIN

I D1
T1

I D2
T2

VDS1 = VGS2

(2)

VIN = VGS1 VDS2 = VIN

VDS1

VGS1

VGS2

VDS2

ID2

(3)

VGS2 = VDS1
(4)

IIN

VIN
(a) (b)

Figure 4.7 (a) Schematic and (b) operating principles of SET-based NDR device where IBIAS is a MOSFET current mirror.

The spice netlist for the simulation of the NDR cell is available in the Eldo\set_ndr.cir and Eldo\set_hysteresis.cir files and in the Smartspice\ set_ndr.in and Smartspice\set_hysteresis.in files in the associated CD-ROM.
4.4.3 Multiple Value Logic Circuit

Multiple valued logic (MVL) is defined as a nonbinary logic and involves switching between more than two states. MVL has potential advantages over binary logic with respect to the number of elements per function and operating speed. Furthermore, MV data storage would require less physical space than binary data [21, 22]. Most MVL circuits, fabricated with MOS and bipolar devices, have limited success partially because the devices are inherently single

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Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

IBIAS

IIN VIN

T1

T2

(a)

VIN IIN

VIN
(b)

IIN

Figure 4.8 (a) Schematic and (b) operating principles of a SET-based hysteresis device.

threshold or single peak and are thus not fully suited for MVL. Inokawa et al. [8, 23] have recently proposed a hybrid CMOS-SET MVL circuit for practical applications (e.g., quantizer for digital communication systems). Figure 4.12 shows the schematic of a hybrid CMOS-SET universal literal gate that acts as a MVL building block. The simulated Vin-Vout characteristics of this circuit are depicted in Figure 4.12, which demonstrates good agreement with the measured data. Figure 4.13 exhibits the application of such architecture as a quantizer in a digital communication system. The origin of the rectangular waveforms and MVL applications of SET devices will be discussed in more detail in Chapter 5. The spice netlist for the simulation of NTTs universal literal gate is available in the Eldo\hybrid_universal_literal_gate.cir file and in the Smartspice\ hybrid_universal_literal_gate.in file in the associated CD-ROM.

4.4.4

Hybrid Digital-to-Analog and Analog-to-Digital Converters

Ou and Wu [24] have proposed an alternative circuit for a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC) based on the hybrid architecture introduced by the NTT laboratory (Figure 4.12).

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60

T = 150C
50

Input current, IIN (nA)

50 nA 40 40 nA 30 20 10 30 nA 20 nA

IBIAS = 10 nA
0 0.00 0.10 0.20 Input voltage, VIN (V) (a) 0.40 40 nA 0.35 30 nA 20 nA 50 nA 0.30 0.40

Input voltage, VIN (V)

IBIAS = 0.30 10 nA
0.25 0.20 0.15

T = 150C
0.10 0 10 20 30 40 50 60 Input current, IIN (nA) (b)

Figure 4.9 (a) Characteristics of the SET NDR architecture (with CG = 0.2 aF, CT = 0.15 aF, RT = 1 M) for different values of the bias current (IBIAS), as predicted by SIMON (symbol) and Smartspice (solid and dotted lines). The dotted line represents the MIB model without the VDS > e/C extension. (b) Corresponding hysteresis behavior. Here both SET transistors are identical to each other.

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Hybrid CMOS Single-Electron-Transistor Device and Circuit Design


40 35

IBIAS = 20 nA
200C T= 150C 100C

Input current, IIN (nA)

30 25 20 15 10 5 0 0.00 0.05

0.10

0.15 0.20 0.25 Input voltage, VIN (V) (a)

0.30

0.35

0.35 0.30

Input voltage, IN (V)

100C 0.25 150C 0.20 0.15 0.10

T = 200C

IBIAS = 20 nA
0.05 5 10 15 20 (b) 25 30 35 Input current, IIN (nA)

Figure 4.10 Effect of the temperature on (a) NDR and (b) hysteresis characteristics as predicted by Smartspice.

Figure 4.14(a) shows the schematic of the n-bit hybrid ADC circuit. It consists of a sampling and hold circuit block, a signal divider circuit block, and an ADC unit block. The analog input signal is applied first to the sampling and hold circuit and then is divided by the capacitor divider into n signals, whose amplitudes are weighted by the ratio factors 1/2i (i = 0, 1, 2,, n1). Finally, the n analog signals are converted into the n-bit digital signal D0, D1, D2,,

Hybridization of CMOS and SET


50 T =150C, IBIAS = 20 nA 40

99

Input current, IIN (nA)

0.3e 30 0.2e 0.1e 0e

20

10

0.1e

0 0.00

0.05

0.10

0.15 0.20 0.25 Input voltage VIN (V) (a)

0.30

0.35

0.35

T =150C, IBIAS = 20 nA
0.30 0e 0.2e 0.25 0.20 0.15 0.10 0.05 10 15 20 Input current, IIN (nA) (b) 25 30 0.3e 0.1e 0.1e

Figure 4.11 Effect of the background charge on (a) NDR and (b) hysteresis characteristics as predicted by Smartspice.

Dn-2Dn-1 by the n ADC circuit units. The sampling and holding circuit block consists of a MOS switch transistor and a capacitor. The signal divider block consists of a capacitor net, which produces discrete analog signals with weight coefficients 1/2i. The SET consists of two gates: input gate IN and phase control gate PG. The discrete input analog signal Vin(t)/2i is applied to the input gate.

Input voltage, ViN (V)

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Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

Experimental 5 4 3 2 1 0

Vout VGG

Vout (V)

Vin(V)
6 5 4 3 2 1 0 1 2 Simulation

Vout (V)

Vin

3 Vin(V)

Figure 4.12 Schematic of the universal literal gate comprising a SET and a MOSFET, and a comparison between measured and simulated VinVout characteristics of the universal literal gate at T = 27K. The SET device parameters are CG = 0.27 aF, CTD = CTS = 2.7 aF, RD = RS = 200 k, and MOS device parameters are W = 12 m, L = 14 m, tox = 90 nm, VTH = 0.64V. VGG is set to 1.08V, and Vout is hard-limited at 5V. EKV model is used to simulate the MOS device at the same temperature. (Measured characteristics are reproduced with permission from [8]. 2003 IEEE.)

The drain-source current of the SET depends on the input voltage Vin(t)/2i and exhibits the periodic oscillation output characteristic for a linearly increasing input signal (similar to Figure 4.12). A bias voltage VPG is applied to the phase control gate PG of the SET to control the phase of the periodic oscillation output voltage Vout. The phase control gate PG and control voltage VPG possess two important functions: one is to align the phases of the output signals of the n-ADC units so that the ADC circuit can operate correctly, and the other is to cancel the background charge effects on the ADC characteristics. The simulated behavior of the hybrid ADC is shown in Figure 4.14(b). Comparing with the conventional ADC circuit, the architecture of the ADC circuit is simple. It does not need comparators, latches, and ramp generators. The number of devices in the hybrid ADC circuit is proportional to the resolution n of the ADC circuit and is much less than that of the conventional ADC circuit with the resolution n, which is proportional to n2. The schematic of a hybrid DAC circuit and its simulated characteristics are depicted in Figure 4.15. It consists of an input capacitance array and an

Hybridization of CMOS and SET

101

(a)

(b)

Figure 4.13 (a) Measurement setup for the quantizer application. The central SET and MOSFET are on the same wafer. The external MOSFET1 is a transfer gate, and MOSFET2 is used as an FET probe to measure the Vout sustained by a small current (~nA). (b) Quantizer operation measured by the setup in (a), with Vgg of 1.08V and a CC load of 4.5 nA. Operation speed is not limited by the intrinsic performance of the device but by the large stray capacitance of 370 pF at Vout. (Reproduced with permission from [8]. 2003 IEEE.)

output circuit. The capacitors with values 20C, 21C, , 2n-2C and 2n-1C in the array are used as input capacitors, respectively. The n-bit digital signal D0D1D2Dn-2Dn-1 is applied to the input capacitors directly. The capacitance array performs multiply-accumulate operations of the input signals and the capacitances. Then, the output of the capacitance array is applied to the input of the output circuit. The structure of the output circuit is the same as the ADC unit circuit. However, the SET input gate and the drain of the NMOS are

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Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

Sample/hold CLK

Divider

ADC units Vdd


Current source NMOS

Vin CH Vin(t)/2
0

Vg CIN Vdd CPG VPG

D1

2C

C Vin(t)/2
1

Vg CIN CPG VPG

D1

2C

Single electron tunneling junction

Vdd
2C C

Vg CIN
(a)

Dn1 CPG VPG

Vin(t)/2

n1

Input voltage (V)

3.0 2.5 (a) 2.0 4 2 (b)

T = 300K

D0

Digital output (V)

0 4 2 0 4 2 0 2.0 (d) 2.2 2.6 2.4 Input voltage (V) 2.8 (c)

D1

D2
3.0

(b)

Figure 4.14 (a) Schematic of hybrid DAC, and (b) its simulated characteristics. (Reproduced with permission from [24]. 2005 IEEE.)

shorted in the output circuit. The drain current Ids of the SET oscillates periodically with the input voltage signal at the input gate. If the output current value of the current source is set between the maximum value and the minimum value

Hybridization of CMOS and SET


Vdd
Current source NMOS

103

Vg CPG D0 D1
2n1C
2C

Vout VPG

CIN
Single electron tunneling junction Output circuit

Dn1 VH

CH

Input capacitance array

(a)
5

Digital output (V)

D0
0 5 (a)

D1
Analog output (V)
0 3.0 (b)

T = 300K 2.5 VH = 2.5V, CH = 12C


(c) 2.0 0.0 2.0 107 4.0 107 6.0 107 8.0 107 1.0 106 Time(s)

(b)

Figure 4.15 (a) Schematic of a hybrid ADC and (b) its simulated characteristics. (Reproduced with permission from [24]. 2005 IEEE.)

of the oscillation current Ids of the SET, some stable output voltages Vout of the output circuit can be obtained when we change the n-bit input digital signal D0D1D2Dn-2Dn-1 from 000 00 to 111 11. The stable output voltage Vout is used as the analog output signal of the hybrid DAC circuit.
4.4.5 Selective Multiband Voltage Filter

Combining the NTTs MVL building block (Figure 4.12) with the SETMOS NDR architecture (to be discussed in the next section), Song et al. [25] have proposed and experimentally demonstrated the functionality of a novel CMOS-SET hybrid multiband voltage filter circuit. The schematic and the

104

Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

working principle of the circuit are depicted in Figure 4.16(a). The Vmod versus Vin characteristics are the usual periodic rectangular-shaped waveforms, as demonstrated before in Figure 4.12. When Vmod is high, it turns on the MOSFET and lets the input voltage (Vin) be available at the output (Vout), as explained in Figure 4.16(b). By applying proper voltage to the second SET gate (Vp), we can change the phase of the Vout-Vin oscillation. In this way, the circuit behaves as a selective multiband voltage filter. Experimentally measured behavior of the circuit is shown in Figure 4.17.
4.4.6 Automatic Oscillation PhaseControlled SET

Another interesting hybrid architecture proposed by NTT Research Lab is the automatic Coulomb blockade oscillation phasecontrolled SET [9]. The control of the oscillation phase in SET is required mainly because of the random background charge variation. Figure 4.18(a) indicates the equivalent circuit of the hybrid phasecontrolled SET architecture. An input signal is applied to the

Ibias Vgg Vmod

Vout

Vin

Vp

(a)

Output voltage, Vout (V)

1.6 1.4 1.2 1.0 0.8 0.0 0.0

Vout Vmod

0.8 1.0 1.2 1.4 1.6 Input voltage, Vin (V) (b)

Figure 4.16 (a) Schematic and (b) working principle of CMOS-SET hybrid multiband voltage filter. (Reproduced with permission from [25]. 2005 IEEE.)

Hybridization of CMOS and SET


Vin Vmod

105

1.6 1.4

Voltage (V)

1.2 1.0 0.8 0.2 0.0 0 10 20 30 Time (sec) (a) 40

1.6 1.4

Vin

Vout

Voltage (V)

1.2 1.0 0.8 0.2 0.0 0 10 20 30 Time (sec) (b) 40

Figure 4.17 Time domain multiband blocking operation of the multiband filter: (a) Vin-Vmod and (b) Vin-Vout characteristics. Blocking bands are represented at the voltage domain, y axis, which corresponds to the high-level region of Vmod. (Reproduced with permission from [25]. 2005 IEEE.)

gate of the SET, and an output signal is obtained from the load device connected to the SET in series. The SET also has a memory node (MN) capacitively coupled to the SET island, which is used for controlling the phase shift. The MN is also connected to a MOSFET (MN-FET), and we can change the number of charges in the MN by closing and opening the gate of the MN-FET and by changing its source voltage (VMN). For feedback, Vout is connected to the control gate (CG) of the MN-FET. This connection allows the number of charges in the MN to vary according to Vout, and this variation continues until Vout becomes a certain value, at which the gate of the MN-FET closes. The operating principle and the band diagram of the SET-MN-FET system is explained in Figure 4.18. When the gate of the MOS is connected to Vcg0 , one can charge the MN by properly tuning the VMN voltagesee Figures 4.18(b) to (d). When the feedback is performed (gate of the FET is connected to the Vout), it makes the Vout independent fromVinsee Figures 4.18(e) to (g).

106

Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

Figure 4.18 (a) Equivalent Boolean logic circuit of the SET combined with an MN-FET. The CG is switched to the output terminal during feedback operation. (b)(f) Sequences for stocking electrons in the MN-FET. Figures indicate the band diagram in the MN-FET and the SET island. (g) Phase change of the output signal of the proposed device during the feedback process. (Reproduced with permission from [9]. 2004 IEEE.)

Such phase controlled hybrid architecture can be used for Boolean logic operation, whose function can be programmed electrically. Figure 4.19 shows the operation of such an architecture as a NOR gate. This SET-MN-FET architecture can be used for other applications such as a pass-transistor logic or multiplevalued logic.

4.5 SETMOSCoulomb Blockade Oscillations in the Microampere Range


We have seen that the most exciting analog feature of a SET device is its unique Coulomb blockade oscillation characteristics. However, at the same time, we

Hybridization of CMOS and SET

107

Figure 4.19 (a) Flow of the measurement for the automatic phase-controlled SET-MN-FET architecture. (b) Input Vg (Vin) output Vout characteristics of the circuit shown in Figure 4.18. The measurement temperature was 25K. The combined SET-MOSFET circuit was used. The dashed-dotted line is shifted vertically by 1V. Curves after the feedback indicate characteristics when Vin of VF 1,2,3, 1.17V, 1.25V, and 1.4V, respectively, was applied, during the feedback. (c) A multifunctional logic composed of two SETs. A shaded and a white box represent the SETs serving as a Boolean inverter and as a noninverting buffer, respectively. (d) Experimental transient waveforms of input and output. The inverter can be changed to the noninverting buffer by shifting the phase of Coulomb oscillation by . (Reproduced with permission from [9]. 2004 IEEE.)

have also seen that the low current drive is the major limitation of the SET technology. SETMOS is a hybrid CMOS-SET architecture that amalgamates the virtues of both SET and CMOS devices, in order to offer SET-like Coulomb blockade oscillations with a much higher current driving ability than traditional SETs. Moreover SETMOS exhibits a unique quasi-periodic NDR behavior, which could be extremely valuable for MV SRAM design.

108

Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

4.5.1

Architecture and Working Principle of SETMOS

The architecture and circuit symbol hybrid SETMOS cell is depicted in Figure 4.20. The SET is biased by a constant current source, with its drain connected to the MOSFET gate, and the drain terminal of the MOSFET serves the output of the device. The working principle of SETMOS is demonstrated in Figure 4.21. As explained earlier, the output of the current biased SET (VDS1) is a periodic (period = e/CG) function of input gate voltage (VGS), which extends the Coulomb blockade oscillations in the drain current of the MOSFET such that output of more than a few of As can be achieved. It is worth noting that the MOSFET is operated in the subthreshold region (weak inversion) in order to obtain effective
Drain (D)

IBIAS I D1
Gate

I D2 G VGS2 VDS1
Source

IBIAS

D ID

VGS 1

S
Symbol

VDS 2

Figure 4.20 Architecture and symbol of the three-terminal SETMOS cell.

VDS1,MAX e/CG
VDS1
~e/C

VGS

Log10 ID2

Exponentially amplified drain current

VTH
Figure 4.21 Working principle of SETMOS cell.

VGS2

Hybridization of CMOS and SET

109

Coulomb blockade (high sensitivity of current characteristics when VGS varies by only tens of mV ) and low power dissipation. Thus, in SETMOS, the output drain current exponentially amplifies the oscillations of the drain voltage of the constant currentbiased SET[ID exp(VG2/VT) = exp (VDS1/ VT), where is the subthreshold slope factorand the amount of current amplification also depends on the MOSFET aspect ratio. We could also observe that because of the exponential behavior (diodelike operation), the peaks and the valleys of oscillating VGS2(=VDS1) are not equally amplified. We can therefore understand that the maximum value of VDS1 (VDS1,MAX) should be close to the threshold voltage (VTH) of the MOSFET in order to obtain Coulomb blockade oscillations on the order of microamperes. As VDS1,MAX e/C , therefore such a condition can be satisfied by proper tuning of C and VTH. However, if C and VTH are already defined by the fabrication technology, one can tune the bias current to control VDS1,MAX or can use different alternative architectures (see Figure 4.22) for SETMOS in order to meet the VDS1,MAX VTH criterion.
4.5.2 Device Parameters and Operating Temperature

As explained in Section 4.2, the operating temperature of a CMOS-SET architecture should be chosen in such a manner that both the MOS and SET devices could exhibit their full functionalities in that temperature regime. It is also known that the maximum operating temperature depends on the total island capacitance (C ) of the SET. In present technology, the single dot SET devices [23, 26, 27] can be operated up to a maximum temperature of around 70K

VBIAS

VBIAS
(a) (b) (c)

Figure 4.22 Alternative SETMOS architectures to meet the VDS1,MAX VTH criterion: (a) extra resistance (could be implemented by SET or MOSFET) so that VDS1,MAX + IBIASR VTH; (b) applying negative bias to the source of MOSFET so that VDS1,MAX VBIAS VTH; (c) tuning the VTH by substrate biasing.

110

Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

(157C), whereas room temperature operation has been demonstrated for multidot devices [3]. At the same time the subambient operation of MOSFET devices has attracted much attention [28, 29]. As the operating temperature of the CMOS moves from room temperature to the subambient regime, the mobility, static power dissipation, leakage current, and switching speed improve manifold. The improvement of the CMOS performance factor as a function of operating temperature is presented in Figure 4.23. The SETMOS is designed and simulated with SET having a C ~0.5 aF (which makes effective Coulomb blockade oscillations in 50C to 150C) and a 65-nm gate length MOSFET. Total island capacitance of 0.5 aF requires island diameter on the order of 12 nm, which appears to be quite feasible in the near future.
4.5.3 SETMOS Characteristics

The simulated ID-VGS and corresponding transconductance (gm) characteristics of the SETMOS in a subambient temperature regime are presented in Figure 4.24, which reveals SET-like periodic Coulomb blockade oscillation behavior.
2.5

Relative performance factor

L = 0.1 m Vdd = 1.5V


2.0 Same off-current Room temp.

1.5

Same threshold

Same hardware 1.0 200 150 100 50 0 50 Temperature (C) 100 150

Figure 4.23 Relative performance factors (with respect to the 100C value) of 1.5V CMOS circuits as a function of temperature. Threshold voltages are adjusted differently with temperature in each of the three scenarios shown. (Reproduced with permission from [9]. 1997 IEEE.)

Hybridization of CMOS and SET


9 8

111

IBIAS = 40 nA VDS (V) =


1.6 1.3 1.0 0.7 0.4 0.1

T = 100C

Drain current, ID (A)

7 6 5 4 3 2 1 0 1.0

e/CG

0.5 0.0 0.5 Gate-to-source voltage, VGS (V) (a)

1.0

40 30

Transconductance, gm (S)

20 10 0 10 20 30 40 50

VDS (V) = 1.6

0.1

T = 100C IBIAS = 40 nA 60 1.0 0.5 0.0 0.5 1.0 Gate-to-source voltage, VGS (V)
(b)

Figure 4.24 (a) ID-VGS and (b) gm-VGS characteristics of SETMOS as obtained by Smartspice simulation. The device parameters are CG = 0.2 aF, CT = 0.15 aF, RT = 1 M for SET, and L = 65 nm, W = 100 nm, tox = 1.7 nm, VTH = 0.32V for MOSFET. Here we have used BSIM parameters for 65-nm gate length MOSFET [13] for the CMOS-SET cosimulation.

Similar to the normal SET, the periodicity of the SETMOS is determined by the e/CG factor. The effect of MOSFET gate leakage current (IG) on the

112

Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

SETMOS performance is explained in Figure 4.25. IG increases with VDS, and at high VDS (greater than 1.5V) it becomes comparable with the bias current (IBIAS) of the SET. As a result, the equivalent bias current (IG + IBIAS) gets augmented, and hence VDS1 and ID get magnified. Therefore, at high VDS, the Coulomb blockade region in SETMOS characteristics shrinks down. The effect of SET bias current on SETMOS characteristics is presented in Figure 4.26(a). With the increase of IBIAS, VDS1 increases, which drives the MOSFET toward the strong inversion region. As a result, although the MOSFET drain current increases, the Coulomb blockade region (and hence the peak-to-valley ratio) reduces. It should be noted that the SET exhibits Coulomb blockade oscillations for both positive and negative values of VDS. However, the SETMOS does not, as negative values of VDS turn on the drain-to-substrate diode of the MOSFET. Figure 4.26(b) reveals the effect of temperature on the SETMOS behavior: as the temperature increases, the peak-to-valley ratio of the SETMOS characteristics drastically degrades. This is because with the increase of temperature, the VDS1,MAX decreases; however, the MOSFET threshold voltage decreases and the subthreshold current increases at a much faster rate (Figure 4.27) that eventually decreases the peak-to-valley ratio of the SETMOS characteristics. Note that the MOSFET model card [30] is calibrated at room temperature; however, the temperature dependence of each parameter is captured in BSIM4.0. Therefore, one can see that a small subthreshold slope is a demanding factor for obtaining acceptable Coulomb blockade (and high peak-to-valley ratio) in SETMOS characteristics. Nevertheless, we will see in the next chapter that oscillation in SETMOS drain current is much more important than effective Coulomb blockade for its applications in MV logic and memory. The spice netlist for the simulation of the SETMOS cell is available in the Eldo\setmos.cir file and in the Smartspice\ setmos.in file in the associated CD-ROM. The subthreshold slopes of the SETMOS, SET, and MOSFET are compared in Figure 4.28. Similar to the SET, the SETMOS has two subthreshold slopes due to the oscillating ID-VGS characteristics; one is positive, and the other is negative. However contrary to SET, their magnitudes are not equal. This is due to the fact that the inverting gain (CG /CT) of the current biased SET is greater than unity, while the noninverting gain is less than unity (CG /(CT + CG)). Consequently, the subthreshold slope of the SETMOS can be approximated as (CT /CG)SMOS and (CT + CG)SMOS /CG, where SMOS is the subthreshold slope for a MOSFET. Therefore the magnitude of the negative slope of a SETMOS having CG > CT is smaller than that of MOSFET (Figure 4.28). These asymmetric subthreshold slopes also make the negative transconductance of the SEMOS larger than its positive counterpartsee Figure 4.24(b).

Hybridization of CMOS and SET

113

IBIAS
VDS1

IG

IG > 0 IG = 0 VGS
(a)

18 16

IBIAS = 40 nA

MOSFET gate current, IG (nA)

14 12 10 8 6 4 2 0 1.0 1.0

T = 100C VDS (V) = 1.6

1.3 0.7

0.5 0.0 0.5 SETMOS Gate-to-source voltage, VGS (V) (b)

1.0

0.40

IBIAS = 40 nA
0.35

T = 100C VDS (V) = 1.6

0.30

VDS1 (V)

0.25

0.1

0.20

0.15 1.0

0.5

0.0

0.5

1.0

SETMOS Gate-to-source voltage, VGS (V) (c)

Figure 4.25 (a) Effect of MOSFET gate leakage on the drain-to-source voltage of the SET. (b) Simulated gate current characteristics of SETMOS cell and (c) corresponding SET drain-to-source voltage (VDS1) variation. Here all the device parameters are the same as in Figure 4.24.

114

Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

IBIAS = 100 nA
10
1

Drain current, ID (A)

10

101 10
2

10 nA

103 10
4

VDS = 1V

T = 100C 1.0

1.0

0.5 0.0 0.5 Gate-to-source voltage, VGS (V) (a)

101

IBIAS = 40 nA

Drain current, ID (A)

100

25C

10

10

T = 150C

VDS = 1V
0.0 0.2 0.4 0.6 0.8 Gate-to-source voltage, VGS (V) (b) 1.0

Figure 4.26 (a) Effect of bias current on SETMOS ID-VGS characteristics, and (b) influence of the operating temperature on SETMOS ID-VGS characteristics from subambient to room temperature. Both the characteristics are plotted in semilog scale. Here all the device parameters are the same as in Figure 4.24.

4.5.4

SETMOS NDR Architecture

By shortening the gate and the drain terminals of the SETMOS, we can use it as a unique quasi-periodic NDR device, as shown in Figure 4.29(a). According to the qualitative explanation given in Figure 4.29(b), the current source (IBIAS) and the SET create a feedback loop that decreases the gate-to-source voltage (VGS2) of the MOSFET (biased in the subthreshold region) for a certain range of increasing VDS (when the SET is in the positive transconductance region). That leads to

Hybridization of CMOS and SET


0.40

115

T = 150C
0.35

0.30

VDS1 (V)

25C 0.25

0.20

IBIAS = 40 nA
0.15 0.00 0.20

VDS = 1V
0.40 0.60 0.80 Gate-to-source voltage (V) (a) 1.00

104 105 10
6

MOSFET drain current (A)

25C

VDS = 1V

107 108 109 1010 0.15

T = 150C

0.00 0.15 0.30 0.45 0.60 0.75 MOSFET gate-to-source voltage (V) (b)

Figure 4.27 Effect of the operating temperature on (a) the SET drain-to-source voltage (VDS1) and (b) on MOSFET characteristics from subambient to room temperature. Here all the device parameters are the same as in Figure 4.24.

a decrease in the drain current of the MOSFETsee the qualitative evolution of operating points on SET and MOSFET characteristics as depicted in Figure 4.29(b). For another set of operating points (in the negative transconductance region of the SET) just the opposite phenomenon occurs (i.e., the ID increases with VDS). Although the working principle of SETMOS NDR is similar to the SET-based NDR device discussed earlier (Section 4.4.2), SETMOS exhibits NDR for much larger values of VDS (or VIN) and temperatures, and it does not need to satisfy the CG > CT condition.

116

Hybrid CMOS Single-Electron-Transistor Device and Circuit Design


= e /(CkBT)
2

300

32

30

28

26

24

22

20

18

16

14

12

Subthreshold slope (mV/dec)

250

SETMOS (+ve)

200 MOSFET 150 SET SETMOS (ve) 100

50 150

125

100

75 50 Temperature (C)

25

25

Figure 4.28 Comparison of SET, SETMOS, and MOSFET gate subthreshold slopes as a function of temperature. SET subthreshold slopes are not calculated over 75C, as there is no more Coulomb blockade.

Figure 4.30(a) depicts the effect of IBIAS on the quasi-periodic SETMOS device characteristics as predicted by Smartspice simulation. Figure 4.30(b) shows the corresponding conductance of the SETMOS NDR cell, which reveals clear NDR regime. It is worth noting that when the MOSFET gate leakage current becomes comparable with the SET bias current, the NDR property of the device becomes jeopardized (see Figure 4.31), and finally the device acts as an ordinary two-terminal resistor. Therefore, for proper operation, the VDS should be maintained at such a value (e.g., 1.25V for our simulated 65-nm channellength MOSFET) that gate leakage current becomes much less than the SET bias current. The effect of the operating temperature on SETMOS NDR behavior is presented in Figure 4.32, which is quite similar to 4.26(b). It should be noted that the quasi-periodic NDR behavior is visible even at room temperature. The effect of the background charge on SETMOS characteristics is exactly similar to that on normal SET devices, as shown in Figure 4.33(a). However, the effect of temperature on SETMOS NDR behavior is quite different, as demonstrated in Figure 4.33(b). It can be seen that even three NDR peaks are visible for negative values of the background charge, as it shifts the drain-to-source voltage of the SET on the VDS scale, as explained in Figure 4.34. The spice netlist for the simulation of SETMOS NDR cell is available in the Eldo\setmos_ndr.cir file and in the Smartspice\setmos_ndr.in file in the associated CD-ROM.

Hybridization of CMOS and SET

117

VDS1
Drain

(1)

IBIAS

I D1

IBIAS VGS1 = VDS


VDS1
(2a) (2b)

Source

VDS = VGS1

VDS = VGS1

Log ID2

D ID

Log ID2

(3a)

(3b)

VDS VGS2 = VDS1

VDS VGS2 = VDS1

VDS
(4)

IBIAS S
(a)

ID

VDS
(b)

Figure 4.29 (a) Schematic and (b) operating principle of SETMOS NDR architecture.

NDR devices primarily find their applications in the field of RF ICs, where they are used for oscillator design. The peak-to-valley ratio of any NDR characteristics is considered a figure of merit of that device. Comparisons between the SETMOS NDR device and other NDR devices (e.g., Essaki diode, resonant tunnel diode, and SET-based NDR devices) are presented in Table 4.3. The proposed SET NDR exhibits the same orders of magnitude of Vv /Vp and Ip/Iv compared to other devices (here Ip and Iv are peak current and valley current, respectively, and Vp and Vv are the voltages at which Ip and Iv occur). However, by tuning its IBIAS , the peak-to-valley ratio of SETMOS could be substantially increased.
4.5.5 NEMS-SETMOS Architecture

The nanoelectromechanical system (NEMS) platform has attracted special attention for RF ICs, especially wireless, because of its gain in terms of device and system miniaturization, CMOS compatibility, power savings, higher performance, and new functionality (such as reconfigurable circuit architectures

118

Hybrid CMOS Single-Electron-Transistor Device and Circuit Design


8 MOSFET gate leakage dominated region

Drain current, ID (A)

IBIAS (nA) = 50 T = 100C


40 30

20 10

0 0.0 0.5 1.0 1.5 Drain-to-source voltage, VDS (V) (a) T = 100C 2.0

60 50 40

Conductance, gd (S)

IBIAS (nA) = 50

30 20 10 0 10 20 30 40 50 0.0 0.5 1.0 1.5 Drain-to-source voltage, VDS (V) (b) 2.0 10

Figure 4.30 (a) ID VDS and (b) transconductance characteristics of SETMOS NDR architecture for the same device parameters as in Figure 4.24.

in which RF switches could program signal coupling to interconnect lines and passive components are programmable and/or tunable). Hybrid analog CMOSSET cells such as SETMOS could directly benefit from the recent progress achieved in developing NEMS technology. With a suspended conductive layer using a nanoair gap on the order of some tens of nanometers, a tunable-gate SET device can be imagined and modeled. A hypothetical architecture of such a tunable gate SET is demonstrated in Figure 4.35. Such a SET has two gates; one is fixed (buried gate), and the other is suspended over the island. Applying

Hybridization of CMOS and SET


0.05 T = 100C

119

MOSFET gate current, IG (nA)

0.04

0.03

0.02

IBIAS (nA) = 10
0.01 50 0.00 0.0 0.5 1.0 1.5 Drain-to-source voltage, VDS (V) (a) 0.5 T = 100C 0.4 0.3 2.0

IBIAS (nA) = 50

VDS1 (V)

0.2 10 0.1 0.0 0.0 0.5 1.0 1.5 Drain-to-source voltage, VDS (V) (b) 2.0

Figure 4.31 (a) MOSFET gate leakage current and (b) its effect on the drain-to-source voltage of the SET with the same device parameters as in Figure 4.24.

external bias through VG2 or VACT can electrostatically actuate this suspended gate. The characteristics of such a suspended gate capacitance are demonstrated in Figure 4.36. We can see that when the effective actuation voltage (V G 2 V ACT ) becomes larger than the pull-in voltage (VPI), tgap becomes zero; hence, the capacitance gets changed. Possible layouts of such an architecture are presented in Figures 4.37(a) and (b). The hybrid device architecture depicted in Figure 4.37(b) is based on a movable metallic carbon nanotube (CNT) actuated by a separate electrode; it takes full advantage of the CNT nanometer scale

120

Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

101

IBIAS = 40 nA
25C

Drain current, ID (A)

10

101

102

T = 150C

10

0.0

0.5 1.0 1.5 Drain-to-source voltage, VDS (V)

2.0

Figure 4.32 Effect of temperature on SETMOS NDR characteristics. Here all the device parameters are the same as in Figure 4.24.

dimensions (diameter), being a much more attractive alternative in terms of size and electromechanical functionality for a future implementation. By coupling a NEMS tunable capacitor model with SET analog analytical model MIB and BSIM, simulated electrical characteristics of the hybrid NEMS-SET-MOSFET architecture are reported in Figure 4.38, which couples electrical and mechanical characteristics at the nanoscale and suggests another novel functionality device: the tunable-gate NEMS-SETMOS. It is worth noting that here we have not considered the change of mechanical properties (e.g., spring constant) with temperature, as they only change the pull-in voltage. Exploiting the fact that tuning CG2 by external bias changes the C of the device, we can design a novel threshold gate (hard limiter), as shown in Figure 4.39(a). Such a NEMS-SETMOS threshold gate can be realistically used to design high-density neural networkssee Figures 4.39(b) and 4.40or a dense array of analog-to-digital flash converterssee Figure 4.41which demand highspeed operation with low power consumption. Tunable-gate SET architectures can also find their application in background chargeindependent data encoding systems. We know that background charge only changes the phase of Coulomb blockade oscillation by keeping its frequency constant. Therefore, using tunable-gate SET architecture, we can generate Coulomb blockade oscillation with different frequency and encode signals in frequency that remain unaffected from background charge variation [34]. It is worth noting that a change in gate capacitance also changes the C of the SET. Therefore a tunable-gate current-biased SET can also be used for amplitude modulation purposes.

Hybridization of CMOS and SET

121

4.0

IBIAS = 40 nA

T = 100C

Drain current, ID (A)

3.0

0.25e

2.0 0.25e 1.0 0 0.0 0.0 0.2 0.4 0.6 0.8 Gate-to-source voltage, VGS (V) (a) 1.0

12

IBIAS = 40 nA
10

T = 100C

Drain current, ID (A)

8 6 4 2 0 0.0 0.25e 0 0.25e

0.5 1.0 1.5 Drain-to-source voltage, VDS (V) (b)

2.0

Figure 4.33 Effect of the background charge on (a) SETMOS and (b) SETMOS NDR characteristics with the same device parameters as in Figure 4.24.

4.6 Summary
In this chapter we have described the concept of the hybridization of CMOS and SET. The motivation and challenges for designing such hybrid architec-

122

Hybrid CMOS Single-Electron-Transistor Device and Circuit Design


BC = +ve BC = ve

VDS1

VDS

MOSFET gate leakage dominated region

Figure 4.34 Schematic of the effect of the background charge on the current-biased SET output characteristics as a function of NDR drain-to-source voltage. A negative value of background charge shifts the characteristics to the left, and hence three peaks are available before the MOSFET gate leakage current starts to dictate the SETMOS NDR behavior.

Table 4.3 Comparison Between Different NDR Devices Peak Current Operating or Current Temperature Density 9.2 kA/cm2 100 A/cm2 0.15 MA/cm2 300K 300K 300K

Device Type Ga0.47In0.53As Esaki diode [31] Si tunnel diode [32] In0.8Ga0.2As/AlAs resonant tunnel diode [33] SET NDR [19] SETMOS NDR

Vp (V )
0.12 0.175 0.43

Vv (V )
0.5 0.3 0.75

Vv /Vp
4.16 1.714 1.744

Ip /Iv
16 2 7.7

0.180.3
-3

0.280.32 0.12510
-3

1.061.55 1.041.85 1351 nA 1.25 22.5 30 8531 6.5 pA 0.53 A

123K 27 mK 173K

SEB-SET NDR [18] 0.110

Multiple Multiple (~0.1 to 1) (~0.1 to 1)

tures have also been explained. We have discussed different CMOS-SET cosimulation and codesign issues and developed a CAD framework (that is available in the CD-ROM) for cosimulation and codesign of hybrid structures. Using this CAD framework, we have then performed case studies for several analog hybrid CMOS-SET circuits (e.g., neural cell and ML). At the end, we have presented the architecture and characteristics of the novel SETMOS cell,

Hybridization of CMOS and SET


Movable gate Movable Gate VD VG1 G1 SiO 22 Spring Bulk Si

123

t gap tgap

VG2 VS
VG1

VD

VACT

(a)

VS

VACT
(b)

Figure 4.35 (a) Schematic of tunable-gate SET architecture. Here the principle gate is buried one (VG1), and the secondary gate is suspended over the island. (b) Circuit symbol of tunable-gate SET.

100 Gate up 80 High CG2

0.26

0.22 60 0.18 40
Low CG2

tgap (nm)

0.14

20 Pull-in voltage VPI = 0.6V 0 0 0.2 0.4 0.6 Gate down 0.8 1 Actuation, VACT VG2 (V) 0.1

Figure 4.36 The displacement characteristics of the NEMS movable gate (left axis) and corresponding CG2 variation (right axis) versus effective actuation voltage, VACT VG2, for VG2 = 0V. In fact, the tunable NEMS capacitor acts as a two-state capacitive switch (the n+ region underneath the movable membrane is covered with a 20-nm thin oxide) with a pull-in voltage VPI = 0.6V (applied voltage at which the movable electrode snaps down). Device parameters used for calculation are tox = 20 nm, tgap = 100 nm, kspring (spring constant) = 1 N/m, and AACT (surface area for actuation) = 120 m2. See [35, 36] for more details.

which offers SET-like Coulomb blockade oscillation with a much higher current level than traditional SET and suggested some possible applications.

CG2 (aF)

VG2

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Hybrid CMOS Single-Electron-Transistor Device and Circuit Design


Nanowire SET (70 nm x 2 mm)

VG
Drain

Buried electrode n+ (Gate G)

Movable electrode (Gate G 2) Anchor Source Buried electrode n+

Hinges

VG 2

VACT
(a) Suspended metallic CNT V G2 Drain

VG

VACT
Source (b)

Figure 4.37 (a) Layout for NEMS-SET device. The moveable metal electrode (G2) is electrostatically actuated by VACT VG2. A relatively high movable electrode surface (~tens of m2), a small air gap (< 100 nm), and a low stiffness design (with elastic hinge coefficient, k = 1 N/m) are required for low-voltage (<1V) actuation. (b) Layout for CNT/NEMS-SET device, with electrostatically movable CNT; this hybrid device takes advantage of the intrinsic nanoscale dimensions of the metallic CNT.
0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 1.0 0.5 0.0 0.5 1.0 1.5 Gate-to-source voltage, VGS (V) 2.0 3.0

SET drain-to-source-voltage, VDS1 (V)

2.0 1.5 1.0

VACT = 0.7V

0.5 0.0

Figure 4.38 Characteristics of tunable-gate NEMS-SETMOS device at T = 100C. When CG 2 changes (i.e., VG 2 VACT ), it actually changes the C of the SET, and hence both the SET and SETMOS behaviors get changed.

Drain current, ID (A)

VPI = 0.6V VGS2 = 0V VDS = 0.8V

VACT = 0V

2.5

Hybridization of CMOS and SET


0.60

125

VBIAS 1 = 0.46V
0.50

VBIAS 2 = 0.1V VBIAS 1 = 0.64V VBIAS 2 = 0.3V

Output voltage, VOUT (V)

0.40

VDD = 1V
R = 1M

0.30

VOUT VBIAS 1 VBIAS 2

0.20

VIN
0.10 0.0 0.2 0.4 0.6 Input voltage, VIN (V) (a) 0.8 1.0

VDD = 1 R = 1M VOUT VIN1 VIN2 VIN3 VIN1 h VIN2 VIN3 u h


(b)

VBIAS VBIAS

VOUT

Figure 4.39 (a) Application of NEMS-SETMOS as a threshold gate or a hard limiter; (b) schematic of a CMOS-SET hybrid neuron cell by using the NEMS-SETMOS threshold gate.

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Hybrid CMOS Single-Electron-Transistor Device and Circuit Design

x1 y1 xm xp
Quantifier subnet
Post-processing (analog/digital)

yn

Discriminator subnet

Figure 4.40 Schematic of the Hamming artificial neural network by using NEMS-SETMOS threshold gate [37]. Here xis and yis are input and output vectors, respectively.
R OUT3 16 8

OUT2 16 12 8

OUT1 16 14 8 4

OUT0 16 E 15 8 4 2

VREF VA VDD

Figure 4.41 Application of NEMS-SETMOS threshold gate as an analog-to-digital flash converter [38]. A very dense array design demands SET-CMOS hybrid circuit design instead of standard CMOS technology.

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