of numbers (n
1
+n
2
+1 bits):
Binary coding (subunitary, N<1)
Natural binary (unsigned)
1
k n =
Natural binary (unsigned)
1
2
n
k
k
k
N b
=
=
min
0 N =
max
1 2
n
N
=
2
n
N
=
Offset binary (signed)
1
2 2
n
k
k
N b
=
min
1
N =
max
1
2
n
N
=
2
n
N
=
Twos complement (signed)
1
2 2
k
k
N b
=
=
min
2
N =
max
2
2
N =
2
n
N
=
Twos complement (signed)
( )
1
1
2
2 2
n
k
k
k
N b b
=
= +
2
n
N
=
min
1
2
N =
max
1
2
2
n
N
=
3
2 k=
2 2
EIM Chap 2 Digital to analog converter
Binary coding (contd)
Sign Magnitude (signed)
( )
1
2
1 2
n
b
k
k
k
N b
=
=
1
min
2 2
n
N
= +
1
max
2 2
n
N
+
=
2
n
N
=
Binary coded decimal (BCD) 4 bits (nibble) used to
represent one digit ;
2 k=
represent one digit ;
Gray the difference between codes of two successive
number is 1 bit; number is 1 bit;
Ones complement (signed);
4
EIM Chap 2 Digital to analog converter
Unipolar Codes Unipolar Codes
N (natural) Fraction ( subunitar nr) NB BCD Gray
0 0 0000 0000 0000
1 1/16 0001 0001 0001 1 1/16 0001 0001 0001
2 2/16 0010 0010 0011
3 3/16 0011 0011 0010
4 4/16 0100 0100 0110 4 4/16 0100 0100 0110
5 5/16 0101 0101 0111
6 6/16 0110 0110 0101
7 7/16 0111 0111 0100
8 8/16 1000 1000 1100
9 9/16 1001 1001 1101
10 10/16 1010  1111
11 11/16 1011  1110
12 12/16 1100  1010 12 12/16 1100  1010
13 13/16 1101  1011
14 14/16 1110  1001
15 15/16 1111  1000
5
15 15/16 1111  1000
EIM Chap 2 Digital to analog converter
Bipolar Codes
N Fraction SM C1 C2 OB* OB
+3 +3/8 011 011 011 111 000
+2 +2/8 010 010 010 110 001 +2 +2/8 010 010 010 110 001
+1 +1/8 001 001 001 101 010
+0 +0 000 000 000 100 011 +0 +0 000 000 000 100 011
0 0 100 111   
1 1/8 101 101 111 011 100 1 1/8 101 101 111 011 100
2 2/8 110 101 110 010 101
3 3/8 111 100 101 001 110
4 4/8   100 000 111
6
EIM Chap 2 Digital to analog converter
Binary codes conversion
7
EIM Chap 2 Digital to analog converter
Binary codes conversion
8
EIM Chap 2 Digital to analog converter
Ideal characteristic for unipolar DAC :
( )
2
n
k
R k
U N U b
=
2
n
CS
U
U U
= =
b
1
b
n
V(N)
( )
1
2
R k
k
U N U b
=
=
( )
min
0..0h 0V U U N = = =
2
2 1
CS
R
n
U U = =
V
R
V(N)
Ideal characteristic for bipolar DAC
V(N)
V
V
CS
R
( )
( )
max
... h 1 2
n
R CS
U U N F F U U
= = = =
Ideal characteristic for bipolar DAC
(offset binary code)
V
MSB
n
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
N
V
LSB
N
m
a
x
+
1
( )
1
1
2 2
n
k
R k
k
U N U b
=
=
=
( )
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
N
L
S
B
M
S
B
N
m
a
x
0 1/8 4/8 7/8
N
m
a
x
+
1
1
min
2
R
U U
=
( )
1
max
2 2
n
R
U U
=
2
n
R
U U
=
9
0 1/8 4/8 7/8
2
R
U U =
EIM Chap 2 Digital to analog converter
Nonideality errors
Static errors
Offset error  analog output response to an input code Offset error  analog output response to an input code
corresponding to output zero;
Gain error difference between slope of actual and ideal Gain error difference between slope of actual and ideal
transfer function;
FullScale error  difference between the actual and the ideal
output maximum value (offset error + gain error) ; output maximum value (offset error + gain error) ;
Integrated nonlinearity error (INL)  deviation of an actual
transfer function from a straight line (after nullifying offset and transfer function from a straight line (after nullifying offset and
gain errors);
Differential nonlinearity error (DNL)  difference between the
ideal and the measured output responses for successive ideal and the measured output responses for successive
DAC codes;
Dynamic error: overshoot, undershoot (during settling time)
10
EIM Chap 2 Digital to analog converter
Offset error
Gain error
Factor scale error Factor scale error
U
O
U
O
(N)
Overshoot
2
V
+
U
O
(N)
Undershoot
2
V
p(t)
hold
( ) ( )
T S
t t nT
+
=
( )
y t
( )
sh
y t
Y( f ) 
( ) ( )
T S
n
t t nT
=
=
( ) { } ( ) ( ) ( ) { }
sh S S
n
y t y nT t nT p t
+
=
=
F F F
( ) ( ) ( )
sinc
sh s k s
n
Y f w f w f Y f nf
=
=
f
m
f
m
For w = T (practical DAC converter)
f
m
f
m
Y
sh
( f ) 
( ) ( )
sinc 2
2
s
sh k s
T
Y f f Y f nf
=
For w = T
S
(practical DAC converter)
f
m
f
m
f
S
f
S
1/w
( ) ( )
sinc 2
2
sh k s
n
Y f f Y f nf
=
=
13
f
S
f
S
EIM Chap 2 Digital to analog converter
Types of DACs
Binary Weighted Resistor Network Binary Weighted Resistor Network
R2R Ladder Network
Stochastic
Multiplying DAC
14
EIM Chap 2 Digital to analog converter
V
R
BinaryWeighted Resistor DAC
2 R
n
bn
1
( )
1 1
{0,1}
n n
i
b
V N V b
+ =
Using Tellegens theorem:
8R
b3
.....
0 ( )
1 1
1 1
{0,1}
2 2 2
i
g R i
i n i
i i
b
V N V b
R R R
= =
+ =
( )
2
n
i
g R i R
V N V b V N
= =
4R
2R
b2
1
1
0
R(N)
( )
1
2
g R i R
i
V N V b V N
=
= =
( )
_min
0...0h 0V
g g
V V = = ( )
R
0...1h 2 V
n
g g
V V
= =
b1
2R
RT=2 R
n
0
Vg(N)
After source passivization:
( )
( )
_max
... h 1 2
n
g g R
V V F F V
= =
After source passivization:
( )
( )
1
1 1 1 1
2 2
n
i n
i
R N R
R N R R R
=
= + = =
15
EIM Chap 2 Digital to analog converter
Steady state voltage command
BinaryWeighted Resistor DAC (contd)
( ) ( )
0 g
V N V N =
Dynamic regime (Laplace transform )
Steady state voltage command
voltage command
0
1 1 1 1
( ) ( ) ( )
1 1/
g g
p
V s V s V s
sRC s s s
= =
+ +
1
t
( )
( )
0
1
( ) 1 ,
t
g
p
V t V e t
R N C
= =
V
R(N)
V (t)
current command
( )
( )
1
0
1
( ) ln 2
2
n
R
s g s
g
V
V t V N V t
V N
V
g
(N) (t)
C
p
V
0
(t)
( )
( )
( ) ( )
0 g g
R
V N V N V N
R N
= =
Steady state current command
16
( )
R N
EIM Chap 2 Digital to analog converter
Disadvantages:
BinaryWeighted Resistor DAC (contd)
Resistance Values Require Great Accuracy:
e.g. Tolerance of R must be < 1/2
n
Disadvantages:
e.g. Tolerance of R must be < 1/2
n
Often limited to 4Bit conversions because of the limited current
range possible with resistors; range possible with resistors;
Larger bit numbers difficult due desired current changes being
close in magnitude to noise amplitudes (for less significant bits); close in magnitude to noise amplitudes (for less significant bits);
Hardware difficult realization for large bits number (due the weight Hardware difficult realization for large bits number (due the weight
inaccuracy for the large range);
17
EIM Chap 2 Digital to analog converter
I
R
R R R I
t
R R R
R2R ladder network DAC
b1 b2 bn1 bn
I
R
2R 2R
I1
I2
2R
.....
2R RT=2R
R R R I
t
V
R
1
2
2 2
k k
R
k k R
V
R
I I I
= = =
+
b1 b2 bn1 bn
R
r
V0(N)
0 1
[B]
1 0
1
2 2
2 2
k k R
I I I
R R R
= = =
+
( ) ( )
0 r
V N R I N =
V0(N)
Convertor I  U
( ) ( )
0 r
V N R I N =
( ) ( )
0
1 1 1
1
2 2
n n n
k k
r
k R k R k
k k k
R
I N I V b V N V b
R R
= = =
= = =
( )
0_max
0...0h 0V V N= =
( )
( )
0_min
... h 1 2
n
r
R
R
V N F F V
R
= =
1 1 1 k k k
R R
= = =
0_max
R
( )
0
0...1h 2
n
r
R
R
V V N V
R
= = =
18
EIM Chap 2 Digital to analog converter
R2R ladder network resistor DAC (contd)
Maintains constant current through all branches = no voltage
transients;
Less hardware constrain (easy to find R2R resistor pair
values);
Faster response time due to lack of voltage transients.
19
EIM Chap 2 Digital to analog converter
Stochastic DAC (without resistor network)
NUM
f
CK
n
NUM
SUM
Cy out
R
C
V(N)
out
( )
0
1
2
cos
y out k k
k
C t A A k t
T
=
= + +
n
n
N
Cy out
C
out
(nefolosit)
T =/2
n
unused
1 k
T
=
( )
2 1
n
CK
T T =
1 1
T=2 T
CK
n
t
T =/2
n
T = (2
n
1)T
CK
( )
2
1 1
1 2
1
T
H f
j fRC
f
f
= =
+
+
1 1
2
T
f
RC T
= <<
T=2 T
CK
Cy out()
A
0
A
1
LPF
T = (2 1)T
CK T
f
( )
1
0
1
2
2
2 1 2 1
n
n
k
R k
n n
k
N E
V N A E E N V b
T
=
= = = = =
A
0
2/
A
2
4/ 0
N subunitary number (N
1
supraunitary )
EIM Chap 2 Digital to analog converter
Multiplying DAC
U
slow time varying external
( )
out
U t
Ref
U
slow time varying external
( )
Ref in
U U t =
t
( )
Ref in
( )
out
U t
( )
o
d
d 2
in
U t
U
t t
<<
t
conv
max
d 2 t t
<<
= =
( )
0
2
n n
k
R
k k
V
I N I b
R
= =
( ) ( )
0
1 1
' ' 1 2
k k
k k
ref
I N I b
R
= =
= =
( )
0
1 1
k k
k k
ref
R
= =
( )
0_min
' FFh 0 I N= = ( )
( )
8
0_max
' 00h 1 2
R
ref
V
I N
R
= =
8
0
' 2
R
ref
V
I
R
=
ref
R
ref
R
( )
0_min
00h 0 I N= = ( )
( )
8
0_max
FFh 1 2
R
ref
V
I N
R
= =
8
0
2
R
ref
V
I
R
=+
23
EIM Chap 2 Digital to analog converter
Example 2: Inversion amplifier with digital adjustment gain
R
( )
v RI N =
I
I
+
_
DAC  08
u(t)
IN
Vout
( ) ( ) ( )
n
R
( )
out
v RI N =
I
N
u(t)
IN
Vout
( ) ( ) ( )
1
( ) 2
n
k
out in k u in
k
ref
R
v t u t b A N u t
R
=
= =
n
( )
1
2
n
k
u k
k
ref
R
A N b
R
=
=
24
EIM Chap 2 Analog to digital converter
{n} s(t)
Analog to Digital Converter
{n}
ADC
s(t)
Function: converts input analog signal into a digital signal; Function: converts input analog signal into a digital signal;
ADC conversion comprises :
Time sampling: samples are taken from the analog signal Time sampling: samples are taken from the analog signal
(sampling frequency) and its values are maintained for a certain
time interval;
Quantization : rounding off of the sampled value to the nearest of Quantization : rounding off of the sampled value to the nearest of
a limited number of digital values;
Binary coding: conversion of the quantized value into a binary
code; code;
Sampling and quantization operation may give rise to loss of information.
Under certain conditions ADC loss can be limited to an acceptable Under certain conditions ADC loss can be limited to an acceptable
minimum;
25
EIM Chap 2 Analog to digital converter
{n} s(t)
Analog to Digital Converter
{n}
ADC
s(t)
Mathematical representation of ADC Function: Mathematical representation of ADC Function:
f
ADC
:RN
Parameters: Parameters:
Conversion type: unipolar, bipolar;
Quantization type: truncate, round, roundceiling;
Binary code (natural, offset, twos complement, etc.); Binary code (natural, offset, twos complement, etc.);
Input type (U, I);
Input range;
Resolution  the smallest change required in the ADC analog input to Resolution  the smallest change required in the ADC analog input to
change its output code by one level;
 number of bits used for binary cod (n);
Conversion time  required time before the converter can provide valid Conversion time  required time before the converter can provide valid
output data
Accuracy of conversion  the difference between the actual input voltage
and the fullscale weighted equivalent of the binary output code
26
and the fullscale weighted equivalent of the binary output code
EIM Chap 2 Analog to digital converter
Parameters (contd)
Converter Throughput Rate  the number of times the input signal can be Converter Throughput Rate  the number of times the input signal can be
sampled maintaining full accuracy
 Inverse of the total time required for one
successful conversion successful conversion
 Inverse of Conversion time if no S/H
(Sample and Hold) circuit is used
ADC Interface Signals : ADC Interface Signals :
Data: Digital I/O pins the ADC uses to supply data
Parallel output n+1 pins (fast transmission, short distances)
Serial output 2 pins (for long distances, need a internal shiftregister)
Start: Pulse high to start conversion (input)
EOC (End of Conversion): Typically active low low level of pulse EOC (End of Conversion): Typically active low low level of pulse
indicate complete conversion (output value can be read);
Clock: Clock used for conversion (for synchronising ADC subblocks, for
internal FSM);
27
internal FSM);
EIM Chap 2 Analog to digital converter
A/D Converter traditional data converter at Nyquist rate
(f
s
>2f
m
)
s m
( )
SH
X f ( )
Q
X f
Successive operations for AD conversion process.
f f f f
Successive operations for AD conversion process.
ADC introduces a noncompensable quantization noise.
28
EIM Chap 2 Analog to digital converter
Sampling process (remember)
 continuous signal conversion into a discrete time samplers sequence
(ideal sampling, natural sampling, flattop sampling); (ideal sampling, natural sampling, flattop sampling);
Ideal sampling
( ) ( ) [ ] ( )
s s
x t x t x n x nT R = =
( ) ( ) ( ) ( ) ( )
x t x t t nT x t t
+
= =
( )
2
1
S
S
jn t
T
T
n
t e
T
+
=
=
( ) ( ) ( ) ( ) ( )
S
s S T
n
x t x t t nT x t t
=
= =
n
S
T
=
( ) ( ) ( )
{ }
( )
1
S
S T
n
S S
n
X f x t t X f f
T T
+
=
= =
F
f
m
f
m
X
S
( f )
( )
1
n
S S
S S
n n
S S
T T
n
X f f X f n f
T T
=
+ +
= =
= =
f f f f
29
f
m
f
m
f
S
f
S
EIM Chap 2 Analog to digital converter
Sampling process (contd) Sampling process (contd)
Natural sampling
( ) ( ) ( )
( )
S
s T
x t x t x t p t =
2
( )
2
S
S
jn t
T
T n
n
p t P e
+
=
=
f f
( )
2
2 /2
2
/2
1
d
S
S
S S
S
nT
n T
j j t
T T
n T
s T
P e p t e t
T
f
m
f
m
( ) ( ) ( )
/2
sinc n 1 sinc n
S
s T
n
jn
T
e
= =
( ) ( ) ( )
{ }
S
S T n
n
S
n
X f x t p t P X f
T
+
=
= =
F
f
m
f
m
f
S
f
S
30
EIM Chap 2 Analog to digital converter
Sampling process (contd)
Flattop sampling Flattop sampling
( ) ( ) ( ) ( )
( )
s S
n
x t x t x t t nT p t
+
=
=
n=
( ) ( ) { } ( )
sinc
= =
S
j fT
S S
P f p t T e f T F
( ) ( )
sinc
S
j fT
S S
n
X f e f T X f
T
( ) ( ) { } ( )
S S
F
f
m
f
m
( ) ( )
sinc
=
=
S S
n
S
X f e f T X f
T
f
m
f
m
Sampling rate is given in Samples/s
(S/s, kS/s, MS/s, GS/s);
f
m
f
m
f
S
f
S
31
EIM Chap 2 Analog to digital converter
Quantizing process Quantizing process
 analog signal approximation to the nearest discrete value:  analog signal approximation to the nearest discrete value:
[ ]
[ ] , 1, ,
q k k M
x n x n q k k M q Q =
a
a
M
q
M
M
q
M
M
x
q
(t)
Quant.
Quantized
a
1
a
k1
a
k
q
2
2
q
k
k
q
2
2
q
k
k
Quant.
thresholds
Quantized
values
a
0
a
1
1 2 2 k M
q
1
1
t
q
1
1
n
q
(t)
+/2
/2
t
t
/2
Quantization of nonsampled signal (continuous)
32
EIM Chap 2 Analog to digital converter
Sampling & quantizing process Sampling & quantizing process
T
s
a
a
k
a
k1
q
k
k
q
k1
k1
Quantization
thresholds
Quantized
values
a
0
q
1
1
n
sq
(t)
a
1
a
2
q
2
2
Quantization

t
Analog signal
Sampled signal (sample & hold)
Quantization
noise
Sampled signal (sample & hold)
Quantized signal
Quantization uniform (constant step) linear ADC
nonuniform (variable step) nonlinear ADC
33
Quantization
EIM Chap 2 Analog to digital converter
Quantization
Truncating quantization
1 k k
q a
=
1 1
2 2
n n
i n i
qt ref i i t
i i
U U b U b N U
= =
= = =
Quantization noise
p(n )
Quantization noise
1
2
i
qt qt ref i
i n
n U U U b
= +
= =
+
n
q
p(n
q
)
0
1 i n = +
+
n
q
0
1
{ } ( )
2
qt qt qt qt qt qt
E n p n n dn n dn
= = =
Noise mean value
0
{ } ( )
2
qt qt qt qt qt qt
E n p n n dn n dn
= = =
Noise variance (power)
2 2
2 2 2 2
2
{ } [ { }]
12 12
n
qt qt qt ref
E n E n U
= = =
Ideal characteristic
34
Quantization (contd)
EIM Chap 2 Analog to digital converter
Quantization (contd)
Rounding quantization
1
1
2
k k
k
a a
q
+
+
+
=
2
1 1
1
1 1
2 2
( ) , {0,1}
n
n i
qr n qt ref n i
i
t n r n
U U b U U b b
N b U N U b
+ +
=
+ +
= + = +
= + =
Quantization noise
( 1)
( 2 2 )
n
n i
n U U U b b
+
= = +
1 1
( ) , {0,1}
t n r n
N b U N U b
+ +
= + =
( 1)
1
2
( 2 2 )
n i
qt qt ref n i
i n
n U U U b b
+
+
= +
= = +
p(n
q
)
/ 2
1
{ } 0 E n n dn
+
= =
= =
= = =
Ideal characteristic
35
Noise variance (power)
12 12
Quantization (contd)
EIM Chap 2 Analog to digital converter
Quantization (contd)
Roundceiling quantization
k k
q a =
1
(2 2 )
( 1)
=
= + = +
= + =
n i
qm qt ref i
i
t m
U U U U b
N U N U
Quantization noise
( 2 2 )
n i
qm qm ref i
n U U U b
= = +
t m
1
( 2 2 )
qm qm ref i
i n
n U U U b
= +
= = +
0
1
= =
= =
= = =
Ideal characteristic
36
Quantization (contd)
EIM Chap 2 Analog to digital converter
Quantization (contd)
Noise value as: voltage (rms, pp), LSB (rms, pp), SNR;
Signal to quantization noise ratio (SNR)
Considering a periodic signal at input, with period T, having power:
( )
1
T
( )
2 2
_
0
1
d
T
x x ef
P x t t U
T
= =
( )
2 2 2
_ _ _
2
12 12
10 log 10 log 10 log 10 log 2
x ef x ef x ef
n x
U U U
P
SNR n
= = = =
( )
_ _ _
2
2 2 2
_
10 log 10 log 10 log 10 log 2
6, 02 10,8 20 log [dB]
q
x ef x ef x ef
n x
n q ref
x ef
P
SNR n
P U
U
n
= = = =
= + +
Total SNR after quantization process:
For analog noisy signal, the total noise power is
2 2 2
= +
6, 02 10,8 20 log [dB]
ref
n
U
= + +
For analog noisy signal, the total noise power is
effective bit number :
2 2 2
T a q
= +
2
2
_
4 4
2 2
log log 1
x ef
a
ef
T q
U
n n
= = +
37
T q
Quantization (contd)
EIM Chap 2 Analog to digital converter
Quantization (contd)
Example: a full range sine wave input ( ) ( )
sin
2
ref
U
x t A t A =
Signal power and rms value:
2
( )
2
2
2 2
_
0
1
d
2 8
T
ref
x x ef
U
A
P x t t U
T
= = = =
2
( )
( )
2
2 2
2 2 2 2
3
6
10 log 10 log 10 log 10 log
2 2 2
6.02 1.76 dB (for sinwave quantization)
q
ref
x
q
n
n q ref
U
P A A
SNR n
P U
SNR n n
= = = =
= +
( )
max
min
6.02 1.76 dB (for sinwave quantization)
Dynamic range: 20 lg 6, 02 1.76 dB=
q
q
SNR n n
S
DR n SNR
S
= +
= = +
min
S
( )
10 bit 62 dB
q
SNR =
Example:
( )
1, 76 dB / 6.02 ENOB DR =
( )
10 bit 62 dB
q
SNR =
Example:
total effective bit number:
2 2
4 4 4
2 2
1
log log log 1
3
a
ef
T q
A
n n
= + = +
38
3
T q
EIM Chap 2 Analog to digital converter
Nonideality errors
Static errors
Offset error (linear error);
Gain error (linear error);
FullScale error (offset error + gain error) ;
Integrated nonlinearity error (INL);
Differential nonlinearity error (DNL); Differential nonlinearity error (DNL);
Dynamic error:
Aperture error (due to the delay between Aperture error (due to the delay between
the clock signal of S/H block and the effective holding time)
( ) ( )
sin x t A t = For sin wave input ( ) ( )
sin x t A t =
( )
d
1
d 2 2
A A A
n
x t
V
E T T
t f
= < =
For sin wave input
39
d 2 2 t f
EIM Chap 2 Analog to digital converter
Offset error
Gain error
Factor scale error Factor scale error
INL error DNL error
40
Effects of static errors and quantizing error (examples)
EIM Chap 2 Analog to digital converter
Effects of static errors and quantizing error (examples)
An ideal threebit quantizer, with
a gain of 1.25 instead of 1.00
An ideal threebit quantizer, with
a gain of 1.25 instead of 1.00
An ideal threebit quantizer, with
+0.6 LSB offset error
..
An ideal threebit quantizer, with INL
error caused by important DNL error
An ideal threebit quantizer, with
INL error and small DNL error
error caused by important DNL error
41
EIM Chap 2 Analog to digital converter
Improving A/D conversion techniques
Oversampling
Signal
spectrum
Antialiasing
filter Imagine
spectrum
Oversampling
OSR oversampling ratio
= =
S S
f f
OSR
spectrum
Quant.
noise
( ) ( )
6.02 1.76 10log SNR n n OSR = + +
min
2
= =
S S
S sig
f f
OSR
f f
Dithering adding a small amount
( ) ( )
6.02 1.76 10log
q
SNR n n OSR = + +
of random noise (maximum = 1/2U)
to the input before conversion (for constant
and slow varying analog signal).
Nyquist rate ADC Oversampling ADC
and slow varying analog signal).
LSB oscillates randomly between 0 and 1
in the presence of very low input levels.
42
EIM Chap 2 Analog to digital converter
Acronyms for A/D converter Acronyms for A/D converter
SNR  Signal to (quantization) Noise Ratio;
THD Total Harmonic Distortion (due nonzero INL) = the ratio of the THD Total Harmonic Distortion (due nonzero INL) = the ratio of the
rms value of the fundamental signal to the mean value of the rootsum
square of its harmonics (usually the first five harmonics); Specified in
dBc (decibels below carrier);
SINAD (dBc)  SignaltoNoise Plus Distortion ratio (same as SNDR) = SINAD (dBc)  SignaltoNoise Plus Distortion ratio (same as SNDR) =
ratio of the rms value of the fundamental signal to the mean value of
the rootsumsquare of its harmonics plus all noise components;
SNDR  Signal to Noise + Distortion Ratio; SNDR  Signal to Noise + Distortion Ratio;
SFDR  Spurious Free Dynamic Range = the ratio of the rms value of
the signal to the rms value of the worst spurious signal (that may be or
may not be an harmonic of the original signal ); may not be an harmonic of the original signal );
Specified in dBc or in dBFS;
ENOB  Effective Number of Bits:
_
[dB]  10, 8 dB20 log
6,02
x ef
ref
U
SNR
U
n
(
 
( ]
]
(
\
=
( ENOB  Effective Number of Bits:
FOM ADC Figure of Merit : [ ]
ENOB
Power
Joule/level resolved
2
S
FOM
f
=
6,02
n =
(
(
(
(
43
ENOB
Joule/level resolved
2
S
FOM
f
EIM Chap 2 Analog to digital converter
Input Tone
input tone
harmonics
Quantization Noise
Other quantization impairments:
intermodulation products
Other quantization impairments:
SFDR
Harmonics Harmonics
intermodulation products
44
EIM Chap 2 Analog to digital converter
A/D converter structures A/D converter structures
Without integration
Without feedback Without feedback
Flash ADC (direct conversion)
Folding ADC (Twostep ADC)
Pipelined ADC (serial ADC)
speed accuracy
Pipelined ADC (serial ADC)
Timeinterleaved ADC
Charged coupled device ADC (CCDADC)
Timestretch ADC (optical ADC)
speed accuracy
Timestretch ADC (optical ADC)
With feedback
Successive approximation ADC (SAR)
Rampcompare ADC Rampcompare ADC
Deltaencoded ADC
With integration
Sigmadelta ADC
ADC with intermediate FM stage
Integrating ADC (singleslope, dualslope, multiple slope)
45
EIM Chap 2 Analog to digital converter
Flash ADC
bank of 2
n
1 parallel comparators (high complexity); bank of 2 1 parallel comparators (high complexity);
very fast  GHz sampling rates (limited only by
delays of comparators and logic network);
references resistor ladder references resistor ladder
few bits of resolution (4 8 bits, rarely 10 bits)
high input capacitance
expensive power / area (in IC)
D
i
g
i
t
a
l
b
a
c
k
e
n
d
Input
D
OUT
are prone to produce glitches (clock skew
comparators sample the inputs at different instants)
high cost
applications: video, wideband communications,
D
i
g
i
t
a
l
b
a
c
k
e
n
d
applications: video, wideband communications,
optical storage
clock
46
EIM Chap 2 Analog to digital converter
Flash ADC
Improving technique track / hold Improving technique track / hold
T/H for good dynamic performance
Offset correction in comparators
Input
Track / Hold
D
OUT
Example: AD9066 Dual 6 AD9066 Dual 6bit, 60MSPS bit, 60MSPS
Flash ADC Flash ADC Flash ADC Flash ADC
Key specifications: Key specifications:
Input Range: 500mV pp
Input Impedance: 50k  10pF
Offset
correction
Input Impedance: 50k  10pF
ENOB: 5.7 bits @15.5MHz Input
OnChip Reference
Power Supply: Single +5V Power Supply: Single +5V
Package: 28pin SOIC
Ideal for Quadrature Demodulation
47
EIM Chap 2 Analog to digital converter
Interpolating Flash ADC
reduces the number of comparator reduces the number of comparator
preamplifiers at the input of a Flash
converter by a factor of two;
substantially reduces the input substantially reduces the input
capacitance, power dissipation, area of
flash converters;
preserves the onestep nature of a Flash preserves the onestep nature of a Flash
architecture ( VLSI technology);
48
EIM Chap 2 Analog to digital converter
Timeinterleaved ADC (TIADC)
uses M parallel flash ADCs; uses M parallel flash ADCs;
ADC sample data every Mth cycle of
the effective sample clock; the effective sample clock;
sample rate is increased M times;
complexity is increased M times;
requires correction of time
interleaving mismatch errors;
applications: video, wideband applications: video, wideband
communications, optical storage;
49
EIM Chap 2 Analog to digital converter
Folded Flash ADC (two steps)
Folding = technique that reduces hardware
maintaining the fast nature of a full Flash
INPUT
FOLDING
CIRCUIT
FINE
ADC
N
F
maintaining the fast nature of a full Flash
ADC;
An analogue preprocessing circuit
generates a residue which is digitised to
COARSE
ADC
DIGITAL ADDER &
CORRECTION CIRCUIT
generates a residue which is digitised to
obtain the LSBs;
The MSBs are resolved using a coarse
ADC that operates in parallel with the folding
DIGITAL OUTPUT
WORD
N
C
ADC that operates in parallel with the folding
circuit;
increase latency;
Folding principle
Folded ADC reduces latches and logic:
N
C
+N
F
bits need 2
Nc
+2
Nf
2 comparators;
First stage determine the output sign;
Folding principle
First stage determine the output sign;
At every stage (except the last) the LSB
is wasted;
1 bits
C
N + bits
C
N bits
F
N
50
EIM Chap 2 Analog to digital converter
Serial/Parallel ADC (pipelined)
uses more steps of subranging (with same bits number N
C
); uses more steps of subranging (with same bits number N
C
);
one stage
a coarse conversion is done
amplifies the difference of the input signal (determined with a DAC), then go
to next stage
fast conversion  GHz sampling rates;
data latency greater than flash, but less than SAR
high resolution with less complexity; high resolution with less complexity;
ADC overload in next stage need Digital Error Correction;
1 bits
C
N +
bits N bits
C
N 1 bits N +
STAGE 2 STAGE 1
1 bits
C
N +
bits
C
N bits
C
N 1 bits
C
N +
51
STAGE 2 STAGE 1
EIM Chap 2 Analog to digital converter
Serial/Parallel ADC (pipelined)
Example: AD 9220/9221/9223 12 bits pipelined ADC Example: AD 9220/9221/9223 12 bits pipelined ADC
 Latency is four cycles;
 1 bit overlap between adjacent stages
 accuracy of ADC in stages 14 needs 4
bits; 5th stage needs greater accuracy; bits; 5th stage needs greater accuracy;
 entire ADC accuracy established by 5th
stage
Family Members: Family Members:
AD9221 (1.25MSPS), AD9223 (3MSPS),
AD9220 (10MSPS)
Power Dissipation: 60, 100, 250mW,
Respectively Respectively
FPBW: 25, 40, 60MHz, Respectively
Effective Input Noise: 0.1 LSB RMS (Span =5V)
SINAD: 71 dB
SFDR: 88dBc SFDR: 88dBc
OnChip Reference
Differential NonLinearity: 0.3 LSB
Single +5V Supply
28Pin SOIC Package
52
28Pin SOIC Package
EIM Chap 2 Analog to digital converter
Serial ADC (1 bit per stage)
it uses the truncating it uses the truncating
quantization in intermediate
stages.
Example for bipolar case; Example for bipolar case;
Single stage ADC
Obs: dont confuse with serial
output ADC of other
technologies (flash, SAR, technologies (flash, SAR,
folded flash, etc )
53
EIM Chap 2 Analog to digital converter
Successive approximation register ADC (SAR)
SAR = Successive approximation register SAR = Successive approximation register
DAC = digitaltoanalog converter
EOC = end of conversion
SAR = successive approximation register SAR = successive approximation register
S/H = sample and hold circuit
Vin = input voltage
Vref = reference voltage Vref = reference voltage
 use a binary search to converge on the
closest quantisation level
 Binary search:
V
AX
 Binary search:
 select middle element
 If too high select middle element of lower group
 If too low select middle element of upper group  If too low select middle element of upper group
 Repeat until 1 element remains
 Constant conversion time (n cycles)
54
EIM Chap 2 Analog to digital converter
Successive approximation algorithm
B
i
t
2
=
0
B
i
t
2
=
0
B
i
t
3
=
1
B
i
t
4
=
0
V
DAC
B
i
t
3
=
1
B
i
t
1
=
1
T nT =
conv CK
T nT =
4 Bit SAC
Slower than Flash, but far fewer comparators
allows for higher accuracy
55
allows for higher accuracy
EIM Chap 2 Analog to digital converter
Delta  encoded ADC (tracking ADC)
an updown counter feeds the DAC;
_
CK
CMP R
sens
Num. rev.
Up/Dw
UP/DOWN
an updown counter feeds the DAC;
CMP compares U
X
and DAC output;
CMP drives U/D counter sens ;
+
_
N
CK
CMP
U
x
n
n
n
[z]
R
I(N)
sens
UP/DOWN
Counter
use a feedback to adjust the counter;
very wide range and high resolution;
conversion time is dependent of the input signal level (has a guaranteed value
CNA
R I(N)
I
DAC
conversion time is dependent of the input signal level (has a guaranteed value
for the worst case);
introduces granular noise for constant and very low frequency signals; introduces granular noise for constant and very low frequency signals;
can expect overflow error for rapid variable signal;
Granular
noise
Overflow
56
EIM Chap 2 Analog to digital converter
Ramp Compare ADC
A comparison voltage V(N) is ramped up;
FC
CK
EOC
A comparison voltage V(N) is ramped up;
When the comparison voltage matches
the sampled voltage (VA) the comparator is
triggered the sampled voltage has been
+
_
N
SC
CMP
U
x
n
z
NUM
triggered the sampled voltage has been
determined;
Variable Conversion Time (depends when
ramp signal matches actual signal):
CNA
V(N) V
R
N
DAC
ramp signal matches actual signal):
 Best case = 1 cycle
 Worst case = 2
n
cycles
U
X
V(N)
 Worst case = 2
n
cycles
Slower than SAR, same accuracy;
57
EIM Chap 2 Analog to digital converter
Sigmadelta ADC
the output is in the form of a 1 bit serial the output is in the form of a 1 bit serial
bit stream;
analog input variation proportional to
the duty of the output digital signal;
Oversampling (sampling freq 16 512 Oversampling (sampling freq 16 512
times greater than Nyquist rate);
low complexity;
presents granular noise for constants
Sigmadelta ADC of the first order
presents granular noise for constants
and possible overflow error for fast
analog input;
applications: typical low bandwidth applications: typical low bandwidth
digital transmission 22KHz(voice in digital
telephone network); recently  ADSL
network access, 12MHz (multibit ADC
and multibit feedback DAC ); digital and multibit feedback DAC ); digital
audio equipment (1624 bit resolution,
48kS/s);
Oversampling ADC ( ADC)
58
Oversampling ADC ( ADC)
EIM Chap 2 Analog to digital converter
Sigmadelta ADC
Quantization noise is Quantization noise is
pushed out of the signal
band;
digital filter eliminates digital filter eliminates
out of band noise ;
very high SNR
Signal Quant. Noise Signal
spectrum
Quant. Noise
spectrum
59
EIM Chap 2 Analog to digital converter
Sigmadelta ADC
better performances for high order better performances for high order
ADC (second, third, etc.);
changing LPF (integrator) BPF we can changing LPF (integrator) BPF we can
reduce the noise mDSP (N
0
) in band of interest;
Spectral noise shaping SNR vs OSR ()
Second order  ADC
mPSD
Spectral noise shaping SNR vs OSR ()
60
EIM Chap 2 Analog to digital converter
Integrating ADC single slope
similar with ramp  compare ADC, but analog similar with ramp  compare ADC, but analog
devices
contain: voltage comparator, digital counter,
sawtooth wave generator
Sawtooth
Phases:
0. Reset counter and sawtooth wave generator
1. Start conversion (SC) start generator and
counter
Sawtooth
wave gen.
counter
2. Finish conversion (FC) When the comparison
voltage (analog input) matches the output
generator the conversion finish and stop the
U
X
generator the conversion finish and stop the
counter:
Variable Conversion Time (depends when ramp
X X
N k U =
Variable Conversion Time (depends when ramp
signal matches actual signal):
 Best case = 1 cycle
 Worst case = 2
n
cycles
61
 Worst case = 2 cycles
EIM Chap 2 Analog to digital converter
Integrating ADC dual slope
2 , ' = =
n
T T T N T
1 2
2 , ' = =
n
CK CK
T T T N T
( )
1 1
R
0
1 1
d = d
+
X
T T t
x
T
U t t V t
RC RC
1
0 T
RC RC
( )
( )
1
1
'
= = 2
2
=
= =
n
x i x
x R i R
n
i
R
U t
t
N
U t V b V N
V T
Absolute values of R and C dont affect operation
Conversion time is given by:
1
1
2
= i
R
V T
( )
+
Digital output word gives average value of U
X
during first integration phase
( )
1
2 ' 2
+
= +
n n
conv CK CK
T N T T
during first integration phase
Can be used to get resolutions exceeding 20 bits
but at lower conversion rates
62
EIM Chap 2 Analog to digital converter
Integrating ADC dual slope with autozero
Phase 1 auto zero
(K
1
=0, K
2
=0)
Phase:
Phase 2 unknown
voltage integrating (K
1
=1,
K
2
=1) K
2
=1)
Phase 3  reference
voltage integrating (K1=2,
K2=2) K2=2)
63
EIM Chap 2 Analog to digital converter
U
Dual slope ADC application: digital voltmeter
U
X
64
EIM Chap 2 Analog to digital converter
U
Functioning principle ICL7106
U
X
Switches Phase 0 Phase 1 Phase 2 Switches Phase 0
(AZ)
Phase 1 Phase 2
INPUT open close open
+REF open open funct. of
V
in
sign
REF open open funct. of
V
in
sign
AUTO
ZERO
close open open
65
EIM Chap 2 Analog to digital converter
ADC with intermediate FM stage
comprise
ADC with intermediate FM stage
U
GI
comprise
a voltagetofrequency converter
a frequency counter to convert
frequency into a digital count frequency into a digital count
( )
0
1
d
P x
V V U t t
R C
=
( )
( )
2
1 1
0
1
0 p
2 1
d
1 1
V =V + d d
P x
T
GI x
T T
V V U t t
R C
U t U t t
R C R C
=
V
1 1
2 1
1
1
1 2 2
1
T T
x GI out
R C R C
R
U U T K f
T T R
= =
+
V
0
66
EIM Chap 2 Analog to digital converter
U
Example Uf converter LM331
Longer integration times allow
U
X
Longer integration times allow
higher resolutions;
the speed of the converter can be
improved by sacrificing resolution; improved by sacrificing resolution;
few analog devices high accuracy
are very popular for low frequency
application with remote analog application with remote analog
sensor;
1
V R
1
2.09V
in S
out
L t t
V R
f
R R C
=
67
EIM Chap 2 Analog to digital converter
Application. Remote analog voltage measurement with LM331
(National Semiconductor)
l inie lunga
(transmi sie la distanta)
Remote transmission
U
U
x
x Uf
fU
Catre fmetru
Tx Tx
to fmetru
1
2.09V
in S
out
L t t
V R
f
R R C
= 2.09
L
out in t t
S
R
V f R C
R
=
68
Catre fmetru
Tx Tx
to fmetru
2.09V
L t t
R R C
S
R
EIM Chap 2 Analog to digital converter
Ultrafast ADC
Pure electronic ADC: CCDADC;
CCDs  ADC
Optical ADC : Timestretch ADC.
CCDs  ADC
ChargedCoupled device (CCD)  sampled analog clocked delay line that
memories the input voltage at the clock impulse (analogical memory);
Typically size 512 stages (samples) and 100MS/s;
An slower ADC quantizes these analogical values;
For greater effective sample rate (400MS/s) are necessary several CCDs
in parallel with staggered clock drive.
Application digital video signal capturing Application digital video signal capturing
69
EIM Chap 2 Analog to digital converter
CCD matrix scheme
Ultrafast ADC
CCD matrix scheme
CCD output waveform
70
EIM Chap 2 Analog to digital converter
CCD  ADC
Ultrafast ADC electronic ADC
CCD  ADC
Correlated double sampling (CDS) minimise
switching noise at output switching noise at output
71
EIM Chap 2 Analog to digital converter
Ultrafast ADC optical ADC
Electronic (pure) realtime analogto digital conversion is limited to onversion
rates of few GS/s;
Communication, image processing and radar applications require extremely
fast real time A/D conversion;
A way out of this conversion bottleneck may be the use of photonic concepts
for A/D conversion;
Concept for ADC optical conversion: Concept for ADC optical conversion:
Photonic time stretching converter;
SelfElectrooptic Effect Device based alloptical A/D conversion;
Optical foldingflash converter; Optical foldingflash converter;
Optoelectronic thyristor based photonic smart comparator;
72
EIM Chap 2 Analog to digital converter
Ultrafast ADC optical ADC (contd)
Absolute analog to digital conversion rate limits for a required SNR
q
Absolute analog to digital conversion rate limits for a required SNR
q
73
EIM Chap 2 Analog to digital converter
Timestretch ADC (TSADC) Digitizes a very wide bandwidth analog
Ultrafast ADC optical ADC
Timestretch ADC (TSADC)
signal by timestretching the signal prior to digitization using a photonic
preprocessor.
Improvements:
Effective sampling rate increased by M ; Effective sampling rate increased by M ;
Effective Input bandwidth increased by M ;
Reduce jitter noise ; Reduce jitter noise ;
Eliminates the need for samples interleaving ;
Ideal for timelimited signals or fast timevarying signals ;
74
EIM Chap 2 Analog to digital converter
Schematic photonic preprocessor for timestretching
Ultrafast ADC optical ADC (contd)
Schematic photonic preprocessor for timestretching
Each ADC see the sloweddown signal;
Full Nyquist sampling by each ADC;
By allowing for finite overlap between segments, mismatch error can be
estimated from the signal itself;
Digitizer
x 4
1
WDM
P
R
I
S
M
Digitizer
x 4
x 4
Digitizer
2
T
P
R
I
S
M
4
x 4
x 4
Digitizer
3
Time
Time/ wavelength
2
T
4T
Time Stretch
x 4
T
Digitizer
4
Flash ADCs
or TIADCs
75
T
4T
Time Stretch
or TIADCs
EIM Chap 2 Analog to digital converter
Ultrafast ADC optical ADC (contd)
Photonic Time Stretch System Photonic Time Stretch System
W
a
v
e
l
e
n
g
t
h
Stretched Signal
Input RF
Signal
W
a
v
e
l
e
n
g
t
h
Time
BW
Chirp
Signal
Dispersion
PD
Modulator
Dispersion
SC
Chirped Optical Pulse
PD
Modulator
L1 L2
Source
SC Optical Pulse
Stretch Factor = 1 + L
2
/ L
1
Time Aperture = D x x L
1
Time Aperture = D x x L
1
Baseband BW* =
Time BW Product* =
RF op
f f 2 /
) 8 /( 1
1 2
L
76
EIM Chap 2 Analog to digital converter
Ultrafast ADC optical ADC (contd)
Mismatches in TS Mismatches in TSADC Arrays ADC Arrays
Offset
Mismatch
T
seg
=
=
1
0
) (
2
) (
L
k
s
k
s
L
k
F
T
S
Analog Signal
Mismatch
Gain
=0 k
s
2
1
k
L
=
L
N k
j
L
k
L
kN
M
km
j b
L
F
M
m
m k
) 1 (
exp
sin
sin
)
2
exp(
1
1
0
Gain
Mismatch ) (
2
) (
1
0
L
k
F
T
S
s
o
L
k
k
s
=
Clock
Skew
=
=
k
s
k
s
L
k
F
T
S ) (
1
) (
0
=
L
N k
j
L
k
L
kN
M
km
j T r j
L
F
M
m
s m k
) 1 (
exp
sin
sin
)
2
exp( ) exp(
1
1
0
0