Ferroelectric RAM

From Wikipedia, the free encyclopedia This article is about an information storage medium. For other uses, see Fram (disambiguation). Computer memory types Volatile • RAM o DRAM (e.g., DDR SDRAM) o SRAM • In development o T-RAM o Z-RAM o TTRAM • Historical o Delay line memory o Selectron tube
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Williams tube Non-volatile

ROM Mask ROM PROM EPROM EEPROM Flash memory Early stage o FeRAM o MRAM o PRAM In development o CBRAM o SONOS o RRAM o Racetrack memory o NRAM o Millipede memory Historical o Drum memory o Magnetic-core memory o Plated wire memory o Bubble memory
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Twistor memory

Ferroelectric RAM (FeRAM or FRAM[1]) is a random-access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility.2 Power consumption o 3. as well as specialized chips (e. Work was done in 1991 at NASA's Jet Propulsion Laboratory on improving methods of read out.3 Performance 4 Overall 5 See also 6 References 7 External links [edit] History Ferroelectric RAM was proposed by MIT graduate student Dudley Allen Buck in his master's thesis. FeRAM is one of a growing number of alternative non-volatile memory technologies that offer the same functionality as Flash memory. Ferroelectrics for Digital Information Storage and Switching. University of Toronto. Hynix. Cambridge University. One major licensee is Fujitsu. Disadvantages of FeRAM are much lower storage densities than Flash devices.g.[4] Much of the current FeRAM technology was developed by Ramtron.1 Density o 3. In the fall of 2005.[3] Development of FeRAM began in the late 1980s. faster write performance[2] and a much greater maximum number (exceeding 1016 for 3. chips for smart cards) with embedded FeRAMs within. who operate what is probably the largest semiconductor foundry production line with FeRAM capability. Fujitsu and Seiko-Epson were in 2005 collaborating in the development of a 180 nm FeRAM process. Fujitsu produces devices for Ramtron. a fabless semiconductor company. and the Interuniversity Microelectronics Centre (IMEC. [edit] Description . including a novel method of nondestructive readout using pulses of UV radiation. Contents [hide] • • • • • • • 1 History 2 Description 3 Comparison with other systems o 3. Since at least 2001 Texas Instruments has collaborated with Ramtron to develop FeRAM test chips in a modified 130 nm process. Infineon. Oki. Matsushita. Since 1999 they have been using this line to produce standalone FeRAMs. Belgium). and higher cost. FeRAM advantages over Flash include: lower power usage. storage capacity limitations. Symetrix.3 V devices) of write-erase cycles. FeRAM research projects have also been reported at Samsung. Toshiba. Ramtron reported that they were evaluating prototype samples of an 8-megabit FeRAM manufactured using Texas Instruments' FeRAM process. published in 1952.

transistor. draining the cell to write a "0". once the cell has been read. DRAM cells scale directly with the size of the semiconductor fabrication process being used to make it. Since this process overwrites the cell. A ferroelectric material has a nonlinear relationship between the applied electric field and the apparent stored charge. is somewhat different than in DRAM. Specifically. in the figure a "1" is encoded using the negative remnant polarization "-Pr". and some amount of "blank space" between the various parts — it appears 35% utilization is typical. Reading. If it did hold a "1. a cell. Writing is accomplished by activating the associated control transistor.Conventional DRAM consists of a grid of small capacitors and their associated wiring and signaling transistors. the transistor is again activated. and requires the cell to be re-written if it was changed. the ferroelectric characteristic has the form of a hysteresis loop. The dielectric constant of a ferroelectric is typically much higher than that of a linear dielectric because of the effects of semi-permanent electric dipoles formed in the crystal structure of the ferroelectric material. produced by small shifts in the positions of atoms and shifts in the distributions of electronic charge in the crystal structure. which is very similar in shape to the hysteresis loop of ferromagnetic materials. If the cell held a "1". Writing is accomplished by applying a field across the ferroelectric layer by charging the plates on either side of it. reading FeRAM is a destructive process. a so-called "1T-1C" device.22 μm². For instance. however. When an external electric field is applied across a dielectric. leaving 65% of the space wasted. with the lack of charge in general representing "0". which includes the capacitor. draining the charge to a sense amplifier. FeRAM is similar to DRAM. on the 90 nm process used by most memory providers to make DDR2 DRAM. forcing the atoms inside into the "up" or "down" orientation (depending on the polarity of the charge). If the cell already held a "0". the cell held a charge and thus reads "1". In a DRAM cell capacitor. For example. In terms of operation. say "0". The presence of this pulse means the cell held a "1". the dipoles tend to align themselves with the field direction. The transistor forces the cell into a particular state. . Each storage element. nothing will happen in the output lines. The 1T-1C storage cell design in an FeRAM is similar in construction to the storage cell in widely used DRAM in that both cell types include one capacitor and one access transistor. or sending current into it from a supply line if the new value should be "1". the cell size is 0. the lack of such a pulse indicates a "0". Note that this process is destructive. Reading is similar in nature. whereas in an FeRAM cell capacitor the dielectric structure includes ferroelectric material. After the charge is removed. Binary "0"s and "1"s are stored as one of two possible electric polarizations in each data storage cell. typically lead zirconate titanate (PZT). a linear dielectric is used. the dipoles retain their polarization state. Data in a DRAM is stored as the presence or lack of an electrical charge in the capacitor. the re-orientation of the atoms in the film will cause a brief pulse of current in the output as they push electrons out of the metal on the "down" side. and a "0" is encoded using the positive remnant polarization "+Pr". If a pulse of charge is noticed in the amplifier." it must be re-charged to that value again. thereby storing a "1" or "0". it must be actively refreshed at intervals. wiring. Since a cell loses its charge after some time due to leak currents. consists of one capacitor and one transistor.

In comparison. the technology that scales to the smallest cell size will end up being the least expensive per bit. FeRAM and DRAM are similar. and fewer of them. In terms of construction. This improves yield. the operation of FeRAM is similar to ferrite core memory. [edit] Comparison with other systems [edit] Density The main determinant of a memory system's cost is the density of the components used to make it up. and can in general be built on similar lines at similar sizes. In both cases. FeRAM requires far less power to flip the state of the polarity. means that more cells can be packed onto a single chip. the lower limit seems to be defined by the amount of charge . and does so much faster. one of the primary forms of computer memory in the 1960s. The lower limit to this scaling process is an important point of comparison. Smaller components.In general. Structure of a 1 transistor FeRAM cell and its working mechanism. which in turn means more can be produced at once from a single silicon wafer. which is directly related to cost. In general. Structure of a FeRAM cell.

every cell must be periodically read and then re-written. but this limitation has since been removed. Another non-volatile memory type is Flash RAM. as the charge density of the PZT layer may not be the same as the metal plates in a normal capacitor. uses molecular adsorbates. since power has to flow into the cell for reading and writing. for example. In DRAM. An additional limitation on size is that materials tend to stop being ferroelectric when they are too small. and the heat that power generates. as the write power in FeRAM is only marginally higher than reading. this appears to be a problem at around 55 nm.needed to trigger the sense amplifiers. However. For a "mostly-read" device the difference might be slight. FeRAM only requires power when actually reading or writing a cell. [edit] Power consumption The key advantage to FeRAM over DRAM is what happens between the read and write cycles. this means that FeRAM could be much faster than DRAM.[5] To date. Each cell must be refreshed many times every second (~65 ms[7]) and this requires a continuous supply of power. at least for writing.) There is ongoing research on addressing the problem of stabilizing ferroelectric materials. In order for a DRAM to store data for anything other than a microscopic time. one approach. [edit] Performance DRAM performance is limited by the rate at which the charge stored in the cells can be drained (for reading) or stored (for writing). but for devices with more balanced read and write the difference could be expected to be much higher. In general. indicating power usage about 99% lower than DRAM.[5][6] (This effect is related to the ferroelectric's "depolarization field". the charge deposited on the metal plates leaks across the insulating layer and the control transistor. and disappears. a process known as refresh. which are built up in a charge pump over time. leading to very low densities. the capacitance of the lines carrying power to the cells. This process requires high voltages. It is not clear as to whether FeRAM can scale to the same size. In contrast. This means that FeRAM could be expected to be lower power than Flash. In theory. settling in about 1 ns. Flash works by pushing electrons across a high-quality insulating barrier where they get "stuck" on one terminal of a transistor. . the commercial FeRAM devices have been produced at 350 nm and 130 nm. Early models required two FeRAM cells per bit. and like FeRAM it does not require a refresh process. For DRAM. FeRAM is based on the physical movement of atoms in response to an external field. The vast majority of power used in DRAM is used for refresh. this ends up being defined by the capability of the control transistors. so it seems reasonable to suggest that the benchmark quoted by TTR-MRAM researchers is useful here too. at which point the charge stored in the capacitor is too small to be detected. which happens to be extremely fast.

As a consequence. reducing the cell size may cause the data signal to become to too weak to be detectable. Although slow compared to modern DRAMs.7 million. printers. perhaps the largest FeRAM vendor. the integration of FeRAM on microcontrollers. which limits current somewhat. whereas FeRAM would have been written to before the charge would have drained. However. The theoretical performance of FeRAM is not entirely clear. Flash typically requires nine masks. automotive (e. [edit] Overall FeRAM remains a relatively small part of the overall semiconductor market. In 2005. there is a delay in writing because the charge has to flow through the control transistor. business machines (e. the areal bit densities of flash memory are much higher than those of FeRAM.[citation needed] The 2005 annual sales of Ramtron. whereas current FeRAMs may complete a write in less than 150 ns. In 2005. and thus the cost per bit of flash memory is orders of magnitude lower than that of FeRAM. Ramtron reported significant sales of its FeRAM products in a variety of sectors including (but not limited to) electricity meters[9]. may seek to enter similar niche markets in competition with FeRAM. such as the development of vertical capacitor structures (in the same way as DRAM) to reduce the area of the cell footprint. This makes it possible for example. The much larger sales of flash memory compared to the alternative NVRAMs support a much larger research and development effort. because DRAMs need to hold the charge.the electrical and switching delays would likely be similar to DRAM overall. RAID disk controllers). and the number of bits per flash cell is projected to increase to 4 or even to 8 as a result of innovations in flash cell design.g. smart air bags). the advantages are much more obvious.[8] so FeRAM performance appears to be comparable given the same fabrication technology. were reported to be US $32. medical equipment.6 billion (according to IC Insights). worldwide semiconductor sales were US $235 billion (according to the Gartner Group). common 350 nm DRAMs operated with a read time of about 35 ns. Flash memories commonly need a millisecond or more to complete a write. a process that FeRAM does not need. Whereas the read operation is likely to be similar in performance. The density of FeRAM arrays might be increased by improvements in FeRAM foundry process technology and cell structures. Existing 350 nm devices have read times on the order of 50-60 ns. Flash memory is produced using semiconductor linewidths of 30 nm at Samsung (2007) while FeRAMs are produced in linewidths of 350 nm at Fujitsu and 130 nm at Texas Instruments (2007). Flash memory cells can store multiple bits per cell (currently 3 in the highest density NAND flash devices). black boxes. In comparison to Flash. The other emerging NVRAMs. and radio frequency identification tags. the charge pump used for writing requires a considerable time to "build up" current. instrumentation. with the flash memory market accounting for US $18. Texas Instruments proved it to be possible to embed FeRAM cells using two additional masking steps[citation needed] during conventional CMOS semiconductor manufacture.g. However. which can be found with times on the order of 2 ns. industrial microcontrollers. such as MRAM. It does seem reasonable to suggest that FeRAM would require less charge than DRAM. .

However. the materials used to make FeRAMs are not commonly used in CMOS integrated circuit manufacturing. Both the PZT ferroelectric layer and the noble metals used for electrodes raise CMOS process compatibility and contamination issues. [10] . Texas Instruments have incorporated an amount of FRAM memory into its MSP430 microcontrollers in its new FRAM series.where a simplified process would reduce costs.

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