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LALITH KARSANI, B.E.
Submitted to the Graduate Faculty
of Texas Tech University in
Partial Fulfillment of
the Requirements for
the Degree of
MASTER OF SCIENCE
Kwong S. Chao
Chairperson of the Committee
Dean of the Graduate School
It has been a great privilege to be a graduate student in the Electrical and
Computer Engineering department at the Texas Tech University and work closely with
my advisor Prof. Dr. Kwong S. Chao. His keen insight into system and integrated circuit
design is the key factor in the success of this research. I would also like to thank Prof. Dr.
Sunanda Mitra, for her willingness to serve in my committee.
I greatly appreciate my colleagues in Dr. Chao’s group for the numerous technical
discussions. I would like to thank Chintan Trehan who has worked closely with me in the
past two years. He is a person who would never run out of ideas. I thank my friends for
all the encouragement and support.
The financial assistance in the form of scholarship from Electrical and Computer
Engineering department is appreciated. I would also like to acknowledge and appreciate
the financial assistance provided by Lucia S. Barbato, Senior Research Associate, Center
for Geospatial Technology.
I am grateful to my parents for their love and support in my whole life. Their
confidence in me and their high expectation of me are the driving forces for completion
of this work.
TABLE OF CONTENTS
LIST OF FIGURES vi
I. INTRODUCTION 1
1.1 Motivation 1
1.2 Organization of the Thesis 5
1.3 Terms used in PLL Literature 5
1.4 Types of PLL 7
1.4.1 ADPLL 8
II. BASIC BUILDING BLOCKS 9
2.1 Phase detector 10
2.2 Voltage controlled oscillator 11
2.3 Loop filter 13
2.4 Charge pump 13
2.5 Bandwidth of PLL 15
III. PROPOSED ARCHITECTURE 18
3.1 Dual feedback frequency synthesizer 18
3.1.1 Operation of FVC loop 21
3.1.2 Effect of FVC on the synthesizer system 22
3.2 Loop parameter design 24
IV. CIRCUIT LEVEL DESIGN OF THE
PROPOSED ARCHITECTURE 27
4.1 Phase frequency detector 27
4.2 Charge pump 32
4.2.1 Buffer Stages 34
4.2.2 Current Sources 35
4.3 Voltage controlled oscillator 35
4.4 Loop filter 41
4.5 Divider 43
4.6 Frequency-to-Voltage Converter 46
4.6.1 Pulse-to-Digital Converter 47
4.6.2 Digital-to-Analog Converter 51
4.7 Dual-loop frequency synthesizer 58
V. SIMULATIONS AND RESULTS 61
VI. CONCLUSIONS AND FUTURE WORK 70
VII. REFERENCES 71
A dual-loop frequency synthesizer is proposed to reduce the phase noise
introduced by the Voltage Controlled Oscillator (VCO) which is the main source of noise
in a traditional PLL-based frequency synthesizer. The focus of this thesis is on the
analysis and simulation of the proposed dual-loop frequency synthesizer architecture and
comparison of results with that of the standard frequency synthesizer. Instead of the
traditional PLL-based frequency synthesizer with a single feedback loop from the VCO
output through a divider back to the phase detector, an additional feedback path from the
VCO output through a Frequency-to-Voltage Converter (FVC) to the input of the loop
filter is introduced. Results show considerable improvement in the phase noise
performance and the lock time. The improved performance can be attributed to noise
suppression in the loop for reasons similar to a sigma-delta modulator. Due to this
improved noise performance, a dual-loop frequency synthesizer is suitable for
applications which require high phase noise suppression.
LIST OF FIGURES
1.1 PLL-based frequency synthesizer 2
1.2 First-order sigma-delta modulator 3
1.3 Second-order sigma-delta modulator 3
1.4 Equivalent of Second-order sigma-delta modulator 4
1.5 Dual-loop frequency synthesizer 4
1.6 Scope of static and dynamic limits of stability of a PLL 7
1.7 All digital phase locked loop 8
2.1 A basic phase locked loop synthesizer 9
2.2 Phase detector characteristic 10
2.3 Signal flow model of phase detector 11
2.4 VCO characteristic 12
2.5 Signal flow model of VCO 13
2.6 Charge pump 14
2.7 Average current vs. phase error plot 15
2.8 Linear model of a PLL 16
3.1 Desired frequency spectrum of synthesizer 18
3.2 Measured frequency spectrum of synthesizer 19
3.3 Sources of noise in synthesizer 20
3.4 Block diagram of FVC 22
3.5 Dual-loop synthesizer model 22
3.6 Noise transfer function of dual-loop synthesizer 23
3.7 Magnitude plot of FVC noise 24
3.8 Loop filter response curve 25
4.1 Implementation of phase frequency detector 27
4.2 Positive edge-triggered D-flip-flop with reset 28
4.3 Two-input NOR gate 29
4.4 State diagram of PFD 30
4.5 Dead zone in PFD 31
4.6 Two-input AND gate 32
4.7 Charge pump implementation 33
4.8 Inverter schematic 34
4.9 VCO differential cell 36
4.10 Voltage controlled oscillator schematic 37
4.11 VCO transfer characteristic curve with out self bias 38
4.12 VCO transfer characteristic curve with self bias 39
4.13 Power spectral density of VCO 40
4.14 Periodic phase noise response 41
4.15 Second-order passive lead-lag filter 42
4.16 Magnitude and phase response of loop filter 43
4.17 T-flip-flop and its input-output waveforms 44
4.18 Divide-by-32 circuit 45
4.19 Waveforms of divide-by-32 circuit 45
4.20 Frequency-to-Voltage Converter 46
4.21 Characteristic curve of FVC 47
4.22 Pulse generating circuit 48
4.23 Output of pulse generating circuit 49
4.24 4-bit counter 50
4.25 Pulse-to-Digital Converter 51
4.26 Digital-to-Analog Converter 52
4.27 Two-stage op-amp 53
4.28 AC response of op-amp 55
4.29 Step response of op-amp 56
4.30 Characteristic curve of DAC 57
4.31 Complimentary CMOS switch 58
4.32 Implemented PLL-based frequency synthesizer 59
4.33 Implemented dual-loop frequency synthesizer 60
5.1 VCO control voltage for PLL-based frequency synthesizer 61
5.2 VCO control voltage for dual-loop frequency synthesizer 62
5.3 Ripple in control voltage after lock for PLL-based frequency synthesizer 63
5.4 Ripple in control voltage after lock for dual-loop frequency synthesizer 64
5.5 Lock-in process of reference and VCO frequencies 65
5.6 PSD of VCO output for PLL-based frequency synthesizer 66
5.7 Zoom-in of Figure 5.6 67
5.8 PSD of VCO output for dual-loop frequency synthesizer 68
5.9 Zoom-in of Figure 5.8 69
Phase Locked Loops (PLL) find wide applications in areas such as
communications, wireless systems, digital circuits, and disk drive electronics. While the
concept of phase locking has been in use for more than half a century, monolithic
implementation has become possible only around 1965. A few years later the first digital
PLLs became available. Recent advances in integrated circuit design techniques have led
to an increased use of the PLL as it has become more economical and reliable.
A PLL is a circuit synchronizing an output signal with a reference or input signal
in frequency as well as in phase. It can be considered as a negative feedback control
system. The basic building blocks of PLL are Phase Detector (PD), Loop Filter (LF) and
Voltage Controlled Oscillator (VCO)
The PD is a circuit capable of delivering an output signal that is proportional to
the phase difference between its input signal and the feedback signal. This output signal
of PD consists of a dc component and a superimposed ac component. The latter is
undesired, hence it is canceled by the loop filter. In most cases a first-order, low-pass
filter is used. This dc control voltage from the loop filter controls the VCO output
frequency. Due to the negative feedback, the loop will make sure the output signal is in
phase with the reference signal. When this happens the phase error between the input and
output frequencies is zero and PLL is said to be in lock.
As long as the initial difference between the input signal and the VCO is not too
big, the PLL eventually locks onto the input signal. This period of frequency acquisition,
is referred to as pull-in time, which depends on the bandwidth of the PLL. The bandwidth
of a PLL depends on the characteristics of the phase detector, voltage controlled
oscillator and on the loop filter.
The above described architecture with a divider in the feedback is widely used as
a frequency synthesizer and is shown in Figure 1.1. PLL can be thought of as a
synthesizer with output frequency equal to reference frequency. Most of the research in
this field is done on optimizing individual building blocks to get better performance. The
most important component with respect to noise in a PLL is the oscillator. Digital PLL
(DPLL) is more suitable for implementation on an integrated circuit than the linear PLL.
Digital versions of VCO are called Digital Controlled Oscillator (DCO). But DCO is
more prone to phase noise than VCO. So, it is more important to suppress this phase
noise in DPLL than Linear PLL (LPLL).
Figure 1.1: PLL-based frequency synthesizer
If we look at the noise suppression in a phase locked loop closely it is similar to a
first-order Sigma-Delta Modulator (SDM). Let us look at how SDM works. As the name
implies in a SDM the input is integrated (sigma) prior to delta modulation coding. The
signal amplitude remains constant with the increasing frequency, hence SDM is also
known as pulse density modulation (PDM). In SDM the signal is quantized directly and
not its derivative as in Delta Modulation (DM). Hence maximum quantizer range is
determined by the maximum signal amplitude and is not dependent on the signal
spectrum. The SDM is achieved by over-sampling the input data and shaping the
quantization noise. The complete literature for SDM can be found in . A first-order
sigma-delta modulator is shown in Figure 1.2. We can observe the similarity in
architectures of Figures 1.1 and 1.2.
Figure 1.2: First-order sigma-delta modulator
The noise introduced by a VCO can be compared to the quantization noise of a
SDM. For better noise shaping, a second-order SDM can be utilized as shown in Figure
1.3. This structure is equivalent to the introduction of another feedback with an additional
integrator and DAC as shown in Figure 1.4.
Figure 1.3: Second-order sigma-delta modulator
Figure 1.4: Equivalent of Second-order sigma-delta modulator
Similarly, the proposed structure of a dual-loop frequency synthesizer has a
feedback path from output to the loop filter output as shown in Figure 1.5. The use of
feedback implies a conversion from the frequency to the voltage using a Frequency-to-
Voltage Converter (FVC). This introduces more noise due to additional circuitry, but this
noise of high frequency can be reduced by the feedback loop.
Figure 1.5: Dual-loop frequency synthesizer
The proposed architecture is simulated in SIMULINK and the design is verified
by transistor level implementation and simulations using cadence.
1.2 Organization of the Thesis
The remainder of the thesis is organized as follows. The remainder of this chapter
introduces common terms used in PLL literature and different types of PLL. Chapter 2
discusses basic building blocks of PLL and frequency synthesizer. It also explains the
effect of bandwidth on PLL performance. Chapter 3 consists of the proposed architecture
and the design problems associated with it. Design procedures for the dual-loop
frequency synthesizer circuit and its implementation at circuit level are explained in
Chapter 4. Chapter 5 compares the simulation waveforms of PLL-based frequency
synthesizer and dual-loop frequency synthesizer, the results show definite improvement
of phase noise suppression in dual-loop frequency synthesizer. Finally, conclusions and
the future work related to the improved performance of proposed frequency synthesizer
are included in Chapter 6.
1.3 Terms used in PLL literature
Let us look at some common terms used in PLL literature .
- Center frequency: This is the frequency at which the loop VCO operates when not
locked to an input signal. It is also called the free running frequency of the VCO.
- Lock-in process: The process in which the PLL system acts to reduce the phase
difference between the two input signals is called lock-in process.
- Lock time: This is the time the PLL needs to get locked when the acquisition
process is a lock-in process.
- Pull-in process: The process in which the PLL system acts to reduce the
frequency difference between the two input signals is called pull-in process.
- Pull-in time: This is the time the PLL needs to get locked when the acquisition
process is a pull-in process.
- Hold range: This is the frequency range in which a PLL can statically maintain
phase tracking. A PLL is conditionally stable only within this range.
- Pull-out range: This is the dynamic limit for stable operation of a PLL. If tracking
is lost within this range, a PLL normally will lock again, but this process can be
slow if it is a pull-in process.
- Pull-in range: This is the range within which a PLL will always become locked,
but the process can be rather slow.
- Lock range: This is the frequency range within which a PLL locks within one
single beat note between reference frequency and output frequency. Normally the
operating frequency range of a PLL is restricted to the lock range. It is sometimes
referred to as capture range.
Figure 1.6 is the graphical representation of the above parameters .
Figure 1.6: Scope of static and dynamic limits of stability of a PLL
1.4 Types of PLL
The first PLL ICs appeared around 1965 and consisted of analog components. An
analog multiplier was used as the phase detector, the loop filter was built from a passive
or active RC filter, and the voltage-controlled oscillator (VCO) was used to generate the
output signal of the PLL. This type of PLL is referred to as the Linear PLL (LPLL). In
the following years the PLL drifted slowly but steadily into digital domain. The very first
Digital PLL (DPLL), which appeared around 1970, was in effect a hybrid device: only
the phase detector was built from a digital circuit, e.g., from an EXOR gate or a JK-flip
flop, but the remaining blocks were still analog. A few years later, the all-digital PLL
(ADPLL) was introduced. The ADPLL is exclusively built from digital function blocks
and hence does not contain any passive components such as resistors and capacitors. PLL
can also be implemented by software. In this case, the function of the PLL is no longer
performed by a piece of specialized hardware, but rather by a computer program. This is
referred to as Software PLL (SPLL). We will talk more about the digital PLL in later
chapters, for now let us look at ADPLL in some detail.
ADPLL consists exclusively of logical devices. A signal within an ADPLL can be
binary signal or a word signal. To realize an ADPLL, all functional blocks of the system
must be implemented by digital circuitry. Digital versions of PD will be discussed in the
next chapter. We will now look at digital circuits for loop filter and for VCO. The digital
counterpart of the VCO is the digital controlled oscillator (DCO).
The widely used loop filter is built from an up/ down counter. The up/ down
counter loop filter preferably operates in combination with a PD delivering UP and DN
pulses, such as the PFD. A pulse forming circuit is first needed to convert the incoming
UP and DN pulses into a counting clock and a direction signal UP/ DN. On each UP
pulse generated by the PD, the content N of the up/ down counter is incremented by 1. A
DN pulse will decrement N in the same manner. The content N is the output of the loop
filter and it is the control word for the DCO to generate proportional frequencies.
The simplest DCO is the down(DN) counter. A DN counter is used to scale down
the signal generated by a high-frequency oscillator operating at a fixed frequency. The N-
bit parallel output signal of a digital loop filter is used to control the scaling factor N of
the DN counter. One of the possible ADPLL structures is shown in Figure 1.7 .
Figure 1.7: All digital phase locked loop
BASIC BUILDING BLOCKS
A PLL is a feedback control system that operates on the excess phase of
nominally periodic signals. Shown in Figure 2.1 is a simple PLL, consisting of three
basic blocks Phase Detector (PD), Low-Pass Filter (LPF) and Voltage Controlled
Figure 2.1: A basic phase locked loop synthesizer
A PD serves as an error amplifier in the feedback loop, thereby minimizing the
phase difference, Ao, between
f . The loop is considered locked if Ao is
constant with time, a result of which is that the input and output frequencies are equal.
In the locked condition, all the signals in the loop have reached a steady state. The
PD produces an output whose dc value is proportional to Ao. The low-pass filter
suppresses the high-frequency components in the PD output, allowing the dc value to
control the VCO frequency. The VCO then oscillates at a frequency equal to the input
frequency and with a phase difference equal to Ao. Thus, the LPF generates the proper
control voltage for the VCO. Before examining the overall loop operation, let us discuss
the three main functional blocks in some detail.
2.1 Phase detector
The role of a phase detector in a PLL is to generate an error signal proportional to
the phase error between the input signal and the VCO output signal. Let u
phase difference between the input phase and the VCO phase. In response to this phase
difference the PD produces a proportional voltage v
. The relation between voltage v
and the phase difference u
is shown in Figure 2.2 . The curve is linear and periodic, it
repeats every 2t radians. This periodicity is necessary as a phase of zero is
indistinguishable from a phase of 2t.
Figure 2.2: Phase detector characteristic
The slope of the curve gives the gain of PD, and is given by
A simple PD can be modeled by the following equation
do e d d
v k v + =
This is represented by the block diagram in Figure 2.3.
Figure 2.3: Signal flow model of phase detector
There are many ways to implement a PD circuit. In LPLL a multiplier is used as
PD. In the more popular DPLL mainly three types of phase detectors are used EXOR
gate, JK flip-flop and Phase Frequency Detector (PFD).
EXOR and JK flip-flop output gives information about the phase difference
between input signals, but don’t have any information about the frequency difference.
They are used anyway for the ease of implementation. More popular PD is PFD, which as
the name implies detects the difference in phase as well as frequency between input
2.2 Voltage controlled oscillator
A Voltage Controlled Oscillator (VCO) is a circuit whose output frequency e
linearly proportional to the control voltage
V generated by the phase detector. A typical
characteristic of a VCO is shown in Figure 2.4.
Figure 2.4: VCO characteristic
Ideally the slope of the curve is constant. As the control voltage varies from 0 to
V volts, the output frequency of the VCO varies from
. Outside this range the
curve may not be linear and the VCO performance becomes non-linear. Depending on the
requirements of the circuit, the range can be selected such that the circuit always remains
in its linear range. The slope of the curve is the VCO gain K
and is given by
A simple VCO can be modeled by the following equation
0 co c
v v k ÷ = A
This is represented by the block diagram in Figure 2.5
Figure 2.5: Signal flow model of VCO
2.3 Loop filter
The output of a PD consists of a dc component superimposed with ac component,
latter being undesirable. The loop filter is basically a low-pass filter at the output of the
PD to filter out the undesired ac component. Loop filter is the most important block in the
loop which determines the overall performance of the PLL. A loop filter introduces poles
in the PLL transfer function, which in turn determine the bandwidth of the PLL. Since
higher order loop filters offer better noise cancellation, we tend to go for higher order
filters. But higher order filters make the loop unstable, so the filter order is limited to first
or second in most of the PLL circuits.
2.4 Charge pump
In the low-pass filter the average value of the PD output is obtained by depositing
charge onto a capacitor during each phase comparison and allowing the charge to decay.
In a charge pump, on the other hand, there is negligible decay of charge between phase
comparison instants. Charge pump consists of two switched current sources driving a
capacitor as shown in Figure 2.6 .
Figure 2.6: Charge pump
Charge pump is used mostly with PFD. In Figure 2.6, let Q
be the UP
and DN outputs of PFD representing the pulse width by which one input of the PFD leads
or lags the other input signal and I
is the charge pump current.
Each field effect transistor (FET) acts as a simple switch that closes when its input
goes high. Hence the output goes high when Q
goes high, and it is grounded when Q
goes high. The output current of charge pump, I
is thus a logical function of the PFD
state. When PFD is in state 1,
I must be positive, and when PFD is in state 2, I
negative. For state 0, I
will be zero. If we plot the average I
vs. phase error u
sawtooth function is obtained as shown in Figure 2.7.
Figure 2.7: Average current vs. phase error plot
The curve is linear between -2t to 2t, and then repeats every 2t. If the phase
exceeds 2t, the PFD behaves as if the phase error is rotated back to zero. Hence
it is a periodic curve with a period of 2t. The gain of PFD is calculated as
K = (2.5)
2.5 Bandwidth of PLL
The bandwidth of a PLL determines how fast a PLL output will track the input
frequency. This parameter is dependent on the characteristics of PD, VCO and the loop
filter. Since the bandwidth is associated with the ac model, let us consider an ac model of
PLL which is shown in Figure 2.8 .
Figure 2.8: Linear model of a PLL
The VCO can be represented by an integrator whose transfer function is 1/ s, where s
represents complex frequency. The closed loop transfer function H(s) is
) ( 1
K K K
h d 0
) ( =
The bandwidth e
occurs when 1 ) ( = j G . From the above equation, this occurs
= K = K
The bandwidth of the PLL is thus determined by
- Gain of PD, K
- High frequency gain of loop filter, K
- Gain of VCO, K
The designs of PD and VCO are usually less flexible. The design of the loop filter
is the principle tool in selecting the bandwidth of the PLL. The selection of loop
bandwidth forces trade offs in the frequency acquisition speed. Since PLL pull-in speed is
a function of the loop bandwidth, the simplest method for improving the lock time is to
widen the loop bandwidth. Wider bandwidth improves the lock time but at the same time
it degrades the noise characteristics of the loop. So an optimum bandwidth has to be
achieved depending on the requirements.
3.1 Dual feedback frequency synthesizer
In the design of a PLL frequency synthesizer, we hope to get a nicely clean output
signal with high frequency stability and no phase jitter. Ideally the spectrum of the
synthesizer’s output signal should consist of just one single line at the desired frequency
as shown in Figure 3.1.
Figure 3.1: Desired frequency spectrum of synthesizer
Unfortunately, when measuring the signal spectrum, we may observe phase jitters
and sidebands or spurs around the desired center frequency as shown in Figure 3.2.
Figure 3.2: Measured frequency spectrum of synthesizer
Every module of the synthesizer circuit can contribute to output phase noise.
There are basically four sources of phase jitter and spurs that can be recognized as shown
in Figure 3.3 .
Figure 3.3: Sources of noise in synthesizer
These are the phase jitter created by the reference oscillator (
), the phase
jitter created by the VCO (
), the ripple signal at the input of VCO due to backlash
U ) and the divider noise.
These noise sources can be broadly classified into two types:
- The noise that is low pass filtered by the loop (low frequency noise). The noise
due to the reference oscillator and divider come under this category.
- The noise that is high pass filtered by the loop (high frequency noise). The Phase
noise due to the VCO comes under this category.
In the proposed architecture our concentration is in the reduction of the high
frequency phase noise generated by the VCO without adding any low frequency noise
that would degrade the performance of the loop at lower frequencies.
In the PLLs we have discussed so far, there is only one feedback loop from the
VCO output to the PD. Proposed architecture has dual feedback loops. Second loop
consists of a Frequency-to-Voltage Converter (FVC) and an error amplifier, it has a path
from VCO output to the input of the loop filter. This additional circuitry introduces some
noise in the loop. By analyzing the operation of FVC we can conclude that, the noise due
to the additional circuitry does not degrade the performance of the loop.
3.1.1 Operation of FVC loop
As the name implies, FVC is a frequency to voltage converter. It provides the
output voltage precisely proportional to the input pulse train frequency. There are several
ways to build an FVC aiming for high linearity. Probably, the easiest way to build one
with the required linearity is a counter followed by a Digital-to-Analog Converter (DAC).
The resolution of FVC is limited by the counter clock frequency and the quantization step
size of the DAC. As shown in Figure 3.4, the input to FVC is a frequency which is
divided by a higher frequency clock of the counter. For every rising edge of the input
frequency the counter value is buffered to a register and the counter is reset to zero. The
value stored in the register is fed as the input to the DAC, which converts this digital
word into its respective analog voltage.
Figure 3.4: Block diagram of FVC
3.1.2 Effect of FVC on the synthesizer system
The Dual loop frequency synthesizer model is shown in Figure 3.5.
Figure 3.5: Dual-loop synthesizer model
) 1 (
N-bit Digital Word
Frequency to Voltage Converter
s F = (3.2)
And ’s are selected to 4 5 . 7
÷ = e , 6 9
÷ = e , 6 3 . 1
÷ = e and 6 6 . 3
÷ = e
Now let us analyze the effect of FVC loop on the noise performance of the overall
system. As mentioned earlier, we do not want the additional circuitry to add any noise at
the low frequency. Let us analyze the loop with additional noise from FVC.
Figure 3.6: Noise transfer function of dual-loop synthesizer
The output transfer function can be written as
) ( ) ( ) (
2 2 2 1 1
s F K s F s F K s
s F K
÷ = (3.3)
For small values of s, the equation above approximates to
) ( 1
s F s E
where, the poles and zeros of ) (
s F are selected with
4 5 . 7 ) (
2 1 1
÷ = + = e C C R
1 1 2
÷ = = e C R
6 3 . 1
2 1 1
C C R
To yield the output to noise transfer function
2 ) 6 9 (
) 4 5 . 7 ( ) 10 75 . 9 (
÷ + ÷
e s e s
Figure 3.7 shows the magnitude plot of this transfer function
Figure 3.7: Magnitude plot of FVC noise
It is seen from Figure 3.7, the overall system acts as high-pass filter to the noise added by
3.2 Loop parameter design
The loop bandwidth of the synthesizer needs to be optimized in order to achieve
minimum overall phase noise at the offset frequency where the performance is most
critical. A reference frequency of 705KHz is chosen according to the specification. The
loop bandwidth should be less than 1/10 of the reference frequency for the stability of the
loop. For this design, the loop bandwidth is chosen to be about 70KHz for maximum
suppression of the VCO noise while maintaining low noise from the reference, loop filter
Knowing the desired loop bandwidth, we can determine the RC parameters of the
second order passive lead lag loop filter by leaving enough phase margin for the loop.
Figure 3.8 represents the effect of
on overall loop performance.
Figure 3.8: Loop filter response curve
The system is designed such that
is set one-fourth the value of
four times that of
R K I
z vco cp
p z z
C C R
C C +
This result in following set of values,
R = 12 O K
C = 4.5 nf
C = 250 pf
I = 12.5 A ,
K = 15 MHz/ V, N = 32 and
= 70 KHz
CIRCUIT LEVEL DESIGN OF THE
The proposed architecture of dual loop synthesizer has been explained in chapter
3. This chapter deals with various design steps involved in the implementation. TSMC
0.25 CMOS technology is selected for implementation. Design and simulations of the
circuit are accomplished in Cadence.
4.1 Phase frequency detector
Many different types of phase detectors are available. Some accept sinusoidal
inputs and operate like analog multiplier type PDs and others accept digital signals. Each
type of PDs has advantages and disadvantages. In a frequency synthesizer the input is
digital, hence a digital PD is required. Among different types of digital PDs, Phase
Frequency Detector (PFD) turns out to be the best . It offers an unlimited pull-in range
which guarantees PLL acquisition even under the worst operating conditions. The three-
state phase frequency detector implemented in Cadence is shown in Figure 4.1.
Figure 4.1: Implementation of phase frequency detector
As the name implies, its output signal depends not only on phase error but also on
frequency error, when the PLL has not yet acquired lock. The PFD is built from two D-
flip-flops, whose outputs are denoted UP and DN (down), respectively. The circuit for
positive edge triggered D flip flop with reset is shown in Figure 4.2.
Figure 4.2 Positive edge-triggered D-flip-flop with reset
The transistor-level implementation of NOR gate used in D flip flop of Figure 4.2 is
shown in Figure 4.3.
Figure 4.3: Two-input NOR gate
The PFD can be in one of the following four states:
- UP = 0, DN = 0
- UP = 0, DN = 1
- UP = 1, DN = 0
- UP = 1, DN = 1
The fourth state is inhibited, using an additional AND gate as shown in Figure
4.1. Whenever both flip-flops’ are in the 1 state, a logic high level appears at their reset
inputs, which resets both flip-flops. Consequently the device acts as a tri-stable device.
We assign the symbols -1, 0 and 1 to these three states:
- UP = 0, DN = 1 state = -1
- UP = 0, DN = 0 state = 0
- UP = 1, DN = 0 state = 1
The actual state of the PFD is determined by the positive going transients of the
signals ref (reference) and fb (feedback), as explained by the state diagram of Figure 4.4.
Figure 4.4: State diagram of PFD
As Figure 4.4 shows, a positive transition of ref forces the PFD to go into its next higher
state, unless it is already in the 1 state. Similarly, a positive transition of fb forces the
PFD to go into its next lower state, unless it is already in the -1 state. As soon as ref and
fb are high PFD goes to 0 state.
As shown in Figure 4.5, if the delay time between ref and fb reduces, the output
DN does not reach the AND gate threshold level and hence will not reach 1. This is
known as dead zone . Dead zone is undesirable in a phase locked system which leads
to peak to peak jitter equal to the width of the dead zone at the output. This can easily be
avoided by introducing gate delays. The reset delay ensures that UP and DN reach full
logic level and they should be high for sufficient amount of time such that the difference
of current representing the phase error can be converted to its corresponding control
Figure 4.5: Dead zone in PFD
The transistor level implementation of AND gate is shown in Figure 4.6. The reset delay
is introduced by making aspect ratios of transistors higher than the required minimum
Figure 4.6: Two-input AND gate
4.2 Charge pump
The output of a PFD which represents the phase error between the input signals
can be converted to DC in many different ways. In most digital PLLs the combination of
PFD and passive lead-lag filter is the preferred arrangement. The passive lead-lag loop
filter performs like a real integrator when driven by a PFD. This is because the charge on
the loop filter capacitor remains unchanged when the output of the PFD is in the high-
impedance state. But this circuit has a property that can be disturbing in critical
applications. The phase detector gain
K of the PFD is not constant as predicted by
theory, but varies with the operating point of the loop. By operating point we mean the
average loop filter output signal that is required to create the desired output frequency at
One way to avoid that problem is application of a phase detector having a current
output instead of a voltage output. Such phase detector is said to be cascaded with charge
pump. Figure 4.7 shows the implemented charge pump.
Figure 4.7: Charge pump implementation
The charge pump consists of two switched current sources that pump charge into
or out of the loop filter according to two logic inputs UP/ DN from the PFD. If UP is high
and DN is low, then current through PMOS charges output capacitor. If DN is high and
UP is low, current through NMOS discharges the capacitor. In the implementation above
we see buffer stages, current sources and MOSFET switches.
4.2.1 Buffer stages
Buffer stages in cascade are used to drive the signals to their full logic levels at
the load. Buffer stages in cascade have increasing W/ L ratio to be able to drive the
signals properly. Number of stages required is calculated based on the load capacitance of
the loop filter.
Buffer stages are implemented with inverters. The inverter circuit is shown in
Figure 4.8: Inverter schematic
4.2.2 Current sources
The current sources are implemented by connecting the gate of PMOS to ground
and the gate of NMOS to Vdd. Current source implemented with PMOS transistor acts as
a current source and the other implemented with NMOS acts as current sink. MOSFET
current sources are used in place of resistors since the actual implementation of resistors
requires a relatively large area on a silicon chip. The aspect ratios of current sources are
adjusted to generate output current of 12.5uA according to the following equation.
th GS p cp
K I ÷ =
where the channel length modulation is neglected. Here,
K is the process
transconductance of a PMOS transistor, W and L are the width and length of the
V is the gate to source voltage and
V is the threshold voltage.
4.3 Voltage controlled oscillator
Voltage controlled oscillator (VCO) generates a frequency which is proportional
to its input voltage. A VCO can be realized using a wide range of technologies in many
different ways, they can be divided into two basic classes. One is relaxation oscillators
(astable multi-vibrators) and the other is resonant oscillators (vanderpole oscillators). The
difference in these two classes is digital and analog outputs. Since we require digital
output we will go for relaxation type VCO design.
Different circuit configurations and technologies offer different capabilities and
performances. As mentioned previously that the selection of a circuit configuration and
technology is driven by the requirements of an application, and the selection process
usually involves tradeoffs and compromises.
The trend to combine the whole PLL on one IC chip met with monolithic VCOs,
particularly in the megahertz ranges. A ring oscillator based VCO is designed which
meets our specifications.
Figure 4.9 shows a VCO differential cell. Differential architecture is chosen to
increase the supply and common mode rejection. VBIAS supplies the constant current
and VCNTR is the control voltage input from the charge pump/ loop filter. The value of
RC time constant varies with the control voltage. Hence if VCNTR increases, current
increases leading to the increase in frequency of oscillations.
Figure 4.9: VCO differential cell
In general, if VCO has n stages, the oscillator frequency would be
is the time constant of one stage.
For an oscillation frequency of 22.5 MHz, 5 stages of differential cells are connected in
series. The schematic is shown in Figure 4.10.
Figure 4.10 Voltage controlled oscillator schematic
An important issue with the differential cell of Figure 4.9 is that as control voltage
varies so do the currents steered through the top bias transistors. Thus, the output voltage
swing is not constant across the tuning range. To minimize this effect, self bias circuit is
introduced which varies in opposite direction to control the voltage so as to keep the
current fairly constant in the circuit and hence improve linearity.
Buffer stages are added at the output of the ring oscillator to decrease the rise and
fall time of the pulses. The frequency of the output is plotted as a function of the input
voltage to get the transfer characteristic curve. Observation of the VCO characteristic
curve with out self bias in Figure 4.11 and the characteristic curve with self bias in Figure
4.12 shows an improvement in linearity of the self biased VCO.
Figure 4.11 VCO transfer characteristic curve with out self bias
Figure 4.12 VCO transfer characteristic curve with self bias
Some of the important observations that can be made about the designed VCO
from Figure 4.12 are:
- Linear operating range of frequencies: 20.5 MHz to 23.5 MHz
- Voltage range for this frequency: 1.1 V to 1.4 V
- Gain of VCO:
= 15 MHz / V
Power Spectral Density (PSD) plot of VCO is shown in Figure 4.13. It is seen that
the center frequency is located at the desired frequency of 22.5 MHz.
Figure 4.13 Power spectral density of VCO
Figure 4.14 shows the phase noise response of the designed VCO.
Figure 4.14 Periodic phase noise response
4.4 Loop filter
Loop filter is the most important component of PLL. The design of loop filter is
the principle tool in selecting the bandwidth of the PLL. Since higher order loop filters
offer better noise cancellation, a second-order low-pass filter is used.
Because the input variable of VCO is frequency, it always has a 1/s term in the
transfer function to integrate this frequency to phase. The loop filter introduces another
pole at DC in order to have enough suppression on the spurious tones from the frequency
comparison process. These two poles at DC introduce a phase shift of 180 degrees per
decade. Without compensation, the loop will have a phase shift of 180 degree before the
unity-gain bandwidth, which makes the loop unstable. A zero is introduced before the
center frequency minus the loop bandwidth to provide enough phase margin. A third pole
above the center frequency plus the loop bandwidth is introduced to provide more
suppression. The loop filter capable of meeting these requirements is a second-order lead-
lag filter. Designed filter is shown in Figure 4.15.
Figure 4.15: Second-order passive lead-lag filter
The transfer function of the above loop filter is
) 1 (
2 1 1
C C R
+ = (4.4)
1 1 2
C R = (4.5)
2 1 1
C C R
R is the input impedance of the filter which is represented by the ratio of
the voltage to the current input from the charge pump.
O = = = K
5 . 12
5 . 2
The magnitude and phase response plots of the designed filter from MATLAB are
shown in Figure 4.16.
Figure 4.16: Magnitude and phase response of loop filter
Asynchronous dividers are the simplest form of frequency dividers. They consist
of a series of T flip flops, where each T flip flop is made of D flip flop whose inverted
output is connected back to its D input pin, making it a divide by two circuit. If an input
frequency is fed into the T input of this circuit the output frequency will be half of the
input frequency. A circuit configuration of such a form and its input output behavior is
shown in Figure 4.17.
Figure 4.17: T-flip-flop and its input-output waveforms
A nice feature of this circuit is that the output is perfectly symmetrical square
wave regardless of whether the input square wave is symmetrical or not. By cascading
several T flip flops in the same configuration, it is easy to make a divide-by-
The non-inverting output of one flip flop can be used as an input to the next flip flop to
make it a divide-by-4 circuit. Thus to divide an input frequency by 32, we only need to
have 5 T flip flops connected in this configuration. The designed circuit for the divide-
by-32 is shown in Figure 4.18 and its input output waveforms are shown in Figure 4.19.
Figure 4.18: Divide-by-32 circuit
Figure 4.19: Waveforms of divide-by-32 circuit
The circuit is performing as expected; one period of output square wave is equal
to 32 periods of input square wave. Therefore output frequency is input frequency
divided by 32.
4.6 Frequency-to-Voltage Converter
As mentioned earlier Frequency-to-Voltage Converter (FVC) provides the
precise output voltage that is proportional to the input pulse train frequency. FVC can be
implemented with a Pulse-to-Digital Converter (PDC) followed by a Digital-to-Analog
Converter (DAC). Figure 4.20 shows FVC implementation in Cadence. FVC is designed
to have linear characteristics in the operating range of VCO. The characteristic curve of
the implemented FVC is shown in Figure 4.21.
Figure 4.20: Frequency-to-Voltage Converter
Figure 4.21: Characteristic curve of FVC
The following two sections explain the design of PDC and DAC modules used in
4.6.1 Pulse-to-Digital Converter
Pulse-to-Digital Converter (PDC) can be implemented with the help of two basic
blocks, a pulse generating circuit which is basically an RC network followed by an
NAND gate and a 4-bit counter. Implementation of these modules is shown in Figure
4.22 and Figure 4.24.
Figure 4.22: Pulse generating circuit
The RC network in Figure 4.22 is used as a delay network. The delayed signal
and the original VCO output are supplied as inputs to a NAND gate followed by an XOR
gate as shown in Figure 4.22. Output of this circuit is positive pulses at every rising edge
of VCO clock, which are passed through an inverter to generate negative pulses at the
rising edges of VCO output frequency as shown in Figure 4.23. These negative pulses are
used to reset the counter.
Figure 4.23: Output of pulse generating circuit
The 4-bit counter is implemented with four T flip flops as shown in Figure 4.24.
Figure 4.24: 4-bit counter
The architecture of the overall Pulse-to-Digital Converter (PDC) is shown in
Figure 4.25. A 4-bit buffer is added at the end of the circuit to invert the outputs and to
drive them to their respective full logic levels.
Figure 4.25: Pulse-to-Digital Converter
4.6.2 Digital-to-Analog Converter
The settling time of DAC should be small to meet the requirements of our
application. Settling time is the time it takes a DAC to settle within +/- ½ of a LSB of its
final value when a change occurs in the input code. Figure 4.26 shows the DAC
implementation. A binary weighted resistor network type DAC is implemented to meet
Figure 4.26: Digital-to-Analog Converter
The structure contains one resistor for each bit of the DAC connected to a
summing point. These precise voltages sum to the correct output value. This is one of the
fastest conversion methods but suffers from poor accuracy if used for more than 8-bit
resolution, because of the high precision required for each individual voltage. The
bandwidth of the summing amplifier used decides the settling time of the DAC.
Figure 4.27: Two-stage op-amp
Figure 4.27 shows a two-stage amplifier used as summing amplifier in DAC. The
two stage op-amp is designed with sizes of the transistors, the resistors and the capacitors
shown in Table 4.1.
Table 4.1: Transistor sizes of op-amp
M1, M2 2.1/0.6
M3, M4 60/0.6
Using the small signal analysis the dc gain of op-amp is calculated as:
2 / 1
6 3 6 3
L L I I
W W K K
= 60dB (4.8)
Figure 4.28 shows the gain and phase responses of the op-amp with an output
load of 500fF. From the ac response we see that the amplifier has a gain of 60dB, unity
gain bandwidth of 60MHz and a phase margin of 75 degrees.
Figure 4.28: AC response of op-amp
The step response of op-amp is shown in Figure 4.29. A settling time of 12ns and
a slew rate of 1.25 V/µS are achieved.
Figure 4.29: Step response of op-amp
Figure 4.30 is the characteristic curve of the DAC. It is a plot of 4-bit input digital
word on x-axis to the corresponding analog voltage output on y-axis. We see that the
designed DAC has very linear response.
Figure 4.30: Characteristic curve of DAC
The switches used in the DAC have to conduct both logic 0 and 1 perfectly. An
NMOS transistor is the simplest of the switches that can be used. This conducts logic 0
perfectly, but introduces threshold drop because of source-drain voltage drop when
conducting logic 1. This threshold drop causes next stage to be turned on weakly.
Similarly, p-type switch do not conduct logic 0 properly.
Complementary switch designed to produce full-supply voltages for both logic 0
and logic 1 is shown in Figure 4.31. In complementary switches n-type conducts logic 0
and p-type conducts logic 1.
Figure 4.31: Complimentary CMOS switch
4.7 Dual-loop frequency synthesizer
The individual building blocks designed in previous sections can be integrated
together to build two different architectures of frequency synthesizers. One is the
proposed dual loop frequency synthesizer and the other is the conventional PLL-based
single loop frequency synthesizer. These two architectures will be simulated with similar
inputs and the results will be compared with each other. Figure 4.32 shows the PLL-
based frequency synthesizer and Figure 4.33 shows the proposed dual loop frequency
Figure 4.32: Implemented PLL-based frequency synthesizer
The procedure for designing PLL-based frequency synthesizer of Figure 4.32
from the circuits designed in the previous sections is described below. The reference
input frequency of 705KHz from the external oscillator and the feedback frequency from
the voltage controlled oscillator are fed as inputs to the PFD which, generates UP/ DN
pulses. The charge pump forces a current into the loop filter which is proportional to the
time intervals of UP/ DN pulses. The dc voltage from the output of loop filter controls the
VCO frequency. The VCO frequency is fed back to the PFD through a divide-by-32
circuit. Thus the PLL loop tries to synchronize the phase of output frequency to that of
Figure 4.33: Implemented dual-loop frequency synthesizer
Design of dual-loop frequency synthesizer of Figure 4.33 is similar to that of the
PLL-based frequency synthesizer except for the additional feedback loop. The VCO
output is fed back to the error amplifier through a frequency-to-voltage converter. The
error amplifier used here is a difference amplifier with a gain of 5 . 1 =
Simulation waveforms of PLL-based frequency synthesizer and the dual loop
frequency synthesizer circuits are compared in chapter 5.
SIMULATIONS AND RESULTS
This chapter shows the simulation results of the dual-loop frequency synthesizer
and the PLL-based frequency synthesizer. The input frequency for these simulations is
705KHz and the achieved output is 22.5MHz. The simulation results for dual-loop and
PLL-based frequency synthesizers are compared with respect to lock time and the phase
noise at the VCO output frequency.
Figure 5.1 below is the time response of VCO control voltage for PLL-based
frequency synthesizer. Based on this waveform the lock time of this synthesizer is
obtained as 95us.
Figure 5.1: VCO control voltage for PLL-based frequency synthesizer
Figure 5.2 below is the time response of VCO control voltage for dual-loop
frequency synthesizer. The lock time of the dual-loop synthesizer is 85us. The time
responses of Figures 5.1 and 5.2 show an improvement of 10us in the lock time of dual-
loop frequency synthesizer as compared to the PLL-based frequency synthesizer.
Figure 5.2: VCO control voltage for dual-loop frequency synthesizer
Ripple in the VCO control voltage when the synthesizer is in lock state is an
indication of jitter at the output frequency. Figure 5.3 is a closer look at the control
voltage of Figure 5.1 after the synthesizer is locked to the input frequency. Calculating
the ripple in the control voltage of the PLL-based frequency synthesizer from Figure 5.3
V (ripple voltage) of 22mV.
Figure 5.3: Ripple in control voltage after lock for PLL-based frequency synthesizer
Figure 5.4 is a closer look at the control voltage of Figure 5.2 after the synthesizer
is locked to the input frequency. Calculating the ripple in the control voltage of the dual-
loop frequency synthesizer from Figure 5.4 gives a
V (ripple voltage) of 14mV. There is
an improvement of 8mV in the ripple voltage for the dual-loop frequency synthesizer
over the PLL-based synthesizer.
Figure 5.4: Ripple in control voltage after lock for dual-loop frequency synthesizer
Figure 5.5 shows the lock-in process of the dual-loop frequency synthesizer. We
can observe that the phase difference between the reference frequency and the output
frequency approaching exactly 90 as the synthesizer enters the locked state.
Figure 5.5: Lock-in process of reference and VCO frequencies
Figure 5.6 is the power spectral density (PSD) plot of the output frequency for
PLL-based frequency synthesizer. We can calculate the signal-to-noise plus distortion
ratio (S[N+D]R) of any system by dividing the signal power to the noise plus distortion
power in the bandwidth of interest. In our case the bandwidth is 70KHz around the center
frequency of 22.5MHz. The signal-to-noise plus distortion ratio of PLL-based frequency
synthesizer is calculated using MATLAB as S[N+D]R=39dB.
Figure 5.6: PSD of VCO output for PLL-based frequency synthesizer
By taking a closer look around the center frequency in the PSD plot shown in
Figure 5.7, we can observe couple of spurs close to the center frequency due to distortion.
These spurs are undesirable and may cause synthesizer to go out of lock.
Figure 5.7: Zoom-in of Figure 5.6
The PSD plot of the output frequency for the dual loop frequency synthesizer is
shown in Figure 5.8. It’s S[N+D]R is calculated using MATLAB as S[N+D]R = 46dB.
Figure 5.8: PSD of VCO output for dual-loop frequency synthesizer
Comparing the S[N+D]R of the PLL-based synthesizer and the dual-loop
synthesizer we can observe an improvement of 7dB.
S[N+D]R = 46dB
By taking a closer look at Figure 5.8 which is shown in Figure 5.9, we can
observe that the spurs that were visible in the PSD of PLL-based synthesizer are reduced
in the dual-loop synthesizer. The output of the dual-loop synthesizer is closer to the
desired frequency response as shown in Figure 3.1.
Figure 5.9: Zoom-in of Figure 5.8
CONCLUSIONS AND FUTURE WORK
A dual-loop frequency synthesizer has been proposed for reducing the phase noise
introduced by the VCO. Simulations have shown an improvement of 10us in the lock
time and a 7dB improvement in signal-to-noise plus distortion ratio over the traditional
PLL-based frequency synthesizer.
It is necessary to accurately characterize the noise performance because each of
the components contributes noise which affects the system in a non-linear fashion. Major
contributors of noise are phase detector/ charge pump and the VCO. The proposed
architecture with two feedback loops has shown to reduce the VCO phase noise in the
Applications such as transceiver require the synthesizer to maintain its phase
noise and spurious tone performance in the presence of current and voltage perturbations
in both the substrate ground and supply. Fully differential implementation of the
complete synthesizer path is important for this reason. A differential cell ring oscillator is
designed for VCO to reduce the substrate noise introduced. A differential charge pump
with active loop filter can be implemented to minimize spurious tones and to maximize
the frequency tuning range of VCO by making the synthesizer fully differential.
In the PLL-based frequency synthesizer the phase noise can be reduced by using a
fractional-N-divider in the feedback. Using the fractional divider allows the use of higher
reference frequencies thereby reducing the phase noise. The integer divider in the
proposed dual-loop synthesizer architecture can be replaced by a fractional divider to
suppress the phase noise further.
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McGraw-Hill Irwin, New York, 2001.
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Electrical Engineering Department, Texas Tech University, 2003.
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Synthesizers for Multi-standard Wireless Communication Applications,
Dissertation, EECS, University of California, Berkeley, 2000.
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Noise, IEEE Circuits and Systems, 2004.
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