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CSE 307: Digital Technique

Registers and Counters

What is a Register?
• A Register is a collection of flip-flops with some common function or characteristic
Control signals - common clock, clear, load, etc. Function - part of multi-bit storage, counter, or shift register

• At a minimum, we must be able to:
Observe the stored binary value Change the stored binary value
30 May 2011 CSE 307: Digital Technique Page 2

Kinds of Registers and Counters
Storage Register
V+

Group of storage elements read/written as a unit 4-bit register constructed from 4 D FFs Shared clock and clear lines Schematic Shape

CLR

D3

D C

Q Q

Q3 Q3F

D2

D C

Q Q

Q2 Q2F

171
12 CLK 13 CLR 11 5 4 14 D3 D2 D1 D0 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 9 10 7 6 2 3 1 15

D1

D C

Q Q

Q1 Q1F

D0 CLK

D C

Q Q

Q0 Q0F

TTL 74171 Quad D-type FF with Clear (Small numbers represent pin #s on package)

30 May 2011

CSE 307: Digital Technique

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Kinds of Registers and Counters Input/Output Variations Selective Load Capability Tri-state or Open Collector Outputs True and Complementary Outputs 11 1 18 17 14 13 8 7 4 3 377 CLK EN D7 D6 D5 D4 D3 D2 D1 D0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 19 16 15 12 9 6 5 2 11 18 17 14 13 8 7 4 3 374 CLK H QH G QG F QF E QE D QD C QC B QB A QA OE 1 19 16 15 12 9 6 5 2 74377 Octal D-type FFs with input enable EN enabled low and lo-to-hi clock transition to load new data into register 74374 Octal D-type FFs with output enable OE asserted low presents FF state to output pins. otherwise high impedence 30 May 2011 CSE 307: Digital Technique Page 4 .

organized as four rows (words) of four elements (bits) 74670 4x4 Register File with Tri-state Outputs 30 May 2011 CSE 307: Digital Technique Page 5 .Kinds of Registers and Counters Register Files Two dimensional array of flip-flops Address used as index to a particular word Word contents read or written 670 11 4 5 12 13 14 3 2 1 15 RE RB RA WE WB WA D4 D3 D2 D1 Q4 Q3 Q2 Q1 6 7 9 10 Separate Read and Write Enables Separate Read and Write Address Data Input. Q Outputs Contains 16 D-ffs.

Kinds of Registers and Counters Shift Registers Storage + ability to circulate data among storage elements Vcc Reset Shift Direction Q1 Shift 1 0 Shift 0 Shift Reset Q2 0 1 0 0 Q3 0 0 1 0 Q4 0 0 0 1 J Q CLK Q1 J Q CLK Q2 J Q CLK Q3 CLK J Q K Q Q4 K Q Shift Vcc K Q K Q 0 Shift from left storage element to right neighbor on every lo-to-hi transition on shift signal Wrap around from rightmost element to leftmost element 30 May 2011 CSE 307: Digital Technique Page 6 .

Data Transfer • Information is moved from register to register by: Parallel data transfer Serial data transfer • For example: Older printers use parallel data transfer USB devices use serial data transfer 30 May 2011 CSE 307: Digital Technique Page 7 .

all bits of A are copied to B 30 May 2011 CSE 307: Digital Technique Page 8 . B clock When clock occurs. A Reg.Parallel Data Transfer Parallel data transfer moves data from one register to another at one time Reg.

it takes ‘n’ clocks for data move 1 bit signal Reg. B clock Usual implementation is with a shift register. A Reg. For ‘n’ bit registers.Serial Data Transfer Serial transfer moves data bits from A to B one bit per clock Rx and Tx have single wire between the two. 30 May 2011 CSE 307: Digital Technique Page 9 .

Serial Data Transfer • Typical serial transfer is a multi-step process Load transmit shift register with data to send Shift data bit by bit from transmit to receive SR Transfer received data to other registers • The transmit SR must have parallel load AKA parallel to serial shift register • The receive SR must have parallel outputs AKA serial to parallel shift register • Other control/timing signals usually needed 30 May 2011 CSE 307: Digital Technique Page 10 .

B (S to P) ‘n’ bits clock Parallel Receive Data 30 May 2011 CSE 307: Digital Technique Page 11 . A (P to S) Reg.Serial Data Transfer Parallel Transmit Data ‘n’ bits load L S 1 bit signal (serial data) Reg.

Serial Data Transfer • Serial data transfer used where data rate is relatively slow and/or parallel bit transfer channels are expensive PC serial port and USB interfaces wireless/fiber optic data transmissions Cell phones Wireless networks Satellite telephone/TV Mars rover/orbiter communications 30 May 2011 CSE 307: Digital Technique Page 12 .

A Parallel Outputs: QD. QB.S0 determine the shift function S1 = 1. S0 = 0: hold state Multiplexing logic on input to each FF! 74194 4-bit Universal Shift Register Shifters well suited for serial-to-parallel conversions. QA Clear Signal Positive Edge Triggered Devices S1. S0 = 1: Load on rising clk edge synchronous load S1 = 1.Typical Multi-Function Shift Register Shift Register I/O Serial vs. S0 = 0: shift left on rising clk edge LSI replaces element D S1 = 0. B. S0 = 1: shift right on rising clk edge RSI replaces element A S1 = 0. RSI Parallel Inputs: D. Right S1 S0 LSI A B C D RSI CLK CLR QA QB QC QD Serial Inputs: LSI. Parallel Inputs Serial vs. such as terminal to computer communications 30 May 2011 CSE 307: Digital Technique Page 13 . Parallel Outputs Shift Direction: Left vs. QC. C.

Serial Transfer with Shift Registers Shift Register Application: Parallel to Serial Conversion Sender S1 S0 194 LSI D QD C QC B QB QA A RSI CLK CLR S1 S0 194 LSI D QD C QC B QB A QA RSI CLK CLR Receiver S1 S0 194 LSI D QD C QC B QB A QA RSI CLK CLR S1 S0 194 LSI D QD C QC B QB A QA RSI CLK CLR D7 D6 D5 D4 Clock D7 D6 D5 D4 Parallel Inputs Parallel Outputs D3 D2 D1 D0 D3 D2 D1 D0 Serial transmission 30 May 2011 CSE 307: Digital Technique Page 14 .

. 010. 3 Bit Down-counter: 111. 011. . The count sequence can be Binary or BCD or Gray Code or any other sequence you want. 111. clock. The basic counter is a sequential circuit The basic counter is a sequential circuit where the state (the count value) is the output.. The counter circuit may have no other input other than the The counter circuit may have no other input other than the clock. This is known as an autonomous sequential circuit. 111. 110. . Usually there will be a set of control inputs (enable. 000. 101. 010. reset) in addition to the clock. 001. 101.. 000. where the state (the count value) is the output. 3 Bit Up-counter: 000. 011. load.Kinds of Registers and Counters Counters Proceed through a well-defined sequence of states in response to the count signal. 100. 100. 110. 30 May 2011 CSE 307: Digital Technique Page 15 . This is known as an autonomous sequential circuit. 001..

used for cascading counters "Ripple Carry Output" 74163 Synchronous 4-Bit Upcounter 74161: similar in function. C. A P.Kinds of Registers and Counters A common 4-bit counter 7 P 10 T 163 15 2 CLK RCO 6 5 4 3 9 1 D C B A LOAD CLR QD QC QB QA 11 12 13 14 Synchronous Load and Clear Inputs Positive Edge Triggered FFs Parallel Load Data from D. B. T Enable Inputs: both must be asserted to enable counting RCO: asserted when counter enters its highest state 1111. asynchronous load and reset 30 May 2011 CSE 307: Digital Technique Page 16 .

single bit change per state. useful for avoiding glitches Must be initialized V+ S J Q CLK K Q R S J Q CLK K Q R S J Q CLK K Q R S J Q CLK K Q R Shift 100 Shift Q1 Q2 Q3 Q4 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 30 May 2011 CSE 307: Digital Technique Page 17 .Kinds of Registers and Counters Ring Counter 1 0 \Reset Q1 Q2 Q3 Q4 +V +V +V End-Around 4 possible states.

Mobius) Counter +V +V +V Inverted End-Around 1 0 \Reset Q1 Q2 Q3 Q4 S J Q CLK K Q R S J Q CLK K Q R S J Q CLK K Q R S J Q CLK K Q R Shift 8 possible states.Kinds of Registers and Counters Twisted Ring (Johnson. single bit change per state. useful for avoiding glitches +V 100 Shift Q1 Q2 Q3 Q4 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 30 May 2011 CSE 307: Digital Technique Page 18 .

no decisions on state assignment or transitions current state is the output Example: 3-bit Binary Upcounter Present state 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 0 Decide to implement with Toggle Flipflops What inputs must be presented to the T FFs to get them to change to the desired state bit? We need to use the T FF excitation table to translate the present/next state values to FF inputs 000 111 Next state 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 001 110 010 101 011 100 30 May 2011 CSE 307: Digital Technique Page 19 .Counter Design Procedure Introduction The process is a special case of the general sequential circuit design procedure.

counter may be in any possible state Designer must guarantee that it (eventually) enters a valid state Especially a problem for counters that validly use a subset of states Self-Starting Solution: Design counter so that even the invalid states eventually transition to valid state S6 S5 S0 S4 S0 S4 S1 S3 S1 S3 S5 S2 S7 S6 S2 S7 Two Self-Starting State Transition Diagrams 30 May 2011 CSE 307: Digital Technique Page 20 .Self-Starting Counters Start-Up States At power-up.

no translation is needed from state transitions to FF inputs FF next state value IS the FF input value • T. JK FFs need an extra step in the design procedure We start with the transition.Implementation with Different Kinds of FFs • D FFs are easiest to use for implementation. next state values What we need to find is what FF input values are needed that result in the defined transitions • This information is the FF EXCITATION TABLE Derived from the FF characteristic table Defines inputs needed for all four possible PS/NS combinations 30 May 2011 CSE 307: Digital Technique Page 21 . SR. pairs of present state.

Q(t+) values.Implementation with Different Kinds of FFs Derivation of JK Excitation Table Characteristic Table J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Q(t) Q(t+) 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 Excitation Table Q(t) Q(t+) 0 0 1 1 0 1 0 1 J K Look for rows in the characteristic table that have the same Q(t).K inputs are for those cases 30 May 2011 CSE 307: Digital Technique Page 22 . observe what the J.

K is 0 in one case. J is constant 0. J must be 0.0 transition.0 cases. 1 in the other. K is a don’t care.Implementation with Different Kinds of FFs Derivation of JK Excitation Table Characteristic Table J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Q(t) Q(t+) 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 Excitation Table Q(t) Q(t+) 0 0 1 1 0 1 0 1 J K For the two 0. 30 May 2011 CSE 307: Digital Technique Page 23 . Therefore for the 0.

K values are then entered in the excitation table 30 May 2011 CSE 307: Digital Technique Page 24 .Implementation with Different Kinds of FFs Derivation of JK Excitation Table Characteristic Table J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Q(t) Q(t+) 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 Excitation Table Q(t) Q(t+) 0 0 1 1 0 1 0 1 J 0 K X The necessary J.

Implementation with Different Kinds of FFs Derivation of JK Excitation Table Characteristic Table J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Q(t) Q(t+) 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0 Excitation Table Q(t) Q(t+) 0 0 1 1 0 1 0 1 J 0 1 X X K X X 1 0 30 May 2011 CSE 307: Digital Technique Page 25 .

Implementation with Different Kinds of FFs Exication tables for D. T. SR. JK flip-flops Excitation Tables Q(t) Q(t+) 0 0 1 1 0 1 0 1 D 0 1 0 1 T 0 1 1 0 S 0 1 0 X R X 0 1 0 J 0 1 X X K X X 1 0 30 May 2011 CSE 307: Digital Technique Page 26 .

Enter the values in the FF input true table We’ll use a T FF for Qa. and a JK FF for QC Qa Qb Qc 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Qa+ Qb+ Qc+ 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 Ta 0 0 0 0 1 1 1 1 Sb Rb 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Jc 0 0 0 0 1 1 1 1 Kc 0 0 0 0 1 1 1 1 30 May 2011 CSE 307: Digital Technique Page 27 .Implementation with Different Kinds of FFs Translation from State Transition to FF Inputs The determination of the FF input values now becomes: 1. Look up the FF inputs needed in the excitation table 3. For each present state/next state transition value pair 2. an SR FF for Qb.

JK FFs 3 bit binary counter Q(t) Q(t+) 0 0 1 1 0 1 0 1 D 0 1 0 1 T 0 1 1 0 S 0 1 0 X R X 0 1 0 J 0 1 X X K X X 1 0 Qa Qb Qc 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Qa+ Qb+ Qc+ 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 Ta 0 1 0 0 1 0 1 1 Sb Rb 0 X 1 0 X 0 0 1 1 X 1 0 X 0 0 1 Jc Kc 1 X 1 X 1 X 1 X X 1 X 1 X 1 X 1 30 May 2011 CSE 307: Digital Technique Page 28 .Implementation with Different Kinds of FFs FF Inputs for T. SR.

Implementation with Different FF Types Comparison • T FFs well suited for straightforward binary counters But yielded worst gate and literal count for this example! • No reason to choose R-S over J-K FFs: it is a proper subset of J-K R-S FFs don't really exist anyway J-K FFs yielded lowest gate count Tend to yield best choice for packaged logic where gate count is key • D FFs yield simplest design procedure Best literal count D storage devices very transistor efficient in VLSI Best choice where area/literal count is the key 30 May 2011 CSE 307: Digital Technique Page 29 .

Synchronous Counters Ripple Counters Deceptively attractive alternative to synchronous design style T Q A T Q B T Q C CLK Q Count CLK Q CLK Q Count signal ripples from left to right State transitions are not sharp! Can lead to "spiked outputs" from combinational logic Can lead to "spiked outputs" from combinational logic decoding the counter's state decoding the counter's state 30 May 2011 CSE 307: Digital Technique Page 30 .Asynchronous vs.

Ripple Counters (Up or Down) • Three characteristics determine if a ripple counter counts up or down FF clock input polarity FF output to clock polarity Counter output polarity • A ripple counter with negative clock polarity. and Q counter outputs counts UP • Change an odd number of characteristics and the counter counts DOWN 30 May 2011 CSE 307: Digital Technique Page 31 . Q to next FF clock.

Cascaded Counters Cascaded Synchronous Counters with Ripple Carry Outputs First stage RCO enables second stage for counting RCO asserted soon after stage enters state 1111 ET EP A B C D LD CLR RCO QA QB QC QD ET EP A B C D LD CLR RCO QA QB QC QD also a function of the T Enable Downstream stages lag in their 1111 to 0000 transitions Affects Count period and decoding logic 30 May 2011 CSE 307: Digital Technique Page 32 .

D C B A Clock R Q Q QQ D CBA C C O L P T K DCBA 1 6 3 100 Load L O C A L D R D C B A + + Load 0 1 0110 is the state to be loaded Use RCO signal to trigger Load of a new state Since 74163 Load is synchronous. 1111. 1011.. 1110. 1001.g. . 1010. 1100. 0110. 1000.. 0111. state changes only on the next rising clock edge 30 May 2011 CSE 307: Digital Technique Page 33 .Other Counter Sequences The Power of Synchronous Clear and Load Starting Offset Counters: e. 0110.. 1101.