TM

MWS5114
1024-Word x 4-Bit LSI Static RAM
as 2V Min • All Inputs and Outputs Directly TTL Compatible • Three-State Outputs • Low Standby and Operating Power

March 1997

Features
• Fully Static Operation • Industry Standard 1024 x 4 Pinout (Same as Pinouts for 6514, 2114, 9114, and 4045 Types) • Common Data Input and Output • Memory Retention for Standby Battery Voltage as Low

Description

Ordering Information
200ns MWS5114E3 MWS5114D3 MWS5114D3X 250ns MWS5114E2 MWS5114E2X MWS5114D2 300ns MWS5114E1 MWS5114D1 TEMPERATURE RANGE 0oC to +70oC 0oC to +70oC PACKAGE PDIP Burn-In SBDIP Burn-In PKG. NO. E18.3 E18.3 D18.3 D18.3

Pinout
MWS5114 (PDIP, SBDIP) TOP VIEW

A6 A5 A4 A3 A0 A1 A2 CS VSS

1 2 3 4 5 6 7 8 9

18 VDD 17 A7 16 A8 15 A9 14 I/O1 13 I/O2 12 I/O3 11 I/O4 10 WE

OPERATIONAL MODES FUNCTION Read Write Not Selected CS 0 0 1 WE 1 0 X DATA PINS Output: Dependent on data Input High Impedance

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001. All Rights Reserved

File Number

1325.2

160

MWS5114 Functional Block Diagram A4 VDD A5 VSS MEMORY ARRAY 64 ROWS 64 COLUMNS A6 ROW SELECT A7 A8 A9 I/O1 INPUT DATA CONTROL COLUMN I/O CIRCUITS COLUMN SELECT I/O2 I/O3 I/O4 A0 A1 A2 A3 CS ENABLE WE 6-161 .

. .6 0. . +150oC Maximum Lead Temperature . . . . . . . . . .8 V VIH - 5 2. . . . . . . .1 - 0 0. . . . . . . 4. . .5 0. . . . . . . . (V DD) (All Voltages Referenced to VSS Terminal) .8 - 1.5V to VDD +0.1 ±5 - ±0. . . . . . . . .4 - - 2. All Inputs . +175oC Plastic Package . . . . . . . .1 - 0 0. . . . . . . . . . . 75 20 Operating Temperature Range (TA) Package Type D . . . +265oC Recommended Operating Conditions At TA = Full Package Temperature Range. . . . . -0.5.4 -1 - mA VOL - 0. . . . . . . . . . . 4. . 75 N/A SBDIP Package. . . . . . . . . . . . . . . . . . 5 5 4.4 -1 - -0. .4 - - 2.5V DC Input Current. . . . . . Except as Noted LIMITS MWS5114-3 MWS5114-2 (NOTE 1) TYP 75 MWS5114-1 (NOTE 1) TYP 75 CONDITIONS PARAMETER Quiescent Device Current Output Low (Sink) Current Output High (Source) Current Output Voltage Low-Level Output Voltage High-Level Input Low Voltage Input High Voltage Input Leakage Current (Note 2) Operating Current (Note 3) SYMBOL IDD VO (V) - VIN (V) 0. .4 -1 - -0. .2 0. . . .2 0.-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . -0. . . . . . 5 5 - ±0. . . . . . . . . . . . . . . . VDD = ±5%. . . For maximum reliability. . . .9 5 - 4. . . . . .4 - - V IIN 0.1 ±5 - ±0. . .-40oC to +85oC Maximum Storage Temperature Range (TSTG) . . . 5 VDD (V) 5 MIN - (NOTE 1) TYP 75 MAX 100 MIN - MAX 100 MIN - MAX 250 UNITS µA IOL 0. . . . . 5 5 2 4 - 2 4 - 2 4 - mA IOH 4.-55oC to +125oC Package Type E . . . . . . . . . . . .4 0. . . Any One Input . . . . . . . . . . ±10mA Thermal Information Thermal Resistance (Typical) θJA ( oC/W) θJC (oC/W) Plastic DIP Package . . .5. . . .1 V VOH - 0. . . 5 5 - 0 0. . 5 5 -0. .5 - - 5 - 1.1 ±5 µA IDD1 - 0. . .9 5 - V VIL 0. . .5 VDD UNITS V V Static Electrical Specifications At TA = 0oC to +70oC. .5 VSS MAX 6. operating conditions should be selected so that operation is always within the following ranges: LIMITS ALL TYPES PARAMETER DC Operating Voltage Range Input Voltage Range MIN 4. . .2 0. . 5 5 - 4 8 - 4 8 - 4 8 mA 6-162 .9 5 - 4. .MWS5114 Absolute Maximum Ratings DC Supply Voltage Range. . . . . . .5V to +7V Input Voltage Range. . . .8 - 1. . .

5 MWS5114-2 (NOTE 1) TYP ±0.5 MWS5114-1 (NOTE 1) TYP ±0. All inputs in parallel. cycle time = 1µs. 3. All outputs in parallel.5 pF COUT - - - - 10 15 - 10 15 - 10 15 pF 1. 6-163 . Typical values are for TA = 25oC and nominal VDD . 4.5 - 5 7. 5 VIN (V) 0.5 - 5 7. 5 VDD (V) 5 (NOTE 1) TYP ±0. Outputs open circuited. 2. Except as Noted (Continued) LIMITS MWS5114-3 VO (V) 0.MWS5114 Static Electrical Specifications At TA = 0oC to +70oC.5 CONDITIONS PARAMETER Three-State Output Leakage Current (Note 4) Input Capacitance Output Capacitance NOTES: SYMBOL IOUT MIN - MAX ±5 MIN - MAX ±5 MIN − MAX ±5 UNITS µA CIN - - - - 5 7. VDD = ±5%.

Time required by a limit device to allow for the indicated function. tWC tW tWR tACS 200 125 50 0 160 100 40 0 250 150 50 0 200 120 40 0 300 200 50 0 220 140 40 0 ns ns ns ns tAW 25 20 - 50 40 - 50 40 - ns tDSU 75 50 - 75 50 - 75 50 - ns tDH 30 10 - 30 10 - 30 10 - ns 6-164 .MWS5114 Dynamic Electrical Specifications at TA = 0oC to +70oC. Input tR. tF = 10ns. CL = 50pF and 1 TTL Load LIMITS MWS5114-3 (NOTE 1) MIN (NOTE 2) TYP MWS5114-2 (NOTE 1) MIN (NOTE 2) TYP MWS5114-1 (NOTE 1) MIN (NOTE 2) TYP PARAMETER SYMBOL MAX MAX MAX UNITS READ CYCLE TIMES (FIGURE 1) Read Cycle Access from Address Chip Selection to Output Valid Chip Selection to Output Active Output Three-State from Deselection Output Hold from Address Change tRC tAA 200 160 160 200 250 200 200 250 300 250 250 300 ns ns tCO - 110 150 - 150 200 - 200 250 ns tCX 20 100 - 20 100 - 20 100 - ns tOTD - 75 125 - 75 125 - 75 125 ns tOHA 50 100 - 50 100 - 50 100 - ns WRITE CYCLE TIMES (FIGURE 2) Write Cycle Write Write Release Address to Chip Select Setup Time Address to Write Setup Time Data to Write Setup Time Data Hold from Write NOTES: 1. VDD = 5V ±5%. Typical values are for TA = 25oC and nominal V DD. 2.

Timing measurement reference level is 1. WE is low during the Write Cycle.MWS5114 tRC tAA ADDRESS CS tCO tCX tOTD tOHA ACTIVE VALID DOUT NOTE: 1. tF SYMBOL VDR IDD VDR (V) 2 2 2 2 VDD (V) 5 5 5 MIN 2 300 300 1 (NOTE 1) TYP 25 25 60 MAX 50 50 125 UNITS V µA µA µA ns ns µs 6-165 . FIGURE 2. WRITE CYCLE TIMING WAVEFORMS Data Retention Specifications at TA = 0oC to +70oC.5V. FIGURE 1. READ CYCLE TIMING WAVEFORMS tWC ADDRESS tACS CS tWR tAW WE tW tDSU tDH DIN DON’T CARE VALID NOTE: 1. See Figure 3 TEST CONDITIONS LIMITS ALL TYPES PARAMETER Minimum Data Retention Voltage Data Retention Quiescent Current MWS5114-3 MWS5114-2 MWS5114-1 Chip Deselect to Data Retention Time Recovery to Normal Operation Time VDD to VDR Rise and Fall Time tCDR tRC tR. WE is high during the Read Cycle. Timing measurement reference level is 1.5V.

see www. Palm Bay. See Figure 3 TEST CONDITIONS LIMITS ALL TYPES PARAMETER NOTE: 1. SYMBOL VDR (V) VDD (V) MIN (NOTE 1) TYP MAX UNITS All Intersil U.com Sales Office Headquarters NORTH AMERICA Intersil Corporation 7585 Irvine Center Drive Suite 100 Irvine. Typical Values are for TA = 25oC and nominal VDD. Intersil Corporation’s quality certifications can be viewed at www. no responsibility is assumed by Intersil or its subsidiaries for its use. FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7946 EUROPE Intersil Europe Sarl Ave.S. products are manufactured. Accordingly.intersil.MWS5114 Data Retention Specifications at TA = 0oC to +70oC. the reader is cautioned to verify that data sheets are current before placing orders. nor for any infringements of patents or other rights of third parties which may result from its use. Information furnished by Intersil is believed to be accurate and reliable. For information regarding Intersil Corporation and its products. William Graisse. CA 92618 TEL: (949) 341-7000 FAX: (949) 341-7123 Intersil Corporation 2401 Palm Bay Rd. Kowloon Hong Kong TEL: +852 2723 6339 FAX: +852 2730 1433 166 . software and/or specifications at any time without notice.com/design/quality Intersil products are sold by description only. 3 1006 Lausanne Switzerland TEL: +41 21 6140560 FAX: +41 21 6140579 ASIA Intersil Corporation Unit 1804 18/F Guangdong Water Building 83 Austin Road TST. assembled and tested utilizing ISO9000 quality systems. Intersil Corporation reserves the right to make changes in circuit design. However. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.intersil.

95 VDD CS FIGURE 3.95 VDD VDR tCDR tF VIH VIL VDR tR VIH VIL tRC 0.DATA RETENTION MODE VDD 0. LOW VDD DATA RETENTION TIMING WAVEFORMS 6-167 .