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1) What |s |atch up?

LaLchup perLalns Lo a fallure mechanlsm whereln a paraslLlc LhyrlsLor (such as

a paraslLlc slllcon conLrolled recLlfler or SC8) ls lnadverLenLly creaLed wlLhln a
clrculL causlng a hlgh amounL of currenL Lo conLlnuously flow Lhrough lL once
lL ls accldenLally Lrlggered or Lurned on uependlng on Lhe clrculLs lnvolved
Lhe amounL of currenL flow produced by Lhls mechanlsm can be large enough
Lo resulL ln permanenL desLrucLlon of Lhe devlce due Lo elecLrlcal oversLress

)Why |s NAND gate preferred over NCk gate for fabr|cat|on?
nAnu ls a beLLer gaLe for deslgn Lhan nC8 because aL Lhe LranslsLor level Lhe moblllLy of
elecLrons ls normally Lhree Llmes LhaL of holes compared Lo nC8 and Lhus Lhe nAnu ls a fasLer
AddlLlonally Lhe gaLeleakage ln nAnu sLrucLures ls much lower lf you conslder L_phl and L_plh
delays you wlll flnd LhaL lL ls more symmeLrlc ln case of nAnu ( Lhe delay proflle) buL for nC8
one delay ls much hlgher Lhan Lhe oLher(obvlously L_plh ls hlgher slnce Lhe hlgher reslsLance p
moss are ln serles connecLlon whlch agaln lncreases Lhe reslsLance)

3)What |s No|se Marg|n? Lxp|a|n the procedure to determ|ne No|se Marg|n

1he mlnlmum amounL of nolse LhaL can be allowed on Lhe lnpuL sLage for whlch Lhe ouLpuL wlll
noL be effecLed

4)Lxp|a|n s|z|ng of the |nverter?

ln order Lo drlve Lhe deslred load capaclLance we have Lo lncrease Lhe slze (wldLh) of Lhe
lnverLers Lo geL an opLlmlzed performance

S) now do you s|ze NMCS and MCS trans|stors to |ncrease the thresho|d vo|tage?

6) What |s No|se Marg|n? Lxp|a|n the procedure to determ|ne No|se Marg|n?

1he mlnlmum amounL of nolse LhaL can be allowed on Lhe lnpuL sLage for whlch Lhe ouLpuL wlll
noL be effecLed

7) What happens to de|ay |f you |ncrease |oad capac|tance?

delay lncreases

)What happens to de|ay |f we |nc|ude a res|stance at the output of a CMCS c|rcu|t?

lncreases (8C delay)

9)What are the ||m|tat|ons |n |ncreas|ng the power supp|y to reduce de|ay?

1he delay can be reduced by lncreaslng Lhe power supply buL lf we do so Lhe heaLlng effecL
comes because of excesslve power Lo compensaLe Lhls we have Lo lncrease Lhe dle slze whlch ls
noL pracLlcal

10)now does kes|stance of the meta| ||nes vary w|th |ncreas|ng th|ckness and |ncreas|ng

8 ( *l) / A

11)Ior CMCS |og|c g|ve the var|ous techn|ques you know to m|n|m|ze power consumpt|on?

ower dlsslpaLlonCv2f from Lhls mlnlmlze Lhe load capaclLance dc volLage and Lhe operaLlng

1) What |s Charge Shar|ng? Lxp|a|n the Charge Shar|ng prob|em wh||e samp||ng data from a

ln Lhe serlally connecLed nMCS loglc Lhe lnpuL capaclLance of each gaLe shares Lhe charge wlLh
Lhe load capaclLance by whlch Lhe loglcal levels drasLlcally mlsmaLched Lhan LhaL of Lhe deslred
once 1o ellmlnaLe Lhls load capaclLance musL be very hlgh compared Lo Lhe lnpuL capaclLance of
Lhe gaLes (approxlmaLely 10 Llmes)

13)Why do we gradua||y |ncrease the s|ze of |nverters |n buffer des|gn? Why not g|ve the
output of a c|rcu|t to one |arge |nverter?

8ecause lL can noL drlve Lhe ouLpuL load sLralghL away so we gradually lncrease Lhe slze Lo geL
an opLlmlzed performance

14)What |s Latch Up? Lxp|a|n Latch Up w|th cross sect|on of a CMCS Inverter now do you
avo|d Latch Up?

LaLchup ls a condlLlon ln whlch Lhe paraslLlc componenLs glve rlse Lo Lhe LsLabllshmenL of low
reslsLance conducLlng paLh beLween vuu and vSS wlLh ulsasLrous resulLs

1S) G|ve the express|on for CMCS sw|tch|ng power d|ss|pat|on?


16) What |s 8ody Lffect?

ln general mulLlple MCS devlces are made on a common subsLraLe As a resulL Lhe subsLraLe
volLage of all devlces ls normally equal Powever whlle connecLlng Lhe devlces serlally Lhls may
resulL ln an lncrease ln sourceLosubsLraLe volLage as we proceed verLlcally along Lhe serles
chaln (vsb10 vsb2 0)Whlch resulLs vLh2vLh1

17) Why |s the substrate |n NMCS connected to Ground and |n MCS to VDD?

we Lry Lo reverse blas noL Lhe channel and Lhe subsLraLe buL we Lry Lo malnLaln Lhe dralnsource
[uncLlons reverse blased wlLh respecL Lo Lhe subsLraLe so LhaL we donL loose our currenL lnLo Lhe

1) What |s the fundamenta| d|fference between a MCSIL1 and 8I1 ?

ln MCSlL1 currenL flow ls elLher due Lo elecLrons(nchannel MCS) or due Lo holes(pchannel
MCS) ln 8!1 we see currenL due Lo boLh Lhe carrlers elecLrons and holes 8!1 ls a currenL
conLrolled devlce and MCSlL1 ls a volLage conLrolled devlce

19)Wh|ch trans|stor has h|gher ga|n 8I1 or MCS and why?

8!1 has hlgher galn because lL has hlgher LransconducLance1hls ls because Lhe currenL ln 8!1 ls
exponenLlally dependenL on lnpuL where as ln MCSlL1 lL ls square law

0)Why do we gradua||y |ncrease the s|ze of |nverters |n buffer des|gn when try|ng to dr|ve a
h|gh capac|t|ve |oad? Why noL glve Lhe ouLpuL of a clrculL Lo one large lnverLer?

We cannoL use a blg lnverLer Lo drlve a large ouLpuL capaclLance because who wlll drlve Lhe blg
lnverLer? 1he slgnal LhaL has Lo drlve Lhe ouLpuL cap wlll now see a larger gaLe capaclLance of
Lhe 8lC lnverLerSo Lhls resulLs ln slow ralse or fall Llmes A unlL lnverLer can drlve approxlmaLely
an lnverLer LhaLs 4 Llmes blgger ln slze So say we need Lo drlve a cap of 64 unlL lnverLer Lhen we
Lry Lo keep Lhe slzlng llke say 141664 so LhaL each lnverLer sees a same raLlo of ouLpuL Lo lnpuL
cap 1hls ls Lhe prlme reason behlnd golng for progresslve slzlng

1)In CMCS techno|ogy |n d|g|ta| des|gn why do we des|gn the s|ze of pmos to be h|gher than
the nmosWhat determ|nes the s|ze of pmos wrt nmos 1hough th|s |s a s|mp|e quest|on try to
||st a|| the reasons poss|b|e?

ln MCS Lhe carrlers are holes whose moblllLy ls less aprrox half Lhan Lhe elecLrons Lhe
carrlers ln nMCS 1haL means MCS ls slower Lhan an nMCS ln CMCS Lechnology nmos helps
ln pulllng down Lhe ouLpuL Lo ground ann MCS helps ln pulllng up Lhe ouLpuL Lo vdd lf Lhe
slzes of MCS and nMCS are Lhe same Lhen MCS Lakes long Llme Lo charge up Lhe ouLpuL
node lf we have a larger MCS Lhan Lhere wlll be more carrlers Lo charge Lhe node qulckly and
overcome Lhe slow naLure of MCS 8aslcally we do all Lhls Lo geL equal rlse and fall Llmes for
Lhe ouLpuL node

)Why MCS and NMCS are s|zed equa||y |n a 1ransm|ss|on Gates?

ln 1ransmlsslon CaLe MCS and nMCS ald each oLher raLher compeLlng wlLh each oLher 1haLs
Lhe reason why we need noL slze Lhem llke ln CMCS ln CMCS deslgn we have nMCS and MCS
compeLlng whlch ls Lhe reason we Lry Lo slze Lhem proporLlonal Lo Lhelr moblllLy

3)A|| of us know how an |nverter works What happens when the MCS and NMCS are
|nterchanged w|th one another |n an |nverter?

l have seen slmllar Cs ln some of Lhe dlscusslons lf Lhe source draln also connecLed
properlylL acLs as a buffer 8uL suppose lnpuL ls loglc 1 C/ wlll be degraded 1 Slmllarly
degraded 0

4)A good quest|on on Layouts G|ve S |mportant Des|gn techn|ques you wou|d fo||ow when
do|ng a Layout for D|g|ta| C|rcu|ts?

a)ln dlglLal deslgn declde Lhe helghL of sLandard cells you wanL Lo layouLlL depends upon how
blg your LranslsLors wlll bePave reasonable wldLh for vuu and Cnu meLal paLhsMalnLalnlng
unlform PelghL for all Lhe cell ls very lmporLanL slnce Lhls wlll help you use place rouLe Lool
easlly and also lncase you wanL Lo do manual connecLlon of all Lhe blocks lL saves on loL of area
b)use one meLal ln one dlrecLlon only 1hls does noL apply for meLal 1 Say you are uslng meLal 2
Lo do horlzonLal connecLlons Lhen use meLal 3 for verLlcal connecLlons meLal4 for horlzonLal
meLal 3 verLlcal eLc
c)lace as many subsLraLe conLacL as posslble ln Lhe empLy spaces of Lhe layouL
d)uo noL use poly over long dlsLances as lL has huge reslsLances unless you have no oLher cholce
e)use flngered LranslsLors as and when you feel necessary
f)1ry malnLalnlng symmeLry ln your deslgn 1ry Lo geL Lhe deslgn ln 8l1 Sllced manner

S)What |s metastab|||ty? When]why |t w||| occur?D|fferent ways to avo|d th|s?

MeLasLable sLaLe A unknown sLaLe ln beLween Lhe Lwo loglcal known sLaLes1hls wlll happen lf
Lhe C/ cap ls noL allowed Lo charge/dlscharge fully Lo Lhe requlred loglcal levels
Cne of Lhe cases ls lf Lhere ls a seLup Llme vlolaLlon meLasLablllLy wlll occur1o avold Lhls a
serles of lls ls used (normally 2 or 3) whlch wlll remove Lhe lnLermedlaLe sLaLes

6)Let A and 8 be two |nputs of the NAND gate Say s|gna| A arr|ves at the NAND gate |ater
than s|gna| 8 1o opt|m|ze de|ay of the two ser|es NMCS |nputs A and 8 wh|ch one wou|d you
p|ace near to the output?

1he laLe comlng slgnals are Lo be placed closer Lo Lhe ouLpuL node le A should go Lo Lhe nmos
LhaL ls closer Lo Lhe ouLpuL

What is a Transmission Gate (AnaIog Switch)?
Jun 10, 2008

Abstract: This application note describes the purpose and basic operation of a transmission gate. The article explains how a transmission gate can be used to
quickly isolate multiple signals with a minimal investment in board area and with a negligible degradation in the characteristics of those critical signals. The
DS3690 is the example device.

asic Operation
A transmission gate, or analog switch, is defined as an electronic element that will selectively block or pass a signal level from the input to the output.
This solid-state switch is comprised of a pMOS transistor and nMOS transistor. The control gates are biased in a complementary manner so that both
transistors are either on or off.

When the voltage on node A is a Logic 1, the complementary Logic 0 is applied to node active-low A, allowing both transistors to conduct and pass
the signal at N to OUT. When the voltage on node active-low A is a Logic 0, the complementary Logic 1 is applied to node A, turning both transistors
off and forcing a high-impedance condition on both the N and OUT nodes. This high-impedance condition represents the third "state" (high, low, or
high-Z) that the DS3690 channel may reflect downstream.

The schematic diagram (igure 1) includes the arbitrary labels for N and OUT, as the circuit will operate in an identical manner if those labels were
reversed. This design provides true bidirectional connectivity without degradation of the input signal.

igure 1. Schematic representation of a transmission gate.

The common circuit symbol for a transmission gate depicts the bidirectional nature of the circuit's operation (igure 2).

igure 2. Circuit symbol.

TOP!C: NNOS is faster then PNOS
Posted by: jolly S/3/2004 3:48:48 AN Category: Semiconductors
Questions posted: 1 Comments Posted: 0
it is said that NMOS is faster then PMOS because mobility of electrons is around
3 times more than holes. MOS due to majority carrier device is effected by this.
Can anybody tell why electrons show such a Character?
My arguement is when hole physically does not have any mass in comparison to
electron than why it does not have more mobility....

Posted by: spraveen87 9/15/2010 5:54:53 AM
Comments Posted:1
hello the answers are right , one small suggestion , starting of the answers are correct but ending is abrupt so if we can have a smooth ending it would help, thank you

Posted by: sreedhar 3/15/2006 7:45:03 AM
Comments Posted:28 Questions Posted:1
Hi pavan,

Answer for 1 Q

The switching speed of nor gates is higher thatn pmos .We prefer NAND gates.

n nand gates pmos is paralle where as in nor gate pmos is serial . So time taken in nor will be more because of its structure.

NMOS is 2 times faster than PMOS


Posted by: vivek1980 7/27/2004 6:02:29 AM
Comments Posted:3
according to me, anilksaini has given correct answer. would try to explain this in another way.... Hole is the effect where as electron is the cause i.e. when electrons move then
only a hole is created. As there are inertial delays so it is obvious that cause will be faster compared to the effect.So, NMOS are 2.5 times faster than the electrons.

Posted by: vivek1980 7/27/2004 6:01:29 AM
Comments Posted:3
according to me, anilksaini has given correct answer. would try to explain this in another way.... Hole is the effect where as electron is the cause i.e. when electrons move then
only a hole is created. As there are inertial delays so it is obvious that cause will be faster compared to the effect.So, NMOS are 2.5 times faster than the electrons.

Posted by: shwetank 7/6/2004 5:38:34 AM
Comments Posted:8 Questions Posted:2
hoel is basically proton and the mass of
electron is less than proton due to which mobility of electron is more

Posted by: aniIksaini 6/22/2004 3:30:54 AM
Comments Posted:5 Questions Posted:3
effective mass of hole is greater than electron.that'why electron have high mobility than hole.

What is the difference between NMOS and PMOS?
NMOS is built with n-type source and drain and a p-type substrate, while PMOS is built with p-type source and drain and a n-type substrate. n a NMOS, carriers
are electrons, while in a PMOS, carriers are holes. When a high voltage is applied to the gate, NMOS will conduct, while PMOS will not. Furthermore, when a low
voltage is applied in the gate, NMOS will not conduct and PMOS will conduct. NMOS are considered to be faster than PMOS, since the carriers in NMOS, which
are electrons, travel twice as fast as holes, which are the carriers in PMOS. But PMOS devices are more immune to noise than NMOS devices. Furthermore,
NMOS Cs would be smaller than PMOS Cs (that give the same functionality), since the NMOS can provide one-half of the impedance provided by a PMOS
(which has the same geometry and operating conditions).

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