This action might not be possible to undo. Are you sure you want to continue?
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
“Digital Logic
For VLSI Design”
Sandeepani School of VLSI Design
Bangalore/Hyderabad
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
System:
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Digital System!
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Combinational vs. Sequential
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Levels of integrated circuits
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Binary Valued Signals
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Binary Valued Signals … contd
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Binary Valued Signals … contd
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Two logic levels but very powerful
applications……… possible!
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
VLSI: but why?
Integration improves the design:
lower parasitics = higher speed;
lower power;
physically smaller.
Integration reduces manufacturing cost(almost) no
manual assembly.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
VLSI Applications
VLSI is an implementation technology for electronic
circuitry  analogue or digital
It is concerned with forming a pattern of
interconnected switches and gates on the surface of
a crystal of semiconductor
Microprocessors
personal computers
microcontrollers
Memory  DRAM / SRAM
Special Purpose Processors  ASICS (CD players, DSP
applications)
Optical Switches
Has made highly sophisticated control systems mass
producible and therefore cheap
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
What is a Silicon Chip?
A pattern of interconnected switches and gates on the
surface of a crystal of semiconductor (typically Si)
These switches and gates are made of
areas of ntype silicon
areas of ptype silicon
areas of insulator
lines of conductor (interconnects) joining areas
together
Aluminium, Copper, Titanium, Molybdenum,
polysilicon, tungsten
The geometry of these areas is known as the layout
of the chip
Connections from the chip to the outside world are
made around the edge of the chip to facilitate
connections to other devices
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Logic families
Commonly used are 3
TransistorTransistor logic (TTL)
Complementary metal oxide semiconductor
(CMOS)
Emitter Coupled Logic (ECL)
Most important characteristics of TTL & CMOS
are that
TTL gates switch very fast
CMOS has very low power dissipation
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CMOS Technology: Modern Logic Design
First proposed in the 1960s. Was not seriously considered
until the severe limitations in power density and
dissipation occurred in NMOS circuits
Now the dominant technology in IC manufacturing
Employs both pMOS and nMOS transistors to form logic
elements
The advantage of CMOS is that its logic elements draw
significant current only during the transition from one
state to another and very little current between
transitions  hence power is conserved.
In the case of an inverter, in either logic state one of the
transistors is off. Since the transistors are in series, (~ no)
current flows.
See twinwell cross sections
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
BiCMOS
A known deficiency of MOS technology is its limited load
driving capabilities (due to limited current sourcing and
sinking abilities of pMOS and nMOS transistors.
Bipolar transistors have
higher gain
better noise characteristics
better high frequency characteristics
BiCMOS gates can be an efficient way of speeding up VLSI
circuits
See table for comparison between CMOS and BiCMOS
CMOS fabrication process can be extended for BiCMOS
Example Applications
CMOS  Logic
BiCMOS I/O and driver circuits
ECL  critical high speed parts of the system
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CMOS Inverter
V
DD
A Y
GND
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CMOS NAND gates
A
B
Y
V
dd
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CMOS NOR gates
A
B
Y
V
DD
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
NMOS gates
Inverter
Nand
Nor
Nand/Nor preference
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Exercise
Implement AND,OR gates using CMOS
logic
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CMOS Vs Bipolar Technology
CMOS Technology
Low static power
dissipation
High i/p impedance
(low drive current)
Medium speed
High packing density
Low o/p drive current
Bidirectional capability
A near ideal switching
Bipolar Technology
High power dissipation
Low i/p impedance (high
drive current)
High speed
Low packing density
High o/p drive current
Essentially unidirectional
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Moore’s
Law
Gordon Moore: cofounder of Intel.
Predicted that number of transistors per
chip would grow exponentially (double
every 18 months).
Exponential improvement in technology
is a natural trend: steam engines,
dynamos, automobiles. Moore’s Law
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Moore’s Law plot
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CPLD Basics Review:
What is a CPLD?
Definition:
Complex
Programmable
Logic Device  A
hybrid of PLD
blocks and
interconnect for
midsize logic
designs
IO/Registers/Logic IO/Registers/Logic Interconnect
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CPLD Architecture
• I/O  Input Output block. The gateway between the CPLD fabric and the outside world
• MC  Macrocell. The Part of the CPLD architecture containing the register
• Logic Block  Where product terms are built
• Product Term  Single logical function made out of AND and OR terms
• Interconnect Array  Connection between the I/O, MC, and logic blocks
• Function Block  The name for a logic block and its associated macrocells
I
n
t
e
r
c
o
n
n
e
c
t
A
r
r
a
y
MCn
MC0
I/O I/O
MCn
MC0
I/O I/O
Logic
Block
MCn
MC0
Logic
Block
Logic
Block
Logic
Block
MCn
MC0
Function Block
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CPLD Definitions:
High Performance
Pintopin
combinatorial delay
Time from input
through interconnect
to output (ns)
Maximum registered
frequency
Fastest operation of
flipflops (MHz)
Tpd (ns) Fmax (MHz)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CPLDs versus FPGAs
• CPLD architecture
• FPGA architecture
– Product term array
– Interconnect array
– Wide fanin
– Deterministic timing
– Pin locking
– Lookup table based
– X/Y routing matrix
– Higher density
– Additional features
• DLL
• Multipliers
I
n
t
e
r
c
o
n
n
e
c
t
A
r
r
a
y
MCn
MC0
I/O
I/O
MCn
MC0
I/O
I/O
Logic
Block
MCn
MC0
Logic
Block
Logic
Block
Logic
Block
MCn
MC0
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
Logic
Cell
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CPLD or FPGA?
CPLD
Nonvolatile
Consistent pintopin timing
Simple timing model
Very low power consumption
Lowest cost point
Fast internal performance
Small packages (CP56, 132)
Applications  Logic decode/
integration, state machines
• FPGA
– Volatile
– Requires memory device
to load design at power up
– Complex timing model
– Large complex designs
– Memory resources
– Applications  PCI, high
speed serial
communication, embedded
processors
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Fieldprogrammable gate arrays
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
FPGAs and VLSI
FPGAs are standard parts:
Premanufactured, shorter design cycle.
Don‟t worry (much) about physical design.
Time to market is less, but FPGAs are slower,
larger, more powerhungry.
Custom silicon:
Tailored to your application.
Generally lower power consumption.
Time to market is more
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Embedded Digital System: The big
picture
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
A Historical Perspective: the
PLA
x
0
x
1
x
2
AND
plane
x
0
x
1
x
2
Product terms
OR
plane
f
0
f
1
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
TwoLevel Logic
Inverting format (NOR
NOR) more effective
Every logic function can be
expressed in sumofproducts
format (ANDOR)
minterm
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
ArrayBased Programmable Logic
PLA PROM PAL
I
5
I
4
O
0
I
3
I
2
I
1
I
0
O
1
O
2
O
3
Programmable AND array
Programmable
OR array
I
5
I
4
O
0
I
3
I
2
I
1
I
0
O
1
O
2
O
3
Programmable AND array
Fixed OR array
Indicates programmable connection
Indicates fixed connection
O
0
I
3
I
2
I
1
I
0
O
1
O
2
O
3
Fixed AND array
Programmable
OR array
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Programming a PROM
f
0
1 X
2
X
1
X
0
f
1
NA NA
: programmed node
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
More Complex PAL
From Smith97
i inputs, j minterms/macrocell, k macrocells
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Number System & Conversions
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
• Code conversions
• Selfcomplementary code
• Weighed & Non Weighed codes
Recap
• Binary Addition
• Binary Subtraction
• Binary multiplication
• Binary Division
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Exercise
Convert 101100.101 into hexadecimal, octal and
decimal.
Convert F4A into binary
Answers :
 101100.101 (2) = 2C.A (16) = 44.625 (10)
 101100.101 (2) = 54.5 (8)
 F4A (16 )=111101001010 (2)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
General Positional Number
Conversion
radixr to decimal :
decimal to radixr :
 Successive division of D by r
 The remainder of the long division will give the
digits starting from the least significant digit
D d r i
i n
p
i
= ·
=÷
÷
¿
1
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Example  Decimal to Binary :
179 (10)
179/2 = 89 ( 1 ) LSB
89/2 = 44 ( 1 )
44/2=22 ( 0 )
22/2=11 ( 0 )
11/2=5 ( 1 )
5/2=2 ( 1 )
2/2=1 ( 0 )
1/2=0 (1)MSB
Result : 10110011 (2)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Hexadecimal Addition
Add digits in Convert each digit into decimal
decimal
Convert the result into Hexadecimal
Produce carry when digits sum is > = the radix (16 )
Example
1 0 1 0 1 0 1 0
2 F A 5 2 15 10 5
+ A 9 3 C 10 9 3 12
_________ _______________
D 8 E 1 (13) (16+8) (14) (16+1)
D 8 E 1
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Switching Algebra
Definition
Shannon’s expansion theorem
Principle of duality
Complementation rules
SOP and POS
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Duality
Axioms and Theorems – come in
pairs
Get one of the pair from the other by:
1. Replacing AND with OR
2. Replacing OR with AND
3. Replacing 1 with 0
4. Replacing 0 with 1
If E is a valid Boolean expression,
then E
d
(its dual) is also valid
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Canonical Forms
Literal – switching variable or its
complement (e.g., x or y)
Product Term or Implicant – series of
literals related by AND operator
Sum Term – Series of literals related by
OR operator
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Boolean Algebra
AXIOMS :
DEFINITIONS:
THEOREMS:
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Prove the following:
(Do not use Kmaps)
1. A + A’B = A+B
2. Sum of products of three variables is equal to 1.
3. Product of sums of three variables is equal to 0.
4. A’B’C’+A’B’C+A’BC’+AB’C’+ABC’ = A’B’+C’
Problems
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Representation Of Numbers: a revision
• Signed magnitude
• 1’s Complement
• 2’s Complement
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Signed magnitude representation
Humans use a signedmagnitude system: we add + or  in front of a
magnitude to indicate the sign.
We could do this in binary as well, by adding an extra sign bit to the
front of our numbers. By convention:
A 0 sign bit represents a positive number.
A 1 sign bit represents a negative number.
Examples:
1101
2
= 13
10
(a 4bit unsigned number)
01101 = +13
10
(a positive number in 5bit signed magnitude)
1 1101 = 13
10
(a negative number in 5bit signed magnitude)
0100
2
= 4
10
(a 4bit unsigned number)
00100 = +4
10
(a positive number in 5bit signed magnitude)
1 0100 = 4
10
(a negative number in 5bit signed magnitude)
• Range?
• Limitation?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
The MSB represents the sign bit ( 0 = +ve , 1 = ve )
The range for nbit is :
Example: n=5
* Range : from 15 to 15
* 10011= 3 , 01100 = +12
* 00000= 0 , 10000 =  0
Disadvantages :
1 Two possible representations of zero
2 Complicated digital adders
from to
n n
÷ ÷ + ÷
÷ ÷
( ) ( ) 2 1 2 1
1 1
Signed Magnitude Representation
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
One’s complement Representation
A different approach, one’s complement, negates numbers by
complementing each bit of the number.
We keep the sign bits: 0 for positive numbers, and 1 for negative.
The sign bit is complemented along with the rest of the bits.
Examples:
1101
2
= 13
10
(a 4bit unsigned number)
0 1101 = +13
10
(a positive number in 5bit one’s
complement)
1 0010 = 13
10
(a negative number in 5bit one’s
complement)
0100
2
= 4
10
(a 4bit unsigned number)
0 0100 = +4
10
(a positive number in 5bit one’s complement)
1 1011 = 4
10
(a negative number in 5bit one’s
complement)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Why is it called “1’s complement?”
Complementing a single bit is equivalent to subtracting it from 1.
0’ = 1, and 1  0 = 1 1’ = 0, and 1  1 = 0
Similarly, complementing each bit of an nbit number is equivalent
to subtracting that number from 2
n
1.
For example, we can negate the 5bit number 01101.
Here n=5, and 2
n
1 = 31
10
= 11111
2
.
Subtracting 01101 from 11111 yields 10010:
1 1 1 1 1
 0 1 1 0 1
1 0 0 1 0
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
1’s complement addition
To add one’s complement numbers:
First do unsigned addition on the numbers, including the sign
bits.
Then take the carry out and add it to the sum.
Two examples:
This is simpler and more uniform than signed magnitude addition.
0111 (+7)
+ 1011 + (4)
1 0010
0010
+ 1
0011 (+3)
0011 (+3)
+ 0010 + (+2)
0 0101
0101
+ 0
0101 (+5)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Two’s complement
Our final idea is two‟s complement. To negate a number, complement
each bit (just as for ones‟ complement) and then add 1.
Examples:
1101
2
= 13
10
(a 4bit unsigned number)
0 1101 = +13
10
(a positive number in 5bit two’s complement)
1 0010 = 13
10
(a negative number in 5bit ones’ complement)
1 0011 = 13
10
(a negative number in 5bit two’s complement)
0100
2
= 4
10
(a 4bit unsigned number)
0 0100 = +4
10
(a positive number in 5bit two’s complement)
1 1011 = 4
10
(a negative number in 5bit ones’ complement)
1 1100 = 4
10
(a negative number in 5bit two’s complement)
• Range?
• Limitation?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Floating – point numbers
• Fixed point number can not represent very large and very small
numbers.
• Example: N = ± M * B
E
for 8bit E range from –128 to +127
• IEEE format
N= ± 1. M * 2
E‟  127
(single precision – 32 bit) E = E‟ 127
± 1. M * 2
E‟  1023
(single precision – 64 bit) E = E‟ –1023
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Problems
Q. Represent the following in single precision format
(i ) 0.0110 * 2
6
(ii) –1
(iii)(10)
10
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
1. (500.21)
10
= ( ? )
2
2. (436.71)8 = ( ? )
16
3. Convert (231.3)Base 4 to Base 7
Convert Base 4 to Base 10
Convert Base 10 to Base 7
Ans : (63.515) Base 7
Examples
4. 316
8
– 451
8
= ? (Hint: Use 8’s Complement)
5. CB2
H
– 972
H
= ? (Hint: Use 16’s Complement)
6. 0011.1001
2
– 0001.1110
2
= ? Using 1’s complement form
7. 79  26 in BCD representation? (Hint: Use 9’s
Complement)
8. 5  8 in XS3?
9. Divide (10)
10
by (4)
10
in binary representation.
10. Convert (847)
10
to gray code representation.
11. Perform direct subtraction: (9)
10
– (10)
10
?
12. What is Hamming code?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Gates: electronic circuit that realizes a logical expression
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Logical Expressions
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
NAND/NOR Networks
Convert AND/OR Network into NAND/NOR
Network
Tips and Tricks
Think of bubbles on gates as inverters
Think of EXOR & EXNOR as parity ckts that
produce a 1 out if the number of 1’s in is odd
or even respectively
Use alternative NAND/NOR symbols
A 2 level NANDNAND /NORNOR ckt is
equivalent to a 2 level ANDOR / ORAND ckt
respectively and realize SOP / POS logical
expressions
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Structural Model of gates
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Ideal and real gates are different
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Discussion…
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
KMaps
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
SOP and POS Implementation
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Some Arithmetic Circuits
Adders:
Half adder
Full adder
Serial adder
Ripple carry adder
Carry Bypass adder
Carry look ahead adder
Carry select adder
Multipliers:
2bit by 2bit Multiplier
4bit by 3bit Multiplier
Magnitude Comparator
2bit Comparator
4bit Comparator
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Adders
Adder delay is dominated by carry
chain.
Carry chain analysis must consider
transistor, wiring delay.
Modern VLSI favors adder designs
which have compact carry chains.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Implementation of Half Adder
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Implementation of Full Adder
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
4Bit Ripple carry adder
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Ripple Carries
Cascade 64 full adders to get a 64bit
ripple carry adder
Problem: Slow – carries ripple
If stage delay = 20 nsec, Total delay =
64 X 20 = 1280 nsec
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Full adder
Computes onebit sum, carry:
s
i
= a
i
XOR b
i
XOR c
i
c
i+1
= a
i
b
i
+ a
i
c
i
+ b
i
c
i
Half adder computes twobit sum.
Ripplecarry adder: nbit adder built
from full adders.
Delay of ripplecarry adder goes
through all carry bits.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
4Bit Carry AdderSubtractor
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Serial Adder
Delay
Xi
Yi
Si
Ci + 1
Ci
Full Adder
Q. Design a 4bit serial adder with the help of two shift
register?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Carry Lookahead Adder
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Carrylook ahead adder
First compute carry
propagate,
generate:
P
i
= a
i
+ b
i
G
i
= a
i
b
i
Compute sum and
carry from P and G:
s
i
= c
i
XOR P
i
XOR G
i
c
i+1
= G
i
+ P
i
c
i
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Carry Equations
4 stage binary carry lookahead adder
A
14
, B
14
are addends, C
0
is input carry
Outputs are Sum S
14
and Carries C
14
Multiply out equations:
C
1
= G
1
+ P
1
C
0
C
2
= G
2
+ P
2
C
1
= G
2
+ P
2
G
1
+ P
2
P
1
C
0
C
3
= G
3
+ P
3
C
2
= G
3
+ P
3
G
2
+ P
3
P
2
G
1
+
P
3
P
2
P
1
C
0
C
4
= G
4
+ P
4
C
3
= G
4
+ P
4
G
3
+ P
4
P
3
G
2
+
P
4
P
3
P
2
G
1
+ P
4
P
3
P
2
P
1
C
0
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Carry LookAhead Adder
Big speedup – At most 4 logic delays to get all
carries
n = # full adder chips
t
total
= t
XOR
+ log
4
n X t
LACG
+ t
FA
t
XOR
= 10 nsec
t
LACG
= carry lookahead stage delay = 21 nsec
t
FA
= full adder delay = 15 nsec
t
total
= 10 nsec + 1 X 21 nsec + 15 nsec = 46
nsec
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Depth4 carrylook ahead
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Analysis
Deepest carry expansion requires gates
with large fan in: large, slow.
Carrylook ahead unit requires complex
wiring between adders and look ahead
unit—values must be routed back from
look ahead unit to adder.
Layout is even more complex with
multiple levels of look ahead.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
4 bit Carry Lookahead Adder
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Carryskip adder
Looks for cases in which carry out of a
set of bits is identical to carry in.
Typically organized into bbit stages.
Can bypass carry through all stages in a
group when all propagates are true: P
i
P
i+1
…P
i+b1
.
Carry out of group when carry out of last
bit in group or carry is bypassed.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Twobit carryskip structure
AND
P
i
P
i+1
P
i+b1
…
OR
C
i+b1
c
i
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Carryskip structure
b adder stages
skip
P[0,b1] Carry out
b adder stages
skip
P[b,2b1] Carry out
b adder stages
skip
P[2b,3b1]
Carry out
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Worstcase carryskip
Worstcase carrypropagation path goes
through first, last stages:
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Delay analysis
Assume that skip delay = 1 bit carry
delay.
Delay of kbit adder with block size b:
T = (b1) + 0.5 + (k/b –2) + (b1)
block 0 OR gate skips last block
For equal sized blocks, optimal block
size is sqrt(k/2).
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Carryselect adder
Computes two results in parallel, each
for different carry input assumptions.
Uses actual carry in to select correct
result.
Reduces delay to multiplexer.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Carry select adder
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Carryselect structure
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Carrysave adder
Useful in multiplication.
Input: 3 nbit operands.
Output: nbit partial sum, nbit carry.
Use carry propagate adder for final sum.
Operations:
s = (x + y + z) mod 2.
c = [(x + y + z) –2] / 2.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Pseudo or Carry Save Adder
Advantage – only final stage of partial
product addition needs to propagate
carries
A
16
B C
IN
Carries Sum
16 16
16 16
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Carry Save Addition (CSA)
A full adder sums 3 inputs and produces 2 outputs
Carry output has twice weight of sum output
N full adders in parallel are called carry save adder
Produce N sums and N carry outs
Z
4
Y
4
X
4
S
4
C
4
Z
3
Y
3
X
3
S
3
C
3
Z
2
Y
2
X
2
S
2
C
2
Z
1
Y
1
X
1
S
1
C
1
X
N...1
Y
N...1
Z
N...1
S
N...1
C
N...1
nbit CSA
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CSA Application
Use k2 stages of CSAs
Keep result in carrysave redundant form
Final CPA computes actual result
4bit CSA
5bit CSA
0001 0111 1101 0010
+
1011
0101_
0001
0111
+1101
1011
0101_
X
Y
Z
S
C
0101_
1011
+0010
X
Y
Z
S
C
A
B
S
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CSA Application
Use k2 stages of CSAs
Keep result in carrysave redundant form
Final CPA computes actual result
4bit CSA
5bit CSA
0001 0111 1101 0010
+
1011
0101_
01010_ 00011
0001
0111
+1101
1011
0101_
X
Y
Z
S
C
0101_
1011
+0010
00011
01010_
X
Y
Z
S
C
01010_
+ 00011
A
B
S
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CSA Application
Use k2 stages of CSAs
Keep result in carrysave redundant form
Final CPA computes actual result
4bit CSA
5bit CSA
0001 0111 1101 0010
+
1011
0101_
01010_ 00011
0001
0111
+1101
1011
0101_
X
Y
Z
S
C
0101_
1011
+0010
00011
01010_
X
Y
Z
S
C
01010_
+ 00011
10111
A
B
S
10111
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Adder comparison
Ripplecarry adder has highest
performance/cost.
Optimized adders are most effective in
very long bit widths (> 48 bits).
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
0
50
100
150
200
250
300
350
8
4
0
7
2
Bits
C
o
s
t
(
C
L
B
s
)
0
50
100
150
200
250
300
350
400
8
3
2
5
6
8
0
Bits
P
e
r
f
o
r
m
a
n
c
e

C
o
s
t
R
a
t
i
o
Ripple
Complet e
CLA
Skip
RCselect
© 1998 IEEE
0
20
40
60
80
100
120
8
3
2
5
6
8
0
Bits
O
p
e
r
a
t
i
o
n
a
l
T
i
m
e
(
n
s
)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Serial adder
May be used in signalprocessing
arithmetic where fast computation is
important but latency is unimportant.
Data format (LSB first):
0 1 1 0
LSB
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Serial adder structure
LSB control signal clears the carry shift
register:
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
BCD Adder
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
2bit X 2bit Multiplier
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
4bit X 3bit Multiplier
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Magnitude Comparator
Q. Design a 2bit digital comparator that accepts two
words A and B and gives three outputs :
G(>),
E(=) and
L(<).
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Magnitude Comparator
Q. Design a 4bit digital comparator that accepts two
words A and B and gives three outputs :
G(>),
E(=) and
L(<).
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
2bit Magnitude Comparator
Answer:
let x
1
= (A
1
exnor B
1
)
x
0
= (A
0
exnor B
0
)
Z
A=B
= x
1
. x
0
Z
A>B
= A
1
B‟
1
+ x
1
. A
0
B‟
0
Z
A<B
= A‟
1
B
1
+ x
1
. A‟
0
B
0
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
4bit Magnitude Comparator
Answer:
Z
A=B
= x
3
. x
2
. x
1
. x
0
Z
A>B
= A
3
B‟
3
+ x
3
. A
2
B‟
2
+x
3
. x
2
. A
1
B‟
1
+ x
3
. x
2
. x
1
. A
0
B‟
0
Z
A<B
= A‟
3
B
3
+ x
3
. A‟
2
B
2
+x
3
. x
2
. A‟
1
B
1
+ x
3
. x
2
. x
1
. A‟
0
B
0
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
A0
B0
A1
B1
A2
B2
A>B
A<B
A=B
A=B
output
A<B
output
A>B
output
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Binary Multipliers
1. Extremely complex even for small
word length
2. Very hard to test
3. Truth table expansion varies with
word length
4. Must use at least one carry
propagating full adder to sum up
partial products
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Multiplication Equations
Multiplicand A = A
h
X 2
4
+ A
l
Multiplier B = B
h
X 2
4
+ B
l
Product P = A X B = A
h
X B
h
X 2
8
+ (A
h
X
B
l
+ A
l
X B
h
) X 2
4
+ (A
l
X B
l
)
Must sum the 4 partial products
Since A & B are 8 bits, product is 16 bits
Need 5 full adders to do this
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
74LS274 – Produces 8bit product
4X4 bit Binary Multiplier
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Example
…
…
…
…
Cell 1
X
11
X
12
X
1l
Z
11
Z
12
Z
1m
…
…
…
Cell 2
X
21
X
22
X
2l
Z
21
Z
22
Z
2m
Y
21
Y
22
Y
2k
…
…
…
…
…
Cell i
X
i1
X
i2
X
il
Z
i1
Z
i2
Z
im
Y
i1
Y
i2
Y
ik
Y
i1
Y
i2
Y
ik
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Multiplication
Example:
1100 : 12
10
0101 : 5
10
1100
0000
1100
0000
00111100 : 60
10
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Multiplication
Example:
M x Nbit multiplication
Produce N Mbit partial products
Sum these to produce M+Nbit product
1100 : 12
10
0101 : 5
10
1100
0000
1100
0000
00111100 : 60
10
multiplier
multiplicand
partial
products
product
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
General Form
Multiplicand: Y = (y
M1
, y
M2
, …, y
1
, y
0
)
Multiplier: X = (x
N1
, x
N2
, …, x
1
, x
0
)
Product:
1 1 1 1
0 0 0 0
2 2 2
M N N M
j i i j
j i i j
j i i j
P y x x y
÷ ÷ ÷ ÷
+
= = = =
 
 
= =


\ .
\ .
¿ ¿ ¿¿
x
0
y
5
x
0
y
4
x
0
y
3
x
0
y
2
x
0
y
1
x
0
y
0
y
5
y
4
y
3
y
2
y
1
y
0
x
5
x
4
x
3
x
2
x
1
x
0
x
1
y
5
x
1
y
4
x
1
y
3
x
1
y
2
x
1
y
1
x
1
y
0
x
2
y
5
x
2
y
4
x
2
y
3
x
2
y
2
x
2
y
1
x
2
y
0
x
3
y
5
x
3
y
4
x
3
y
3
x
3
y
2
x
3
y
1
x
3
y
0
x
4
y
5
x
4
y
4
x
4
y
3
x
4
y
2
x
4
y
1
x
4
y
0
x
5
y
5
x
5
y
4
x
5
y
3
x
5
y
2
x
5
y
1
x
5
y
0
p
0
p
1
p
2
p
3
p
4
p
5
p
6
p
7
p
8
p
9
p
10
p
11
multiplier
multiplicand
partial
products
product
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
16X16 Mult. Dot Diagram
Each dot represents a bit
partial products
m
u
l
t
i
p
l
i
e
r
x
x
0
x
15
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Parallel Binary Multiplier
+
Y
P C
Y
X
CO
PO
X
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
X
+
Y
P C
Y
X
CO
PO
OneBit Multiplier Cell
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Comparator Time Delays
Linear connection
t
c
= individual comparator delay
t
total
= m t
c
, for m comparators = 4
X 27 = 162 nsec (4bit slices)
Cascaded connection
t
total
= (log
4
m + 1) X t
c
= 2 X 27 = 54
nsec
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Problems
Q.1. Design a circuit which will accept 4bit binary and
will provide 5bit BCD code?
Q.2. Design a 3bit squarer?
Q.3. A circuit accepts a 4bit I/p data & generates an o/p
Z=1whenever I/p is a prime number. Design the
circuit?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Problems
Q.4. The conditions under which an insurance company
will issue a policy are :
A married female 25 years old or older, or
A female under 25 years or
A married male under 25 years with no accident record, or
A married male with accident record, or
A married male under 25 years or older with no accident
record.
Obtain a simplified logic expression starting to whom a policy can be
issued.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Universal Logic Element
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Universal Logic Element
Which of these are Universal logic
elements?
1. 2:1 MUX
2. Exor2
3. {f(x,y)=x‟y}
4. {f(x,y,z)=(x+y)z‟}
5. Nand2
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Universal Logic Gate
Introduction
A set of gates is said to be universal if any
combinational system can be implemented using
gates just from that set.
The set {AND,NOT} or {OR,NOT} is universal .
So any set of gates that can implement either
{AND,NOT} or {OR,NOT} is universal.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Universal Logic gate : Nand2
Lets start with NAND gate.
• NAND(x,y)= (xy)‟ ⇒NAND(x,x)=(xx)‟=x‟ ⇒NOT(x)=NAND(x,x)
NOT gate can be implemented by a NAND gate
• AND(x,y)= xy = ((xy)‟)‟=(NAND(x,y))‟ . From the previous step, we know
how to implement NOT gate by a NAND gate
AND(x,y)=(NAND(x,y))‟=NAND(NAND(x,y), NAND(x,y))
• So,AND gate can be implemented by only using NAND gates
Since we can implement AND and NOT by only NAND gates,
{NAND, NOR} is a universal set,even without NOR gate.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Universal Logic Gate NAND Function
NAND ::= Negative AND
Y = ( A • B )´
NOT
OR
AND
Y
INV
A
A Y
A
B
A
B
AND 2
Y
Y
OR 2
B
Y
A
Y
A
B
=
=
=
NAND 2
Y
Y
A
B
A
Y
A A
NAND 2
B
Y
Y
NAND 2
B
B
A
A
NAND 2
A
NAND 2
B
Y
Y
A
NAND 2
B
Y
A
B
Y
B
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Universal Logic Gate NOR Function
NOR ::= Negative OR
Y = ( A + B )´
NOT
OR
AND
NOR 2
Y
INV
A
A Y
A
B
A
B
AND 2
Y
Y
OR 2
B
Y
A
Y
A
B
=
=
=
A
NOR 2
B
Y
Y A
A
A
NOR 2
B
Y
Y
A
NOR 2
B
Y
A
B
Y
B
Y
A A
NOR 2
B
Y
Y
NOR 2
B
B
A
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Universal Logic Gate Multiplexor Function
Multiplexor
Y = A • S + B • S´
NOT
OR AND
Y
Y
A
Y
V C C
G N D
G N D
G N D
G N D
Y
S 1 S 0
Y
D 0
D 1
D 2
D 3
D 0
D 1
D 2
D 3
M X 4 M X 4
M X 4
A
B
Y
Y
Y
Y
V C C
S 1 S 0
V C C
Y
D 0
D 1
D 2
D 3
S 1 S 0
Y
A
B
Y
Y
Implement the same using 2 to 1 Multiplexer
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Basic Data Processing Circuits
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
24 line Decoder with Enable Input
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Decoder (3:8)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Problems using Decoder
Q1. Implement 4:16 Decoder using two 3:8 Decoders
Q2. Realize a full adder using one 3:8 decoder & residual gates
Q3. Design BCD to decimal converter
• with false data rejected
• with false data accepted
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
4:16 Decoder using 3:8 Decoder
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Full Adder using Decoder
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Encoder
• DecimaltoBCD Encoder
• OctaltoBinary Encoder
Limitations?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
4Input priority Encoder
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Multiplexer
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
4:1 line Multiplexer
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Q1. Realize the following using only one 2:1 Mux
1. NOT
2. And2
3. OR2
4. Exor2
5. Exnor2
6. Latch
Problems
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Q2. Show how two 2to1 multiplexers (with no added gates)
could be connected to form a 3to1 MUX. Input selection should
be as follows:
If AB = 00, select Io
If AB = 01, select I1
If AB = 1 – (B is don`t care), select I2.
Problems
Q3. Realize the function F(A,B,C,D)=Σm(1,2,3,6,8,9,11,14) using an
8to1 MUX with control inputs A,B, and C.
Q4. Repeat Q2 with control inputs A,C, and D.
Q5. Repeat Q2 using a 4to1 MUX and added gates.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
2input mux
as programmable logic block
F
A 0
B
S
1
Configuration
A B S F=
0 0 0 0
0 X 1 X
0 Y 1 Y
0 Y X XY
X 0 Y
Y 0 X
Y 1 X X
1
Y
1 0 X
1 0 Y
1 1 1 1
XY
XY
X
Y
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Q6. Design a sequence generator that generates the sequence
“11100011”.
Q7. Design 1:8 demultiplexer using two 1:4 demultiplexers.
Q8. Implement the following boolean function using 8:1 MUX,
F(A,B,C,D) = E(0,1,3,4,8,9,15)
Problems, more problems
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Buffer
• A Buffer is a logic circuit which has one I/p line & one output line.
• It is a current amplifier & also called as driver.
A TriState Buffer
Q. Implement a 2to1 Mux with Tristate buffers
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Answer
Or
21 line Mux with Tristate buffer
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Wired logic
• Power dissipation in LOW output state increases
• Speed of the operation increases
• Fan out decreases
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Clock Generator Circuit ?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Now, solve this?
Look at the circuit diagram is given.
The “thermometer to binary
conversion” logic is a simple
combination circuitry which is to be
designed to provide a natural binary
representation using b
1
and b
0
for
the analog input V
in
, here b1 is the
most significant bit. Also realize the
logic for b
1
and b
o
using 2input
NAND gates only.
Try to find the resolution of this
circuit.
What circuit is this?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Combinational.
Output depends only on current input values.
Sequential.
Output depends on current input values and
present state of the circuit, where the present
state of the circuit is the current value of the
devices‟ memory.
Sequential circuits…
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Bistable Elements
The simplest sequential circuit.
It consist of a pair of inverters connected as
shown below. Notice the feedback loop.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Digital Analysis
Two stable states.
If Q is HIGH then the lower inverter has a HIGH at its
input and a LOW at its output. This in turn forces the
upper inverter‟s input to be LOW and its output to be
HIGH.
If Q is LOW then the lower inverter has a LOW at its
input and a HIGH at its output. This in turn forces the
upper inverter‟s input to be HIGH and its output to be
LOW.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Analog Analysis
Metastable behavior:
Consider the middle intersecting point in the
diagram shown below.
What would happen if a small amount of noise
varies either input voltage.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Latches and FlipFlops
Binary cells capable of storing 1 bit of
information.
Generates one of two possible stable states.
Two outputs labeled Q and Q‟.
One or more inputs.
These sequential devices differ in the way their
outputs are changed:
– The output of a latch changes independent
of a clocking signal.
– The output of a flip–flop changes at specific
times determined by a clocking signal.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
SR Latch with Control Input
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
D Latch
This latch eliminates the problem that occurs in the S‟R‟ latch when R=S=0.
C is an enable input:
When C=1 then the output follows the input D and the latch is said to be
open. Due to this fact this latch is also called transparent latch.
When C=0 then the output retains its last value and the latch is said to
be closed.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
D Latch
For proper operation
the D input must
not change during a
time interval around
the falling edge of C.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Edge Triggered D FlipFlop
This flipflop is made out of two D latches. The first latch is the master, and
the second the slave.
When CLK_L= 1 the master is open and the slave is closed. Q
m
and D
s
follow D
m
.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Edge Triggered D FlipFlop
Positive edgetriggered D flipflop.
Q* = D
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
JK Flip Flop
(USING D flip flop)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Excitation table of Flip Flops
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Flip Flop to Flip Flop conversions
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
FF – FF conversions
1. DT D=T⊕Q
2. TD T=D⊕Q
3. DJK D=Q’J+QK’
4. DSR
5. TSR
6. JKSR
7. SRJK
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
D from JK Flip Flop
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Problems (doubts)
Q. Design a circuit that generates two waveforms of 90° phase shift.
Q. Design a 50% duty cycle frequency doubler for an input
clk pulse of 50% duty cycle.
More Problems, Many more Problems………. Let us continue!
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Timing Issues
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Timing Issues
• Timing parameters
• Timing diagram
• Set up time
• Hold time
• Clock Skew
• Slack
• Critical path
• Maximum Frequency of Operation
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Timing parameters
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Timing parameters…contd
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Timing parameters…contd
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Timing diagram
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Setup and Hold Time
•Setup and hold time define a window of time which the D input must
be valid and stable in order to assure valid data on the Q output.
•Setup Time (Tsu) – Setup time is the time that the D input must be valid before
the FlipFlop samples.
•Hold Time (Th) – Hold time is the time that D input must be maintained valid
after the FlipFlop samples.
•Propagation Delay (Tpd) – Propagation delay is the time that takes to the
sampled D input to propagate to the Q output.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
FF1 FF2
Q1
Q2
CLOCKD
A LONG SLOW PATH
IN
CLK
Clock Skew
Synchronous systems using edge triggered flipflops work
properly only if all flipflops see the triggering edge at the
same time.
The difference between arrival times of the clock at different
devices is called clock skew.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Slack
At each node is a group of events modeling signal transitions
Arrival Time (AT)  when the signal arrives
AT
D Q
QB
RT
Required Time (RT)  when the signal is needed
SLEW
Slew (SLEW)  time for signal transition from logic levels
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Slack
AT RT
SLEW
Q. Am I meeting timing at this node?
SLACK = RT  AT
+SLACK
Timing is met when slack is greater than or equal to zero
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Maximum Operating Frequency
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Recap
Shift registers: SISO, PISO, PIPO, SIPO
Shift register counters ring counters and twisted
ring counters
Asynchronous/ synchronous counters
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Counters
Clocked sequential circuit with singlecycle state
diagram
Modulom counter = dividebym counter
Most Common:
nbit binary counter, where m = 2
n
n flipflops, counts 0 …
2
n
1
S3
S2
S1
Sm
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Ripple Counter
Q
Q
T
Q
Q
T
Q
Q
T
Q
Q
T
CLK
Q0
Q1
Q2
Q3
1 bit
divideby2
2 bit
divideby4
3 bit
divideby8
4 bit
divideby16
Uses
Minimal
Logic!
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Ripple Counter Timing
CLK
Q0
Q1
Q2
0 1 2 3 4
1A
2A
3A
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CLK
Q0
Q1
Q2
7 Should be 0! 1 2
n  T
CQ
for MSB change for nbit ripple counter => minimum clk period
1A
2A
3A
Ripple Counter Problem (It’s Slow!)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Synchronous Counters
All clock inputs connected to common
CLK signal
So all flipflop outputs change
simultaneously t
CQ
after CLK
Faster
More Complex Logic
Most Frequently Used Type of Counter
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Synchronous Serial Counter
Flipflops enabled
when all lower
flipflops = 1.
Enable
propagates
serially — limits
speed
Requires
(n1) A t < T
CLK
All outputs
change
simultaneously
t
CQ
after CLK
>T
Q EN
CLK
CNTEN Q0
Q1
Q2
Q3
Q EN
>T
Q EN
>T
Q EN
>T
Equation?
Delay?
A t
A t
A t
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Synchronous Parallel Counter
Singlelevel
enable logic per
flipflop
Fastest and most
complex type of
counter
Requires A t <
T
CLK
All outputs
change
simultaneously
t
CQ
after CLK
>T
Q EN
>T
Q EN
>T
Q EN
>T
Q EN
CLK
CNTEN Q0
Q1
Q2
Q3
Equation?
Delay?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CLOCK
/S0
/S1
/S2
/S3
/S4
/S5
/S6
/S7
0
1
2
3
4
5
6
7
0
1
Decoded Modulo8 Counter: Glitches!
More than 1 bit changes simultaneously
Glitches NOT a problem for synchronous inputs.
Glitches BAD for asynchronous inputs!
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Solve these:
Q1: Design a JK counter that goes through the states
1,2,3,6,7,8,11,13,1,… Implement the circuit and avoid locout
condition
Q2. Design a MOD 5 counter (divide by 5) counter using JK
flipflop. Also construct the timing diagram. Also draw the
timing diagram of MOD 10 counter.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Solve these: …contd
Q3. Design a asynchronous MOD 10 (decade) counter.
Q4. Design a nonsequential ripple counter, which will go
through the states 3,5,7,8,9,10,3,4,…..
Q5. Determine f
max
for the 4bit synchronous counter if t
pd
for each flipflop is 50 ns and tpd for each AND gate is 20 ns.
Compare this with fmax for a MOD16 ripple counter.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Interesting Problems:
Q1. Design a divideby3 counter with 50% duty cycle?
Question: Why in most of the designs only 50% duty cycle clocks
are used? Why can't we use a lesser duty cycle (less than 50%)
clock?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Q2. Design a divideby 1.5 counter?
Q3. Design a black box whose input clock and
output relationship as shown in diagram
below.
Interesting Problems … contd
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Finite State Machines
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Topics
FSM Basics
Types of Machines
Example Designs
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Example
Assume a stream of 50k bits are given to the
circuit whose output Z=1 when no. of 1`s in
50k bits are odd else Z = 0. Design the circuit.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Finite state machines are so named because the
sequential logic that implements them can be in
only a fixed number of possible states.
FSM is a systematic way of specifying any
sequential logic.
Ideally suited for complex sequential logic.
Finite State Machines
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
What is an FSM?
Design Specification Point of View
State machines are a means of specifying
sequential circuits which are generally
complex in their transition sequence
and depend on several control inputs.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
State machines are a group of flipflops, whose
groupstate transition pattern from one set of
values to another and depends on several
control inputs
What is an FSM?
Digital Circuit Point of View
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CLOCK
ASYNC
CONTROL
CURRENT
STATE
CONTROL
INPUTS
NEXT
STATE
CURRENT
STATE
COMB.
LOGIC
for
NEXT
STATE
STATE
REGISTER
FLIPFLOPS
PORTS
FSM Structure
COMBO. FOR
OUTPUT
OUTPUTS
MEALY
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Mealy Machine
The outputs depend on the current state and
the present value of the inputs.
Mealy outputs are asynchronous and can
change in response to any changes in the
inputs, independent of the clock.
GlitchesHow to avoid?
Require less no. of states compared to
Moore Machine.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Moore Machine
The outputs depend only on the present
state.
The outputs are computed by a
combinational logic block whose only
inputs are the flipflops' state outputs
The outputs change synchronously with the
state transition and the clock edge.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Finite state machine
FSM Structure:
. State register
 Stores current state
. Next state decoder logic (A)
 Decides next state based on
current state and inputs
. Output logic (B)
Decodes state (or states and
inputs) to produce outputs
.Outputs from the FSM can be a
function of:
 Current state only (moore)
 Current state and the current
inputs (Mealy)
A
B
A
B
c1k
c1k Moore FSM
Mealy FSM
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
FSM Design examples
Q1. Design a circuit that asserts its single output
whenever its input string has two 1's in
sequence.
Cases:
(i) Nonoverlapping
(ii) Overlapping of sequence
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Q2. Assume a stream of 50k bits are given to the
circuit whose output Z=1 when no. of 1`s in
50k bits are odd else Z = 0. Design the
circuit. (using Mealy machine)
FSM Design examples
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Q3. Design a circuit to detect a sequence “010”
(i) nonoverlapping
(ii) overlapping
using Mealy machine.
FSM Design examples
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
FSM design example
Design a circuit to detect a sequence “1010”
(i) nonoverlapping
(ii) overlapping
using Mealy machine.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
FSM design example
Design a circuit to detect a overlapping
sequence “101”
using
(1) Mealy machine.
(2) Moore machine
And compare the two designs
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Q4. A sequential circuit accepts two i/p`s X & Y
and generates an o/p Z = 1 whenever the i/p`s
are equal & same in the present as well as
previous clock cycle. Design a Mealy
machine.
Note: If any state machine has „n‟ inputs, no.
of arrows leaving the state will be 2
n
.
FSM Design examples
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
FSM design example
A sequential circuit has one input (X) and one
output (Z).The circuit examines groups of 4
consecutive inputs and produces an output
Z=1 if the input sequence 0101 or 1001
occurs. The circuit resets after every 4 inputs.
Find the Mealy state graph.
Ex: X= 0101  0010  1001  0100
Z= 0001  0000  0001  0000
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Q5.Design a Moore finite state recognizer that
has one input (X) and one output (Z). The
output is asserted whenever the input
sequence 010 has been observed, as long
as the sequence 100 has never been
seen.(Overlapping)
FSM Design examples
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Q6. A sequential circuit has one I/p and one
o/p. when I/p sequence “110” occurs the o/p
becomes 1 and remains 1 until the sequence
“110” occurs in which case the o/p returns
to zero. The output remains zero until “110”
occurs the third time. Draw the state
diagram and state table.
FSM Design examples
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Q7. State diagram of a transmitter is shown below.
Sketch the state diagram for the receiver.
Tx
Rx
X
X
Y
Y
0 1
1/0
0/0
0/1
1/1
Tx
Rx
??
FSM Design examples
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Problems, more
problems…
Design a pulse train generator circuit using
shift register for the following pulse train:
… 1 0 0 0 1 1 0 …
Next Question: Now can you design a circuit
to generate a specified waveform.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Introduction to Memories
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Classification
MEMORY
RAM
HYBRID
ROM
SRAM
DRAM
FLASH
EEPROM
PROM
EPROM
MASKED
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Memory array architecture
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Latch and Register based Memory
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
RAM
Types : SRAM& DRAM
Primary difference: lifetime of the data they
store.
Which to choose & on what basis?
Speed, Area & Cost.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Types : MASKED, PROM& EPROM
They are class of PLD s.
Distinguished by the methods used to write new
data to them (usually called programming) and
the number of times they can be rewritten.
ROM
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
MASKED : Programmed by manufacturer.
PROM: One time programmable.
EROM: Erased & reprogrammable again & again.
ROM
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
PLD s
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
ROM
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
ROM
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Exercise on PLAs
Design a full adder using PLA
Design a Binary to Gray code converter
using PLA
It is desired to generate the following 3
Boolean functions:
F1=ab’c+a’bc’+bc
F2=ab’c+bc+a’bc’
F3=a’b’c’+abc+a’c
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
BY using OR gate array write down the terms
p1,p2,p3,p4 and p5
p1 *
p2 * *
p3 *
P4 *
p5 *
f1 f2 f3
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
HYBRID
Combine features of both
EEPROM: Once written, the new data will remain
in the device foreveror at least until it is
electrically erased.
FLASH: The major difference is that flash devices
can only be erased one sector at a time, not byte
bybyte as in EEPROM.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Comparison: memories
Type Volatile Writeable Erase Size Cost(per Byte) Speed
SRAM Yes Yes Byte Expensive Fast
DRAM Yes Yes Byte Moderate Moderate
RAM No No N/A Inexpensive Fast
PROM No Only once N/A Moderate Fast
EPROM No Yes Entire Chip Moderate Fast
EEPROM No Yes Byte Expensive Fast
FLASH No Yes Sector Moderate Fast
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Problems
Expanding word size, capacity and both
Store 16 8 bit words using 16x4 RAMs
Obtain 1Kx8 module using 1Kx1 RAMs
Store 32 4 bit words using 16x4 chips
Obtain 8Kx8 ROM using 2Kx8 ROMs
Obtain 4Kx8 ROM using 1Kx4 ROMs
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Introduction to
STATIC TIMING ANALYSIS
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Concepts Covered
Introduction to STA
Timing Paths
Skew
Problems
Clock & Timing Constraints
Exceptional Paths
Multicycle relations with multiple clocks
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
STA is an exhaustive method of analyzing, debugging and
validating the timing performance of a design.
STA – What is Static Timing Analysis?
Advantages:
Much faster than timingdriven, gatelevel
simulation.
Exhaustive
Vector generation NOT required.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Setup Requirement
Hold Requirement
What are our circuit timing
requirements?
Clk
100 200 300 400 500 0
Data
Data Cannot
Change Within
These Windows
Data
Clk
D Q
QB
Output
OutputBar
STA – What is Static Timing Analysis?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Setup Requirement
Hold Requirement
Clk
100 200 300 400 500 0
Data
Clk
100 0
Data
Early
Required Time
Late
Required Time
STA – What is Static Timing Analysis?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Limitations of STA
• Multiple clocks
• False paths: Proper circuit functionality is not checked
• Latches
• Multicycle paths
Works best with synchronous (not asynchronous)
logic
Complex to learn
Must define timing requirements / exceptions
Difficulty in handling:
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
What is Dynamic Timing Analysis?
Advantage:
Can be very accurate (spicelevel)
Disadvantages:
•Analysis quality depends on stimulus vectors
•Nonexhaustive, slow
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
STA in ASIC Design Flow – Pre layout
Logic Synthesis
Design For test
Floor planning
Constraints
(clocks, input drive,
output load)
Static Timing Analysis
Static Timing Analysis
(estimated parasitics)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
STA in ASIC Design Flow – Post
Layout
Floor planning
Clock Tree Synthesis
Place and Route
Parasitic Extraction
SDF
(extracted parasitics)
Constraints
(clocks, input drive,
output load)
Static Timing Analysis
(estimated parasitics)
Static Timing Analysis
(extracted parasitics)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Wire Load Model
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Timing Graphs
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
STA  Timing Graph Introduction
Data
Clk
D Q
QB
Output
OutputBar
A node exists for every
Model pin 4
Cell Pin 8
Bottom
Top
Hierarchical pin 2
14
Q. How many nodes are in our design?
Node: where timing information is stored on the design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
STA  Node Types
Data
Clk
D Q
QB
Output
OutputBar
Top
Clock Nodes
All nodes along clock path
Created from “force clock constraints”
Data Nodes
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
STA  Events
At each node is a group of events modeling
signal transitions
Arrival Time (AT)  when the signal arrives
AT
D Q
QB
RT
Required Time (RT)  when the signal is needed
SLEW
Slew (SLEW)  time for signal transition from logic levels
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
STA  Meeting Timing
AT RT
SLEW
Q. Am I meeting timing at this node?
SLACK = RT  AT
+SLACK
Timing is met when slack is greater than or equal to
zero
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
STA  Meeting Timing
AT
RT
Q. Am I meeting late mode timing at this node?
SLACK = RT  AT
+SLACK
No, the falling edge slack is negative...
AT
RT
SLACK
HINT: RT should always be after AT
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
STA  Levels
Q. How many levels of logic are in this design?
1
Q. How many timing levels are in this design?
HINT: Determine the nodes first
2
3
4
1 2
3
5
7
8
9
10
6
HINT: Timing Levels = 2 * Logic Levels + 2
4
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
1.0
1.0
1.0
1.0
1.0
STA  Calculating AT
STEP 1 : Calculate timing level for each node
8
10
7
9
6
1
1
1
1
1
2
2
2
2
2
3
3
9
5
5
4
4
4
STEP 2 : Calculate AT from level 1 to level n
Simplifying assumptions:
Input arrival time of 1
Wire delay 0.2 ; gate delay 0.5
3.8
1.2
1.2
1.2
1.2
1.2
3.3
4.0
1.7
1.7
3.1
1.9
1.9
1.9
2.4
2.4
2.6
2.6
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
1.0
1.0
1.0
1.0
1.0
STA  Calculating RT
STEP: Calculate RT from level n to level 1
8
10
7
9
6
1
1
1
1
1
2
2
2
2
2
3
3
9
5
5
4
4
4
3.8
1.2
1.2
1.2
1.2
1.2
3.3
4.0
1.7
1.7
3.1
1.9
1.9
1.9
2.4
2.4
2.6
2.6
Simplifying assumptions:
One number for rise and fall
Output required time of 2.8
Wire delay 0.2 ; gate delay 0.5
2.8
2.6
2.1
1.9
2.1
1.4
0.2
1.2
0.5
0.2
0.5
0.5
1.2
1.4
0.7
1.4
1.9
1.2
0.7
0.7
0.0
1.4
0.0
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
1.0
1.0
1.0
1.0
1.0
STA  Calculating Slack
8
10
7
9
6
1
1
1
1
1
2
2
2
2
2
3
3
9
5
5
4
4
4
3.8
1.2
1.2
1.2
1.2
1.2
3.3
4.0
1.7
1.7
3.1
1.9
1.9
1.9
2.4
2.4
2.6
2.6
2.6
2.1
1.9
2.1
1.4
0.2
1.2
0.5
0.2
0.5
0.5
1.2
1.4
0.7
1.4
1.9
1.2
0.7
0.7
0.0
1.4
0.0
SLACK = RT  AT
Q: What is the formula for late mode slack?
0.5
1.2
0.2
0.5
1.2
1.2
0.5
1.2
1.2
1.2
1.2
1.2
0.5
0.5
1.2
0.5
1.2
0.5
0.5
1.2
1.2
0.5
0.2
2.8
Slack is calculated on an as needed basis
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
What Does Register Bound Mean ?
D Q
QB
D Q
QB
D Q
QB
D Q
QB
• Register bound implies that the combinational logic is
bounded by registers on the inputs and the outputs.
• Combinational logic is represented by a symbolic blob.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
STA Introduction Summary
• Basics (setup, hold)
• Timing Graph (Clock nodes, Data nodes)
• Event description (RT, AT, slew)
• Timing information for a design is stored on nodes
• At each node a group of events models signal
transitions.
• Slack expresses the relationship between signal
arrival time and required time at a node.
• Specifying the clocks constraints all registerto
register (registerbound) paths.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Basic Terminologies
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Concepts Covered
Minimum clock
period
Hold constraint
Clock skew
Clock latency
Clock jitter
Setup time
Hold time
ClocktoQ time
Cause and effect of
timing violations
Critical path
False path
Multicycle path
Specifying clocks
Ideal and computed
clocks
Generated clocks
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Basic Terminologies
Critical path: The slowest path on the chip
between flops or flops and pins. The critical
path limits the maximum clock speed.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Setup time:
The amount of time the synchronous input
must be stable before the active edge of clock.
Hold time:
The amount of time the synchronous input
must be stable after the active edge of clock.
Basic Terminologies
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Recovery time: It is the time available between the
asynchronous signal going inactive to the active clock
edge.
Removal time: It is the time between active clock edge
and asynchronous signal going inactive.
Recovery time:
Like setup time for asynchronous port (set, reset)
Removal time:
Like hold time for asynchronous port (set, reset)
Basic Terminologies
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Three Steps in Static Timing Analysis
Circuit is broken down into sets of timing
paths.
Delay of each path is calculated.
Path delays are checked to see if timing
constraints have been met.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
What is a Timing Path?
A Timing Path is a pointtopoint path in a
design which can propagate data from one flip
flop to another.
Each path has a startpoint and an endpoint
Startpoints:
Input ports, Clock pins of flipflops
Endpoints:
Output ports, Data input pins of flipflops
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Types of Timing Paths
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Organizing Timing Paths Into Groups
Timing paths are grouped into path groups by the
clocks controlling their endpoints.
Synthesis tools like Prime Time and Design
Compiler organize timing reports by path groups.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Critical path??
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Critical path??
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Basic Terminologies
Maximum Clock Frequency/ Minimum Clock
Period
The clock frequency for a synchronous
sequential circuit is limited by the timing
parameters of its flipflops and gates. This limit
is called the maximum clock frequency for the
circuit. The minimum clock period is the
reciprocal of this frequency.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Condition for Hold time
To satisfy hold time: Tc2q + Tpd (minimum) > Thold
D Q
QB
D Q
QB
clkbar
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
D Q Combinational
logic
D Q
CLK
t
ffpd
t
comb
t
setup
& t
hold
t
ffpd
 CLK to Q, FF propagation delay (min, max)
t
comb
 combinational logic dely (min, max)
t
setup
 input stable before clock (min)
t
hold
 input stable after clock (min)
JAL
Synchronous System 
Detailed Timing
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Example Timing Violations: Good Timing
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Required: t
clk,min
> t
ffpd,max
+ t
comb,max
+ t
setup,min
Difference = Setup time margin
>= 0 for guaranteed operation
Required: t
ffpd, min
+ t
comb,min
> t
hold,min
Difference = Hold time margin
>= 0 for guaranteed operation
Synchronous System  Detailed Timing
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
t
comb
= 2 ns, min and 20 ns, max t
ffpd
= 3 ns, min and 15 ns, max
t
setup
= 5 ns, min
t
hold
= 2 ns, min
Setup margin @ 10 MHz clk?
Max Frequency?
Hold Margin?
Combinational
logic
State
Register
Q3
Q2
Q1
in1
in2
JAL
Synchronous System Example
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
t
comb
= 2 ns, min and 20 ns, max t
ffpd
= 3 ns, min and 15 ns, max
t
setup
= 5 ns, min
t
hold
= 2 ns, min
Setup margin @ 10 MHz clk? 100  (15 + 20 +5) = 60 ns
Max Frequency? t
clk,min
>= 40 ns, so f
max
<= 25 MHz
Hold Margin? (3 + 2) 2 = 3ns
Combinational
logic
State
Register
Q3
Q2
Q1
in1
in2
Synchronous System Example
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
74LS74 Data Sheet Timing
Parameter Min Max Units
t
W
Pulse Width  Clock High 18 ns
 Preset Low 15 ns
 Clear Low 15 ns
t
SU
Setup Time 20 ns
t
H
Hold Time 0 ns
f
MAX
Max Clock Frequency 20 MHz
t
PLH
Prop Delay, ClocktoQ 35 ns
t
PLH
Prop Delay, PresettoQ 35 ns
t
PLH
Prop Delay, CleartoQ 35 ns
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Functional Timing Diagram
Shows no delays, so all edges line up
Shows what happens each clock, ignoring exact
delays
Illustrates operation, but does not specify upper and
lower limits
INSUFFICIENT information for a REAL system design
Clock
Sig1
Sig2
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
t
H
t
L
Clock
t
ffpd
flipflop
outputs
combinational
outputs
t
comb
t
clk
setuptime
margin t
setup
t
hold
flipflop
inputs
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Example Timing Violations: Setup Violation
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Example Timing Violations: Hold Violation
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Clock Skew
• Clock Skew: The maximum difference in arrival time of the
clock signal to each register in the design
clock
Clock arrival
time at 1.1ns
Clock arrival
time at 1.3ns
Skew = 1.3ns  1.1ns = .2ns
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Absolute Clock Skew – A Definition
Your chip
clock input
Flip
Flop
Time from clock input (at pin) to
clock input at a given flip flop
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Relative Clock Skew
Your chip
clock input
Flip
Flop
Time between 2 flip flops receiving
the clock signal
Flip
Flop
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Failure / Data loss Due To Large
Skew
Combinational
Logic
Flip
Flop
Flip
Flop
o delay
clk
“B”
Aout Ain
“A”
Bin
If new data (Ain) gets to point
“Bin” before clock does, system
will fail by simply skipping over
old data…
For this illustration  ignore t
setup
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Combinational
Logic
Flip
Flop
Flip
Flop
o delay
clk
“B”
Aout Ain
“A”
Bin
Clock arrives at point “A”
T = 0ns
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Data arrives at combo logic input
Combinational
Logic
Flip
Flop
Flip
Flop
o delay
clk
“B”
Ain
“A”
Bin
Aout
T = t
clktoQ
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Data Exits Comb Logic
Combinational
Logic
Flip
Flop
Flip
Flop
o delay
clk
“B”
Ain
“A”
Aout
new
Bin
Bin
T = t
clktoQ
+ t
logic
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Clock Reaches “B”
Combinational
Logic
Flip
Flop
Flip
Flop
clk
“B”
Ain
“A”
Aout
new
Bin
Bin
o delay
T = t
clktoQ
+ t
logic
T
skew
= t
o
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Failure!!!
Combinational
Logic
Flip
Flop
Flip
Flop
clk
“B”
Ain
“A”
Aout
new
Bin
Bin
o delay
New
Bin
What happened to old Bin???
If t
clktoQ
+t
logic
< t
o
it fails…
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Clock Jitter
jitter
clock
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Clock jitter is caused by:
• temperature and voltage variations over time
• temperature and voltage variations across different locations on a chip
• manufacturing variations between different parts
• etc.
Clock Jitter
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
More on Skew
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Positive & Negative Skew
R1
In
(a) Positive skew
Combinational
Logic
D Q
t
CLK1
CLK
delay
t
CLK2
R2
D Q
Combinational
Logic
t
CLK3
R3
• • •
D Q
delay
R1
In
(b) Negative skew
Combinational
Logic
D Q
t
CLK1
delay
t
CLK2
R2
D Q
Combinational
Logic
t
CLK3
R3
• • •
D Q
delay CLK
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Positive Skew
CLK1
CLK2
T
CLK
o
T
CLK
+ o
+
t
h
o
2
1
4
3
R1
In
Combinational
Logic
D Q
t
CLK1
CLK
delay
t
CLK2
R2
D Q
Combinational
Logic
t
CLK3
R3
• • •
D Q
delay
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Negative Skew
CLK1
CLK2
T
CLK
o
T
CLK

o
2
1
4
3
R1
In
Combinational
Logic
D Q
t
CLK1
delay
t
CLK2
R2
D Q
Combinational
Logic
t
CLK3
R3
• • •
D Q
delay CLK
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Example Timing Violations: Minimum Clock Period
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Example Timing Violations: Hold Constraint
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Analysis of Timing Report
#### Path 1 ############################################
Start rp.PC.outreg_reg[0]/Q
End rp.PC.outreg_reg[15]/D
Reference rp.PC.outreg_reg[15]/CK
Path slack 1p
Reference arrival time 704
+ Cycle adjust (clock:R#1 vs. clock:R#2) 13000
 Margin 100
 Setup time 646
 
Endofpath required time (ps) 12957
Starting arrival time 0
+ Clock path delay 704
+ Data path delay 12252
 
Endofpath arrival time (ps) 12956
Starting and ending points
Slack
time = 0
starting and
reference edge
arrival time
data
slack = required time  arrival time
clock period
data arrival
time
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
A Timing Example:
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Example 1
D Q
Q
CK
Q
T
W
≥ max t
PFF
+ t
su
For the 7474, max t
PLH
= 25ns, max t
PHL
= 40ns, t
su
= 20ns
T
W
≥ max (max t
PLH
+ t
su,
max t
PHL
+ t
su)
T
W
≥ max (25+20, 40+20) = 60
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
D Q
CK
Q
T
W
≥ max t
PFF
+ max t
PINV
+ t
su
Example 2
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
D Q
Q
D Q
Q
MUX
0
1
Q0 Q1
CK
T
W
≥ max t
PFF
+ max t
PMUX
+ t
su
Example 3
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Paths from Q1 to Q1:
Paths from Q1 to Q2:
Paths from Q2 to Q1:
Paths from Q2 to Q2:
None
T
W
≥ max t
PDFF
+t
JKsu
= 20 +10 = 30 ns
T
W
≥ max t
PDFF
+ max t
AND
+ t
JKsu
= 20 + 12 + 10 = 42 ns
T
W
≥ max t
PJKFF
+ t
OR
+ T
Dsu
= 25 + 10 + 5 = 40 ns
T
W
≥ max t
PJKFF
+ max t
AND
+ t
JKsu
= 25 + 12 + 10 = 47
TW ≥ 47 ns
Example 4
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Example 5 : Effect of clock skew on clock rate
Q1
Q2
D Q
Q
D Q
Q
CK
C1
C2
D2
T
W
≥ max T
PFF
+ max t
OR
+ t
su
(if clock not skewed, i.e., t
INV
= 0)
T
W
≥ max T
PFF
+ max t
OR
+ t
su
 min t
INV
(if clock skewed, i.e., t
INV
> 0)
•Clock C2 skewed after C1
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Example 6: Maximum Allowable Clock Skew
How much skew between C1 and C2 can be tolerated in the
following circuit?
Case 1: C2 delayed after C1
D Q
Q
D Q
Q
C2
Q1
D2
C1
t
PFF
> t
h
+ t
SK
t
SK
< min t
PFF
 t
h
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Case 2: C1 delayed from C2
D Q
Q
D Q
Q
C2
Q1
D2
C1
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
How does additional delay between the flipflops affect the
skew calculations?
t
SK
≤ min t
PFF
 t
h
t
sk
≤ min t
PFF
+ min t
MUX
 t
h
Example 7
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Understanding
And
Describing Clocks
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Defining Clocks
• A clock is defined by its period, waveform and slew time.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Specifying Clocks
• Standard clock
• Inverted clock
• Virtual clock
• Derived clock
• Gated clock
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
• Blast Fusion(MAGMA) clock command:
force timing clock node period –slew time
waveform {rise R –fall F …} –virtual –name name
• Equivalent SDC command:
create_clock –period –waveform –name name
• Example syntax:
force timing clock $m/clk 10n
Q. Why aren`t we using –waveform option?
A. The default waveform start at 0 with a 50% duty cycle.
Standard Clock Specification
0 5 10
clk
D Q
QB
D Q
QB
clk
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
•create_clock period 20 waveform {0 8}
•create_clock period 20 waveform {10 18}
Standard Clock Specification
SDC commands
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Inverted Clock
• Blast Fusion clock command
force timing clock $m/clkbar 5n
Q. What is an inverted clock with a 10/50 duty cycle shifted by 2ns ?
waveform {fall 2n –rise 3n}
D Q
QB
D Q
QB
clkbar
0 1 2 3 4 5 6
clk
clkbar
0 1 2 3 4 5 6
clkbar
0 1 2 3 4 5 6
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Virtual Clock
• A virtual clock has no sources. It exists in memory but is not part of
a design. A virtual clock lets you associate arrival and required
times with clocks external to the chip or block.
• The name of virtual clock must be a unique name that is not
associated with any port or instance in the synthesized design.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Generated Clock
clk
D Q
QB
D Q
QB
D Q
QB
force timing clock $m/clk 5n
force timing clock $m/f0/Q –generated –source $m/clk –divider 2
f0
D Q
QB
• A design might include clock dividers or other
structures that produce a new clock from a
master source clock.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Gated Clock
CLOCK
CLKEN
GCLK
CLOCK
CLKEN
CGLK
•Clock gating reduces power consumption by switching off
the clock to flipflops when the value of those flipflops does
not change.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Gated Clock: Setup and Hold Margins for
AND & NAND gates
•The setup margin is measured relative to the falling transition of
the gating cell clock input.
•The hold margin is measured relative to the rising transition of
the clock input.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Gated Clock: Setup and Hold Margins for OR &
NOR gates
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Describing Clock Variations
• Clock latency (delay)
• Clock skew
• Jitter
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Source, Network and IO
Latency
Chip
D Q
D Q D Q
D Q
network latency
(onchip)
source latency
(offchip)
Clock
IO
latency
IO
latency
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Source, Network and IO
Latency
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Clock Generation
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Summary: Clocks
• A clock is defined by its period, waveform and
slew time
• Clock variations that can be described for timing
calculation include latency, skew and jitter.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
False Paths
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
What are False paths?
• Paths that physically exist in a design but are not
logic/functional paths
• These paths never get sensitized under any input
conditions
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Logically Impossible Example
Mux 1
C C1 C2 A
B
Mux 2
S
B1 B2
OUT
•A path may exist in the circuit but no combination of
input vectors may ever exercise it
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Logic Removal Example
•A block may be reused and certain signal functions are
no longer required
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Most STA`s can`t leave combinational loops in the
design, because a race condition will occur
"I want to break the
combinational loop at
U1/B"
force timing break from $m/U1/B to $m/U1/Z
D Q
QB
D Q
QB
A
B
Z
U0
A
B
Z
U1
broken arc
Combinational Loop Example
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Multicycle Path
A start point, end point and/or "through" point is
specified, along with the number of allowed clock
cycles.
•Multicycle paths are paths which intentionally
require more than one clock cycle to propagate.
•This information cannot possibly be inferred by the
timing analyzer, so it must be specified by the
designer so the analyzer can mark the path and
correctly compute the timing.
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
D Q
QB
D Q
QB
CK
U1 U2
force timing multicycle from $m/U1/Q to $m/U2/D cycle 2
Multicycle Path: Example
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Handling Multiple Clocks
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Multiple Clocks
Step1: Determine the Least Common Multiple (LCM)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A
(6 ns)
B
(8 ns)
• What is the LCM between these two clocks?
The timer needs to calculate the delays of the
circuit to the LCM to find all path relationships
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Setup Relationship: A Rising, B Rising
Find the Setup Relationship between A rising and B rising
• The setup relationship is the closest distance between the launching
clock edge (A) and the receiving clock edge (B)
D Q
QB
D Q
QB
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Setup Relationship: A Rising, B Falling
Find the Setup Relationship between A rising and B falling
D Q
QB
D Q
QB
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Setup Relationship: A Falling, B Rising
Find the Setup Relationship between A falling and B rising
D Q
QB
D Q
QB
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Setup Relationship: A Falling, B Falling
Find the Setup Relationship between A falling and B falling
D Q
QB
D Q
QB
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Hold Relationship: A Rising, B Rising
Find the Hold Relationship between A rising and B rising
• The hold relationship is the closest distance between the
launching clock edge (A) and the previous receiving clock
edge (B)
D Q
QB
D Q
QB
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Hold Relationship: A Rising, B Falling
Find the Hold Relationship between A rising and B falling
D Q
QB
D Q
QB
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Hold Relationship: A Falling, B Rising
Find the hold Relationship between A falling and B rising
D Q
QB
D Q
QB
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Hold Relationship: A Falling, B Falling
Find the hold Relationship between A falling and B falling
D Q
QB
D Q
QB
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Pipelining Concept
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Pipelining
Concept
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Anatomy of a Pipeline Stage
Combinational
Logic
T
clocktoQ
T
logic
T
setup
Flip
Flop

Flip
Flop

One clock cycle
setup logic Q to clock cycle
T T T T + + =
÷ ÷
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Anatomy of a Synchronous System
Comb
Logic
Flip
Flop

Flip
Flop

Comb
Logic
Flip
Flop

Comb
Logic
input input input
• Overall system cycle time
• determined by longest pipeline stage (taking
input arrival times into account)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Latency in Pipelines
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Pipelining Example
Original circuit
– Two logic levels between SOURCE_FFS and
DEST_FF
– f
MAX
= ~207 MHz
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Pipelined circuit
– One logic level between each set of flipflops
– f
MAX
= ~347 MHz
Pipelining Example…contd
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Review Question
Given the original circuit, what is wrong with
the pipelined circuit?
How can the problem be corrected?
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Retiming Concept
Register balancing in order to balance the timing
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Time Borrowing
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
TIME BORROWING
* Time borrowing occurs in latchbased designs
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
TIME BORROWING…contd
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
There is a short delay on the first timing path and a
long delay on the second timing path.
The question is whether time borrowing can
eliminate negative slack
TIME BORROWING…contd
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
GLUE LOGIC
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
AVOID GLUE LOGIC
THE NAND GATE AT THE TOP LEVEL SERVERS ONLY
TO GLUE THE INSTATIATED CELLS
OPTIMIZATION IS LIMITED BECAUSE THE GLUE
LOGIC CANNOT BE ABSORBED
X
clock
RegA
X
clock
RegB
X
clock
RegA
GLUE
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
REMOVE GLUE LOGIC BETWEEN BLOCKS
THE GLUE LOGIC CAN NOW BE OPTIMIZED WITH
OTHER LOGIC
TOP LEVEL DESIGN IS ONLY A STRUCTURAL
NETLIST, DOESN‟T NEED TO BE COMPILED
X
clock
RegA
X
clock
RegB
X+GLUE
clock
RegA
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Signal Interface
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Signal Interface: Model
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Interface Taxonomy (Parallelism)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Interface Taxonomy (Topology)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Interface Taxonomy (Timing)
CGCoreEl
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Interface Taxonomy (Signaling)
CGCoreEl
Sandeepani School of VLSI Design
System:
CGCoreEl
Sandeepani School of VLSI Design
Digital System!
CGCoreEl
Sandeepani School of VLSI Design
Combinational vs. Sequential
CGCoreEl
Sandeepani School of VLSI Design
Levels of integrated circuits
CGCoreEl
Binary Valued Signals
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Binary Valued Signals … contd
CGCoreEl Binary Valued Signals … contd Sandeepani School of VLSI Design .
CGCoreEl Two logic levels but very powerful applications……… possible! Sandeepani School of VLSI Design .
lower power.CGCoreEl Sandeepani School of VLSI Design VLSI: but why? Integration improves the design: lower parasitics = higher speed. Integration reduces manufacturing cost(almost) no manual assembly. . physically smaller.
CGCoreEl Sandeepani School of VLSI Design .
DSP applications) Optical Switches Has made highly sophisticated control systems massproducible and therefore cheap VLSI Applications Sandeepani School of VLSI Design .DRAM / SRAM Special Purpose Processors .analogue or digital It is concerned with forming a pattern of interconnected switches and gates on the surface of a crystal of semiconductor Microprocessors personal computers microcontrollers Memory .CGCoreEl VLSI is an implementation technology for electronic circuitry .ASICS (CD players.
polysilicon. Molybdenum. Copper.CGCoreEl What is a Silicon Chip? Sandeepani School of VLSI Design A pattern of interconnected switches and gates on the surface of a crystal of semiconductor (typically Si) These switches and gates are made of areas of ntype silicon areas of ptype silicon areas of insulator lines of conductor (interconnects) joining areas together Aluminium. tungsten The geometry of these areas is known as the layout of the chip Connections from the chip to the outside world are made around the edge of the chip to facilitate connections to other devices . Titanium.
CGCoreEl Sandeepani School of VLSI Design Logic families Commonly used are 3 TransistorTransistor logic (TTL) Complementary metal oxide semiconductor (CMOS) Emitter Coupled Logic (ECL) Most important characteristics of TTL & CMOS are that TTL gates switch very fast CMOS has very low power dissipation .
CGCoreEl Sandeepani School of VLSI Design CMOS Technology: Modern Logic Design First proposed in the 1960s. Since the transistors are in series.hence power is conserved. In the case of an inverter. Was not seriously considered until the severe limitations in power density and dissipation occurred in NMOS circuits Now the dominant technology in IC manufacturing Employs both pMOS and nMOS transistors to form logic elements The advantage of CMOS is that its logic elements draw significant current only during the transition from one state to another and very little current between transitions . See twinwell cross sections . in either logic state one of the transistors is off. (~ no) current flows.
CGCoreEl A known deficiency of MOS technology is its limited load driving capabilities (due to limited current sourcing and sinking abilities of pMOS and nMOS transistors. Bipolar transistors have higher gain better noise characteristics better high frequency characteristics BiCMOS gates can be an efficient way of speeding up VLSI circuits See table for comparison between CMOS and BiCMOS CMOS fabrication process can be extended for BiCMOS Example Applications CMOS .critical high speed parts of the system BiCMOS Sandeepani School of VLSI Design .I/O and driver circuits ECL .Logic BiCMOS .
CGCoreEl Sandeepani School of VLSI Design CMOS Inverter VDD A Y GND .
CGCoreEl Sandeepani School of VLSI Design CMOS NAND gates Vdd Y A B .
CGCoreEl Sandeepani School of VLSI Design CMOS NOR gates VDD A B Y .
CGCoreEl Sandeepani School of VLSI Design NMOS gates Inverter Nand Nor Nand/Nor preference .
CGCoreEl Sandeepani School of VLSI Design Exercise Implement AND.OR gates using CMOS logic .
CGCoreEl Sandeepani School of VLSI Design CMOS Vs Bipolar Technology CMOS Technology Bipolar Technology Low static power dissipation High i/p impedance (low drive current) Medium speed High packing density Low o/p drive current Bidirectional capability A near ideal switching High power dissipation Low i/p impedance (high drive current) High speed Low packing density High o/p drive current Essentially unidirectional .
Predicted that number of transistors per chip would grow exponentially (double every 18 months).CGCoreEl Sandeepani School of VLSI Design Moore’s Law Gordon Moore: cofounder of Intel. dynamos. automobiles. Exponential improvement in technology is a natural trend: steam engines. Moore’s Law .
CGCoreEl Moore’s Law plot Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
A hybrid of PLD blocks and interconnect for midsize logic designs .CGCoreEl Sandeepani School of VLSI Design CPLD Basics Review: What is a CPLD? IO/Registers/Logic Interconnect IO/Registers/Logic Definition: Complex Programmable Logic Device .
The Part of the CPLD architecture containing the register Logic Block . and logic blocks Function Block . MC.Connection between the I/O.Macrocell.Where product terms are built Product Term . The gateway between the CPLD fabric and the outside world MC .Input Output block.Single logical function made out of AND and OR terms Interconnect Array .The name for a logic block and its associated macrocells .CGCoreEl Sandeepani School of VLSI Design CPLD Architecture Function Block MC0 I/O MCn Logic Block Logic Block MCn Interconnect Array MC0 I/O MC0 I/O MCn Logic Block MC0 Logic Block MCn I/O • • • • • • I/O .
CGCoreEl High Performance Pintopin combinatorial delay CPLD Definitions: Sandeepani School of VLSI Design Maximum registered frequency Time from input through interconnect to output (ns) Fastest operation of flipflops (MHz) Tpd (ns) Fmax (MHz) .
CGCoreEl Sandeepani School of VLSI Design CPLDs versus FPGAs • CPLD architecture – – – – – Product term array Interconnect array Wide fanin Deterministic timing Pin locking I/O MCn MC0 Logic Block Logic Block Interconnect Array MC0 I/O MCn MC0 I/O MCn Logic Block MC0 Logic Block I/O MCn • FPGA architecture – – – – Lookup table based X/Y routing matrix Higher density Additional features • • Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell Logic Cell DLL Multipliers .
PCI. embedded processors .Logic decode/ integration.CGCoreEl Sandeepani School of VLSI Design CPLD or FPGA? CPLD Nonvolatile Consistent pintopin timing Simple timing model Very low power consumption Lowest cost point Fast internal performance Small packages (CP56. state machines • FPGA – Volatile – Requires memory device to load design at power up – Complex timing model – Large complex designs – Memory resources – Applications . 132) Applications . highspeed serial communication.
CGCoreEl Fieldprogrammable gate arrays Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
more powerhungry. but FPGAs are slower.CGCoreEl Sandeepani School of VLSI Design FPGAs and VLSI FPGAs are standard parts: Premanufactured. Don‟t worry (much) about physical design. shorter design cycle. Tailored to your application. Time to market is less. Generally lower power consumption. larger. Time to market is more Custom silicon: .
CGCoreEl Sandeepani School of VLSI Design Embedded Digital System: picture The big .
CGCoreEl A Historical Perspective: the PLA Product terms x0 x1 AND plane x2 OR plane Sandeepani School of VLSI Design f0 x0 x1 x2 f1 .
CGCoreEl Sandeepani School of VLSI Design TwoLevel Logic logic function can be Every expressed in sumofproducts format (ANDOR) minterm Inverting format (NORNOR) more effective .
CGCoreEl Sandeepani School of VLSI Design ArrayBased Programmable Logic I3 I2 I1 I0 Programmable OR array I3 I2 I1 I0 Programmable OR array I5 I4 I3 I2 I1 I0 Fixed OR array I5 I4 Programmable AND array O 3O 2O 1O 0 Fixed AND array O3O2O1O0 Programmable AND array O 3O 2O 1O 0 PLA PROM Indicates programmable connection Indicates fixed connection PAL .
CGCoreEl Sandeepani School of VLSI Design Programming a PROM 1 X2 X1 X0 : programmed node NA NA f 1 f 0 .
k macrocells From Smith97 . j minterms/macrocell.CGCoreEl Sandeepani School of VLSI Design More Complex PAL i inputs.
CGCoreEl Sandeepani School of VLSI Design Number System & Conversions .
CGCoreEl Sandeepani School of VLSI Design Recap • • • • • • • Code conversions Selfcomplementary code Weighed & Non Weighed codes Binary Addition Binary Subtraction Binary multiplication Binary Division .
101 (2) = 54.101100. Convert F4A into binary Answers : .101 (2) = 2C.A (16) = 44.101 into hexadecimal.101100.CGCoreEl Sandeepani School of VLSI Design Exercise Convert 101100.625 (10) . octal and decimal.F4A (16 )=111101001010 (2) .5 (8) .
The remainder of the long division will give the digits starting from the least significant digit .CGCoreEl Sandeepani School of VLSI Design radixr to decimal : General Positional Number Conversion D in d p 1 i r i decimal to radixr : .Successive division of D by r .
Decimal to Binary : 179 (10) 179/2 = 89 ( 1 ) LSB 89/2 = 44 ( 1 ) 44/2=22 ( 0 ) 22/2=11 ( 0 ) 11/2=5 ( 1 ) 5/2=2 ( 1 ) 2/2=1 ( 0 ) 1/2=0 (1)MSB Result : 10110011 (2) .CGCoreEl Sandeepani School of VLSI Design Example .
CGCoreEl Sandeepani School of VLSI Design Hexadecimal Addition Add digits in Convert each digit into decimal decimal Convert the result into Hexadecimal Produce carry when digits sum is > = the radix (16 ) Example 10 1 0 1 0 1 0 2FA5 2 15 10 5 +A9 3C 10 9 3 12 _________ _______________ D8 E 1 (13) (16+8) (14) (16+1) D 8 E 1 .
CGCoreEl Sandeepani School of VLSI Design Switching Algebra Definition Shannon’s expansion theorem Principle of duality Complementation rules SOP and POS .
2. Replacing Replacing Replacing Replacing AND with OR OR with AND 1 with 0 0 with 1 If E is a valid Boolean expression. then Ed (its dual) is also valid .CGCoreEl Sandeepani School of VLSI Design Duality Axioms and Theorems – come in pairs Get one of the pair from the other by: 1. 4. 3.
. x or y) Product Term or Implicant – series of literals related by AND operator Sum Term – Series of literals related by OR operator .g.CGCoreEl Sandeepani School of VLSI Design Canonical Forms Literal – switching variable or its complement (e.
CGCoreEl AXIOMS : Boolean Algebra Sandeepani School of VLSI Design THEOREMS: DEFINITIONS: .
3. Product of sums of three variables is equal to 0. A’B’C’+A’B’C+A’BC’+AB’C’+ABC’ = A’B’+C’ .CGCoreEl Problems Sandeepani School of VLSI Design Prove the following: (Do not use Kmaps) 1. 4. 2. A + A’B = A+B Sum of products of three variables is equal to 1.
CGCoreEl Sandeepani School of VLSI Design Representation Of Numbers: • • • Signed magnitude 1’s Complement 2’s Complement a revision .
A 1 sign bit represents a negative number. Examples: 11012 = 1310 (a 4bit unsigned number) 0 1101 = +1310 (a positive number in 5bit signed magnitude) 1 1101 = 1310 (a negative number in 5bit signed magnitude) 01002 = 410 0 0100 = +410 1 0100 = 410 (a 4bit unsigned number) (a positive number in 5bit signed magnitude) (a negative number in 5bit signed magnitude) • Range? • Limitation? .in front of a magnitude to indicate the sign. By convention: A 0 sign bit represents a positive number.CGCoreEl Sandeepani School of VLSI Design Signed magnitude representation Humans use a signedmagnitude system: we add + or . by adding an extra sign bit to the front of our numbers. We could do this in binary as well.
Complicated digital adders .Two possible representations of zero 2.0 Disadvantages : 1. 01100 = +12 * 00000= 0 . 10000 = .CGCoreEl Sandeepani School of VLSI Design Signed Magnitude Representation The MSB represents the sign bit ( 0 = +ve . 1 = ve ) The range for nbit is : from (2n 1 1)to (2n1 1) Example: n=5 * Range : from 15 to 15 * 10011= 3 .
one’s complement. negates numbers by complementing each bit of the number.CGCoreEl Sandeepani School of VLSI Design One’s complement Representation A different approach. and 1 for negative. We keep the sign bits: 0 for positive numbers. The sign bit is complemented along with the rest of the bits. Examples: 11012 = 1310 (a 4bit unsigned number) 0 1101 = +1310 (a positive number in 5bit one’s complement) 1 0010 = 1310 (a negative number in 5bit one’s complement) 01002 = 410 0 0100 = +410 1 1011 = 410 complement) (a 4bit unsigned number) (a positive number in 5bit one’s complement) (a negative number in 5bit one’s .
CGCoreEl Sandeepani School of VLSI Design Why is it called “1’s complement?” Complementing a single bit is equivalent to subtracting it from 1. n Here n=5.01 1 01 1 00 1 0 . Subtracting 01101 from 11111 yields 10010: 1 1 1 1 1 . and 1 . and 2 1 = 3110 = 111112.1 = 0 Similarly.0 = 1 1’ = 0. complementing each bit of an nbit number is equivalent to subtracting that number from 2n1. For example. 0’ = 1. we can negate the 5bit number 01101. and 1 .
including the sign bits.CGCoreEl 1’s complement addition Sandeepani School of VLSI Design To add one’s complement numbers: First do unsigned addition on the numbers. Two examples: 0111 (+7) + 1011 + (4) 1 0010 0011 (+3) + 0010 + (+2) 0 0101 0010 0101 + 1 + 0 0011 (+3) 0101 (+5) This is simpler and more uniform than signed magnitude addition. . Then take the carry out and add it to the sum.
complement each bit (just as for ones‟ complement) and then add 1. Examples: 11012 0 1101 1 0010 1 0011 = 1310 = +1310 = 1310 = 1310 (a 4bit unsigned number) (a positive number in 5bit two’s complement) (a negative number in 5bit ones’ complement) (a negative number in 5bit two’s complement) 01002 0 0100 1 1011 1 1100 = 410 = +410 = 410 = 410 (a 4bit unsigned number) (a positive number in 5bit two’s complement) (a negative number in 5bit ones’ complement) (a negative number in 5bit two’s complement) • Range? • Limitation? .CGCoreEl Two’s complement Sandeepani School of VLSI Design Our final idea is two‟s complement. To negate a number.
M * 2E‟ . Example: N = ± M * BE for 8bit E range from –128 to +127 IEEE format N= ± 1. M * 2E‟ .1023 (single precision – 64 bit) E = E‟ –1023 • • .127 (single precision – 32 bit) E = E‟ 127 ± 1.CGCoreEl Floating – point numbers Sandeepani School of VLSI Design • Fixed point number can not represent very large and very small numbers.
Represent the following in single precision format (i ) 0.CGCoreEl Sandeepani School of VLSI Design Problems Q.0110 * 26 (ii) –1 (iii)(10)10 .
Perform direct subtraction: (9)10 – (10)10 ? 12. (436.CGCoreEl 1.21)10 = ( ? )2 2. What is Hamming code? Examples Sandeepani School of VLSI Design .8 in XS3? 9.11102 = ? Using 1’s complement form 7. 0011. Divide (10)10 by (4)10 in binary representation. 11.71)8 = ( ? )16 3. (500. 5 .10012 – 0001.515) Base 7 4. CB2H – 972H = ? (Hint: Use 16’s Complement) 6.26 in BCD representation? (Hint: Use 9’s Complement) 8. Convert (847)10 to gray code representation. Convert (231. 79 . 3168 – 4518 = ? (Hint: Use 8’s Complement) 5. 10.3)Base 4 to Base 7 Convert Base 4 to Base 10 Convert Base 10 to Base 7 Ans : (63.
CGCoreEl Gates: Sandeepani School of VLSI Design electronic circuit that realizes a logical expression .
CGCoreEl Logical Expressions Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design NAND/NOR Networks Convert AND/OR Network into NAND/NOR Network Tips and Tricks Think of bubbles on gates as inverters Think of EXOR & EXNOR as parity ckts that produce a 1 out if the number of 1’s in is odd or even respectively Use alternative NAND/NOR symbols A 2 level NANDNAND /NORNOR ckt is equivalent to a 2 level ANDOR / ORAND ckt respectively and realize SOP / POS logical expressions .
CGCoreEl Structural Model of gates Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design Ideal and real gates are different .
CGCoreEl Sandeepani School of VLSI Design Discussion… .
CGCoreEl KMaps Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design SOP and POS Implementation .
CGCoreEl Sandeepani School of VLSI Design Adders: Half adder Full adder Serial adder Ripple carry adder Carry Bypass adder Carry look ahead adder Carry select adder Multipliers: 2bit by 2bit Multiplier 4bit by 3bit Multiplier Magnitude Comparator 2bit Comparator 4bit Comparator Some Arithmetic Circuits .
. Modern VLSI favors adder designs which have compact carry chains. Carry chain analysis must consider transistor. wiring delay.CGCoreEl Sandeepani School of VLSI Design Adders Adder delay is dominated by carry chain.
CGCoreEl Implementation of Half Adder Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design Implementation of Full Adder .
CGCoreEl Sandeepani School of VLSI Design 4Bit Ripple carry adder .
Total delay = 64 X 20 = 1280 nsec .CGCoreEl Sandeepani School of VLSI Design Ripple Carries Cascade 64 full adders to get a 64bit ripple carry adder Problem: Slow – carries ripple If stage delay = 20 nsec.
Delay of ripplecarry adder goes through all carry bits. si = ai XOR bi XOR ci ci+1 = aibi + aici + bici .CGCoreEl Sandeepani School of VLSI Design Full adder Computes onebit sum. carry: Half adder computes twobit sum. Ripplecarry adder: nbit adder built from full adders.
CGCoreEl Sandeepani School of VLSI Design 4Bit Carry AdderSubtractor .
CGCoreEl Sandeepani School of VLSI Design Serial Adder Xi Yi Full Adder Si Ci + 1 Ci Delay Q. Design a 4bit serial adder with the help of two shift register? .
CGCoreEl Carry Lookahead Adder Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design Carrylook ahead adder First compute carry propagate. generate: Pi = ai + bi Gi = ai bi Compute sum and carry from P and G: si = ci XOR Pi XOR Gi ci+1 = Gi + Pici .
B14 are addends.CGCoreEl Sandeepani School of VLSI Design Carry Equations 4 stage binary carry lookahead adder A14. C0 is input carry Outputs are Sum S14 and Carries C14 Multiply out equations: C1 = G1 + P1 C0 C2 = G2 + P2 C1 = G2 + P2 G1 + P2 P1 C0 C3 = G3 + P3 C2 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 C0 C4 = G4 + P4 C3 = G4 + P4 G3 + P4 P3 G2 + P4 P3 P2 G1 + P4 P3 P2 P1 C0 .
CGCoreEl Sandeepani School of VLSI Design Carry LookAhead Adder Big speedup – At most 4 logic delays to get all carries n = # full adder chips ttotal = tXOR + log4 n X tLACG + tFA ttotal = 10 nsec + 1 X 21 nsec + 15 nsec = 46 nsec tXOR = 10 nsec tLACG = carry lookahead stage delay = 21 nsec tFA = full adder delay = 15 nsec .
CGCoreEl Sandeepani School of VLSI Design Depth4 carrylook ahead .
CGCoreEl Sandeepani School of VLSI Design Analysis Deepest carry expansion requires gates with large fan in: large. slow. Layout is even more complex with multiple levels of look ahead. Carrylook ahead unit requires complex wiring between adders and look ahead unit—values must be routed back from look ahead unit to adder. .
CGCoreEl 4 bit Carry Lookahead Adder Sandeepani School of VLSI Design .
. Carry out of group when carry out of last bit in group or carry is bypassed.CGCoreEl Sandeepani School of VLSI Design Carryskip adder Looks for cases in which carry out of a set of bits is identical to carry in. Typically organized into bbit stages. Can bypass carry through all stages in a group when all propagates are true: Pi Pi+1 … Pi+b1.
CGCoreEl Sandeepani School of VLSI Design Twobit carryskip structure ci Pi Pi+1 Pi+b1 … AND OR Ci+b1 .
2b1] .3b1] Carry out skip skip Carry out P[b.b1] skip P[2b.CGCoreEl Sandeepani School of VLSI Design Carryskip structure b adder stages Carry out b adder stages b adder stages P[0.
CGCoreEl Sandeepani School of VLSI Design Worstcase carryskip Worstcase carrypropagation path goes through first. last stages: .
CGCoreEl Sandeepani School of VLSI Design Delay analysis Assume that skip delay = 1 bit carry delay.5 + (k/b –2) + (b1) block 0 OR gate skips last block For equal sized blocks. . optimal block size is sqrt(k/2). Delay of kbit adder with block size b: T = (b1) + 0.
Reduces delay to multiplexer. . Uses actual carry in to select correct result.CGCoreEl Sandeepani School of VLSI Design Carryselect adder Computes two results in parallel. each for different carry input assumptions.
CGCoreEl Carry select adder Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design Carryselect structure .
Input: 3 nbit operands. nbit carry.CGCoreEl Sandeepani School of VLSI Design Carrysave adder Useful in multiplication. c = [(x + y + z) –2] / 2. Operations: . Output: nbit partial sum. Use carry propagate adder for final sum. s = (x + y + z) mod 2.
CGCoreEl Sandeepani School of VLSI Design Pseudo or Carry Save Adder Advantage – only final stage of partialproduct addition needs to propagate carries A 16 16 B CIN 16 16 Carries 16 Sum .
.1 SN...1 ZN.....CGCoreEl Sandeepani School of VLSI Design Carry Save Addition (CSA) A full adder sums 3 inputs and produces 2 outputs Carry output has twice weight of sum output N full adders in parallel are called carry save adder Produce N sums and N carry outs X4 Y4 Z4 X3 Y3 Z3 X2 Y2 Z2 X1 Y 1 Z1 C4 S4 C3 S3 C2 S2 C1 S1 XN.1 YN..1 nbit CSA CN.1 ...
CGCoreEl Sandeepani School of VLSI Design CSA Application Use k2 stages of CSAs Keep result in carrysave redundant form Final CPA computes actual result 0001 0001 0111 1101 0010 0111 +1101 1011 4bit CSA 0101_ 0101_ 1011 0101_ 1011 5bit CSA +0010 + X Y Z S C X Y Z S C A B S .
CGCoreEl Sandeepani School of VLSI Design CSA Application Use k2 stages of CSAs Keep result in carrysave redundant form Final CPA computes actual result 0001 0001 0111 1101 0010 0111 +1101 1011 4bit CSA 0101_ 0101_ 1011 0101_ 1011 5bit CSA +0010 01010_ 00011 00011 01010_ + 01010_ + 00011 X Y Z S C X Y Z S C A B S .
CGCoreEl Sandeepani School of VLSI Design CSA Application Use k2 stages of CSAs Keep result in carrysave redundant form Final CPA computes actual result 0001 0001 0111 1101 0010 0111 +1101 1011 4bit CSA 0101_ 0101_ 1011 0101_ 1011 5bit CSA +0010 01010_ 00011 00011 01010_ + 01010_ 10111 + 00011 10111 X Y Z S C X Y Z S C A B S .
Optimized adders are most effective in very long bit widths (> 48 bits). .CGCoreEl Sandeepani School of VLSI Design Adder comparison Ripplecarry adder has highest performance/cost.
CGCoreEl 350 Sandeepani School of VLSI Design 120 400 300 350 100 300 Operational Time (ns) 80 PerformanceCost Ratio 250 250 Cost (CLBs) Ripple Complete CLA Skip RCselect 200 60 200 150 150 40 100 20 100 50 50 0 40 72 8 0 32 56 80 8 0 32 56 80 8 Bits Bits Bits © 1998 IEEE .
CGCoreEl Sandeepani School of VLSI Design Serial adder May be used in signalprocessing arithmetic where fast computation is important but latency is unimportant. Data format (LSB first): 0 1 1 0 LSB .
CGCoreEl Serial adder structure Sandeepani School of VLSI Design LSB control signal clears the carry shift register: .
CGCoreEl BCD Adder Sandeepani School of VLSI Design .
CGCoreEl 2bit X 2bit Multiplier Sandeepani School of VLSI Design .
CGCoreEl 4bit X 3bit Multiplier Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design Magnitude Comparator Q. E(=) and L(<). . Design a 2bit digital comparator that accepts two words A and B and gives three outputs : G(>).
Design a 4bit digital comparator that accepts two words A and B and gives three outputs : G(>). E(=) and L(<).CGCoreEl Sandeepani School of VLSI Design Magnitude Comparator Q. .
CGCoreEl Sandeepani School of VLSI Design 2bit Magnitude Comparator Answer: let x1 = (A1 exnor B1) x0 = (A0 exnor B0) Z A=B = x1. A‟0 B0 . x0 Z A>B = A1B‟1 + x1. A0 B‟0 Z A<B = A‟1B1 + x1.
x1. x1. x2. x1. A0 B‟0 Z A<B = A‟3B3 + x3. A1B‟1 + x3. A2 B‟2 + x3. x2. x2. x0 Z A>B = A3B‟3 + x3. A‟0 B0 . x2 . A‟2 B2 + x3. A‟1B1 + x3.CGCoreEl Sandeepani School of VLSI Design 4bit Magnitude Comparator Answer: Z A=B = x3. x2.
CGCoreEl Sandeepani School of VLSI Design A2 B2 A1 B1 A>B output A0 B0 A>B A<B A=B A<B output A=B output .
Extremely complex even for small word length Very hard to test Truth table expansion varies with word length Must use at least one carry propagating full adder to sum up partial products . 2. 3.CGCoreEl Sandeepani School of VLSI Design Binary Multipliers 1. 4.
CGCoreEl Sandeepani School of VLSI Design Multiplication Equations Multiplicand A = Ah X 24 + Al Multiplier B = Bh X 24 + Bl Product P = A X B = Ah X Bh X 28 + (Ah X Bl + Al X Bh) X 24 + (Al X Bl) Must sum the 4 partial products Since A & B are 8 bits. product is 16 bits Need 5 full adders to do this .
CGCoreEl Sandeepani School of VLSI Design 4X4 bit Binary Multiplier 74LS274 – Produces 8bit product .
CGCoreEl Sandeepani School of VLSI Design Example X11 X12 X1l X21 X22 X2l Y21 Yi1 Xi1 Xi2 Xil … Cell 1 … Cell 2 Y22 Yi2 … Yi1 … Cell i Yi2 … … … … … Z1m … Z11 Z12 … Z21 Z22 Z2m Y2k Yik … Zi1 Zi2 Zim Yik .
CGCoreEl Sandeepani School of VLSI Design Multiplication Example: 1100 : 1210 0101 : 510 1100 0000 1100 0000 00111100 : 6010 .
CGCoreEl Sandeepani School of VLSI Design Multiplication 1100 : 1210 0101 : 510 Example: 1100 0000 1100 0000 00111100 : 6010 multiplicand multiplier partial products product M x Nbit multiplication Produce N Mbit partial products Sum these to produce M+Nbit product .
yM2. xN2.CGCoreEl Sandeepani School of VLSI Design General Form Multiplicand: Y = (yM1. …. y0) Multiplier: X = (xN1. …. x0) M 1 N 1 i N 1 M 1 P y j 2 j xi 2 xi y j 2i j Product: i 0 j 0 j 0 i 0 y5 x5 x0y5 x1y5 x2y5 x3y5 x4y5 x5y5 x5y4 p9 x4y4 x5y3 p8 x3y4 x4y3 x5y2 p7 x2y4 x3y3 x4y2 x5y1 p6 x1y4 x2y3 x3y2 x4y1 x5y0 p5 p4 p3 p2 p1 p0 y4 x4 x0y4 x1y3 x2y2 x3y1 x4y0 y3 x3 x0y3 x1y2 x2y1 x3y0 y2 x2 x0y2 x1y1 x2y0 y1 x1 x0y1 x1y0 y0 x0 x0y0 multiplicand multiplier partial products p11 p10 product . y1. x1.
Dot Diagram Each dot represents a bit x0 partial products x15 multiplier x .CGCoreEl Sandeepani School of VLSI Design 16X16 Mult.
CGCoreEl Sandeepani School of VLSI Design Parallel Binary Multiplier P Y C Y X + CO X PO .
CGCoreEl Sandeepani School of VLSI Design OneBit Multiplier Cell P Y C Y X + CO PO X .
for m comparators X 27 = 162 nsec (4bit slices) =4 Cascaded connection ttotal = (log4 m + 1) X tc = 2 X 27 nsec = 54 .CGCoreEl Sandeepani School of VLSI Design Comparator Time Delays Linear connection tc = individual comparator delay ttotal = m tc.
A circuit accepts a 4bit I/p data & generates an o/p Z=1whenever I/p is a prime number.3. Design a circuit which will accept 4bit binary and will provide 5bit BCD code? Q.2.CGCoreEl Sandeepani School of VLSI Design Problems Q. Design a 3bit squarer? Q.1. Design the circuit? .
CGCoreEl Sandeepani School of VLSI Design Problems Q.4. The conditions under which an insurance company will issue a policy are : A married female 25 years old or older. or A female under 25 years or A married male under 25 years with no accident record. . or A married male under 25 years or older with no accident record. or A married male with accident record. Obtain a simplified logic expression starting to whom a policy can be issued.
CGCoreEl Sandeepani School of VLSI Design Universal Logic Element .
CGCoreEl
Universal Logic Element
Sandeepani School of VLSI Design
Which of these are Universal logic elements? 1. 2:1 MUX 2. Exor2 3. {f(x,y)=x‟y} 4. {f(x,y,z)=(x+y)z‟} 5. Nand2
CGCoreEl
Sandeepani School of VLSI Design
Universal Logic Gate Introduction
A set of gates is said to be universal if any combinational system can be implemented using gates just from that set. The set {AND,NOT} or {OR,NOT} is universal . So any set of gates that can implement either {AND,NOT} or {OR,NOT} is universal.
CGCoreEl
Sandeepani School of VLSI Design
Universal Logic gate : Nand2
Lets start with NAND gate.
• • NAND(x,y)= (xy)‟ ⇒ NAND(x,x)=(xx)‟=x‟ ⇒ NOT(x)=NAND(x,x) NOT gate can be implemented by a NAND gate AND(x,y)= xy = ((xy)‟)‟=(NAND(x,y))‟ . From the previous step, we know how to implement NOT gate by a NAND gate AND(x,y)=(NAND(x,y))‟=NAND(NAND(x,y), NAND(x,y))
•
So,AND gate can be implemented by only using NAND gates Since we can implement AND and NOT by only NAND gates, {NAND, NOR} is a universal set,even without NOR gate.
CGCoreEl
Sandeepani School of VLSI Design
Universal Logic Gate NAND Function
NAND ::= Negative AND
Y = ( A • B )´
A A B A B
A
Y
NOT AND OR
INV
Y
= = =
A A B A B
A B
A B A B A B
NAND 2
Y
Y
A B Y
A Y B AND 2
Y
NAND 2
Y
NAND 2
Y
A B
OR 2
Y
Y
NAND 2
Y Y
A B
NAND 2
Y
Y
NAND 2
CGCoreEl
Sandeepani School of VLSI Design
NOR ::= Negative OR
Y = ( A + B )´
Universal Logic Gate NOR Function
NOT
A A B A B
A A B
INV
Y
Y Y
= = =
A A B A B
A B A B A B A B
NOR 2
Y Y Y Y
AND
OR
AND 2
Y
NOR 2 NOR 2
A B
NOR 2 A
Y
A B
OR 2
Y
Y
NOR 2
B
NOR 2
Y
CGCoreEl
Sandeepani School of VLSI Design
Universal Logic Gate Multiplexor Function Multiplexor
Y = A • S + B • S´
NOT
A A B
VCC Y Y D0 S1 S0 GND D1 Y D2 MX4 D3 VCC Y
OR
A B
D0 D1
S1 S0 Y
AND
VCC Y
Y
Y
D2 MX4 D3
Y
Y
D0 D1
S1 S0 Y
D2 MX4 D3
Y
Y GND
GND
GND
Implement the same using 2 to 1 Multiplexer
CGCoreEl
Sandeepani School of VLSI Design
Basic Data Processing Circuits
CGCoreEl Sandeepani School of VLSI Design 24 line Decoder with Enable Input .
CGCoreEl Decoder (3:8) Sandeepani School of VLSI Design .
Implement 4:16 Decoder using two 3:8 Decoders Q2. Design BCD to decimal converter • • with false data rejected with false data accepted . Realize a full adder using one 3:8 decoder & residual gates Q3.CGCoreEl Sandeepani School of VLSI Design Problems using Decoder Q1.
CGCoreEl Sandeepani School of VLSI Design 4:16 Decoder using 3:8 Decoder .
CGCoreEl
Full Adder using Decoder
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Encoder
• DecimaltoBCD Encoder • OctaltoBinary Encoder Limitations?
CGCoreEl
4Input priority Encoder
Sandeepani School of VLSI Design
CGCoreEl
Sandeepani School of VLSI Design
Multiplexer
CGCoreEl
Sandeepani School of VLSI Design
4:1 line Multiplexer
CGCoreEl
Sandeepani School of VLSI Design
Problems
Q1. Realize the following using only one 2:1 Mux
1. 2. 3. 4. 5. 6. NOT And2 OR2 Exor2 Exnor2 Latch
CGCoreEl
Problems
Sandeepani School of VLSI Design
Q2. Show how two 2to1 multiplexers (with no added gates) could be connected to form a 3to1 MUX. Input selection should be as follows: If AB = 00, select Io If AB = 01, select I1 If AB = 1 – (B is don`t care), select I2. Q3. Realize the function F(A,B,C,D)=Σm(1,2,3,6,8,9,11,14) using an 8to1 MUX with control inputs A,B, and C. Q4. Repeat Q2 with control inputs A,C, and D. Q5. Repeat Q2 using a 4to1 MUX and added gates.
CGCoreEl Sandeepani School of VLSI Design 2input mux as programmable logic block Configuration A B S F= A B 0 F 1 S 0 0 0 0 X Y Y 1 1 1 0 X Y Y 0 0 1 0 0 1 0 1 1 X Y X X X Y 1 0 X Y XY XY XY X1 Y X Y 1 .
F(A.8. Design 1:8 demultiplexer using two 1:4 demultiplexers.4. Implement the following boolean function using 8:1 MUX.B. Q7.15) .3. Design a sequence generator that generates the sequence “11100011”.C.1.D) = (0.CGCoreEl Problems.9. more problems Sandeepani School of VLSI Design Q6. Q8.
Implement a 2to1 Mux with Tristate buffers . • It is a current amplifier & also called as driver. A TriState Buffer Q.CGCoreEl Sandeepani School of VLSI Design Buffer • A Buffer is a logic circuit which has one I/p line & one output line.
CGCoreEl Sandeepani School of VLSI Design Answer 21 line Mux with Tristate buffer Or .
CGCoreEl Wired logic Sandeepani School of VLSI Design • Power dissipation in LOW output state increases • Speed of the operation increases • Fan out decreases .
CGCoreEl Sandeepani School of VLSI Design Clock Generator Circuit ? .
What circuit is this? .CGCoreEl Now. Try to find the resolution of this circuit. Also realize the logic for b1 and bo using 2input NAND gates only. The “thermometer to binary conversion” logic is a simple combination circuitry which is to be designed to provide a natural binary representation using b1 and b0 for the analog input Vin. here b1 is the most significant bit. solve this? Sandeepani School of VLSI Design Look at the circuit diagram is given.
. Output depends on current input values and present state of the circuit.CGCoreEl Sequential circuits… Sandeepani School of VLSI Design Combinational. Output depends only on current input values. where the present state of the circuit is the current value of the devices‟ memory. Sequential.
. It consist of a pair of inverters connected as shown below.CGCoreEl Bistable Elements Sandeepani School of VLSI Design The simplest sequential circuit. Notice the feedback loop.
If Q is LOW then the lower inverter has a LOW at its input and a HIGH at its output.CGCoreEl Sandeepani School of VLSI Design Digital Analysis Two stable states. . If Q is HIGH then the lower inverter has a HIGH at its input and a LOW at its output. This in turn forces the upper inverter‟s input to be HIGH and its output to be LOW. This in turn forces the upper inverter‟s input to be LOW and its output to be HIGH.
What would happen if a small amount of noise varies either input voltage. .CGCoreEl Sandeepani School of VLSI Design Analog Analysis Metastable behavior: Consider the middle intersecting point in the diagram shown below.
CGCoreEl Latches and FlipFlops Sandeepani School of VLSI Design Binary cells capable of storing 1 bit of information. Generates one of two possible stable states. . One or more inputs. These sequential devices differ in the way their outputs are changed: – The output of a latch changes independent of a clocking signal. – The output of a flip–flop changes at specific times determined by a clocking signal. Two outputs labeled Q and Q‟.
CGCoreEl Sandeepani School of VLSI Design SR Latch with Control Input .
CGCoreEl Sandeepani School of VLSI Design D Latch This latch eliminates the problem that occurs in the S‟R‟ latch when R=S=0. . Due to this fact this latch is also called transparent latch. C is an enable input: When C=1 then the output follows the input D and the latch is said to be open. When C=0 then the output retains its last value and the latch is said to be closed.
CGCoreEl Sandeepani School of VLSI Design D Latch For proper operation the D input must not change during a time interval around the falling edge of C. .
and the second the slave. When CLK_L = 1 the master is open and the slave is closed. Qm and Ds follow Dm .CGCoreEl Edge Triggered D FlipFlop Sandeepani School of VLSI Design This flipflop is made out of two D latches. . The first latch is the master.
Q* = D Sandeepani School of VLSI Design .CGCoreEl Edge Triggered D FlipFlop Positive edgetriggered D flipflop.
CGCoreEl JK Flip Flop (USING D flip flop) Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design Excitation table of Flip Flops .
CGCoreEl Sandeepani School of VLSI Design Flip Flop to Flip Flop conversions .
3. DT TD DJK DSR TSR JKSR SRJK D=T⊕Q T=D⊕Q D=Q’J+QK’ . 5. 6.CGCoreEl Sandeepani School of VLSI Design FF – FF conversions 1. 7. 4. 2.
CGCoreEl Sandeepani School of VLSI Design D from JK Flip Flop .
More Problems. Design a circuit that generates two waveforms of 90° phase shift. Design a 50% duty cycle frequency doubler for an input clk pulse of 50% duty cycle. Q. Let us continue! . Many more Problems……….CGCoreEl Sandeepani School of VLSI Design Problems (doubts) Q.
CGCoreEl Sandeepani School of VLSI Design Timing Issues .
CGCoreEl Sandeepani School of VLSI Design Timing Issues • • • • • • • • Timing parameters Timing diagram Set up time Hold time Clock Skew Slack Critical path Maximum Frequency of Operation .
CGCoreEl Sandeepani School of VLSI Design Timing parameters .
CGCoreEl Timing parameters…contd Sandeepani School of VLSI Design .
CGCoreEl Timing parameters…contd Sandeepani School of VLSI Design .
CGCoreEl Timing diagram Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design Setup and Hold Time •Setup and hold time define a window of time which the D input must be valid and stable in order to assure valid data on the Q output. •Setup Time (Tsu) – Setup time is the time that the D input must be valid before the FlipFlop samples. •Hold Time (Th) – Hold time is the time that D input must be maintained valid after the FlipFlop samples. . •Propagation Delay (Tpd) – Propagation delay is the time that takes to the sampled D input to propagate to the Q output.
CGCoreEl Clock Skew Sandeepani School of VLSI Design Synchronous systems using edge triggered flipflops work properly only if all flipflops see the triggering edge at the same time. The difference between arrival times of the clock at different devices is called clock skew. Q1 Q2 IN FF1 CLOCKD FF2 CLK A LONG SLOW PATH .
when the signal arrives Required Time (RT) .time for signal transition from logic levels .CGCoreEl Slack Sandeepani School of VLSI Design At each node is a group of events modeling signal transitions AT RT D Q QB SLEW Arrival Time (AT) .when the signal is needed Slew (SLEW) .
Am I meeting timing at this node? AT +SLACK RT SLEW SLACK = RT .CGCoreEl Sandeepani School of VLSI Design Slack Q.AT Timing is met when slack is greater than or equal to zero .
CGCoreEl Sandeepani School of VLSI Design Maximum Operating Frequency .
ring counters and twisted ring counters Asynchronous/ synchronous counters . PISO. SIPO Shift register counters. PIPO.CGCoreEl Recap Sandeepani School of VLSI Design Shift registers: SISO.
CGCoreEl
Counters
Sandeepani School of VLSI Design
Clocked sequential circuit with singlecycle state diagram Modulom counter = dividebym counter
S1
Sm
S2
S3
Most Common:
nbit binary counter, where m = 2n n flipflops, counts 0 … 2n1
CGCoreEl
Sandeepani School of VLSI Design
Ripple Counter
Q CLK T Q Q0 1 bit divideby2 2 bit divideby4 3 bit divideby8 Uses Minimal Logic!
Q
T Q Q T Q
Q1
Q2
Q
T Q
Q3
4 bit divideby16
CGCoreEl
Sandeepani School of VLSI Design
Ripple Counter Timing
CLK
1D
Q0
Q1 Q2
0
2D
3D
1
2
3
4
CGCoreEl
Sandeepani School of VLSI Design
Ripple Counter Problem (It’s Slow!)
n TCQ for MSB change for nbit ripple counter => minimum clk period
CLK
1D
Q0
Q1 Q2 7
2D
3D
Should be 0!
1
2
CGCoreEl
Sandeepani School of VLSI Design
Synchronous Counters
All clock inputs connected to common CLK signal
So all flipflop outputs change simultaneously tCQ after CLK Faster More Complex Logic Most Frequently Used Type of Counter
CGCoreEl
Sandeepani School of VLSI Design
Synchronous Serial Counter
Flipflops enabled CNTEN when all lower CLK flipflops = 1. Enable Dt propagates serially — limits speed Dt Requires (n1) Dt < TCLK All outputs change Dt simultaneously tCQ after CLK Equation?
Delay?
EN >T EN >T EN >T EN >T
Q
Q0
Q
Q1
Q
Q2
Q
Q3
CGCoreEl
Sandeepani School of VLSI Design
Synchronous Parallel Counter
CNTEN
EN >T EN >T EN >T EN
Equation? Delay?
Q
Q0
Singlelevel enable logic per CLK flipflop Fastest and most complex type of counter Requires Dt < TCLK All outputs change simultaneously tCQ after CLK
Q
Q1
Q
Q2
Q
Q3
>T
CGCoreEl Sandeepani School of VLSI Design Decoded Modulo8 Counter: Glitches! More than 1 bit changes simultaneously CLOCK /S0 /S1 /S2 /S3 /S4 /S5 /S6 /S7 0 1 2 3 4 5 6 7 Glitches NOT a problem for synchronous inputs. Glitches BAD for asynchronous inputs! 0 1 .
6. Design a MOD 5 counter (divide by 5) counter using JK flipflop. Also draw the timing diagram of MOD 10 counter.13.2. .… Implement the circuit and avoid locout condition Q2. Also construct the timing diagram.3.CGCoreEl Sandeepani School of VLSI Design Solve these: Q1: Design a JK counter that goes through the states 1.7.1.8.11.
7.9.CGCoreEl Sandeepani School of VLSI Design Solve these: …contd Q3. Design a asynchronous MOD 10 (decade) counter.5.8. Compare this with fmax for a MOD16 ripple counter.3. which will go through the states 3.10.4. Determine fmax for the 4bit synchronous counter if tpd for each flipflop is 50 ns and tpd for each AND gate is 20 ns. Q4. Q5.. Design a nonsequential ripple counter.…. .
CGCoreEl Sandeepani School of VLSI Design Interesting Problems: Q1. Design a divideby3 counter with 50% duty cycle? Question: Why in most of the designs only 50% duty cycle clocks are used? Why can't we use a lesser duty cycle (less than 50%) clock? .
. Design a black box whose input clock and output relationship as shown in diagram below.CGCoreEl Sandeepani School of VLSI Design Interesting Problems … contd Q2. Design a divideby 1.5 counter? Q3.
CGCoreEl Sandeepani School of VLSI Design Finite State Machines .
CGCoreEl Sandeepani School of VLSI Design Topics FSM Basics Types of Machines Example Designs .
Design the circuit. . of 1`s in 50k bits are odd else Z = 0.CGCoreEl Sandeepani School of VLSI Design Example Assume a stream of 50k bits are given to the circuit whose output Z=1 when no.
Ideally suited for complex sequential logic. .CGCoreEl Sandeepani School of VLSI Design Finite State Machines Finite state machines are so named because the sequential logic that implements them can be in only a fixed number of possible states. FSM is a systematic way of specifying any sequential logic.
.CGCoreEl Sandeepani School of VLSI Design What is an FSM? Design Specification Point of View State machines are a means of specifying sequential circuits which are generally complex in their transition sequence and depend on several control inputs.
CGCoreEl Sandeepani School of VLSI Design What is an FSM? Digital Circuit Point of View State machines are a group of flipflops. whose groupstate transition pattern from one set of values to another and depends on several control inputs .
FOR OUTPUT CONTROL INPUTS STATE REGISTER FLIPFLOPS CLOCK ASYNC CONTROL PORTS .CGCoreEl Sandeepani School of VLSI Design FSM Structure MEALY CURRENT STATE COMB. LOGIC for NEXT STATE NEXT STATE CURRENT STATE OUTPUTS COMBO.
Mealy outputs are asynchronous and can change in response to any changes in the inputs. . GlitchesHow to avoid? Require less no. of states compared to Moore Machine. independent of the clock.CGCoreEl Sandeepani School of VLSI Design Mealy Machine The outputs depend on the current state and the present value of the inputs.
CGCoreEl Sandeepani School of VLSI Design Moore Machine The outputs depend only on the present state. The outputs are computed by a combinational logic block whose only inputs are the flipflops' state outputs The outputs change synchronously with the state transition and the clock edge. .
Decides next state based on current state and inputs .Current state only (moore) .Stores current state . State register .CGCoreEl Finite state machine Sandeepani School of VLSI Design FSM Structure:. Output logic (B) Decodes state (or states and inputs) to produce outputs .Outputs from the FSM can be a function of: .Current state and the current inputs (Mealy) B Moore FSM A c1k A c1k B Mealy FSM . Next state decoder logic (A) .
Cases: (i) Nonoverlapping (ii) Overlapping of sequence .CGCoreEl Sandeepani School of VLSI Design FSM Design examples Q1. Design a circuit that asserts its single output whenever its input string has two 1's in sequence.
CGCoreEl Sandeepani School of VLSI Design FSM Design examples Q2. of 1`s in 50k bits are odd else Z = 0. (using Mealy machine) . Assume a stream of 50k bits are given to the circuit whose output Z=1 when no. Design the circuit.
CGCoreEl Sandeepani School of VLSI Design FSM Design examples Q3. . Design a circuit to detect a sequence “010” (i) nonoverlapping (ii) overlapping using Mealy machine.
CGCoreEl Sandeepani School of VLSI Design FSM design example Design a circuit to detect a sequence “1010” (i) nonoverlapping (ii) overlapping using Mealy machine. .
(2) Moore machine And compare the two designs .CGCoreEl Sandeepani School of VLSI Design FSM design example Design a circuit to detect a overlapping sequence “101” using (1) Mealy machine.
no. . of arrows leaving the state will be 2n . Note: If any state machine has „n‟ inputs. A sequential circuit accepts two i/p`s X & Y and generates an o/p Z = 1 whenever the i/p`s are equal & same in the present as well as previous clock cycle.CGCoreEl Sandeepani School of VLSI Design FSM Design examples Q4. Design a Mealy machine.
The circuit examines groups of 4 consecutive inputs and produces an output Z=1 if the input sequence 0101 or 1001 occurs. Find the Mealy state graph. Ex: X= 0101  0010  1001  0100 Z= 0001  0000  0001  0000 .CGCoreEl Sandeepani School of VLSI Design FSM design example A sequential circuit has one input (X) and one output (Z). The circuit resets after every 4 inputs.
as long as the sequence 100 has never been seen.(Overlapping) .CGCoreEl Sandeepani School of VLSI Design FSM Design examples Q5.Design a Moore finite state recognizer that has one input (X) and one output (Z). The output is asserted whenever the input sequence 010 has been observed.
when I/p sequence “110” occurs the o/p becomes 1 and remains 1 until the sequence “110” occurs in which case the o/p returns to zero. A sequential circuit has one I/p and one o/p.CGCoreEl Sandeepani School of VLSI Design FSM Design examples Q6. The output remains zero until “110” occurs the third time. Draw the state diagram and state table. .
Sketch the state diagram for the receiver. State diagram of a transmitter is shown below.CGCoreEl Sandeepani School of VLSI Design FSM Design examples Q7. 0/0 1/0 X Tx Y 0 Tx 0/1 1 1/1 Y Rx X Rx ?? .
more problems… Design a pulse train generator circuit using shift register for the following pulse train: …1 0 0 0 1 1 0… Next Question: Now can you design a circuit to generate a specified waveform. .CGCoreEl Sandeepani School of VLSI Design Problems.
CGCoreEl Sandeepani School of VLSI Design Introduction to Memories .
CGCoreEl Sandeepani School of VLSI Design Classification MEMORY RAM SRAM DRAM HYBRID FLASH EEPROM ROM PROM EPROM MASKED .
CGCoreEl Sandeepani School of VLSI Design Memory array architecture .
CGCoreEl Sandeepani School of VLSI Design Latch and Register based Memory .
CGCoreEl Sandeepani School of VLSI Design .
Area & Cost. Which to choose & on what basis? Speed. .CGCoreEl Sandeepani School of VLSI Design RAM Types : SRAM & DRAM Primary difference: lifetime of the data they store.
CGCoreEl Sandeepani School of VLSI Design .
Distinguished by the methods used to write new data to them (usually called programming) and the number of times they can be rewritten.CGCoreEl Sandeepani School of VLSI Design ROM Types : MASKED. . PROM & EPROM They are class of PLD s.
EROM : Erased & reprogrammable again & again.CGCoreEl Sandeepani School of VLSI Design ROM MASKED : Programmed by manufacturer. . PROM : One time programmable.
CGCoreEl PLD s Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design ROM .
CGCoreEl Sandeepani School of VLSI Design ROM .
CGCoreEl Sandeepani School of VLSI Design Exercise on PLAs Design a full adder using PLA Design a Binary to Gray code converter using PLA It is desired to generate the following 3 Boolean functions: F1=ab’c+a’bc’+bc F2=ab’c+bc+a’bc’ F3=a’b’c’+abc+a’c .
p2.p3.CGCoreEl Sandeepani School of VLSI Design BY using OR gate array write down the terms p1.p4 and p5 p1 p2 p3 P4 p5 * * * * * * f3 f1 f2 .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
not bytebybyte as in EEPROM. . FLASH: The major difference is that flash devices can only be erased one sector at a time. the new data will remain in the device foreveror at least until it is electrically erased.CGCoreEl HYBRID Sandeepani School of VLSI Design Combine features of both EEPROM: Once written.
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Comparison: memories Yes Yes No No No Yes Yes No Only once Yes Yes Byte Byte N/A N/A Entire Chip Byte Sandeepani School of VLSI Design Type Volatile Writeable Erase Size SRAM DRAM RAM PROM EPROM Cost(per Byte) Speed Expensive Moderate Inexpensive Moderate Moderate Expensive Fast Moderate Fast Fast Fast Fast EEPROM No FLASH No Yes Sector Moderate Fast .
CGCoreEl Sandeepani School of VLSI Design Expanding word size. capacity and both Problems Store 16 8 bit words using 16x4 RAMs Obtain 1Kx8 module using 1Kx1 RAMs Store 32 4 bit words using 16x4 chips Obtain 8Kx8 ROM using 2Kx8 ROMs Obtain 4Kx8 ROM using 1Kx4 ROMs .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design Introduction to STATIC TIMING ANALYSIS .
CGCoreEl Sandeepani School of VLSI Design Concepts Covered Introduction to STA Timing Paths Skew Problems Clock & Timing Constraints Exceptional Paths Multicycle relations with multiple clocks .
Advantages: Much faster than timingdriven.CGCoreEl Sandeepani School of VLSI Design STA – What is Static Timing Analysis? STA is an exhaustive method of analyzing. . Exhaustive Vector generation NOT required. debugging and validating the timing performance of a design. gatelevel simulation.
CGCoreEl Sandeepani School of VLSI Design STA – What is Static Timing Analysis? Data Clk D Q QB Output OutputBar What are our circuit timing requirements? Clk 0 Data 100 200 300 400 500 Setup Requirement Hold Requirement Data Cannot Change Within These Windows .
CGCoreEl Sandeepani School of VLSI Design STA – What is Static Timing Analysis? Clk 0 Data 100 200 300 400 500 Setup Requirement Hold Requirement Clk 0 Data 100 Early Required Time Late Required Time .
CGCoreEl Limitations of STA Sandeepani School of VLSI Design Works best with synchronous (not asynchronous) logic Complex to learn Must define timing requirements / exceptions Difficulty in handling: • Multiple clocks • False paths: Proper circuit functionality is not checked • Latches • Multicycle paths .
slow .CGCoreEl Sandeepani School of VLSI Design What is Dynamic Timing Analysis? Advantage: Can be very accurate (spicelevel) Disadvantages: •Analysis quality depends on stimulus vectors •Nonexhaustive.
CGCoreEl Sandeepani School of VLSI Design STA in ASIC Design Flow – Pre layout Logic Synthesis Constraints (clocks. input drive. output load) Design For test Floor planning Static Timing Analysis Static Timing Analysis (estimated parasitics) .
output load) Clock Tree Synthesis Place and Route Parasitic Extraction Static Timing Analysis (estimated parasitics) Static Timing Analysis (extracted parasitics) SDF (extracted parasitics) . input drive.CGCoreEl Sandeepani School of VLSI Design STA in ASIC Design Flow – Post Layout Floor planning Constraints (clocks.
CGCoreEl Wire Load Model Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design Timing Graphs .
Timing Graph Introduction Top Sandeepani School of VLSI Design Node: where timing information is stored on the design Data Clk D Q QB Output OutputBar Bottom Q.CGCoreEl STA . How many nodes are in our design? A node exists for every Model pin Cell Pin Hierarchical pin 4 8 2 14 .
CGCoreEl STA .Node Types Top D Q QB Sandeepani School of VLSI Design Data Clk Output OutputBar Data Nodes Clock Nodes All nodes along clock path Created from “force clock constraints” .
CGCoreEl
STA  Events
Sandeepani School of VLSI Design
At each node is a group of events modeling signal transitions
AT
D Q QB
RT
SLEW
Arrival Time (AT)  when the signal arrives Required Time (RT)  when the signal is needed Slew (SLEW)  time for signal transition from logic levels
CGCoreEl
STA  Meeting Timing
AT
Sandeepani School of VLSI Design
Q. Am I meeting timing at this node?
+SLACK
RT
SLEW
SLACK = RT  AT
Timing is met when slack is greater than or equal to zero
CGCoreEl
STA  Meeting Timing
Sandeepani School of VLSI Design
Q. Am I meeting late mode timing at this node?
SLACK = RT  AT
AT
+SLACK
RT
RT
AT
SLACK
No, the falling edge slack is negative... HINT: RT should always be after AT
CGCoreEl
STA  Levels
Sandeepani School of VLSI Design
Q. How many levels of logic are in this design? 5
3
4
1 2 1
2
4 3 6 7 8
9 10
Q. How many timing levels are in this design? HINT: Determine the nodes first HINT: Timing Levels = 2 * Logic Levels + 2
CGCoreEl
STA  Calculating AT
1 1.0 1.2 2.4 25 9 1.2 2 3 1.7 1.0 1.0 2 1.2 2 1.7 3 1.2 4 1.9 5 2.4 6 2.6 4 1.9 4 1.9 2.6 1 1 1 1.0
Sandeepani School of VLSI Design
9 7 3.1 3.3 8 3.8
10 4.0
1 1.0
2 1.2
STEP 1 : Calculate timing level for each node STEP 2 : Calculate AT from level 1 to level n Simplifying assumptions: Input arrival time of 1 Wire delay 0.2 ; gate delay 0.5
CGCoreEl
STA  Calculating RT
1 1.2 1.0 1 0.5 1.0 1 0.2 1.0 1 0.2 1.0 1 1.0 0.5 0.7 2 1.2 1.4 1.2 2 3 1.7 1.2 0.7 4 1.9 5 2.4 1.2 1.9 2.4 5
Sandeepani School of VLSI Design
2 1.2 0.7
6 2.6 1.4
3.1 1.9
3.3 2.1
STEP: Calculate RT from level n to level 1
Simplifying assumptions: One number for rise and fall Output required time of 2.8 Wire delay 0.2 ; gate delay 0.5
8
2 0.0 1.2 2
0.0 1.2
0.5 1.7 3
7
9 9 3.8 2.6 10 4.0 2.8
4 1.9 1.4 1.4 4 1.9
2.1 2.6
CGCoreEl
STA  Calculating Slack
0.2 1 1.2 1.0 0.5 0.5 0.7 2 1 0.5 1.2 1.0 1.2 1 0.2 1.0 1.2 0.0 1 0.2 1.2 1.0 2 1.2 0.0 1.2 1.2 2 1 1.0 0.5 0.5 0.2 1.4 1.2 2 3 1.7 1.2 1.2 0.5 0.5 1.7 0.7 4 1.9 1.2 3 0.5 1.9 2.4 5
Sandeepani School of VLSI Design
Q: What is the formula for late mode slack? SLACK = RT  AT Slack is calculated on an as needed basis
2 1.2 0.7 0.5
6 5 2.6 2.4 1.4 1.2 1.2 1.2
3.1 1.9 1.2
3.3 2.1 1.2
8
9 9 10 3.8 4.0 2.6 2.8 1.2 1.2
4 1.9 0.5 1.4 1.4 0.5 4 1.9 7
0.5 2.1 2.6
CGCoreEl Sandeepani School of VLSI Design D Q QB What Does Register Bound Mean ? D Q QB D Q QB D Q QB • Register bound implies that the combinational logic is • bounded by registers on the inputs and the outputs. Combinational logic is represented by a symbolic blob. .
Data nodes) • Event description (RT. Slack expresses the relationship between signal arrival time and required time at a node. STA Introduction Summary . hold) • Timing Graph (Clock nodes.CGCoreEl Sandeepani School of VLSI Design • Basics (setup. slew) • Timing information for a design is stored on nodes • At each node a group of events models signal • • transitions. AT. Specifying the clocks constraints all registertoregister (registerbound) paths.
CGCoreEl Sandeepani School of VLSI Design Basic Terminologies .
CGCoreEl Concepts Covered Sandeepani School of VLSI Design Minimum clock period Clock latency Hold constraint Clock jitter Setup time Hold time ClocktoQ time Clock skew Cause and effect of timing violations Critical path False path Multicycle path Ideal and computed clocks Specifying clocks Generated clocks .
The critical path limits the maximum clock speed.CGCoreEl Basic Terminologies Sandeepani School of VLSI Design Critical path: The slowest path on the chip between flops or flops and pins. .
. Hold time: The amount of time the synchronous input must be stable after the active edge of clock.CGCoreEl Basic Terminologies Sandeepani School of VLSI Design Setup time: The amount of time the synchronous input must be stable before the active edge of clock.
reset) Recovery time: It is the time available between the asynchronous signal going inactive to the active clock edge.CGCoreEl Basic Terminologies Sandeepani School of VLSI Design Recovery time: Like setup time for asynchronous port (set. . reset) Removal time: Like hold time for asynchronous port (set. Removal time: It is the time between active clock edge and asynchronous signal going inactive.
Path delays are checked to see if timing constraints have been met. .CGCoreEl Sandeepani School of VLSI Design Three Steps in Static Timing Analysis Circuit is broken down into sets of timing paths. Delay of each path is calculated.
Clock pins of flipflops Endpoints: Output ports. Each path has a startpoint and an endpoint Startpoints: Input ports. Data input pins of flipflops .CGCoreEl What is a Timing Path? Sandeepani School of VLSI Design A Timing Path is a pointtopoint path in a design which can propagate data from one flipflop to another.
CGCoreEl Types of Timing Paths Sandeepani School of VLSI Design .
.CGCoreEl Organizing Timing Paths Into Groups Sandeepani School of VLSI Design Timing paths are grouped into path groups by the clocks controlling their endpoints. Synthesis tools like Prime Time and Design Compiler organize timing reports by path groups.
CGCoreEl Critical path?? Sandeepani School of VLSI Design .
CGCoreEl Critical path?? Sandeepani School of VLSI Design .
This limit is called the maximum clock frequency for the circuit.CGCoreEl Sandeepani School of VLSI Design Basic Terminologies Maximum Clock Frequency/ Minimum Clock Period The clock frequency for a synchronous sequential circuit is limited by the timing parameters of its flipflops and gates. The minimum clock period is the reciprocal of this frequency. .
CGCoreEl Condition for Hold time Sandeepani School of VLSI Design D Q QB D Q QB clkbar To satisfy hold time: Tc2q + Tpd (minimum) > Thold .
CGCoreEl Sandeepani School of VLSI Design .
CGCoreEl Sandeepani School of VLSI Design Synchronous System Detailed Timing tffpd D Q tcomb Combinational logic CLK tffpd .input stable before clock thold .input stable after clock JAL D Q tsetup & thold (min. max) tcomb .combinational logic dely tsetup .CLK to Q. max) (min) (min) . FF propagation delay (min.
CGCoreEl Sandeepani School of VLSI Design Example Timing Violations: Good Timing .
CGCoreEl Sandeepani School of VLSI Design Synchronous System .min Difference = Hold time margin >= 0 for guaranteed operation .max + tcomb. min + tcomb.min > tffpd.Detailed Timing Required: tclk.max + tsetup.min Difference = Setup time margin >= 0 for guaranteed operation Required: tffpd.min > thold.
min and 15 ns. min and 20 ns. max tffpd = 3 ns. max tsetup = 5 ns.CGCoreEl Sandeepani School of VLSI Design Synchronous System Example in1 in2 Combinational logic State Register Q3 Q2 Q1 tcomb = 2 ns. min thold = 2 ns. min Setup margin @ 10 MHz clk? Max Frequency? Hold Margin? JAL .
min and 20 ns. max tsetup = 5 ns. so fmax <= 25 MHz (3 + 2) 2 = 3ns Setup margin @ 10 MHz clk? Max Frequency? Hold Margin? .(15 + 20 +5) = 60 ns tclk.CGCoreEl Sandeepani School of VLSI Design Synchronous System Example in1 in2 Combinational logic State Register Q3 Q2 Q1 tcomb = 2 ns.min >= 40 ns. max tffpd = 3 ns. min and 15 ns. min thold = 2 ns. min 100 .
CGCoreEl Sandeepani School of VLSI Design 74LS74 Data Sheet Timing Parameter tW Pulse Width . CleartoQ Min 18 15 15 20 0 20 35 35 35 Max Units ns ns ns ns ns MHz ns ns ns . ClocktoQ tPLH Prop Delay.Preset Low .Clock High .Clear Low tSU Setup Time tH Hold Time fMAX Max Clock Frequency tPLH Prop Delay. PresettoQ tPLH Prop Delay.
but does not specify upper and lower limits INSUFFICIENT information for a REAL system design Clock Sig1 Sig2 . so all edges line up Shows what happens each clock.CGCoreEl Sandeepani School of VLSI Design Functional Timing Diagram Shows no delays. ignoring exact delays Illustrates operation.
CGCoreEl Sandeepani School of VLSI Design Clock flipflop outputs tH tclk tL tffpd combinational outputs flipflop inputs tcom b setuptime margin tsetup thold .
CGCoreEl Sandeepani School of VLSI Design Example Timing Violations: Setup Violation .
CGCoreEl Sandeepani School of VLSI Design Example Timing Violations: Hold Violation .
1ns clock Skew = 1.3ns .CGCoreEl Sandeepani School of VLSI Design Clock Skew • Clock Skew: The maximum difference in arrival time of the clock signal to each register in the design Clock arrival time at 1.2ns Clock arrival time at 1.3ns .1ns = .1.
CGCoreEl Sandeepani School of VLSI Design Absolute Clock Skew – A Definition clock input Time from clock input (at pin) to clock input at a given flip flop Your chip Flip Flop .
CGCoreEl Sandeepani School of VLSI Design Relative Clock Skew clock input Time between 2 flip flops receiving the clock signal Your chip Flip Flop Flip Flop .
CGCoreEl Sandeepani School of VLSI Design Failure / Data loss Due To Large Skew “A” Flip Flop “B” Ain Aout Combinational Logic Bin Flip Flop clk d delay If new data (Ain) gets to point “Bin” before clock does. system will fail by simply skipping over old data… For this illustration .ignore tsetup .
CGCoreEl Sandeepani School of VLSI Design Clock arrives at point “A” “A” Ain Flip Flop “B” Aout Combinational Logic Bin Flip Flop clk d delay T = 0ns .
CGCoreEl Data arrives at combo logic input “A” Ain Flip Flop Sandeepani School of VLSI Design “B” Aout Combinational Logic Bin Flip Flop clk d delay T = tclktoQ .
CGCoreEl Data Exits Comb Logic “A” Ain Flip Flop Sandeepani School of VLSI Design Aout Combinational Logic “B” new Bin Flip Bin Flop clk d delay T = tclktoQ + tlogic .
CGCoreEl Clock Reaches “B” “A” Ain Flip Flop Sandeepani School of VLSI Design Aout Combinational Logic “B” new Bin Flip Bin Flop clk d delay T = tclktoQ + tlogic Tskew = td .
CGCoreEl Failure!!! “A” Ain Flip Flop Sandeepani School of VLSI Design Aout Combinational Logic “B” new Bin Flip Bin Flop New Bin clk d delay What happened to old Bin??? If tclktoQ+tlogic < td it fails… .
CGCoreEl Sandeepani School of VLSI Design Clock Jitter clock jitter .
CGCoreEl Clock Jitter Sandeepani School of VLSI Design Clock jitter is caused by: • temperature and voltage variations over time • temperature and voltage variations across different locations on a chip • manufacturing variations between different parts • etc. .
CGCoreEl Sandeepani School of VLSI Design More on Skew .
CGCoreEl Sandeepani School of VLSI Design Positive & Negative Skew In CLK R1 D Q tCLK1 delay (a) Positive skew In R1 D Q tCLK1 delay (b) Negative skew R2 D Q tCLK2 delay R3 D Q tCLK3 CLK Combinational Logic R2 D Q tCLK2 delay Combinational Logic R3 D Q tCLK3 ••• Combinational Logic Combinational Logic ••• .
CGCoreEl R1 D Q tCLK1 delay Positive Skew Combinational Logic R2 D Q tCLK2 delay Combinational Logic Sandeepani School of VLSI Design R3 D Q tCLK3 In CLK ••• TCLK d CLK1 1 d 2 d th 4 T CLK 3 CLK2 .
d CLK1 1 TCLK 3 CLK2 2 d 4 .CGCoreEl R1 D Q tCLK1 delay Negative Skew Combinational Logic R2 D Q tCLK2 delay Combinational Logic Sandeepani School of VLSI Design R3 D Q tCLK3 CLK In ••• TCLK .
CGCoreEl Sandeepani School of VLSI Design Example Timing Violations: Minimum Clock Period .
CGCoreEl Sandeepani School of VLSI Design Example Timing Violations: Hold Constraint .
PC. clock:R#2) .outreg_reg[0]/Q rp.Margin .outreg_reg[15]/D rp.PC.PC.Setup time Endofpath required time (ps) Starting arrival time + Clock path delay + Data path delay Endofpath arrival time (ps) clock period starting and reference edge arrival time data slack = required time .outreg_reg[15]/CK 1p Starting and ending points Slack 704 13000 100 646 12957 0 704 12252 12956 Reference arrival time + Cycle adjust (clock:R#1 vs.arrival time data arrival time time = 0 .CGCoreEl Sandeepani School of VLSI Design Analysis of Timing Report #### Path 1 ############################################ Start End Reference Path slack rp.
CGCoreEl A Timing Example: Sandeepani School of VLSI Design .
40+20) = 60 . max tPHL = 40ns. max tPHL + tsu) TW ≥ max (25+20. tsu = TW ≥ max (max tPLH + tsu. max tPLH = 25ns.CGCoreEl Example 1 D Q Sandeepani School of VLSI Design Q CK Q TW ≥ max tPFF + tsu For the 7474.
CGCoreEl Example 2 D Q Sandeepani School of VLSI Design Q CK TW ≥ max tPFF + max tPINV + tsu .
CGCoreEl Example 3 Sandeepani School of VLSI Design D Q Q Q0 0 1 MUX D Q Q Q1 CK TW ≥ max tPFF + max tPMUX + tsu .
CGCoreEl Example 4 Sandeepani School of VLSI Design Paths from Q1 to Q1: None Paths from Q1 to Q2: W ≥ max tPDFF +tJKsu = 20 +10 = 30 ns T Paths from Q2 to Q1: W ≥ max tPJKFF + tOR + TDsu = 25 + 10 + 5 = 40 ns T TW ≥ max tPDFF + max tAND + tJKsu = 20 + 12 + 10 = 42 T Paths from Q2 to Q2: W ≥ max tPJKFF + max tAND + tJKsu = 25 + 12 + 10 = 4 TW ≥ 47 ns .
i.. tINV = 0) (if clock skewed.e.. i. tINV > 0) .min tINV (if clock not skewed.e.CGCoreEl Sandeepani School of VLSI Design Example 5 : Effect of clock skew on clock rate •Clock C2 skewed after C1 D Q Q1 D2 C2 D Q Q Q2 C1 CK Q TW ≥ max TPFF + max tOR + tsu TW ≥ max TPFF + max tOR + tsu .
CGCoreEl Sandeepani School of VLSI Design Example 6: Maximum Allowable Clock Skew How much skew between C1 and C2 can be tolerated in the following circuit? Q1 D2 D Q D Q Q Q C1 Case 1: C2 delayed after C1 C2 tPFF > th + tSK tSK < min tPFF .th .
CGCoreEl Sandeepani School of VLSI Design Case 2: C1 delayed from C2 D Q Q Q1 D2 D Q Q C1 C2 .
CGCoreEl Example 7 Sandeepani School of VLSI Design How does additional delay between the flipflops affect the skew calculations? tSK ≤ min tPFF .th .th tsk ≤ min tPFF + min tMUX .
CGCoreEl Sandeepani School of VLSI Design Understanding And Describing Clocks .
.CGCoreEl Defining Clocks Sandeepani School of VLSI Design • A clock is defined by its period. waveform and slew time.
CGCoreEl Sandeepani School of VLSI Design Specifying Clocks • Standard clock • Inverted clock • Virtual clock • Derived clock • Gated clock .
The default waveform start at 0 with a 50% duty cycle. . Why aren`t we using –waveform option? clk 0 5 10 A.CGCoreEl Standard Clock Specification Sandeepani School of VLSI Design • Blast Fusion(MAGMA) clock command: force timing clock node period –slew time waveform {rise R –fall F …} –virtual –name name • Equivalent SDC command: create_clock –period –waveform –name name • Example syntax: force timing clock $m/clk 10n clk D Q QB D Q QB Q.
CGCoreEl Sandeepani School of VLSI Design Standard Clock Specification period 20 waveform {0 8} •create_clock •create_clock SDC period 20 waveform {10 18} commands .
CGCoreEl Sandeepani School of VLSI Design Inverted Clock D Q QB clkbar D Q QB • Blast Fusion clock command force timing clock $m/clkbar 5n Q. What is an inverted clock with a 10/50 duty cycle shifted by 2ns ? clk 0 1 2 3 4 5 6 clkbar 0 1 2 3 4 5 6 clkbar 0 1 2 3 4 5 6 waveform {fall 2n –rise 3n} .
A virtual clock lets you associate arrival and required times with clocks external to the chip or block.CGCoreEl Sandeepani School of VLSI Design Virtual Clock • • A virtual clock has no sources. It exists in memory but is not part of a design. . The name of virtual clock must be a unique name that is not associated with any port or instance in the synthesized design.
D D Q QB Q QB D Q QB clk f0 D Q QB force timing clock $m/clk 5n force timing clock $m/f0/Q –generated –source $m/clk –divider 2 .CGCoreEl Generated Clock Sandeepani School of VLSI Design • A design might include clock dividers or other structures that produce a new clock from a master source clock.
CGCoreEl Gated Clock Sandeepani School of VLSI Design •Clock gating reduces power consumption by switching off the clock to flipflops when the value of those flipflops does not change. CLOCK CLOCK GCLK CLKEN CLKEN CGLK .
CGCoreEl Sandeepani School of VLSI Design Gated Clock: Setup and Hold Margins for AND & NAND gates •The setup margin is measured relative to the falling transition of the gating cell clock input. •The hold margin is measured relative to the rising transition of . the clock input.
CGCoreEl Sandeepani School of VLSI Design Gated Clock: Setup and Hold Margins for OR & NOR gates .
CGCoreEl Sandeepani School of VLSI Design Describing Clock Variations • Clock latency (delay) • Clock skew • Jitter .
CGCoreEl Sandeepani School of VLSI Design Source. Network and IO Latency Chip D Q D Q D Q D Q IO latency source latency (offchip) Clock network latency (onchip) IO latency .
Network and IO Latency .CGCoreEl Sandeepani School of VLSI Design Source.
CGCoreEl Sandeepani School of VLSI Design Clock Generation .
CGCoreEl Sandeepani School of VLSI Design .
waveform and • slew time Clock variations that can be described for timing calculation include latency. .CGCoreEl Sandeepani School of VLSI Design Summary: Clocks • A clock is defined by its period. skew and jitter.
CGCoreEl Sandeepani School of VLSI Design False Paths .
CGCoreEl Sandeepani School of VLSI Design What are False paths? • Paths that physically exist in a design but are not logic/functional paths • These paths never get sensitized under any input conditions .
CGCoreEl Logically Impossible Example Sandeepani School of VLSI Design •A path may exist in the circuit but no combination of input vectors may ever exercise it Mux 1 A B1 B B2 C C1 C2 Mux 2 OUT S .
CGCoreEl Logic Removal Example Sandeepani School of VLSI Design •A block may be reused and certain signal functions are no longer required .
because a race condition will occur U1 A Z broken arc U0 D Q QB A B Z B D Q QB "I want to break the combinational loop at U1/B" force timing break from $m/U1/B to $m/U1/Z .CGCoreEl Combinational Loop Example Sandeepani School of VLSI Design Most STA`s can`t leave combinational loops in the design.
•This information cannot possibly be inferred by the timing analyzer. so it must be specified by the designer so the analyzer can mark the path and correctly compute the timing.CGCoreEl Sandeepani School of VLSI Design Multicycle Path •Multicycle paths are paths which intentionally require more than one clock cycle to propagate. along with the number of allowed clock cycles. A start point. end point and/or "through" point is specified. .
CGCoreEl Sandeepani School of VLSI Design Multicycle Path: Example U1 D Q QB U2 D Q QB CK force timing multicycle from $m/U1/Q to $m/U2/D cycle 2 .
CGCoreEl Sandeepani School of VLSI Design Handling Multiple Clocks .
CGCoreEl Sandeepani School of VLSI Design Multiple Clocks Step1: Determine the Least Common Multiple (LCM) A (6 ns) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 B (8 ns) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 • What is the LCM between these two clocks? The timer needs to calculate the delays of the circuit to the LCM to find all path relationships .
CGCoreEl Sandeepani School of VLSI Design Setup Relationship: A Rising. B Rising Find the Setup Relationship between A rising and B rising D Q QB D Q QB • The setup relationship is the closest distance between the launching clock edge (A) and the receiving clock edge (B) .
B Falling Find the Setup Relationship between A rising and B falling D Q QB D Q QB .CGCoreEl Sandeepani School of VLSI Design Setup Relationship: A Rising.
CGCoreEl Sandeepani School of VLSI Design Setup Relationship: A Falling. B Rising Find the Setup Relationship between A falling and B rising D Q QB D Q QB .
B Falling Find the Setup Relationship between A falling and B falling D Q QB D Q QB .CGCoreEl Sandeepani School of VLSI Design Setup Relationship: A Falling.
B Rising Find the Hold Relationship between A rising and B rising D Q QB D Q QB • The hold relationship is the closest distance between the launching clock edge (A) and the previous receiving clock edge (B) .CGCoreEl Sandeepani School of VLSI Design Hold Relationship: A Rising.
B Falling Find the Hold Relationship between A rising and B falling D Q QB D Q QB .CGCoreEl Sandeepani School of VLSI Design Hold Relationship: A Rising.
B Rising Find the hold Relationship between A falling and B rising D Q QB D Q QB .CGCoreEl Sandeepani School of VLSI Design Hold Relationship: A Falling.
B Falling Find the hold Relationship between A falling and B falling D Q QB D Q QB .CGCoreEl Sandeepani School of VLSI Design Hold Relationship: A Falling.
CGCoreEl Sandeepani School of VLSI Design Pipelining Concept .
CGCoreEl Sandeepani School of VLSI Design Pipelining Concept .
CGCoreEl Sandeepani School of VLSI Design Anatomy of a Pipeline Stage Combinational Logic Flip Flop Flip Flop f f TclocktoQ Tlogic Tsetup One clock cycle Tcycle Tclock toQ Tlogic Tsetup .
CGCoreEl Sandeepani School of VLSI Design Anatomy of a Synchronous System input input input Comb Logic Flip Flop Comb Logic Flip Flop Comb Logic Flip Flop f f f • Overall system cycle time • determined by longest pipeline stage (taking input arrival times into account) .
CGCoreEl Latency in Pipelines Sandeepani School of VLSI Design .
CGCoreEl Pipelining Example Original circuit Sandeepani School of VLSI Design – Two logic levels between SOURCE_FFS and DEST_FF – fMAX = ~207 MHz .
CGCoreEl Sandeepani School of VLSI Design Pipelining Example…contd Pipelined circuit – One logic level between each set of flipflops – fMAX = ~347 MHz .
CGCoreEl Review Question Sandeepani School of VLSI Design Given the original circuit. what is wrong with the pipelined circuit? How can the problem be corrected? .
CGCoreEl Sandeepani School of VLSI Design Retiming Concept Register balancing in order to balance the timing .
CGCoreEl Sandeepani School of VLSI Design Time Borrowing .
CGCoreEl Sandeepani School of VLSI Design TIME BORROWING * Time borrowing occurs in latchbased designs .
CGCoreEl Sandeepani School of VLSI Design TIME BORROWING…contd .
The question is whether time borrowing can eliminate negative slack .CGCoreEl Sandeepani School of VLSI Design TIME BORROWING…contd There is a short delay on the first timing path and a long delay on the second timing path.
CGCoreEl Sandeepani School of VLSI Design GLUE LOGIC .
CGCoreEl AVOID GLUE LOGIC X RegA clock GLUE X Sandeepani School of VLSI Design RegA clock X RegB clock THE NAND GATE AT THE TOP LEVEL SERVERS ONLY TO GLUE THE INSTATIATED CELLS OPTIMIZATION IS LIMITED BECAUSE THE GLUE LOGIC CANNOT BE ABSORBED .
DOESN‟T NEED TO BE COMPILED .CGCoreEl Sandeepani School of VLSI Design REMOVE GLUE LOGIC BETWEEN BLOCKS X+GLUE X RegA clock clock RegA X RegB clock THE GLUE LOGIC CAN NOW BE OPTIMIZED WITH OTHER LOGIC TOP LEVEL DESIGN IS ONLY A STRUCTURAL NETLIST.
CGCoreEl Sandeepani School of VLSI Design Signal Interface .
CGCoreEl Sandeepani School of VLSI Design Signal Interface: Model .
CGCoreEl Sandeepani School of VLSI Design Interface Taxonomy (Parallelism) .
CGCoreEl Sandeepani School of VLSI Design Interface Taxonomy (Topology) .
CGCoreEl Sandeepani School of VLSI Design Interface Taxonomy (Timing) .
CGCoreEl Interface Taxonomy (Signaling) Sandeepani School of VLSI Design .