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Lab Manual Department of E & C Engineering
SIR PADAMPAT SINGHANIA UNIVERSITY Udaipur
School of Engineering
VLSI DESIGN LAB EC-306
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
5. (b). Design a Schematic of CMOS Inverter circuit. 9.Write a program for D latch also for D flip flop using synchronous reset & asynchronous reset.Write a VHDL code for 4X1 MUX and for 16X1 MUX. (a). 10. registers .Write VHDL code using case statement for 2X4 decoder also write program for 3 to 8 decoder using structural style (a).Write program for Mealy & Moore Machines using VHDL 6. N.Write VHDL code for Half adder and Full adder. (a). Design a Schematic Of CMOS NAND gate. Udaipur Lab Manual Department of E & C Engineering LIST OF EXPERIMENTS S.SIR PADAMPAT SINGHANIA UNIVERSITY. (b).Write VHDL code for four bit adder using structural 2. (b). 2 . (b).Write a program in VHDL to implement a comparator circuit. (b).Write the program for basic logic gates using VHDL.Write Verilog code for Half adder and Full adder.Write Verilog code for MUX . (a).counters. (a).Write VHDL code for 4X1MUX using concurrent & sequential statements (b).Write verilog code for d flip flop.Decoder . Write program for Mealy & Moore Machines using VHDL 8. using structural data flow. 1. 3. (b). a). Design a Schematic of CMOS NOR gate Title of the Experiment (a). 4.Write a program in VHDL for implementing a n bit counter. 7.
SIR PADAMPAT SINGHANIA UNIVERSITY. Udaipur Lab Manual Department of E & C Engineering OVERVIEW OF LAB BASIC SIMULATION FLOW 3 .
Udaipur Lab Manual Department of E & C Engineering 4 .SIR PADAMPAT SINGHANIA UNIVERSITY.
Udaipur Lab Manual Department of E & C Engineering MODEL SIM SIMULATION 5 .SIR PADAMPAT SINGHANIA UNIVERSITY.
6 . each time you change the source code you need to re-compile before re-simulating. it is simulated the compiled internal format. Udaipur Lab Manual Department of E & C Engineering MODEL SIM TUTORIAL Step 1: Load ModelSim Using ModelSim to simulate VHDL files is a three step process: 1. Simulate the internal format by instantiating all the design modules and using a top level stimulus file to drive test signals onto the inputs of your design and inspecting the outputs. Hence.SIR PADAMPAT SINGHANIA UNIVERSITY. Compile the VHDL source code into an internal format that is ready for ModelSim to simulate. Edit the VHDL source code so that your design describes the item of hardware you are trying to model. The internal format is the low-level description of your design: it is important to note that VHDL isn't simulating your VHDL source code. 3. 2.
The next step is to either open an existing project or make a new one. Once you start ModelSim. the main window will appear. to do this you need to follow the steps on the online form which detail the sign-up and set-up process. 7 . There are three main parts to the main window which is tiled either vertically or horizontally depending on your preference. Udaipur Lab Manual Department of E & C Engineering The first step is to actually load the ModelSim software. Use the File\Open\Project menu item to open an existing project or File\New\Project to make a new one. The bottom or right pane is the command shell which is used to issue textual commands to ModelSim and where ModelSim prints out any errors. Step 2: Start or Load a Project ModelSim is project based in the sense that it likes you to work on VHDL files grouped into a collection called a project. The top or left pane is the project workspace which details the files and modules that are currently being edited or hand been compiled. At the top of the window is the third pane. a tool-bar which holds the command buttons that act as short cuts for actions such as compilation.SIR PADAMPAT SINGHANIA UNIVERSITY. warnings or output from your code.
SIR PADAMPAT SINGHANIA UNIVERSITY. 8 . Once the new. empty project is created you need to add new or existing VHDL files to it so you can work on them. Udaipur Lab Manual Department of E & C Engineering The first step in making a new project is to name both the project and the library associated with it. There are no rules about these names but it helps to call them something associated with what you are doing. The library for a project is simply where all the compiled modules are stored in the internal format by ModelSim so that it can simulate them. Use the File\Add To Project\New File menu item to add a new file or File\Add To Project\Existing File to add a file you have already. ModelSim will get confused ! The default file type tries to guess the type based on the extension of the file name. The type of the file you are adding should be a VHDL file: ModelSim can deal with other HDL like VHDL. if you add a VHDL file and then put VHDL source code in it.
This will allow you to edit the VHDL code. The name and type of the file are self-evident. a tick indicates the file was compiled and is ready for simulation. A question mark indicates that ModelSim currently has no compiled version of the file. 9 . Step 3: Edit and Compile the Design In order to edit the file and make the source code describe what you want it to. Udaipur Lab Manual Department of E & C Engineering After adding the source file. the project workspace includes this new item. right click on the file name in the project workspace and select Edit to open the editor window. a cross indicates that ModelSim tried to compile it but failed due to some errors. the status of the file refers to the compilation status. maybe a missing semicolon or something like this.SIR PADAMPAT SINGHANIA UNIVERSITY. Note that errors at this stage are syntactic errors. problems with the syntax of your source code.
Having started the compilation process. ModelSim will report and errors in the command window. In the event that there were compilation errors. Correct the errors by re-editing the source code and compile the file again. You can either compile lots of files at once or one at a time: either use the buttons from the tool-bar or the Compile menu item. 10 . In this case there were no errors and the file status indicates the file is ready for simulation.SIR PADAMPAT SINGHANIA UNIVERSITY. right click on the file name in the project workspace and select Compile\Compile Report to open a window which details where and why the errors occurred. Udaipur Lab Manual Department of E & C Engineering Once you are happy with the source code. you need to compile it into the ModelSim internal format ready for simulation.
After refreshing this entry by right clicking on it and selecting the Refresh menu item. you can move to the Library tab of the project workspace. Udaipur Lab Manual Department of E & C Engineering Once the file is ready for simulation. 11 . it should contain all the modules from your design: in this case the alu_cmp and alu_exe modules and the top level stimulus called alu_test.SIR PADAMPAT SINGHANIA UNIVERSITY. You should find an entry for the library which you named earlier.
Common errors at this point include connecting ports of modules together which are the wrong size or the wrong type. Recap on the lecture notes about the rules by which wire and reg connections can be use as input and output if in doubt.SIR PADAMPAT SINGHANIA UNIVERSITY. ModelSim proceeds to build the design and instantiate any modules that your selected module contains. misnaming ports or connecting them in the wrong order. Udaipur Lab Manual Department of E & C Engineering Step 4: Instantiate and Simulate the Design Having edited and compiled the VHDL source code. problems with the meaning of your source code. 12 . This is done by double clicking on the module name in the library. you are now ready to actually simulate the internal representation of your design that ModelSim has constructed. The next step is to ask ModelSim to take this internal representation and instantiate it ready for simulation. At this point you might find ModelSim issues more errors in the command window: these are semantic errors.
we use the wave window. Finally. This gives a list of all the inspectable signals within a given module.SIR PADAMPAT SINGHANIA UNIVERSITY. Select all the signals and use the Add\Wave\Selected Signals menu item to add them to the wave window. we are ready to simulate the design. Udaipur Lab Manual Department of E & C Engineering In this case there were no errors and ModelSim correctly instantiated the alu_cmp. First open the signals window using the View\Signals menu item. in order to inspect the signals being sent to and from our modules. 13 . alu_exe and alu_test modules.
The left hand pane holds the signal name and next to that the signal value at the current time: the yellow line on the actual waveform sets the current time. 14 . The wave window charts the value of signals within the design against time. and check if their behaviour matches what you expect. Udaipur Lab Manual Department of E & C Engineering When the wave window appears. This allows you inspect the value of various signals in relation to one another. it is empty because we have not yet started to run the design.SIR PADAMPAT SINGHANIA UNIVERSITY.
Now use the run button to start the simulation. At first. For example. Here we can see that the output signals from the alu_exe module match what we expect. 15 . the output is ten. the waveform may be too squashed up to see. Note that you can change the radix of the values in the wave window by right clicking on them and using the Radix menu item: this make interpreting binary values easier ! Also note that as well as the value bubbles. you need to issue more run commands. when the operator is set for addition and we feed in the values three and seven. red lines indicate undefined values while blue lines indicate high impedance values: seeing where and when these values occur can be vital in determining why a design doesn't work.SIR PADAMPAT SINGHANIA UNIVERSITY. Udaipur Lab Manual Department of E & C Engineering First. restart the simulation so we are sure that any residual state is cleared and we are starting afresh. ModelSim will simulate the circuit for a given time period and then break ready for more commands: if you want to continue simulation after this. Use the zoom tools and scrollbars to inspect the part of the waveform that is of interest.
SIR PADAMPAT SINGHANIA UNIVERSITY. Udaipur Lab Manual Department of E & C Engineering Finally. 16 . note that since we included a $monitor system task in our source code. This mirrors the output in the wave window and simply offers a faster way to inspect the values in a textual rather than graphical manner. ModelSim has also printed out various values for us in the command window.
SIR PADAMPAT SINGHANIA UNIVERSITY. Udaipur Lab Manual Department of E & C Engineering 17 .
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