ECE 270

Introduction to Digital System Design

2011 by D. G. Meyer

Lecture Summary Module 3-A

Combinational PLDs and ABEL Reference: Text (4th Ed.), pp. 237-255, 370-383; (3rd Ed.), pp. 249-263, 337-351 overview o PLD programmable logic device first were programmable logic arrays (PLAs) two-level, AND-OR, SoP limitations: inputs, outputs, P-terms both true and complemented version of each input available connections made by fuses (non-volatile memory cells) each AND gates inputs any subset of true/complemented input variables each OR gates inputs any subset of AND gate outputs special case of PLA is programmable array logic (PAL) fixed OR array (AND gates can not be shared) each output includes (inverting) tri-state buffer some pins may be used for either input or output (I/O pins) generic array logic (GAL) devices are basically PALs combinational PLDs focus on GAL devices o fixed OR array, with dedicated AND gates o macrocell associated with each output pins contains configuration logic o output polarity control allows 0s (OFF set) or 1s (ON set) of function to be selected, realizing either PoS or SoP form of equation o GALs are erasable and reprogrammable (EPLDs) o your digital parts kit contains three GAL devices: 16V8, 22V10, and 26V12 o a universal programmer is needed to erase and reprogram these devices GAL16V8 closeup o what part number indicates o block diagram o macrocell

ECE 270

Introduction to Digital System Design

2011 by D. G. Meyer

hardware description language o an HDL is a logic programming language (caution: not sequential in nature like a computer programming language, but rather a means of describing hardware design) o we will use the Advanced Boolean Expression Language (ABEL) as an introductory hardware description language o we will compile our ABEL programs using ispLever (software tool available from Lattice Semiconductor go to website to download trial version) ABEL o program contents documentation (e.g., comments) declarations of pins, inputs, outputs statements that specify logic functions (optionally) test vectors o program structure identifiers Module statement comments pin declarations, istype keyword Equations statement equations written like assignments, terminated by a semicolon Truth_Table statement Test_Vectors statement End statement o basic symbols used in formulating ABEL equations & AND # OR ! NOT $ XOR !$ XNOR = assignment
MODULE abel_ex

TITLE 'ABEL Combinational Example for GAL16V8' DECLARATIONS " Input pins A pin 2; B pin 3; C pin 4; D pin 5; " Output pins X pin 12 istype 'com'; Y pin 13 istype 'com'; Z pin 14 istype 'com'; EQUATIONS X = A&B # !C&D; Y = !B&D # !A&B&D; Z = A & !B&C&!D; END

ECE 270

Introduction to Digital System Design

2011 by D. G. Meyer

Lecture Summary Module 3-B

ispLever Demo Reference: ispLever On-Line Documentation detailed example - problem description (arbitrary uniformed grading hack or AUGH) o four input variables (E, R, S, T) o five output functions (A, B, C, D, F) o stick built (using SSI parts) vs. 16V8 PLD (programmed using ABEL)

E
0 4

E
12 8

B
1

A A A C

A
13

B B

T T

D D C R

A A C

15

11

F
10

14

C R

1/4 - 7402

2/3 - 7404

1/3 - 7410 1/6 - 7404

1/2 - 7402 1/2 - 7400 1/4 - 7402

2/3 - 7410 1/4 - 7400

3/4 - 7400 5/6 - 7404 1 - 7402 1 - 7410 4 integrated circuits total

3

ECE 270

Introduction to Digital System Design

2011 by D. G. Meyer

Lecture Summary Module 3-C

Decoders Reference: Text (4th Ed.), pp. 384-398; (3rd Ed.), pp. 351-367 overview o definition decoder

o n-bit binary input code most common o 1-out-of-m output code most common (note: output code bits are mutually exclusive) o binary decoder: n to 2n (n-bit binary input code, 1-out-of-2n output code) example: generic 3-to-8 decoder (74x138)

Note: implied order of input variables is C B A, so a given output is a function F(C,B,A)

key observation #1: each output of an n to 2n binary decoder represents a minterm of an n-variable Boolean function; therefore, any arbitrary Boolen function of n-variables can be implemented with an n-input binary decoder by simply OR-ing the needed outputs key observation #2: if the decoder outputs are active low (e.g., 74x138 example above), a NAND gate can be used to OR the minterms of the function (representing its ON set) key observation #3: if the decoder outputs are active low (e.g., 74x138 example above), an AND gate can be used to OR the minterms of the complement function (representing its OFF set) key observation #4: a NAND gate (or AND gate) with at most 2n-1 inputs is needed to implement an arbitrary n-variable function using an n to 2n binary decoder (that has active low outputs, e.g., a 74x138) 4

ECE 270

Introduction to Digital System Design

2011 by D. G. Meyer

general circuit for implementing an arbitrary n-variable function using a decoder, for case where ON set has 2n-1 members
VCC

Z Y X

1 2 3 6 4 5

A B C G1 G2AN G2BN

Y 0N Y 1N Y 2N Y 3N Y 4N Y 5N Y 6N Y 7N

15 14 13 12 11 10 9 7

F(X,Y,Z)

question: how does circuit change if ON set has < 2n-1 members question: how does circuit change if ON set has > 2n-1 members? 16V8 realization of 74x138
MODULE dec138 TITLE '74x138 decoder implemented using 16V8' DECLARATIONS " Enable input pins G1 pin 1; !G2A pin 2; !G2B pin 3; " Select input pins C, B, A pin 4, 5, 6; " Output pins !Y0, !Y1, !Y2, !Y3, !Y4, !Y5, !Y6, !Y7 pin 19..12 istype 'com'; " Intermediate equation EN = G1 & G2A & G2B; EQUATIONS Y0 = EN & Y1 = EN & Y2 = EN & Y3 = EN & Y4 = EN & Y5 = EN & Y6 = EN & Y7 = EN & END

!C !C !C !C C C C C

& & & & & & & &

!B !B B B !B !B B B

& & & & & & & &

!A; A; !A; A; !A; A; !A; A;

special purpose decoders (e.g., 7-segment display) 5

ECE 270

Introduction to Digital System Design

2011 by D. G. Meyer

Lecture Summary Module 3-D

Encoders Reference: Text (4th Ed.), pp. 408-415; (3rd Ed.), pp. 376-383 overview o defn encoder: inverse decoder (i.e., role of inputs and outputs reversed) o example: 2n-to-n binary encoder o common application: encode device number associated with service request o problem: more than one device may be requesting service at a given instant motivation for priority encoder priority encoders o inputs are numbered, priority is assigned based on number (usually lowest number lowest priority, etc., but not always) o easiest way to do this in ABEL is with a truth table o example 8:3 priority encoder with strobe output (whats a strobe?)
MODULE TITLE pri_enc '8-to-3 Priority Encoder Using 16V8'

DECLARATIONS " Input pins I0..I7 pin;

"Input 0 - lowest priority, Input 7 highest

" Output pins E0..E2 pin istype 'com';

"E2 E1 E0 - encoded output

GS pin istype 'com'; "strobe output (asserted if any input asserted) " Short-hand for don't care X = .X.; TRUTH_TABLE ([I7,I6,I5,I4,I3,I2,I1,I0]->[E2,E1,E0,GS]) [ 0, 0, 0, 0, 0, 0, 0, 0]->[ 0, 0, 0, 0]; [ 0, 0, 0, 0, 0, 0, 0, 1]->[ 0, 0, 0, 1]; [ 0, 0, 0, 0, 0, 0, 1, X]->[ 0, 0, 1, 1]; [ 0, 0, 0, 0, 0, 1, X, X]->[ 0, 1, 0, 1]; [ 0, 0, 0, 0, 1, X, X, X]->[ 0, 1, 1, 1]; [ 0, 0, 0, 1, X, X, X, X]->[ 1, 0, 0, 1]; [ 0, 0, 1, X, X, X, X, X]->[ 1, 0, 1, 1]; [ 0, 1, X, X, X, X, X, X]->[ 1, 1, 0, 1]; [ 1, X, X, X, X, X, X, X]->[ 1, 1, 1, 1]; END

" " " " " " " " "

none active input 0 wins input 1 wins input 2 wins input 3 wins input 4 wins input 5 wins input 6 wins input 7 wins

ABEL-isms to note in this example: the dont care symbol ( .X. ), and how to define a substitute symbol (here, X); also note use of ranges to define the input and output pins. 6

ECE 270

Introduction to Digital System Design

2011 by D. G. Meyer

examine the reduced equation report produced by ispLever (CQ #1)

Title: 8-to-3 Priority Encoder Using 16V8 P-Terms --------4/4 4/3 4/1 8/1 ========= 20/9 Fan-in -----7 6 4 8 Fan-out ------1 1 1 1 Type ---Pin Pin Pin Pin Name (attributes) ----------------E0 E1 E2 GS 9 12 0 2

Best P-Term Total: Total Pins: Total Nodes: Average P-Term/Output:

Equations: E0 = (!I6 & !I4 & !I2 & I1 # !I6 & !I4 & I3 # !I6 & I5 # I7); E1 = (!I5 & !I4 & I2 # !I5 & !I4 & I3 # I6 # I7); E2 = (I4 # I5 # I6 # I7); GS = (I1 # I0 # I2 # I3 # I4 # I5 # I6 # I7); Reverse-Polarity Equations: !E0 = (!I7 & !I5 & !I3 & !I1 # !I7 & !I5 & !I3 & I2 # !I7 & !I5 & I4 # !I7 & I6); !E1 = (!I7 & !I6 & !I3 & !I2 # !I7 & !I6 & I4 # !I7 & !I6 & I5); !E2 = (!I7 & !I6 & !I5 & !I4); !GS = (!I7 & !I6 & !I5 & !I4 & !I3 & !I2 & !I1 & !I0);

example MSI encoder chip: 74x148 o similar to generic example (above), except all inputs and outputs are active low has EI input and EO output to facilitate daisy chaining multiple 148 chips 10-key pushbutton pad encoder (10:4) straight-forward extension of generic 8:3 encoder consider a different (4:2) priority encoder (CQ #2)
MODULE diff_pri TITLE 'Different Priority Encoder' DECLARATIONS A,B,C,D pin; E0..E1 pin istype 'com'; GS pin istype 'com'; X = .X.; TRUTH_TABLE ([ A, B, C, D]->[E1,E0,GS]) [ 0, 0, 0, 0]->[ 0, 0, 0]; [ 0, 0, 0, 1]->[ 1, 1, 1]; [ 0, 0, 1, X]->[ 1, 0, 1]; [ 0, 1, X, X]->[ 0, 1, 1]; [ 1, X, X, X]->[ 0, 0, 1]; END

ECE 270

Introduction to Digital System Design

2011 by D. G. Meyer

Lecture Summary Module 3-E

Tri-State Buffers Reference: Text (4th Ed.), pp. 418-427; (3rd Ed.), pp. 385-394 overview o capability tri-state buffer provides o basic variations inverting / non-inverting active high / low enable o note on propagation delay (and symbols used) goes in to Hi-Z state faster than comes out of Hi-Z (to driven) state, which helps prevent bus fighting

tpLZ tpHZ tpZL tpZH

o party line example note need for dead time to ensure that no bus fights occur

ECE 270

Introduction to Digital System Design

2011 by D. G. Meyer

bus o defn collection of signals with a common purpose shared among multiple entities example: address or data bus in a computer can be uni-directional or bi-directional o a bus transceiver contains pairs of buffers connected in opposite directions o examples: address bus and data bus in a computer

tri-state buffers in ABEL o attribute suffix .OE is used to denote the enable input for a tri-state buffer that outputs the named signal (signal.OE) o example 4:2 priority encoder with tri-state output control
MODULE TITLE prienc42 '4-to-2 Priority Encoder with Tri-State Enable'

DECLARATIONS " Input pins I0..I3 pin; " Input 0 - lowest priority, Input 3 - highest " Output pins E0..E1 pin istype 'com'; " E1 E0 - encoded output GS pin istype 'com'; " strobe output (asserted if any input asserted) EN pin; " tri-state enable control input " Short-hand for don't care X = .X.; TRUTH_TABLE ([I3,I2,I1,I0]->[E1,E0,GS]) [ 0, 0, 0, 0]->[ 0, 0, 0]; [ 0, 0, 0, 1]->[ 0, 0, 1]; [ 0, 0, 1, X]->[ 0, 1, 1]; [ 0, 1, X, X]->[ 1, 0, 1]; [ 1, X, X, X]->[ 1, 1, 1]; EQUATIONS [E0..E1].OE = EN; END

" " " " "

no inputs active input 0 wins input 1 wins input 2 wins input 3 wins

ECE 270

Introduction to Digital System Design

2011 by D. G. Meyer

Lecture Summary Module 3-F

Multiplexers Reference: Text (4th Ed.), pp. 432-443; (3rd Ed.), pp. 398-409 overview o defn multiplexer (mux): a digital switch that uses n select lines to determine which of 2n inputs is connected to its output o equation implemented by n-select line mux is the SoP form of a general n-variable Boolen function: F(X,Y) = a0XY + a1XY + a2XY + a3XY o Q: how many different functions of n variables are possible?

X Y F(X,Y) 0 0 0 1 1 0 1 1 a0 a1 a2 a3 D0 D1 D2 D3

F(X,Y)

i1 i0
Functional values assigned to each combination

X Y

MODULE mux811 TITLE '8-to-1 Mux (74x151) DECLARATIONS " Data inputs D0..D7 pin 1..8; " Enable EN pin 9; " Select lines S0..S2 pin 11..13; " Outputs Y pin 14 istype com; Y_L pin 15 istype com; EQUATIONS Y = EN & (!S2&!S1&!S0&D0 # !S2&!S1& S0&D1 # !S2& S1&!S0&D2 # !S2& S1& S0&D3 # S2&!S1&!S0&D4 # S2&!S1& S0&D5 # S2& S1&!S0&D6 # S2& S1& S0&D7); Y_L = !Y; END

representative 8:1 MSI multiplexer (74x151)

10

ECE 270

Introduction to Digital System Design

2011 by D. G. Meyer

example implementing an arbitrary function using a 74x151 (8:1) mux

VCC

F(C,B,A)
4 3 2 1 15 14 13 12 11 10 9 7 D0 D1 D2 D3 D4 D5 D6 D7 A B C G W Y 6 5

Determine the switches that should be closed to implement the function F(C,B,A) = CA + C(AB)

de-multiplexer: an inverse multiplexer (essentially the same as a decoder with an enable) multiplexer functionality expressed in ABEL (8-bit wide 4:1 mux example)
MODULE mux418a TITLE '4-to-1 X 8-bit Multiplexer' DECLARATIONS EN pin; " output enable control line S0..S1 pin; " select inputs " 8-bit input buses A0..A7, B0..B7, C0..C7, D0..D7 pin; " 8-bit output bus Y0..Y7 pin istype com; " A B C D Y Sets = [A0..A7]; = [B0..B7]; = [C0..C7]; = [D0..D7]; = [Y0..Y7]; MODULE mux418b TITLE '4-to-1 X 8-bit Multiplexer' DECLARATIONS EN pin; " output enable control line S0..S1 pin; " select inputs " 8-bit input buses A0..A7, B0..B7, C0..C7, D0..D7 pin; " 8-bit output bus Y0..Y7 pin istype com; " Sets SEL = {S1..S0]; A = [A0..A7]; B = [B0..B7]; C = [C0..C7]; D = [D0..D7]; Y = [Y0..Y7]; EQUATIONS Y.OE = EN; WHEN (SEL == 0) THEN ELSE WHEN (SEL == 1) ELSE WHEN (SEL == 2) ELSE WHEN (SEL == 3) END

EQUATIONS Y.OE = EN; Y = !S1&!S0&A # !S1&S0&B # S1&!S0&C # S1&S0&D; END

Y = A; THEN Y = B; THEN Y = C; THEN Y = D;

11

ECE 270

Introduction to Digital System Design

2011 by D. G. Meyer

Lecture Summary Module 3-G

XOR/XNOR Functions Reference: Text (4th Ed.), pp. 447-452; (3rd Ed.), pp. 410-417 overview o most PLDs have little capability of realizing XOR functions directly o an n-input XOR function would require 2n-1 product terms to realize o recall that ABEL operator for XOR is $ example: bigxor o (total) product terms required for realization ___ o ability to fit in a small PLD like a 16V8 ___
MODULE bigxor TITLE '9-input XOR Function' DECLARATIONS A,B,C,D,E,F,G,H,I pin; XOUT pin istype 'com'; EQUATIONS XOUT = A $ B $ C $ D $ E $ F $ G $ H $ I; END

example: treexor o ability to fit in a small PLD like a 16V8 ___ o product terms required for each expression (macrocell) ___ o impact on propagation delay ___
MODULE treexor TITLE 'Tree XOR' DECLARATIONS A,B,C,D,E,F,G,H,I,J,K,L pin; T1..T3 pin istype 'com'; XOUT pin istype 'com'; EQUATIONS T1 = A $ B $ C $ D; T2 = E $ F $ G $ H; T3 = I $ J $ K $ L; XOUT = T1 $ T2 $ T3; END

12