Experiment 2: The Design, Fabrication and Testing of Analog IC Amplifiers ECSE 434

PRELAB NOTES • This lab is divided into two parts: the first part involves the design of an integrated differential pair, and the layout of the differential amplifier and output stage. The output stage does not need to be designed in the layout phase. However, it must be laid out with the differential amplifier, as it will later be designed to meet given specifications after the chip is fabricated. In the first part, the output stage will be tested with provided sample component values. The second part will include the completion of the output stage design, buffer stage, and the testing of the fabricated chip.

NOTES • • • • Get your equipment and components from the parts-master in the Trottier building. Ensure that the components you design for are available from the parts-master. It is suggested to assemble some of the circuit components prior to entering the laboratory to save time. Do not rely on the signal generator amplitude readouts, measure your inputs manually with the oscilloscope. When writing the report, make sure to include the following where possible: o hand calculations o simulation results Comparing both and an explanation of your observations in the discussion will help validate your experimental findings. Comment on plots you include.

Plagiarism will NOT be tolerated.

because of the high gain of the differential amplifier. To reduce noise in the circuit. for final testing they should be replaced by fixed resistors. should be supported by calculations and/or simulations. Fabrication and Testing of Analog IC Amplifiers Some post chip fabrication tips You will be forced to use very small input voltages in this experiment.5) between each power supply and the CUT. ECSE 434 -2- .Experiment 2: The Design. This will eliminate many parasitic effects associated with potentiometers. • • • It is very important to compare your experimental results with your predictions (simulated and calculated) both in the lab and in your report. when very small input signals are needed. The following are suggestions to improve the quality of your results: • If required. This procedure will generate high noise levels so use it only if absolutely necessary. Keep the connection between the output of the filter and the CUT as short as possible. you may need to insert a lowpass LC pi-filter (Sedra and Smith section 12. Do this only if it produces a noticeable improvement in the signal-to-noise ratio (SNR). If the signal you are trying to measure is comparable in size to the external interference and to the internal noise of the oscilloscope (indicated by the thickness of the trace on the scope when set to its maximum sensitivity range). Plausible explanations must be given for the discrepancies and. Otherwise you may find that the signal amplitude control of your signal generator is too coarse. insert an op amp-based amplifier of known gain between the source and the oscilloscope. where possible. use a resistive voltage divider of known value between the signal generator and your Circuit Under Test (CUT). Although potentiometers may be used to trim the operating conditions.

the structure will be loaded with passive loads. The main objectives of this lab are hence to design and test some important building blocks used in analog IC amplifiers. An input amplifying stage.1 is a modular differential amplifier to be implemented using a bipolar IC technology. this is known as the main gain stage. If the off-chip interconnect scheme labeled ‘alpha’ in Figure 2. Q1 and Q2. Your design will be fabricated and the resulting chip will be returned to you. passive and active loads. Both loading schemes will be designed. and their advantages and disadvantages will be studied. ECSE 434 -3- . and to become familiar with modern analog IC design techniques.5 micron) BJT technology. Differential gain stage Vin+ VinBuffer stage Ouput stage RLoad Figure 1. the circuit in Figure 2. The purpose of this circuit is to provide the bulk of the gain of the amplifier. In an op-amp. which is a transistor/resistor array.1. the structure is loaded with an active load. This experiment is aimed at the creation of an integrated analog amplifier. The small size of integrated circuits makes them a necessity in all portable applications.1 investigates a Class AB output stage (details to be discussed later).1 is intended to study some important properties of differential amplifiers. current mirrors. using the Gennum GA911 (1.1 is used. a buffer interface stage and an output stage will be designed and interfaced in a feedback configuration to create a unity gain amplifier. The circuit in Figure 3. packaged in a 20 pin DIP casing for testing. This may require the use of frequency compensation techniques to perform in a stable manner.Experiment 2: The Design.1-Operational amplifier block diagram 2 DIFFERENTIAL AMPLIFIER The circuit shown in Figure 2. resulting in a simple operational amplifier (op-amp) as shown on Figure 1. Two interconnection schemes can be used once the chip is fabricated. You will design these circuits with the help of the CAD tool Electric. if the off-chip interconnect ‘beta’ scheme is used. and to understand the relationship between bias and signal conditions. Rpa and Rpb. On the other hand. These two circuits may be linked together via a simple interface circuit. Fabrication and Testing of Analog IC Amplifiers 1 INTRODUCTION Integration of analog circuitry is a crucial component in many cutting edge circuit designs nowadays. In particular.

.Differential amplifier with active/passive loads .Experiment 2: The Design. Fabrication and Testing of Analog IC Amplifiers VCC Q1 Rpa VaDOff-chip interconnect beta Off-chip interconnect alpha Q2 Rpb Off-chip interconnect alpha VaD+ Off-chip interconnect beta VoutDQ3 VoutD+ Q4 VinD+ VinD- R4 R1 VBias Q5 Q6 R5 VID R2 R3 VEE Represents one pin of the chip Figure 2. ECSE 434 -4- ..1.

Experiment 2: The Design.2.2 shows both possible circuit configurations that can be achieved with the different possible wiring schemes. VCC VCC Q1 VaDVoutDVinD+ Q3 VoutD+ Q2 VaD+ Rpa VaDVoutDVoutD+ Rpb VaD+ Q4 VinD- VinD+ Q3 Q4 VinD- R4 R1 VBias Q5 Q6 R5 R1 VID VBias Q5 R4 R5 VID Q6 R2 R3 R2 R3 VEE VEE (a) (b) Figure 2. Fabrication and Testing of Analog IC Amplifiers Figure 2.Two different possible amplifier configurations (a) with an active load (b) with a resistive load Table 2.Resistor components used Component Location Value R1 Off-chip R2 On-chip 2kΩ R3 On-chip 2kΩ R4 On-chip R5 On-chip Rpa Off-chip Rpb Off-chip ECSE 434 -5- .1.

Design the circuit of Figure 2. Determine the values of Rpa and Rpb keeping the values of R4 and R5 unchanged.1.5 2. Discuss.3 2.2(a) in order to obtain a gain of 250V/V ±10%. the input DC offset required to maximize the output swing.1. take into account the parasitic resistor and capacitor values of the oscilloscope (1 MΩ resistor in parallel considered before in parallel with a 20 pF capacitor). take into account the loading caused by the oscilloscope. and accompany both curves with the corresponding time domain waveform plot. take into account the parasitic resistor and capacitor values of the oscilloscope (1 MΩ resistor in parallel with a 20 pF capacitor). 2.Experiment 2: The Design. determine. Ensure that each pin of the chip is modeled as a 5pF parasitic capacitor to ground. which has a load resistance of 1MΩ. Use the models provided on the course website for the GA911 technology. Discuss.1. Determine the required value of R1.2 2.1.1 2. Ensure that each pin of the chip is modeled as a 5pF parasitic capacitor to ground. Fabrication and Testing of Analog IC Amplifiers 2.1. design the current source of the differential pair so that it sinks a current of 0.12 Find the input and output resistances of the two circuits.6 2. take into account the loading caused by the oscilloscope.1. Discuss the curve and maximal output swing. Considering this circuit will be used as a voltage gain stage in an operational amplifier.11 For both circuit setups.1. Design the circuit of Figure 2.1.4 PREPARATION Get familiar with Chapter 7 in Sedra and Smith (5th Edition).9 2. At the output (double-ended in this case).1 2. if any. 1 These power supply values will be used throughout the experiment. At the output.7 2.10 For both circuit setups.1. Also.8 2. Document the maximum output swing. 2. Also. what are the main characteristics that it must have? What is the purpose of R2 and R3? Using VEE = -5V and VCC=5V 1 . plot the differential mode frequency response and determine the 3-dB points. plot the common mode frequency response. For both circuit setups. Discuss. plot the source’s output current versus the output voltage and comment on the results.25mA.1.2(b) in order to obtain a single ended gain of 12V/V ±10%. Considering the current source only.1. Plot the voltage transfer characteristics of both circuits. Discuss. ECSE 434 -6- . which has a load resistance of 1MΩ. Determine the values of R4 and R5. Discuss. 2.1.

g. Fabrication and Testing of Analog IC Amplifiers 2. Make sure you are aware of which resistors are on-chip (hence part of the layout) or off-chip (to be connected later). Make sure to respect the design rules and specifications of the process. 2 Obtained using Electric schematic extraction.1. ECSE 434 -7- . Remember to document your layout for discussion in the report. PNP. Note the location of the substrate connections and observe device current and voltage ratings. VCC. Validate the layout by comparing the extracted schematic 2 with your original schematic (with no parasitics). e. This is especially important for traces where the currents will be higher.Experiment 2: The Design. and LNPN BJTs as well as the cross-unders and pads. 2. Failure to do so could result in a burnt out chip. what are the advantages and limitations of both circuit setups? 2. layout symmetry between both halves of a differential amplifier should be carefully enforced in order to preserve a high degree of balance in that stage. capacitors. Please study carefully the relation between the location of the different devices.1. NPN. VEE and VoutAB. diodes. The relation between the metal route width and its current carrying capacity should be noted and respected. Note the major features on the die.1.15 Layout the circuit using Electric. and making sure that the transient and frequency responses are identical. For example. Locate the resistors.14 Review the GA911 device layout of the standard 1x2 die (chip) supplied (check course’s web page).13 In summary. and your required circuit layout (using a single layer of metallization).

8 2. Measure the differential input resistance and the output resistance.2. Use the 10X probe.2.2.Experiment 2: The Design.2.9 3 4 To be started after the return of the fabricated chip. where possible. Determine the optimal input DC offset that results in a maximum output swing. What must you be careful about when doing the input resistance measurements.5 2.6 2. Measure the maximal output swing achieved.1 2. Ensure that you complete the experiment for both circuit topologies discussed in the preparation.4 2.2 Connect your chip according to the setup you have determined when laying it out.2.2.2.2 EXPERIMENT 3.4 For each of the differential setups perform the following in succession: 2. Plot the differential mode frequency response and find the 3-dB points.7 2. ECSE 434 -8- . compare with expected (simulations and calculations) values. Fabrication and Testing of Analog IC Amplifiers 2. Use the 10X probe. Determine the CMRR.2. compared to what was done in experiment 1? Can you suggest a practical method of measuring the common mode input resistance of the circuit? 2. As for all results in this experiment. and plot the output and input signals.3 2. Plot the voltage transfer characteristic of the circuit. Measure all DC voltages and infer the DC currents.2. You may trim the bias current slightly if you deem it necessary. Plot the common mode frequency response.

1-Class AB Output Stage The circuit shown in Figure 3. you will be familiar with the design of this stage. and you will be required to show your own design and analysis. while remaining linear for large input signals. VCC R6 VcAB RA VbAB RB VeAB Q7 Q9 Q11 LNPN VoutAB Q10 Q12 LNPN VinAB Q8 VrAB R7 VEE Figure 3. complete parts 3.Experiment 2: The Design. which are off-chip). and then work on the remaining parts of this section when the chip returns from fabrication. all you need to do is to include on-chip all the connections for the output stage (excluding all the resistors.1. It also features a built in gain that is provided by transistor Q8. and uses a VBE multiplier circuit to bias the output transistor pairs correctly.1. Fabrication and Testing of Analog IC Amplifiers 3 CLASS AB OUTPUT STAGE Note: For the initial chip submission. you will be able to follow the remaining part of this section. Therefore. ECSE 434 -9- .1 is a quasi-complementary (uses a compound PNP-NPN) Class AB output stage.3. By that time.1 to 3. By the time the chips come back. which is designed to provide high currents to a small output load.

2-Modified (Class B) Output Stage 5 Designed for after chip fabrication. the circuit becomes a Class B output stage.Resistor components used Component Location Value 5 R6 Off-chip R7 Off-chip RA Off-chip RB Off-chip If the VBE multiplier is shorted. as shown in Figure 3. Fabrication and Testing of Analog IC Amplifiers Table 3. ECSE 434 -10- .2.1.Experiment 2: The Design. VCC VCC R6 Q9 Q11 LNPN Q8 Q10 R7 Q12 LNPN VEE VEE Figure 3.

3 needs to be used.2 Plot the voltage transfer characteristic.1.Experiment 2: The Design. 3. Make sure that this configuration provides a gain of 10V/V and can provide a 6Vp-p output to a 330Ω load. the biasing stage in Figure 3. Other biasing approach will be used later when the circuit will be incorporated with the differential amplifier.1.82k ECSE 434 -11- . use the resistor values provided in Table 3.1.2 are necessary to test the circuit in Figure 3.1 Plot the frequency response of the circuit. Fabrication and Testing of Analog IC Amplifiers VCC Rbias1 Vin 1μF Rbias2 Vout VEE Figure 3. To do this.Sample resistor components to test output stage layout Component Value R6 R7 RA RB Rbias1 Rbias2 10kΩ 820Ω 32kΩ 18kΩ 100k 12.1.3-Input biasing network used for standalone output stage testing Figure 3.2.3 shows the biasing circuit you will need to use when testing the output stage as a standalone circuit.1and 3. Table 3. Remember that when the circuit is tested alone.2.1 and provide a validation for your layout before your final design.1 PREPARATION Sections 3. 3. Do not include parasitics. 3. and then perform a transient analysis. Do not use these values for the final design when the chip is fabricated.

3.Experiment 2: The Design. Check that the following specifications are met: the quiescent current (zero input signal) is 0. Remember to include 5pF parasitic capacitors to ground for each pin. what are the main characteristics that it must have? Design the Class AB output stage circuit in Figure 3.1.1.4 3.10 Plot the voltage transfer characteristic of both circuits.6. Considering this circuit will be used as an output stage in an operational amplifier. and the output stage provides a unloaded (disconnected load) gain of 10V/V.8 3. Similarly to 3.1.1.1.3 needs to be used.1. and the output stage provides an unloaded gain of 10V/V. and that the output stage is capable of supplying 6Vp-p to a 330Ω load without significant distortion.13 What is the purpose of transistor Q12? ECSE 434 -12- . and account for the parasitics of the oscilloscope. 3.1 using Electric.5 3. Determine the input resistance of both circuits. Use the same biasing arrangement as that of the Class AB setup. Remember to document your layout for discussion in the report. what are the advantages and limitations of both circuit setups investigated? 3. Comment on how it is different to a small-signal amplifier. Plot the frequency response of both circuits and comment.1.7 3. Respect the design rules and specifications of the process. Make sure all resistors are off-chip (to be connected later).1.9 3. Document the maximal output range. and then perform a transient analysis of both designed circuits.6 Get familiar with chapter 14 in Sedra and Smith (5th Edition). Make sure that they are identical.1.11 Determine the projected size of the dead band zone of the Class B stage.2 to fulfill the following specifications: the output stage is capable of supplying 6Vp-p to a 330Ω load. Remember that when the circuit is tested alone.1.1. and compare it to simulation results by looking at the voltage transfer characteristic plot. the biasing stage in Figure 3.12 In summary. Validate the layout by comparing the transient and frequency responses of both the extracted schematic and the original schematic.1. Fabrication and Testing of Analog IC Amplifiers 3. design the Class B output stage in Figure 3.3 Layout the circuit shown in Figure 3. 3.5mA.1. The following sections are to be completed after the appropriate material on output stages is covered/reviewed in class: 3.

compare with expected (simulations and calculations) values. Plot the voltage transfer characteristic of the circuit.4 3. Comment on the output and maximum output range. Measure the input resistance of the circuit.2 Connect your chip according to the setup you have determined when laying it out.1.14 What are the advantages and disadvantages of having an internal gain to the Class AB output stage. You may have to combine several resistors in parallel to meet the power dissipation specifications for the load. Use the 10X probe. Plot the frequency response and find the 3-dB points. Plot the transient response for a 6Vp-p output.2. These may be suppressed by inserting a small inductance in series with the load. For the Class AB stage only. Make sure to comment on the reasons of the discrepancy and why this correction is important both on the local output stage level. compared to having the bulk of the gain provided only by the differential pair? 3. Fabrication and Testing of Analog IC Amplifiers 3.2. As for all results in this experiment.1 3. observe the maximum power ratings of the transistors and set the current limits on the DC supply accordingly.2. perform the following in succession with a 330Ω load: 3.2.5 3.6 3.2. The load of any circuit must have the capacity to dissipate the ‘maximum’ expected output power. Measure all DC voltages and infer the DC currents where possible. For each of the Class B and Class AB output stage circuits.3 3.Experiment 2: The Design. Most resistors in the labs are rated at 250mW at 25ºC. 3.2. make note of the output DC offset with no input signal. and then on the operational amplifier level.7 ECSE 434 -13- . and trim the resistors in the VBE multiplier to make the offset be as close to 0V as possible (within 10mV). You may observe high frequency oscillations in the output signal due to capacitive loading.2 EXPERIMENT Note: To avoid damage.2.

Experiment 2: The Design. In this section. or buffer circuit. the output stage will not require the input biasing circuit of Figure 3. Fabrication and Testing of Analog IC Amplifiers 4 BUFFER STAGE6 As shown in Figure 1.1. Notice that. both circuits designed need to be interfaced for correct operation by some kind of an interface circuit.3. Note: The active load amplifier and Class AB output stage will be used for the combination throughout the rest of the experiment. you must design an off-chip transistor based circuit which will accomplish this function. ECSE 434 -14- . The purpose of this circuit is to ensure minimal loading of the gain stage and proper DC biasing of both stages. thanks to this circuit. The latter is particularly important as the DC level of the gain stage’s output and the output stage’s input must be kept the same as when they were tested individually. 6 To be completed after chip fabrication.

4.2. Comment of the advantages and disadvantages of your design.1 Measure all DC voltages and infer the DC currents where possible. Based on the design specifications you have decided upon. output resistance. Plot the time domain output of the circuit to an input which is comparable to the maximum expected differential amplifier output. Plot the voltage transfer curve of the circuit. create a circuit capable of meeting these specs and. you can use a biasing network similar to Figure 3.1. Determine the component values and explain the functioning of your interface circuit. Determine the input and output resistances of the circuit.1 4. Plot the frequency response of the circuit. Plot the frequency response and find the 3-dB points. Use the 10X probe.Experiment 2: The Design. input maximal swing.2 For this section.3 to test the circuit standalone. Provide a schematic of the design. Plot the time domain output of the circuit to an input which is comparable to the maximum expected differential amplifier output. Plot the voltage transfer characteristic of the circuit.3 4. Be sure to have a logical reasoning as to why each specification you decide upon is required.1.1.6 4.2. As for all results in this experiment.2 4.5 ECSE 434 -15- .1. input DC insensitivity. Some common design specifications are: Bandwidth. EXPERIMENT 4. Document the maximal output and input ranges.2.2. gain. if necessary. 4.1 PREPARATION Determine the design specifications of the circuit which you believe are required for proper operation of the operational amplifier. Document the maximal output and input ranges. compare with expected (simulations and calculations) values.3 4. and output maximal swing.2 4.4 4.5 4. modify the specifications slightly if you deem them ultimately unattainable.7 4. Ensure that the parasitic capacitors are accounted for.1. Measure the output and input resistances of your circuit.4 4. input resistance.1.2.1. Fabrication and Testing of Analog IC Amplifiers 4.

1. Hint: Remember that. compensate the circuit to yield a minimum phase margin of 25º. Make sure that the DC point at the output is 0V. ECSE 434 -16- . Ensure that the combination of the circuits yields the expected results from Spice simulations. determine where a compensating capacitor could be added to increase the phase margin of the circuit.1. the buffer stage and the Class AB output stage will be combined as shown in Figure 1. and maximal input and output ranges. and finally. Place the circuit in a unity gain feedback topology. the circuit will be used in a closed-loop feedback configuration.5 5. in its simplest form.4 5. By examining the circuit diagram.6 Vout Vin + RLoad Figure 5.1 5. 5. If needed.Experiment 2: The Design. compensation will be performed if needed. the active load differential amplifier.1 in order to yield an operational amplifier with an open-loop gain of around 2500V/V. and Class AB output stage together and load them with a 330Ω resistor. Document the frequency response.2 PREPARATION Get familiar with Chapter 8 in Sedra and Smith (5th Edition). Combine the active load differential amplifier.1.1-Unity gain feedback amplifier 7 To be completed after chip fabrication.1. Why is that critical in the context of feedback? Ensure that the parasitic capacitors are still accounted for.1.1. Determine the phase margin of the circuit. compensating is equivalent to slowing down a circuit’s frequency response to increase its phase margin. voltage transfer characteristic. as shown on Figure 5. buffer stage. gain. 5.1. Make sure you have correctly labeled the positive and negative ports of your circuit to ensure negative feedback is applied. You may use which ever compensating method you deem reasonable. the amplifier’s stability will be investigated. Fabrication and Testing of Analog IC Amplifiers 5 OPERATIONAL AMPLIFIER7 In this section.1 5.3 5. Also.

Connect the circuit in unity gain configuration and repeat steps 5.10 What are the advantages and disadvantages of feedback in this case? 5.5 5.1. Plot the frequency response and voltage transfer characteristic of this circuit. and maximal input and output ranges.2. Design a non-inverting feedback amplifier which provides a gain of 150V/V. time response.2. Measure the maximal input and output ranges of the circuit.2 5.2.2. 5.9 5. Implement your non-inverting amplifier design and plot the time domain output corresponding to an input of your choosing.7 Load the circuit with a 330Ω resistor. Provide a schematic of the design. Plot the frequency response.2.8 5. Do not assume the open-loop gain to be infinite in this case.2. gain.5. comment on the performance of the circuit compared to the open-loop amplifier. Plot a time response of the input and output.1 to 5.6 5.2. Document the frequency response. Comment on the effect of the feedback loop on the characteristics of the amplifier. Mainly. Measure the input resistance of the circuit.Experiment 2: The Design. voltage transfer characteristic. Fabrication and Testing of Analog IC Amplifiers 5. comment on the bandwidth. and input resistance.2 5.4 5.2. 5.1. Plot the circuit’s voltage transfer characteristic.1.7 EXPERIMENT Combine the circuits together and plot the frequency response using the 10X probe and find the 3-dB points.2.1. Hint: You may decouple the load with a capacitor if you have problems. Based on experimental results. and voltage transfer characteristic of this design. but use your measured open loop gain value.8 ECSE 434 -17- .3 5.2.1 5. time response.