You are on page 1of 63


There is an increasing demand for power electronics having reduced size, weight, and cost, as well as improved dynamic performance. Passive components (inductors and capacitors) typically dominate the size and weight of a power converter. Increased switching frequency leads to a reduction in the required energy storage and permits use of smaller passive components. Furthermore, higher frequency can substantially improve transient performance and control bandwidth. Sufficiently high frequencies permit the use of air-core magnetics, paving the way toward fully integrated power converters.

Thus, many benefits can be realized by operating power converters at greatly increased switching frequencies if loss, efficiency, and control challenges can be addressed.

Soft switched resonant dcdc power converters are able to maintain high efficiency at increased switching frequency. The nature of resonant operation, however, typically imposes high device stresses. Furthermore, it is often difficult to maintain high efficiency over a wide load range with resonant converters.

This paper introduces a resonant boost converter topology and control method suitable for designs at VHF, 30300 MHz The topology provides low transistor voltage stress, and requires small passive components, allowing for small size and very fast transient response. Moreover, the design maintains high efficiency across a wide load range, from at least 5% to 100% of full load. It presents the new topology and discusses its design and operation.

Two low-loss resonant gate drive schemes suitable for this topology are also detailed, followed by an explanation of the converter control method in. It also represents the design and experimental validation of two converters implementing the approach.

The first is a 110-MHz, 23-W converter based on a high-performance RF lateral doublediffused MOSFET (LDMOSFET). The second is a 50-MHz, 17-W design using an LDMOSFET implemented in a 50-V integrated power process.


Figure 1.1 Crystal equivalent Circuit.

Figure 1.1 shows the crystal equivalent circuit. R is the effective series resistance, L and C are the motional inductance and capacitance of the crystal. CP is the shunt capacitance due to the crystal electrodes. Figure 1.2 shows the reactance frequency plot of the crystal. When a crystal is operating at series resonance it looks purely resistive and the reactance of the inductor and the capacitor are equal (XL = XC). The series resonance frequency is given by the equation

eqn (1.1)

When the crystal is operating in parallel resonant mode it looks inductive. The frequency of operation in this mode is defined by the load on the crystal. The crystal manufacturer should specify the load capacitance CL for parallel resonant crystals. In this mode the frequency of oscillation is given by the equation.

eqn (1.2)

In parallel resonance mode the crystal can be made to oscillate anywhere on the fs - fa slope of the reactance plot, shown in Figure 1.2, by varying the load of the crystal. All of MXCOMs crystal oscillator circuits recommend using parallel resonant mode crystals.

Figure 1.2 Reactance Vs Frequency plot of a crystal

Figure 1.3 shows the recommended Crystal oscillator circuit diagram. In this type of setup the crystal is expected to oscillate in parallel resonant mode. The inverter which is internal to the chip acts as class AB amplifier and provides approximately 180 phase shift from input to the output and the p network formed by the crystal, R1, C1 and C2 provides additional 180 phase shift. So the total phase shift around the loop is 360. This satisfies one of the conditions required to sustain oscillation.

The other condition, for proper startup and sustaining oscillation is the closed loop gain should be 1. The resistor Rf around the inverter provides negative feedback and sets the bias point of the inverter near mid-supply operating the inverter in the high gain linear region. The value of this resistor is high, usually in the range of a 500KW ~2MW. Some of MXCOMs ICs have this resistor internal, refer to the external component specifications in the data sheet of a particular chip.

Figure 1.3 Crystal oscillator circuit

The capacitors C1 and C2 form the load capacitance for the crystal. The optimum load capacitance (CL) for a given crystal is specified by the crystal manufacturer. The equation to calculate the values of C1 and C2 is eqn (1.3)

Where CS is the stray capacitance on the printed circuit board, typically a value of 5pf can be used for calculation purposes. Now C1 and C2 can be selected to satisfy the above equation. Usually C1 and C2 are selected such that they are approximately equal. Large values of C1 and/or C2 increases frequency stability but decreases loop gain and may cause start-up problems. R1 is the drive limiting resistor, the primary function of this resistor is to limit the output of the inverter so that the crystal is not over driven. R1 and C1 form a voltage dividing circuit, the values of these components are chosen in such a way that the output of the inverter goes close to rail-to-rail and the input to the crystal is 60% of rail-to-rail, usual practice is to make resistance

of R1 and reactance of C1 equal at the operating frequency, i.e. R1 XC1. This makes the input to the crystal half that of the inverter output. Always make sure that the power dissipated by the crystal is with-in the crystal manufacturers specifications.

Over-driving the crystal may damage the crystal. Please refer to the crystal manufacturers recommendations. Ideally the inverter provides 180 phase shift, but the inherent delay of the inverter provides additional phase shift proportional to the delay. In order to ensure the total phase shift of n360 around the loop, the p network should provide 180 less the phase shift due to the inverter delay. R1 can be varied to accomplish this. With fixed C1 and C2, the closed loop gain and phase can be altered by varying R1. In some applications R1 can be ignored if the above two conditions are met. Some ICs have all the external components (Rf, R1, C1, and C2) internal to the chip, thus eliminating worries to the circuit designer. In this case simply connect the crystal across the XTAL and XTAL pins.

1.2 HINTS:

Select a crystal with low effective series resistance (ESR), which helps with crystal startup problems. Lower ESR increases the loop gain. Reduce the stray capacitance on the board layout by shortening the traces. This would help with startup problem and as well as the frequency of oscillation. Always test the circuit in applicable temperature and voltage ranges to ensure the crystal starts and sustains oscillations and tweak the component values if necessary. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of Vdd, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain further crystal oscillator design assistance, consult your crystal manufacturer.

The recommended way to optimize R1 is first calculate C1 and C2 as explained earlier and connect a potentiometer in place of R1, set its initial setting at approximately equal to XC1, then vary the potentiometer setting if required until the crystal starts under all conditions and sustains oscillation under steady state condition.


1.3.1 INTRODUCTION Figure 1 shows a block diagram of the RF components in the GBT RFI monitor station as planned when this document was written. The station includes up to four, two-axis Yaesu antenna positioners, -ve RF transfer switches for filter in/out selections, and two SP5T RF switches for antenna selection in each of two RF signal paths back to the lab via optical fiber. The positioners and switches are controlled remotely using a 40-pin Microchip 16F877A microcontroller at the monitor station that receives commands via RS232 and translates them into hardware control logic. The microcontroller connections to the modules that it controls in the monitor station are shown in Figure 2. This note describes the conventions adopted for the microcontroller and its connections to the hardware to be used in writing the microcontroller assembly language program.

The microcontroller clock is generated by an external 10-MHz crystal. This produces a single instruction cycle time of 0.4 microseconds. The program ash memory can be programmed in the circuit through pins 36, 39, and 40 using the CCS ICD-S40 in-circuit programmer. Interface to the RS232 serial line is via a DS14C232 IC, shown in Figure 3, which converts RS232 logic voltage levels to TTL levels accepted by the 877A. In this application the RS232 signal will be carried on a multi-mode optical fiber by way of an RS232 optical modem. At the lab end of this fiber will be a PC that sends commands to and receives monitor information from the 877A.

The four antenna positioners have a common interface to the 877A as shown in Figure 4. This module is connected to the six most significant bits of register port RD. One of the four positioners is controlled by putting its address on lines A0 and A1, and up/down or CW/CCW motion is commanded by pulling one of the U, D, C, or CC lines low. The azimuth and elevation positions are read by 877A A/D converters AN0 and AN1, respectively. Each of the -ve filter selection transfer switches is controlled with a single bit in port resister RB. Each of the two SP5T RF switches is controlled with three bits in port register RC, where the three bits form an address to one of the -ve switch positions.

Figure 1.4 RF components block diagram of the full GBT RFI Monitors station as planned

Figure 1.5 Schematic diagram of microcontroller connections to the antenna positioners and RF switches that it controls


Figure 1.6 Schematic diagram of RS232 interface circuit

Figure 1.7 Schematic diagram of the control connections to the four antenna positioner circuits



Up to four, two-axis positioner control circuits may be attached to the microcontroller. The control and position readout lines are tied in parallel and the active controller is selected with two address bits, A0 and A1. The Yaesu control box has four control pins on its remote control connector, one for each motion of up, down, clockwise, or counter-clockwise. The selected motion is activated by shorting the appropriate pin to the common pin on this connector.

The Yaesu control line requires about 8 milliamps of sinking current at +13 volts. In the parallel connection shown, the HSR312 is capable of sinking 320 milliamps with a resistance of 3 ohms. The HSR312 is an opto-isolator whose photodiode requires at least 3 milliamps of drive current with a forward voltage of 1.3 volts to turn the switch on. About 5 milliamps of current is supplied by a 2N3094 transistor to minimize the current required from the open-collector 74LS05 logic chip in the 'switch 0' state. The Yaesu control box remote control connector also contains two pins that supply voltages that are proportional to the angular position of the two axes.

The voltage range is 0 to +5 volts with a supply impedance of about 250 ohms. Two of the HSR312 solid state relays are used to connect these monitor pins to the microcontroller A/D converters when the positioner is selected. In the '0' state the HSR3123 leakage current is less than 1 micro amp, which should not affect the accuracy of the selected positioner readout.


The switch is connected so that the filter is in the signal path between ports 2 and 4. When the switch is in position 1 the signal passes from port 1 to port 3, and the filter is shorted. In position 2 the signal passes from port 1 to port 2, through the filter to port 4, then back to port 3. Since the relay latches, no current is drawn except during the switching operation.



The control circuit for each of the two SP5T RF switches that select the antenna to be connected to the signal line to the lab. These switches are Ducommun-Technologies model 5SS2P12. Each switch position requires 135 milliamps of current at -28 volts to close. Only one position should be closed at a time. A 74LA139 decoder IC and a 74LS20 4-input NAND gate are used to activate one of the -ve switch relays according to the selected 3-bit address on the 74LS139 chip. The HSR312 solid state relay is used to supply current to the selected relay as described in Section 2.


Commands to the PIC16F877A microcontroller are received by its serial port with be ASCII character packets terminated by a carriage return character (hex 0D).

For example, to drive positioner 2 to an elevation where the A/D reading is decimal 856, first, select the positioner with the command P2, and then send the command E0856. The calibration of A/D readings in terms of azimuth and elevation in degrees will be the responsibility of the PC sending the commands. The full range of 10-bit A/D readings will be used since this range corresponds to the positioner read-out of about 0 to 5 volts. If a command outside of the available range is issued, the positioner will run to the limit of its motion in that direction and stop.

A new position command will cancel any motion currently in progress from a previous command, if that commanded position had not been reached. The PIC16F877A microcontroller will continuously send position data for the currently selected positioner to the PC approximately once per half second. Each command is echoed by the microcontroller. If an unknown commend is received, a 'U' message will be sent by the 877A. If two commands are received too quickly for the first one to be processed, a missed command 'M', will be sent by the microcontroller.



Figure below shows a schematic of the new resonant boost dcdc converter topology. The design is optimized for low device voltage stress and VHF operation at a fixed frequency and duty ratio. This enables the use of resonant gating and zero-voltage switching for high efficiency. The output is regulated by ONOFF control of the converter (also sometimes called burst-mode control or cell modulation control). The converter can be viewed as a special version of the Class- inverter coupled with a resonant rectifier, as illustrated in Figure. Here, we treat the design of each of the inverter and the rectifier, and then address their interconnection.

Figure 1.8 Schematic of the proposed resonant boost converter topology.


The multi-resonant network comprising LF, L2F, CF, and C2F is a low-order network designed to approximate the symmetrizing properties of a quarter-wave transmission line. This network is tuned to achieve zero-voltage switching while simultaneously maintaining low device voltage stress. In particular, the drain to source voltage is shaped to approximate a quasi-square or trapezoidal waveform. This reduces peak voltage stress across the switch Smain to as low as


two times the input voltage as compared to other single-switch inverters such as the class-E inverter that has a peak voltage stress of 3.6 times the input voltage.

Figure 1.9 Schematic of rectifier implemented in SPICE for design purposes. To accomplish this, the components LF, L2F, CF, and C2F are chosen in the following manner. L2F and C2F are tuned to resonate near the second harmonic of the switching frequency fs to present a low drain to source impedance at the second harmonic. In addition, the components LF and CF are tuned in conjunction with L2F and C2F and the load impedance to present a high drain to source impedance near the fundamental and third harmonic of fs . The relative impedance between the fundamental and third harmonic can be adjusted to shape the drain to source voltage to approximate a square wave, an effective means to limit the peak switch voltage stress to as low as two times the input voltage.

A complete discussion of the tuning methodology for these components is found in. It is worth reiterating here that LF, L2F, and C2F are all resonant elements, and can be selected relative to the component CF in a manner that permits the parasitic output capacitance of the switch to be fully absorbed by the multi-resonant network. Consequently, CF can comprise only the parasitic switch capacitance, or if so desired, can be augmented with an additional discrete capacitor in parallel with the switch.



The inverter is coupled to a resonant rectifier, as shown in the right-hand side of Fig. 1.8.This rectifier is similar to that described, albeit with somewhat different operating characteristics owing to our use of ONOFF control to regulate the output. The substitution of the properly tuned rectifier for the inverter load resistance can be accomplished with minimal effect on the inverter. The pairing is done in a way that allows dc power flow from input to output. Since the fraction of total power that is transferred at dc is subject to much lower loss in the switch or resonant elements than the ac portion, higher efficiency can be achieved as compared to a design that delivers all the power via ac coupling.

The resonant elements Lrect and Crect of Fig. 1.8 are chosen so that the rectifier delivers the desired power at the specified output voltage. In the rectifier topology presented, the parasitic capacitance of the diode is absorbed by Crect. The discrete capacitor Crect can, therefore, be reduced, and in some cases, completely eliminated, when all of the required capacitance is provided by the diode. This can be beneficial in avoiding ringing between Crect and the parasitic inductance of the diode package. However, when precise selection of the diodes die area is possible during design, reducing loss may prove an overriding concern. Optimal diode size depends on the distribution of loss between the diode forward drop and the circulating currents in the lossy diode capacitance.

Assuming the total capacitance across the diode is to be kept constant, increasing diode area decreases conduction loss, but causes an increasing fraction of the reverse current to be conducted through the diode capacitance. Since Crect will be almost lossless by comparison, scaling the diode area evinces a die size that yields minimum loss. Rectifier design proceeds by first creating a model for a simulation program such as SPICE.

A suitable model is detailed in Fig. 1.9 While the bulk of the circuit is clearly the righthand side of Fig. 1.8, the sources at the input and output are added. At the rectifier input, the two sources model the voltage produced by the inverter, i.e., that across the drainsource terminals of the switch. Under the assumption that nearly all the power is delivered at the fundamental and

dc, this voltage can be modeled by a sinusoidal source (with an amplitude equivalent to the fundamental of the inverter drainsource voltage) and a dc offset equal to VIN. These sources are designated by VF and VDC, respectively. The source at the output of the rectifier models the load. A constant voltage source is an appropriate representation when the output voltage is regulated by feedback, the intended control scheme for the converter. To improve the accuracy of the model as regards circuit dynamics and loss, several additional aspects of the main rectifier components are considered. The ESR of Lrect is added to better reflect loss, while inter-winding capacitance can generally be ignored, as the self-resonant frequencies of the inductors selected are typically a few orders of magnitude above the switching frequency.

For Crect, ESR may be ignored because the ceramic capacitors used in these prototypes have Qs over 1000 at the switching frequency. Series inductance, however, is of the order of 1 nH, and must be considered for an accurate reflection of rectifier dynamics. Finally, to capture the large-signal dynamic and loss performance of the diode, it is modeled as a forward drop, series resistance, and ideal diode. This is in parallel with a nonlinear capacitance with an ESR that reflects its lossy nature. Diode parameters are determined by measuring the capacitance under various values of reverse bias using an impedance analyzer. The resulting set of smallsignal data points is used to create a large-signal model. The forward characteristics of the diode can be measured by any number of techniques. Here, the forward drop was measured for a given drive current and junction temperature.

With a SPICE model, rectifier design could be accomplished in a trial and error sense by picking values for Lrect and Crect that result in the desired output power. However, a more convenient approach to selecting component values is to define an effective center frequency and characteristic impedance. First, the total capacitance in parallel with the diode is defined as Ctot = Crect + CD where CD is the diode parasitic capacitance. Then, the effective center frequency becomes eqn (1.4)


o = 1/ Lrect Ctot the characteristic impedance is

eqn (1.5)

ZO = Lrect /Ctot

eqn (1.6)

The center frequency, o, is used to establish resistive operation at a given rectifier input and output voltage, and the characteristic impedance ZO allows the output power to be set. This formulation is approximately orthogonal over a useful range of characteristic impedance, permitting one to easily tune the rectifier by sweeping O followed by ZO. In turn, knowing the desired values of O and ZO readily yields component values for Lrect and Crect . Typically, in-phase fundamental rectifier voltage and current corresponds to the best converter operating efficiency. This is not surprising as it minimizes the circulating currents for a given level of output power. Since the phase of the rectifier voltage and current changes as both the converter input voltage and output voltage change, some care must be taken in selecting O. Often the nominal operating point is a good choice. Then, when the converter is operating under its intended load and input voltage, high efficiency is achieved. However, another tuning point may be better to keep the efficiency above a minimum value over the entire operating range. This is easily accomplished by changing O. Any change in power level at the desired operating point can then be compensated with a change in ZO. It should be noted that finite diode capacitance places a lower bound on the value of Ctot, limiting both the center frequency and characteristic impedance. Using the ideas outlined earlier, a rectifier design can be realized fairly quickly. For a given input and output voltage, the values of the sources VF, VDC, and VL are determined. Using SPICE, O is swept until the rectifier voltage and current are in phase. Output power is then established by sweeping ZO. At this point, the rectifier will deliver the rated power into the load when a fundamental voltage of amplitude VF plus a dc-offset of value VDC appears at its input. This voltage is provided by the inverter.


1.4.3 CONVERTER REALIZATION To design the inverter, the ac and dc portions of the power delivered to the rectifier are treated independently. The inverter needs to deliver the required ac power into an equivalent resistance. This resistance is determined from the fundamental voltage and current at the rectifier input port 2. Once the inverter design is accomplished, connecting the inverter to the rectifier results in a total power that is typically close to the designed power. Any difference may be adjusted via the methods outlined. It is also possible to first design the inverter and then adjusts the rectifier parameters to match the inverter load. The result is a complete dcdc power stage.

Figure 1.10 Trapezoidal resonant gate drive circuit with self-oscillating network.

The converter is enabled by applying the voltage Vgate, and disabled by setting Vgate to zero. This gate driver is employed in the 110-MHz converter.



In this part, three topologies will be evaluated for front end DC/DC application. The major goal is to evaluate the performance of the converter with wide input range. For each topology, the switching frequency is designed at around 200 kHz.


The resonant inductor Lr and resonant capacitor Cr are in series. They form a series resonant tank. The resonant tank will then in series with the load. From this configuration, the resonant tank and the load act as a voltage divider. By changing the frequency of input voltage Va, the impedance of resonant tank will change. This impedance will divide the input voltage with load. Since it is a voltage divider, the DC gain of SRC is always lower than 1. At resonant frequency, the impedance of series resonant tank will be very small; all the input voltage will drop on the load. So for series resonant converter, the maximum gain happens at resonant frequency. For front end DC/DC application, a SRC is designed to meet the specifications with following parameters: Transformer turns ratio: 5:2, Resonant inductance: 37uH, Resonant capacitance: 17nF. With above parameters, the range of Q is from 6 (Full load) to 0 (No load). Operating region is on the right side of resonant frequency fr. This is because of zero voltage switching (ZVS) is preferred for this converter. When switching frequency is lower than resonant frequency, the converter will work under zero current switching (ZCS) condition. In fact, the rule is when the DC gain slope is negative; the converter is working under zero voltage switching condition. When the DC gain slop is positive, the converter will work under zero current switching condition. For power MOSFET, zero voltage switching is preferred. It can be seen from the operating region that at light load, the switching frequency need to increase to very high to keep output voltage regulated. This is a big problem for SRC. To regulate the output voltage at light load, some other control method has to be added.

At 300V input, the converter is working close to resonant frequency. As input voltage increases, the converter is working at higher frequency away from resonant frequency. As frequency increases, the impedance of the resonant tank is increased. This means more and more energy is circulating in the resonant tank instead of transferred to output. From simulation waveforms, at 300V input, the circulating energy is much smaller than 400V input situation. Here the circulating energy is defined as the energy send back to input source in each switching cycle. The more energy is sending back to the source during each switching cycle, the higher the energy needs to be processed by the semiconductors, the higher the conduction loss. Also from the MOSFET current we can see that the turn off current is much smaller in 300V input. When input voltage increases to 400V, the turn off current is more than 10A, which is around the same level as PWM converter. With above analysis, we can see that SRC is not a good candidate for front end DC/DC converter. The major problems are: light load regulation, high circulating energy and turn off current at high input voltage condition.


For parallel resonant converter, the resonant tank is still in series. It is called parallel resonant converter because in this case the load is in parallel with the resonant capacitor. More accurately, this converter should be called series resonant converter with parallel load. Since transformer primary side is a capacitor, an inductor is added on the secondary side to math the impedance. The parameters of parallel resonant converter designed for front end DC/DC application are: Transformer turns ratio: 9:1, Resonant inductance: 58uH, Resonant capacitance: 11.7nF. With above parameters, the range of Q for this converter is 3 (Full load) to (No load). Similar to SRC, the operating region is also designed on the right hand side of resonant frequency to achieve Zero Voltage Switching. Compare with SRC, the operating region is much smaller. At light load, the frequency doesn't need to change too much to keep output voltage regulated. So light load regulation problem doesn't exist in PRC. Same as SRC for PRC, the converter is working close to resonant frequency at 300V.

At high input voltage, the converter is working at higher frequency far away from resonant frequency. From simulation waveforms, at 300V input, the circulating energy is smaller than 400V input situation. Compare with SRC, it can be seen that for PRC, the circulating energy is much larger. Also from the MOSFET current we can see that the turn off current is much smaller in 300V input. When input voltage increases to 400V, the turn off current is more than 15A, which is even higher than PWM converter. For PRC, a big problem is the circulating energy is very high even at light load. For PRC, since the load is in parallel with the resonant capacitor, even at no load condition, the input still see a pretty small impedance of the series resonant tank. This will induce pretty high circulating energy even when the load is zero. With above analysis, we can see that PRC is not a good candidate for front end DC/DC converter too. The major problems are: high circulating energy, high turn off current at high input voltage condition.


Its resonant tank consists of three resonant components: Lr, Cs and Cp. The resonant tank of SPRC can be looked as the combination of SRC and PRC. Similar as PRC, an output filter inductor is added on secondary side to math the impedance. For SPRC, it combines the good characteristic of PRC and SRC. With load in series with series tank Lr and Cs, the circulating energy is smaller compared with PRC. With the parallel capacitor Cp, SPRC can regulate the output voltage at no load condition. The parameters of SPRC designed for front end DC/DC application are: Transformer turns ratio: 6:1, Resonant inductance: 72uH, Series resonant capacitor Cs: 17.7nF, Parallel resonant capacitor Cp: 17.7nF, Range of Q: 1 (Full load) to (No load) Similar to SRC and PRC, the operating region is also designed on the right hand side of resonant frequency to achieve Zero Voltage Switching. From the operating region graph, it can be seen that SPRC narrow switching frequency range with load change compare with SRC. Compare the switching waveforms, the input current in much smaller than PRC and a little larger

than SRC. This means for SPRC, the circulating energy is reduced compare with PRC. Same as SRC and PRC,, the converter is working close to resonant frequency at 300V. At high input voltage, the converter is working at higher frequency far away from resonant frequency. Same as PRC and SRC, the circulating energy and turn off current of MOSFET also increase at high input voltage. The turn off current is more than 10A. With above analysis, we can see that SPRC combines the good characteristics of SRC and PRC. Smaller circulating energy and not so sensitive to load change. Unfortunately, SPRC still will see big penalty with wide input range design. With wide input range, the conduction loss and switching loss will increase at high input voltage. The switching loss is similar to that of PWM converter at high input voltage. By analysis, design and simulation of SRC, PRC and SPRC, the conclusion is that these three converters all cannot be optimized at high input voltage. High conduction loss and switching loss will be resulted from wide input range. To achieve high switching frequency and higher efficiency, we have to look for some other topologies.




2.1 SYSTEM STRUCTURE AND CONTROL Achieving high efficiency in dc-dc converters operating at very high frequencies necessitates means to keep the switching loss to a minimum. In hard-switching converters some energy is lost every time the semiconductor switches commutate, yielding a loss component that is proportional to the switching frequency. Soft switching and in particular zero voltage switching (ZVS) reduces the switching loss by maintaining a low voltage across the semiconductor device during the on/off transitions. Furthermore, ZVS operation is beneficial because it reduces the electromagnetic interference (EMI) normally associated with rapid transitions in hard-switched converters.

However, the resonant methods used to realize ZVS operation tend to incur losses that do not scale back with load, making it difficult to achieve efficient light-load operation. A challenge, then, is to take advantage of the high-frequency capabilities of ZVS topologies while still maintaining efficient operation at light load.

A further challenge in implementing VHF power converters is reducing the losses due to the gating of the semiconductor devices. With conventional gate drives, gating loss is proportional to switching frequency and rapidly becomes unacceptable as frequency is increased. Recovering at least a portion of the energy delivered to charge the gate is thus an important means for extending the achievable switching frequency range. Parasitic elements are another important consideration in RF converters, and become more so with increasing switching frequency. In many RF circuit implementations; the size of some circuit elements is comparable to the parasitic introduced by the devices, packages and interconnections.

For example, the parasitic capacitance of the semiconductor device is typically an important consideration in RF converter design. To address this issue, and to allow for even higher switching frequencies, topologies that absorb or utilize the component parasitic (especially device capacitances) as an integral part of their operation are desirable. This, however, leads to a tighter dependence of circuit performance on device parasitic than is typical in conventional designs.



A block diagram of a system realizing this approach is shown in below figure which consists of a radiofrequency resonant inverter, a transformation stage, and a resonant rectifier, along with an appropriate control system. Another figure shows a simplified schematic of the prototype dc-dc converter implemented to demonstrate this approach. Subsequent sections will focus on key system elements, and will present an evaluation of the different functional blocks of the system.

Figure 2.1 A block diagram illustrating the structure of a high frequency dc-dc converter. An inverter at the system input transfers power from the input source to the subsequent stages by transforming the dc input voltage into a VHF sinusoid. The inverter can be implemented using any of a number of switched-mode RF power amplifier topologies that provide the required ZVS. For the particular implementation in this paper, the inverter utilized was a class E power amplifier operating with a low loaded Q (QL) to deliver power efficiently. Details on the design, characteristics, and limitations of this class of power amplifiers can be found.

Figure 2.2 Schematic of a 100 MHz dc-dc converter.


Inverter output power (under ZVS conditions) is proportional to the capacitance in parallel with the switch. For the intended output power range in the practical implementation described here, the required capacitance is provided by the parasitic drain-source capacitance of the MOSFET and 20 pF of external capacitance. The device selected for the main switching element of the inverter is a lateral doubly-diffused MOSFET (LDMOSFET of the type typically used in cell phone base stations. This semiconductor device offers the characteristics required to operate at high frequencies: it presents an acceptably low output capacitance (Coss) as well as a low input capacitance (Ciss), gate resistance (RG) and reverse transfer capacitance (Crss) that allow for a small gating loss under resonant drive conditions. The system described here also incorporates a new low-loss gate driver that recovers most of the energy used to control the gate of the semiconductor device.

Furthermore, it provides fast response times compatible with control schemes that achieve high bandwidth. An important attribute of this gate drive is the trapezoidal wave-shaping of the gate voltage; this characteristic allows fast commutation of the switch, requires only small passive components for its realization, and provides near-minimum loss. As shown in above figure, the inverter is followed by a transformation stage, which provides a means of scaling the voltages and currents of the inverter to a level at which a set of balanced resonant rectifiers can operate efficiently. This stage also provides resistance compression to mitigate the inherent sensitivity of the class E to variations in load. Design of this type of circuit is treated in so is not considered further here. The next stage in the dc-dc structure is a resonant rectifier which transforms the intermediate RF ac waveforms back down to dc. Rectifier circuits having characteristics similar to tuned resonant inverters can operate efficiently under certain conditions.

This introduces a resonant rectifier structure in which two single-diode resonant rectifiers deliver power to a constant voltage output. The effective impedance of these rectifiers at the switching frequency is desired to be resistive to ensure suitable operation of the previous stages. The design of high efficiency dc-dc converters requires the implementation of output control techniques compatible with all of the requirements. One suitable technique is the on/off or .burstmode. Modulation sometimes used to obtain high efficiency in converters operating at light load2. In the implemented converter, regulation of the output voltage is achieved by modulating

the converter on and off (bang-bang control), forcing the voltage to comply with a ripple specification. The simplicity of this control scheme overcomes the difficulty in efficiently controlling RF amplifiers through other means. The converter system developed here is regulated with a hysteretic controller that maintains the output voltage within a 100 mV hysteresis band through on/off or bang-bang control of the converter. It will evaluate the performance of a 10 W dc-dc converter switching at a frequency of 100 MHz with closed-loop voltage control.


As discussed in the previous section, reducing gating loss is essential to operating at very high switching frequencies. Conventional hard-switched gate drives dissipate all of the energy delivered to the gate from the gate drive supply each cycle. This results in a frequency dependent gate drive loss: Pgate = Ciss gate fs eqn (2.1)

To achieve very high frequency operation while maintaining acceptable gating loss, a resonant energy recovery gate drive is necessary. Switch transitions are effected by ringing charge on and off of the gate. Under these conditions, most of the energy stored on the gate is recovered and total loss is a fraction of what can be expected if the device were hard gated. One approach that has been used previously is a sinusoidal gate drive. In this approach, a resonant network is used to ring charge on and off the gate such that the gate voltage is sinusoidal (possibly with a dc offset). For switching times much longer than a gate RC time constant, this can be an effective method, providing a reduced loss of: eqn (2.2)

Pgate = 2


Where Ciss is the gate input capacitance, MOSFET gate and drive circuit

is the effective series resistance of the

is the peak amplitude of the sinusoidal ac gate voltage. While a sinusoidal resonant drive is effective in some applications, it does have some important limitations. First, many of the commercially-available LDMOS devices suitable for

VHF power conversion incorporate a protective diode between the source and gate terminals, preventing the use of gate drivers which impose negative voltage excursions on the gate. Moreover, even when a sinusoidal gate drive can be used, the ac drive magnitude often has to be larger than needed to fully enhance the device in order to provide a fast gate drive transition time, increasing overall gate loss by a square law. The negative excursions of the gate drive voltage also induce unnecessary gate loss. The most efficient way to charge/discharge the gate capacitance Ciss for a specified transition time is a constant current source. A trapezoidal drive voltage waveform applied at the gate of the semiconductor switch will yield an approximately constant current on the rising and falling edges of the gate voltage, for small gate resistance thus minimizing the power dissipated in the gate resistance.

The power dissipated in

of an MOS transistor driven by a trapezoidal waveform is:

Pgate = (Ciss

eqn (2.3)

Where Vgate is the maximum voltage of the trapezoid Ciss is the input capacitance of the LDMOS tr and tf are the rise time and the fall time respectively of the drive waveform. Here we introduce an efficient gate drive using a simple multi-resonant structure to implement trapezoidal voltage wave shaping. A switched mode driver incorporating wave shaping methods similar to those employed in class F power amplifiers and related circuits. Unlike traditional class F power amplifiers, the driver proposed here operates in switched mode, thus providing maximum efficiency.


Figure 2.3 Schematic of the multi-resonant gate drive

Figure 2.4 Simple multi-resonant network. The input impedance of the network (ZIN) has maxima at two frequencies (poles).The impedance is zero at dc and at a frequency somewhere between the two maxima. The components L2 and C2 are tuned to be series resonant close to the second harmonic as viewed from the drain/source port of the auxiliary device.

The resonant components L1 and C1 are tuned in conjunction with L2 and C2 such that the input impedance ZIN presents relatively high impedance at the switching frequency and the third harmonic of the switching frequency. This is done in such a manner that the voltage vg can support approximately trapezoidal waveforms that contain a dominant fundamental voltage component and a smaller third harmonic component. A good design starting point for tuning the multi-resonant network is to start with impedance maxima (poles) at the fundamental and third harmonic and low impedance (zero) at the second harmonic of the switching frequency.


Component values for tuning the poles of ZIN at exactly the fundamental and third harmonic and placing the zero at the second harmonic can be determined starting from a selected value for C1 eqn (2.4)

eqn (2.5)

Note that the component C1 incorporates the output capacitance Coss of the auxiliary switch and the gate capacitance Ciss of the main semiconductor switch. It is important to minimize the stray inductance between the gate of the main MOSFET and the auxiliary drain node, such that both Coss of the auxiliary device and the gate capacitance Ciss of the main device can be considered connected in parallel. Because the inductor L1 acts as a resonant inductor, it has a very small numerical value and small energy storage.

Figure 2.5 Input impedance vs. frequency of the simple multi-resonant structure When the gate drive auxiliary switch drives this structure at the switching frequency with a duty ratio of somewhat less than 0.5, the voltage waveform at the gate is roughly trapezoidal

and offset so that it never swings negative. Moreover, the dynamic characteristics provide zero voltage switching of the driver switch, such that energy delivered to the gate capacitance is naturally returned to the gate drive supply. These conditions arise as a result of the half-wave symmetry imposed by the impedance of the network. A simulation of the gate to source voltage of the main switch with a switching frequency of approximately 100 MHz is shown in below figure.

One can easily appreciate that the trapezoidal waveform and dc offset characteristics are achievable. Controlled self-oscillation of the driver is achieved by using an appropriate feedback network around the gate drive circuit. A fraction of the drain to source voltage of the gate drive MOSFET is phase shifted and applied to its gate. The figures show the network that provides the required phase shift along with a simplified schematic of the startup circuit. The startup circuit is required to initiate the oscillation at the application of the gate-drive input voltage Components LF, CF and LT provide a phase shift of -180 of the fundamental voltage at the drain of the auxiliary device in order to achieve self-oscillation while at the same time the components are selected to minimize loading that could significantly change the impedance ZIN of the multiresonant network.

This section presents PSPICE simulations of the self-oscillating multi-resonant gate driver implemented in the prototype described in Section V. For this simulation, the gate of the main LDMOSFET (Free scale MRF373ALSR1) is modeled as a series RLC branch with LG;main=700 pH, RG;main=0.3 and Ciss main=114 pF. Referring to Fig. 7, the values of the multiresonant elements are: L1=8.1 nH, L2=4 nH, C2=150.56 pF. Coss;aux=48 pF, which together with Ciss;main makes C1 =162 pF. The magnitude of the impedance ZIN at the drain of the auxiliary LDMOSFET. The phase-shift network responsible for the self-oscillation is also included in the simulation as well as the parasitic elements present in the printed circuit board (PCB). The magnitude of ZIN at the switching frequency (approximately 100 MHz) is higher that than at the third harmonic as explained above.


Figure 2.6 Simplified schematic circuit of the startup control strategy.

The gate of the auxiliary MOSFET Q2 (a Polyfet L8829) is part of the phase shift network and is modeled as series RLC branch with RG;aux=3 and Ciss;aux=30 pF. The gate inductance LG;aux is not significant and is included in the value of LT. The values of the elements comprising the phase shift network are: LF=100 nH, CF=56.8 pF, LB=100 nH, CB=2 nF and LT=84 nH. The magnitude and phase of the transfer function (TF) of the phase-shift network responsible for achieving self-sustained oscillation. As described above, the figure shows that at the intended frequency of oscillation (100 MHz), the phase-shift angle of the TF is -180. The phase-shift network also provides filtering to attenuate the third harmonic, as is demonstrated in the figure. The mechanism for starting the oscillation (and thereby tuning on the converter) is as follows. After the gate drive power supply is applied, a delay of duration Th is provided to allow the voltage at the drain of the auxiliary device to settle. After this interval (Th) a pulse of voltage of duration Tp is applied to the phase-shift network.


Figure 2.7 Simulated input impedance at the drain of the auxiliary switch This momentarily drives down the drain to source voltage of the auxiliary switch. At the end of the pulse, the drain to source voltage will naturally ring with the harmonic characteristics of the network. This voltage, in turn, drives the gate of the main switch. To stop the oscillations, the supply voltage to the multi-resonant gate driver is cut by a logic control signal. The durations of the hold interval (Th) and the pulse interval (Tp) are determined by the timing components RT1,CT1 and RT2, CT2 respectively. Diodes DT1 and DT2 provide a low impedance path to rapidly discharge the timing capacitors to allow for faster activation rates. The simulated voltage at the drain of the auxiliary LDMOSFET (gate of the main switch) under self-oscillating conditions at fs=102.2 MHz. When modulating the dc-dc converter on and off, the energy stored in the bypass capacitors, the timing elements of the network, and the output tank is lost in each transition. This energy loss, as well as the time required for the cell to achieve steady state operation, limits the maximum modulation frequency. On the whole, the small size of the energy storage components keeps this loss to a minimum and allows a relatively large control bandwidth on the order of 200 kHz.


Figure 2.8 Simulated gate voltages at the gates of the main and auxiliary switches. The switching frequency fs=102.2 MHz. 2.4 RESONANT RADIO-FREQUENCY RECTIFIER The high-frequency sinusoidal voltage at the output of the inverter generates sinusoidal currents at the outputs of the transformation/compression stage. These currents are rectified to provide dc power to the converter output. It is desirable for the fundamental voltages at the rectifier inputs to be substantially in phase with the currents at the output of the transformation/compression stage. Under this condition, the transformation/compression network will provide appropriate loading to the inverter to maintain the desired ZVS. The schematic of the resonant rectifier investigated here, loaded with a constant voltage at the output.


Figure 2.9 Resonant rectifier connected to a constant output voltage.

The rectifier is driven by a sinusoidal current source of magnitude IIN. A resonant capacitance Cr represents the sum of an external capacitor CEXT and an equivalent diode capacitance CD. Resonant inductor LR provides a path for the dc current and resonates with capacitance Cr so that the input looks resistive at the fundamental frequency. A similar rectifier structure was presented in the literature in but for very different drive and loading conditions that are not applicable to the cell-modulation converter system considered here. The conduction duty cycle of the diode current depends on the component values.

By adjusting the net capacitance CR in parallel with the resonant inductor, it is possible to trade off the length of the conduction interval and the peak reverse voltage across the diode. It is convenient to have a conduction interval close to 50 percent, as this provides a good tradeoff between peak diode forward current and reverse voltage.

This additional capacitance can either be added externally or can be solely provided by additional diode area, which can have the added benefit of reducing the overall conduction loss in the rectifier. The value of LR of the resonant rectifier is selected in conjunction with Cr to provide the desired resistive input characteristics (fundamental rectifier input voltage in phase with rectifier input current). Appropriate values can be found through straight parametric search using a simulation tool (e.g. PSPICE or a piecewise linear simulator) by looking at the fundamental component of the voltage vrec and minimizing the phase angle between the input current and the fundamental component of the rectifier input voltage at a given nominal output power.

The input current and voltage of a resonant rectifier simulated using PSPICE. For the simulation shown, LR=18.8 nH, CEXT=32 pF, CD is the non-linear device capacitance of the diode (D1, an MBRS260T3 Schottky diode), VOUT=12 V, and the sinusoidal input current IIN=0.67 A at a frequency of 100 MHz. The average power delivered to the load under these conditions is 6.2 W.

The fundamental component of the input voltage and the current are nearly in phase resulting in a rectifier with an equivalent resistance (only at the fundamental) of approximately 29.8. The equivalent impedance at the fundamental frequency of the rectifier will change with the input current. Over the operating range of the rectifier, it is desired that this equivalent input impedance remain substantially resistive.





At VHF frequencies, traditional hard-switched gating typically incurs too much loss for acceptable efficiency. Instead, with a power stage and control scheme designed to operate at a fixed frequency and duty ratio, resonant gating is advantageous. By recovering a portion of the gate energy each cycle, much lower power is required to drive the gate, minimizing the effect gating has on overall converter efficiency.

In addition to achieving low-power operation, a practical gate drive must reach steady state rapidly at startup and shutdown to maintain good converter transient response and high efficiency under ONOFF modulation. To that end, two different low-loss gate drivers were designed, one for optimum efficiency and one for easier integration. In the case of the 110-MHz converter, the gate terminal of the switch cannot be driven below the source due to a protection diode integrated with the switch. For this reason, a scheme similar to that presented was developed. This gate drive realizes a trapezoidal gate voltage waveform that does not drive the gate source voltage negative, and which yields near-minimum loss.

The design here utilizes fewer parts and achieves a faster startup time than the design. It is based on the inverter presented and uses a low-order lumped network to shape the main-switch gate voltage to be approximately trapezoidal. Added components provide a gate signal to the auxiliary MOSFET, Saux, such that a self-sustained oscillation is achieved. The inductor Lstart helps to initiate this oscillation when the voltage Vgate is applied. Component values for this gate driver are presented in Table I.


50 MHz Design 2.5 K 15Pf 100nF

110MHz Design 5.5 nH 13 nH 82 nH

56nH 47nH 100 K FDV303N MA27D27 Inverter NC7WZ04

56 pF 100 pF 68 nH 3.8 nH 139 pF Polyfet L8821P 5.6 nF

Table 3.1 Gate Drive Component Values

Holding integration as a goal demands a less complicated gate drive scheme for the 50MHz converter. A straight totem pole driver is still too inefficient for this application, so only resonant schemes were considered. Perhaps, the simplest resonant scheme available includes a single series resonant inductor placed between a totem pole driver and the gate. This is a sinusoidal resonant gate drive. However, efficiency remains a problem with this scheme. Since all of the resonating current must pass through the totem pole driver, the output resistance of the driver is important. In this case, one can model the gate loss as eqn (3.1)

Pgate = (CISSVacfSW)2 (RG + RI ) where RI is the output resistance of the totem pole driver RG is the gate resistance CISS is the gate capacitance Vac is the ac amplitude at the gate fSW is the switching frequency.


Since the totem pole devices must be small to keep their gating loss to a minimum, RI tends to be several times larger than RG and the total loss of this simple resonant scheme quickly exceeds that of the hard gating case. This problem is addressed by adding a shunt leg to the basic resonant tank, as depicted. The approach is similar to that though different in how the network is tuned. The shunt leg, comprising LP and the blocking capacitor CP, carries a portion of the resonating current, reducing the loss in the inverter bank. LP is chosen to be resonant with CISS below fSW, effectively reducing the equivalent gate capacitance. LS and CB form the series leg, setting the transfer function from the inverter bank to the gate.

While there are many values of LS and LP that result in a functioning gate drive, a number of constraints define a smaller locus of useful values. First, the inverter to gate transfer function, VGS/V1, can have a gain larger than unity. This allows the inverter bank supply voltage to be reduced, in turn, reducing loss. However, tuning the network to maximize VGS/V1 does not result in the best efficiency. Instead, as the value of LS starts to become smaller than LP, an increased fraction of resonating current reaches the inverter bank. The additional loss (caused by dissipation in the inverter bank output resistance) eventually swamps improvements made by reducing the inverter bank supply voltage. On the other hand, if LS becomes too large relative to LP, then the inverter bank cannot effectively control the voltage, VGS, and the drain to gate transfer function VGS/VDS dominates. This can cause the converter to self-oscillate at a frequency other than intended, or it may make the converter difficult to turn OFF. A pull down switch was added to avoid the latter problem, but care is still required to ensure the inverter bank has good authority over the gate voltage.

The gate drive startup time is also affected by component choice. As LS becomes larger, startup tends to extend, which makes it harder to modulate the converter ON and OFF rapidly. In order to find a good choice for LP and LS, a MATLAB script was created to calculate losses in the gate drive. The script finds the branch currents for a given set of inductors and then returns the losses based on the inductor Q, gate resistance, and inverter bank output resistance.


This results in several sets of inductor values (e.g., values for LS and LP constitute a single set) that have approximately the same loss. From those sets, a single set is chosen that has the best startup characteristics and allows for good control over the gate voltage by the inverter bank.

In particular, the inductor sets, where the phase of the transfer function VGS/VDS is closest to 180, seem to return the best efficiency and startup times. This is interpreted as having VGS/VDS satisfy the phase condition for self-sustained oscillation. Since the magnitude of this transfer function is less than unity, the additional energy for continued oscillation is then supplied by the inverter bank.

The resulting component values are listed in the left half of Table I. RT and CT are used in conjunction with an additional CMOS inverter to create a ring oscillator that runs at 50 MHz R1 ensures that the oscillator will start consistently while the diode D1 is used to kill the oscillation, thereby providing a logic-level control input. CB and CP are chosen to be ac short circuits at the switching frequency, serving as dc-blocks that allow the gate voltage to be biased. The bias, in turn, establishes the desired duty ratio (a negative bias will reduce the duty ratio, and positive bias does the opposite). The design power for this gate drive was 204 mW, which is only 40% of the loss expected with hard gating.

Actual measurements showed the power loss to be closer to 500 mW, the major culprit being the ring oscillator. Its output was not transitioning rapidly, likely increasing direct path losses in all the CMOS inverters. Driving the inverter bank with a signal generator results in a gate drive power of only 260 mW, including the power to drive the inverter gates. Even with larger than expected power loss, the resonant gate drive is still much better than an equivalent hard gating network, which would use over 800 mW when the gate is driven directly by an inverter bank. The gate drive design presented reaches steady state in just over 74 ns, which is sufficiently fast for this application.



The control strategy employed is an ONOFF hysteretic control scheme. When the output voltage falls below a specified threshold, the converter is enabled and delivers power to the output, causing the output voltage to gradually increase. When the output rises above a specified threshold, the converter is disabled, and the output voltage will gradually decrease. Effectively, load power is controlled by changing the duty ratio with which the converter is modulated ON and OFF. Such a strategy is possible at VHF because the minimal energy storage required allows for rapid startup and shutdown of the entire power stage. This scheme realizes the advantages of separating the control and power processing functions. When the converter is ON, it operates at a fixed high-efficiency point. When the converter is OFF, many of its loss mechanisms are removed.

The result is efficient operation over a much wider load range than can be achieved with many other strategies. The bulk output capacitance Cout is sized to achieve an intended ONOFF modulation frequency given a load range and the desired ripple voltage. Smaller capacitance will result in higher modulation frequency. Generally, converter efficiency decreases as modulation frequency increases, suggesting a tradeoff between bulk capacitor size and efficiency, though the details are somewhat complicated. It should be noted that the bulk converter input capacitance must also deal with ripple components near the modulation frequency. Nevertheless, the main power stage components are sized based on the very high switching frequency, enabling miniaturization and fast transient response.

Figure 3.1 Block diagram illustrating ON/OFF control of a VHF resonant dcdc converter.


The basic scheme presented utilizes a hysteretic comparator, a voltage reference to set the dc level, and a voltage divider to sense the output voltage. The ripple voltage is determined by the comparator and is equal to the hysteresis band times the divider ratio. Bulk capacitance is added at the output and sized according to the desired modulation frequency range and expected load. It is important to note that the transient performance of the converter is not determined by the modulation frequency, but by the delay around the control loop and the (very high) switching frequency of the converter.



This section presents the design and experimental evaluation of two converters of the type proposed here. The first operates at 110 MHz and uses a high-performance RF LDMOSFET, while the second operates at 50 MHz using an LDMOSFET fabricated in an integrated power process.

3.3.1 110-MHz High-Performance Implementation

A dcdc converter based on the topology introduced and operated at 110MHz was built and evaluated. Table II lists the converter specifications. The transistor Smain is a commercially available RF MOSFET with good high frequency characteristics. Warren et al. describes a method for evaluating transistors for VHF soft-switching converters and contains a detailed analysis of transistor evaluations for the study presented here. The hysteretic network comprising R1, R3, and C10 implements frequency-dependent hysteresis to mitigate problems with the highfrequency content of the output voltage falsely triggering the comparator.

The values of the power stage components are given in Table 3. Note that the capacitor CF is provided entirely by the parasitic switch output capacitance, Coss . The control circuitry that regulates the output voltage is placed on the other side of the printed circuit board. As can be seen in Table 3, the largest inductor in the power stage is 33 nH. The small sizes of the inductors are due both to the high operating frequency of the converter (110 MHz), and to the nature of the topology introduced. Converter waveforms are presented, which show measured drain and gate voltages for Vin = 14.4 V and Vout =33 V. Switching transitions occur at least close to the zero voltage ideal, and the peak device voltage stress is acceptable. As will be seen in the following section, peak device voltage stress can be controlled by design and traded off against other characteristics.

Open-loop efficiency and power over the input voltage range are illustrated, where the input voltage is swept from 8 to 16 V, and the output voltage is kept constant at 32 V. This and


all following efficiency measurements include the losses of the gate driver and control circuitry, which were powered from the converter input.

Nominal Input Voltage Nominal Output Voltage Input Voltage Range Output Voltage Range Switching Frequency Nominal Output Power Gate Drive Input Voltage

14.4 V 33 V 8 16 V 22 34 V 110 MHz 23 W 3.6 V

Table 3.2 Experimental dcdc converter specifications

The output voltage ripples when the converter is regulating the output at 32.4 V. The approximately 200-Mv ripple is set by the hysteresis band of the controller and is independent of the output capacitance of the converter. The modulation frequency at which the converter is turned ON and OFF is set by the load resistance, hysteresis band, and output capacitance, and is 50 kHz. If a smaller output capacitance is desired, this modulation frequency can be set as high as several hundred kilohertz with no noticeable decline in efficiency, as discussed next. The lower part of the figure shows the drainsource voltage of the main switch, and illustrates how the converter is turned ON and OFF as the output is regulated.

It is important to note that while the ONOFF modulation frequency in is 50 kHz, the converter itself is switching at 110 MHz when it is turned ON. In the time scale of this switching frequency is under sampled, but its effect can be seen as the hash in the rising portion of the output voltage ripple and the drain voltage when the converter is turned ON. The effect of modulation frequency on converter efficiency is illustrated, which shows measured converter efficiency versus modulation frequency when the converter is modulated at 50% duty cycle for an input voltage of 14.4 V and an output voltage of 33 V (controlled by an electronic load).


As expected, converter efficiency decreases with increasing modulation frequency, since the fixed per-cycle losses associated with startup and shutdown of the converter limit the efficiency at high modulation frequencies.

Figure 3.2 Schematic drawing of the ONOFF control circuitry for the 110-MHz converter.

The figure illustrates, the converter can be modulated at substantially higher frequencies than what is chosen for this study (20100 kHz, depending on load), without a significant impact on overall efficiency. For designs where minimum output capacitance is desired, this tradeoff can greatly reduce the size of the output capacitor at a small efficiency penalty. An important benefit of the ONOFF control strategy is the high efficiency at light load. It shows the closedloop efficiency over the input voltage range, parameterized by load. The converter regulates the output at 32.2 V and the load is varied from 5% to 90% of full load. Also it illustrates, the converter exhibits excellent light-load performance, maintaining above 81% efficiency at nominal input voltage all the way down to5%load. This substantial improvement in light-load operation as compared to typical resonant converters can be attributed to the control strategy used, which turns the converter ON only for very small periods of time at light load.

When the converter is turned OFF, it consumes no power, and for the brief time when it is turned ON, it operates in a highly efficient state. There is quiescent loss in the control circuitry along with a small fixed power loss associated with turning the converter ON and OFF, which explains why overall efficiency still decreases with lighter load. As the delivered power is reduced, the fixed ONOFF power loss becomes a larger fraction of the total output power, thereby reducing efficiency. The ON/OFF control method used to regulate the output requires that the converter turn ON and OFF quickly. Rapid startup and shutdown improves transient performance, since the converter will be able to quickly respond to a change in load condition, as well as input and output voltage changes.


110-MHz Design 33 nH 12.5 nH 22 nH 0 pF 39 pF 10 pF 70 F Free scale MRF6S9060 Fairchild S310

50-MHz Design 22 nH 22 nH 56 nH 56 pF 115 pF 47 pF 40 F Integrated process Fairchild S310

Table 3.3 Power stage component values

Furthermore, the achievable modulation frequency is determined by the time needed to start up and shut down the converter. If the converter ON/OFF transitions takes too long, the modulation frequency will have to be lower to maintain high efficiency. A higher modulation frequency corresponds to lower output capacitance, which is desirable as it will reduce size, weight, and cost of the converter, as well as enable faster transient performance. It shows the measured converter waveforms during startup and shutdown. The initial delay between the change in command signal and the change in gate voltage is due to the propagation delay of the National Semiconductor LM5112 driver chip used to provide power to the gate drive. As can be

seen from the figure, the converter turns ON in approximately 150 ns, and takes another 100 ns or so to reach steady state, while converter shutdown waveforms show a slightly faster response.

Figure 3.3 Drain and gate voltages for experimental 110-MHz converter operating with Vin = 14.4V and Vout = 33 V. In addition to the size, weight, and cost benefits realized from smaller passive components, an increase in switching frequency also leads to improved transient performance. Because of the small amount of energy stored in the passive components in each switching cycle, the converter can quickly adjust to any changes in load conditions. Because of the small required output capacitance, the converter can quickly change the desired output voltage measured output voltage ripple when the load is changed from 10% to 90% of full load (top), and from 90% to 10% of full load (bottom) at time t = 0. It can be seen from this figure that there is an instantaneous response to the load-step transient, without any voltage deviation outside the ripple range.


Figure 3.4 a) Open-loop power and efficiency of the 110-MHz converter over the input voltage range, with Vout fixed at 32 V. b) Converter open-loop efficiency versus modulation frequency for 50% modulation duty ratio.

This formidable transient response can be attributed to the small inductors and capacitors required for operation at 110 MHz In addition, transient performance is improved by the resonant topology introduced in former section, which uses only small-valued resonant passive components. In conventional dcdc converters, the total required output capacitance is determined by the allowed voltage ripple and the desired transient performance. It is often the latter requirement that determines the minimum capacitance, calling for a larger capacitance than what output ripple requirements alone would require. The VHF resonant boost converter, with its inherently fast transient response, does not have this problem. The output capacitor is sized solely based on the desired ONOFF modulation frequency and output ripple, not by transient response limitations. The below figure an additional advantage of having the output capacitor sized in this manner. The figure shows the measured response of the output voltage to a step change in regulation voltage.


Figure 3.5 Output voltage ripple of the 110-MHz converter for load steps between 10% and 90% of full load.

In this case, the regulated output voltage was changed from 22 V to 32 V at time 0 (for a 60 load), and as seen in the figure, the output voltage settles to the new value in approximately 1 ms. The slew rate of the output voltage is dependent on load, with the output voltage rising faster for a light load when the regulated output voltage is increased. Similarly, the slew rate for a command to decrease the regulated output voltage is higher for a heavy load, since the only means for removing the charge on the output capacitor is through the load resistance. It is important to realize that for a given load the slew rate is inversely proportional to the size of the output capacitor, which can be quite large in a conventional dcdc converter. The proposed converter, with its small output capacitance, therefore offers an advantage in applications that require the regulated output voltage to change rapidly.


3.3.2 50-MHz Integrated Power Process Implementation

The VHF operation of the converter described here lends itself to the possibility of integration. With this in mind, a converter was built where the main switch was fabricated in a 50-V integrated power process and the other components were discrete. The device was not optimized for RF operation or, otherwise, customized. Instead, the goal was to determine the feasibility of implementing the design in conventional power processes thereby avoiding the cost of a custom RF process. The converter was designed for an 818 V input range, a 2233 V output range, and had a 17-W output power rating at the nominal input voltage of 14.4 V. The figure shows (open loop) power and efficiency versus input voltage for an output voltage of 32V.

The switching frequency was 50 MHz, which held the largest inductor value to 56 nH (a complete list of component values appears in Table 3). The small-valued, air-core passive components are promising candidates to be either co-packaged with a switch/controller IC or perhaps realized on-die. The ability to tune the resonant boost converter to minimize peak switch voltage stress was a key factor enabling the use of the 50-V power process. The peak VDS across the switch was 42 V at 18 V input (< 2.4 Vin ).

This is in contrast to the 65-V peak a class-E converter would suffer well beyond the nominal 50-V process limit. Careful study of the gate and drain voltage waveforms for the operating conditions shown in Fig. 20 suggests that the turn- ON transition begins when the drain voltage is below 5 V and the subsequent turn-OFF transition completes by the time the drain source voltage reaches 5 V. This leads to small overlap and discharge switching loss.


Figure 3.6 Open-loop power and efficiency versus input voltage of the 50-MHz power stage for a fixed output voltage of 32 V. At the nominal input voltage, the converter was better than 74% efficient over a load range from 4 to 17 W under closed loop operation. A significant fraction of the increased loss over the high-performance design is related to the integrated device. Its gate-drive figure of merit (Rgate C2gate ) is nearly 80-fold poorer than the RF device. Similarly a larger COSS and its greater equivalent series resistance contributes to increased device loss along with higher conduction loss owing to the somewhat larger 210 m RDS(on) .


Figure 3.7 Drain and gate voltages for experimental 50-MHz converter operating with Vin = 14.4 V and Vout = 32 V.

Since it was not possible to custom-design the device layout on this iteration, there is room for substantial performance enhancement by simple changes in device geometry, such as choosing a more optimum gate finger length. As a minimum, this will reduce gate resistance allowing an increase in operating frequency or greater device area and lower total loss. The detailed efficiency characteristics of the converter are qualitatively similar to those of the 110MHz converter. As a consequence of the small energy storage, the transient performance is excellent and the converter can be modulated at 700 kHz with only a 1% loss of efficiency. Under closed loop operation, the modulation frequency was held to 250 kHz because of a larger than necessary 40-F bulk capacitance. This converter has a 100 mVpp ripple using the hysteretic voltage mode control scheme described earlier.


Figure 3.8 Details of the ONOFF control circuitry for the 50-MHz converter.

Load-step performance is excellent. The application of a load step from 2 to 12 W back to 2 W (corresponding to 13.3% load and 80% load) results in a transient response that never leaves the ripple band. That is, under load step, the output voltage is never more than 50 mV away from the reference voltage and overall good performance achieved with the integrated transistor is encouraging. Plenty of opportunity exists to optimize the device within the constraints of the process, and perhaps, realize higher efficiency, higher operating frequency, or both. Comparator Voltage Reference Synchronous Buck R1 R3 R4 R5 C10 Texas Instruments TLV 3501 Analog Devices ADR394 Texas Instruments TPS62110 300 220 K 10.5 k 1.5 k 12 pF

Table 3.4 50-Mhz OnOff control component values


CONCLUSION This paper has presented a new resonant topology suitable for boost power conversion. The new topology addresses several shortcomings of previous designs, while maintaining all desirable properties necessary for VHF power conversion, such as zero-voltage switching and absorption of device capacitance. The paper describes experimental implementations of two resonant boost converters. One is a 110-MHz, 23-W converter using a commercially available LDMOSFET, which achieves efficiency above 87% for nominal input and output voltages. The other is a 50-MHz, 17-W converter using a switch from a standard 50-V integrated power process.

Both converters utilize a high-bandwidth control strategy that permits excellent light-load efficiency, something that is typically difficult to implement with resonant converters. In addition to greatly reducing the physical sizes of the passive components, the high operating frequency gives the converters an inherently fast transient response. As this paper has demonstrated, it is possible to achieve miniaturization and high performance of dcdc power converters without sacrificing efficiency.

The design implementations described in this paper are expected to contribute to the development of VHF dcdc converters, paving the way for power electronics that can satisfy the needs for improved size, cost, and performance that are demanded by modern applications.



.subckt diodenl a k + params: + Lds=1n; Series inductance +Vdon=0.55; Diode forward drop +Rds=0.3; Series resistance + Cjo=267.77p + Vj=0.365 + M=0.4204 + Rc=0.240; Rcout + Fs=50Meg

*Parasitic lead inductance Lds A 101 { Lds} ic=0

*Ideal diode model Dideal 101 102 dideal .Model dideal D(N=0.001)

*Forward voltage drop model Vdon 102 103 {Vdon} Rds 103 K {Rds}

*Nonlinear capacitance Gcnl K 104 Value={IF((V(K)-V(104))<0,Cjo*V(201)* + (1/Lder),V(201)*(1/Lder) +*(Cjo/((1+((V(K)-V(104))/Vj)) M)))} Rc 101 104 {Rc}

*Evaluate the derivative .Param: + Lder=1U; Inductor for derivative circuit + Pi=3.14159 .Func Rder(Lder,Fs) {3000*2*Pi*Fs*Lder} Gy 0 201 Value={V(K)-V(104)} L1 201 0 {Lder} R1 201 0 {Rder(Lder,Fs)} .Ends Diodenl; Fairchild S310

TRANSISTOR MODEL .Subckt MosfetNlc gate drain source + Params: + Rdson=0.2 + Rg=1.7 + Cgs=246p + Rcout=0.6 + Rshunt=12Meg + Cjo=425.2p + Vj=0.177 + M=0.252 + Ldrain=1n + Lsource=200p + Lgate=400p + Crss=30p + Kres=1 Ldrain drain drainl {Ldrain} Rshunt drainl sourcel {Rshunt} Lsource sourcel source {Lsource} Sw drainl sourcel gmain source swideal

.model swideal vswitch(Ron={Kres*Rdson} +roff=1MEG Von=2.5 Voff=1.5)

*Nonlinear capacitance model Gcnl N101 drainl value={if((V(drainl)-v(n101)) +<0,Cjo*V(201)*(1/Lder),V(201)*(1/Lder)* +(Cjo/((Vdrainl)-V(n101))/Vj)) M)))} Dideal sourcel drainl diode .model Diode D(N=0.001) Rcout N101 sourcel {Rcout*Kres} Lgate gate gatel {Lgate} Rg gatel gmain {Rg} Cgs gmain sourcel {Cgs} Crss drainl gmain {Crss}

*Subcircuit to evaluate the derivative .Param: + Lder=0.01u + Pi=3.14159 .Func Rder(Lder,Fs) {100*2*Pi*Fs*Lder} Gy 0 201 Value={V(N101)-V(drainl)} L1 201 0 {Lder} R1 201 0 {Rder(Lder,Fs)} .EndS MosfetNlc



Figure A1 Experimental Set Up



[1] R. Gutmann, Application of RF circuit design principles to distributed power converters, IEEE Trans. Ind. Electron. Control Instrum., vol. IEC-127, no. 3, pp. 156164, Jun. 1980. [2] R. Redl, B. Molnar, and N. Sokal, Class E resonant regulated dc/dc power converters: Analysis of operations and experimental results at 1.5 MHz, IEEE Trans. Power Electron., vol. PE-1, no. 2, pp. 111120, Apr. 1986. [3] R. Redl and N. Sokal, A 14 MHz 100 Watt class E resonant converter: Principles, design considerations, and measured performance, in Proc.17th Annu. IEEE Power Electron. Spec. Conf., Jun. 1986, pp. 6877. [4] F. Lee, High-frequency quasi-resonant converter technologies, Proc. IEEE, vol. 76, no. 4, pp. 377390, Apr. 1988. [5] W. Bowman, J. Balicki, F. Dickens, R. Honeycutt, W. Nitz, W. Strauss, W. Suiter, and N. Zeisse, A resonant dc-to-dc converter operating at 22 megahertz, in Proc. 3rd Annu. Appl. Power Electron. Conf., 1988, pp. 311. [6] W. Tabisz and F. Lee, Zero-voltage-switching multiresonant technique-a novel approach to improve performance of high-frequency quasiresonant converters, IEEE Trans. Power electron., vol. 4, no. 4, pp. 450458, Oct. 1989. [7] R. Redl and N. Sokal, A new class-e dc/dc converter family with reduced parts count: Derivation, topologies, and design considerations, in Tech. Papers Fourth Int. High Freq. Power Convers. Conf., pp. 395415,1989. [8] J. Jozwik and M. Kazimierczuk, Analysis and design of class-e dc/dc converter, IEEE Trans. Ind. Electron., vol. 37, no. 2, pp. 173183, Apr.1990. [9] H. Koizumi, M. Iwadare, and S. Mori, Class e2 dc/dc converter with second harmonic resonant class e inverter and class e rectifier, in Proc. 3rd Annu. IEEE Appl. Power Electron. Conf., 1994, pp. 10121018. [10] S. Mollov and A. Forsyth, Design and evaluation of a multi-resonant buck converter at 15 MHz, in Proc. Inst. Electr. Eng. Power Electron. Variable Speed Drives, 1998. Seventh Int. Conf., Sep. 2123, 1998, pp. 139144.


[11] J. Rivas, J. Shafran, R. Wahby, and D. Perreault, New architectures for radio-frequency dc/dc power conversion, IEEE Trans. Power Electron., vol. 21, no. 2, pp. 380393, Mar. 2006. [12] J. Rivas, D. Jackson, O. Leitermann, A. Sagneri, Y. Han, and D. Perreault, Design considerations for very high frequency dcdc converters, in Proc. 37th Annu. IEEE Power Electron. Spec. Conf., Jun. 1822, 2006, pp. 111. [13] Y. Lee andY. Cheng, A 580 khz switching regulator using on-off control, J. Inst. Electron. Radio Eng., vol. 57, no. 5, pp. 221226, Sep./Oct. 1987. [14] J.W. Phinney, D. J. Perreault, and J. H. Lang, Radio-frequency inverters with transmissionline input networks, IEEE Trans. Power Electron., vol. 22, no. 44, pp. 11541161, Jul. 2007. [15] J. M. Rivas, Y. Han, O. Leitermann, A. D. Sagneri, and D. J. Perreualt, A high-frequency resonant inverter topology with low-voltage stress, IEEE Trans. Power Electron., vol. 23, no. 4, pp. 17591771, Jul. 2008. [16] J. Phinney, J. Lang, and D. Perreault, Multi-resonant microfabricated inductors and transformers, in Proc. 35th Annu. IEEE Power Electron. Spec. Conf., Jun. 2004, pp. 4527 4536. [17] J. Phinney, D. Perreault, and J. Lang, Radio-frequency inverters with transmission-line input networks, in Proc. 37th Annu. IEEE Power Electron. Spec. Conf., pp.19, Jun. 1822, 2006. [18] J. W. Phinney, Multi-resonant Passive Components for Power Conversion, Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Massachusetts Inst. Technol., Cambridge, MA, Jun. 2005. [19] J. M. Rivas, Radio Frequency dcdc Power Conversion, Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Massachusetts Inst. Technol., Cambridge, MA, Sep. 2006. [20] J. M. Rivas, Y. Han, O. Lietermann, A. Sagneri, and D. J. Perreault, A high-frequency resonant inverter topology with low voltage stress, in Proc. IEEE Power Electron. Spec. Conf., 2007. [21] W. Nitz,W. Bowman, F. Dickens, F. Magalhaes,W. Strauss,W. Suiter, and N. Zeisse, A new family of resonant rectifier circuits for high frequency DCDC converter applications, in Proc. 3rd Annu. IEEE Appl. Power Electron. Conf., 1988, pp. 1222. [22] S. Birca-Galateanu and J.-L. Cocquerelle, Class e half-wave low dv/dt rectifier operating in a range of frequencies around resonance, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 42, no. 2, pp. 8394, Feb. 1995. [23] A. D. Sagneri, The design of a very high frequency dcdc boost converter, Masters thesis, Dept. Elect. Eng. Comput. Sci., Massachusetts Inst. Technol., Cambridge, MA, Feb. 2007.

[24] J. Warren, III, Cell-modulated resonant dc/dc power converter, Masters thesis, Dept. Elect. Eng. Comput. Sci., Massachusetts Inst. Technol.,Cambridge, MA, Aug. 2005. [25] J. R. Warren, III, K. A. Rosowski, and D. J. Perreault, Transistor selection and design of a VHF dcdc power converter, IEEE Trans. Power Electron., vol. 23, no. 1, pp. 2737, Jan. 2008. [26] R. C. Pilawa-Podgurski, Design and evaluation of a very high frequency dc/dc converter, Masters thesis, Dept. Elect. Eng. Comput. Sci., Massachusetts Inst. Technol., Cambridge, MA, Feb. 2007.