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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

A Fast-Response Pseudo-PWM Buck Converter With PLL-Based Hysteresis Control


Yanqi Zheng, Hua Chen, and Ka Nang Leung, Senior Member, IEEE
AbstractHysteresis voltage-mode control is a simple and fast control scheme for switched-mode power converters. However, it is well-known that the switching frequency of a switched-mode power converter with hysteresis control depends on many factors such as loading current and delay of the controller which vary from time to time. It results in a wide noise spectrum and leads to difculty in shielding electro-magnetic interference. In this work, a phase-lock loop (PLL) is utilized to control the hysteresis level of the comparator used in the controller, while not interfering with the intrinsic behavior of the hysteresis controller. Some design techniques are used to solve the integration problem and to improve the settling speed of the PLL. Moreover, different control modes are implemented. A buck converter with proposed control scheme is fabricated using a commercial 0.35- m CMOS technology. The chip area is 1900 m 2200 m. The switching frequency is locked to 1 MHz, and the measured frequency deviation is within 1%. The measured load transient response between 160 and 360 mA is 5 s only. Index TermsBuck converter, hysteresis control, phase-locked loop (PLL).

I. INTRODUCTION

AST transient response is important for high-speed electronic applications [1][4]. Hysteresis voltage-mode control is a simple and straightforward control scheme for switched-mode power converters. Directly operating on the output voltage, the hysteresis voltage-mode control has very fast transient response against load changes and output-voltage spiking. For some other control schemes such as the widely-used pulse-width modulation (PWM) control, it takes several switching cycles, due to the duty-cycle limitation, to recover the output voltage in response to step changes of loading current. In contrast, for hysteresis control, it might take only one switching cycle to complete the same load transient response. It is well-known that the switching frequency of a hysteresiscontrol switched-mode power converter depends on many factors such as loading current, input/output voltage, output capacitance and inductance in the power stage. It is also a strong function of some design values such as the equivalent series resistance (ESR) and the equivalent series inductance (ESL) of the output capacitor, as well as the delay of the comparators in
Manuscript received November 29, 2010; revised March 28, 2011; accepted May 05, 2011. This work was supported by a grant from the Research Grant Council of Hong Kong SAR Government under project CUHK414210. Y. Zheng, H. Chen, and K. N. Leung are with the Department of Electronic Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong SAR. Digital Object Identier 10.1109/TVLSI.2011.2156437

the hysteresis controller, which are difcult to accurately control. In practice, people can only estimate the working frequency but not set the target frequency strictly. Moreover, during operation, the switching frequency is drifted seriously under different loading conditions. The uncertain switching frequency leads to a wide noise spectrum and leads to difculty in shielding electro-magnetic interference (EMI), which is considered as a congenital defect of the hysteresis-control scheme. Therefore, PWM control scheme is generally more preferred than the hysteresis counterparts in many applications. Recently, some ideas have been proposed to regulate the switching frequency of a hysteresis switched-mode power converter, such as the designs reported in [5][14]. In [5], a design articially introduces a small ramp signal that dominates the feedback voltage ripple to control the switching frequency. The designs proposed in [6][9] sense the output-voltage node and the switching node of the inductor in the power stage with some RC lters, and the switching frequency is correlated to the lter parameters. However, the switching frequency cannot be accurately dened and the variations are still very large. The power converter in [10] introduces a ramp signal in the lower boundary of the hysteresis comparator to guarantee a minimum switching frequency under light load. Both designs in [11] and [12] propose to control the delay in the control loop in order to adjust the switching frequency. The design in [13] utilizes a frequency-to-voltage block to control the hysteresis level according to the switching frequency, however, with an extra compensation circuit required. For the work presented in this paper, a hysteresis voltage-mode buck converter will be introduced. A phase-lock loop (PLL) is utilized to control the hysteresis level of the comparator, while not interfere with the intrinsic behavior of the hysteresis controller. The proposed buck converter has the intrinsic fast transient response and its switching frequency in steady state is set by an extra control loop which is controlled by a PLL. As a matter of fact, the design presented in [14] illustrates this concept, however, with no substantiated circuit implementation. This paper focuses on the circuit implementation of the PLL-based hysteresis-control buck converter by considering important circuit design issues. The contributions of the works presented in this paper are: 1) an effective way to use PLL circuit to adjust the hysteresis level to achieve xed-frequency fast-transient buck converter with hysteresis control is developed and 2) a capacitance-reduction method to reduce the capacitance needed for the PLL circuit is implemented and thus all required components of the controller have been successfully implemented on-chip. In Section II, the proposed switching-frequency control loop will be introduced. In Section III, some design techniques are used to solve the

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Fig. 1. Structure of conventional voltage-mode hysteresis control buck converter.

Fig. 2. Waveform of the feedback voltage of the conventional voltage-mode hysteresis control buck converter.

integration problem and to improve the settling speed of the PLL. In addition, a full control system to cover a wide range of the loading is implemented. Additional functions included are pulse-frequency modulation (PFM) control and a standby mode for the light-load scenario. Experimental results will be reported in Section IV. Finally, the conclusion of this paper is presented in Section V. II. SWITCHING FREQUENCY CONTROL LOOP The concept of the proposed design is derived from the basic hysteresis voltage-mode control buck converter, as shown in , lowFig. 1. The power stage consists of high-side switch , inductor , loading capacitor and side switch . and model the ESR and ESL of the loading loading capacitor. is the supply voltage and is the output and that sense voltage. The control circuit consists of output voltage, a hysteresis comparator with hysteresis level and , and some control logic. The feedback voltage is fed into the hysteresis comparator. When is lower than is on and is off, connecting switching node to , and will ramp up. When is higher than is off is on, connecting to the ground, and then and will ramp down. The waveform of is illustrated in Fig. 2. denotes the switching frequency and is the duty cycle. This control scheme directly senses and controls the output voltage, and, in consequence, it has very fast response to sudden changes of the loading and spiking. The control system is also simple in implementation. However, when the input voltage is changed, the switching frequency will also be different. As suggested in [15], the switching frequency of a hysteresis voltage-mode control buck converter can be estimated as (1) where is the delay of the feedback control loop. From (1), it is observed that the switching frequency can be adjusted by ). With this model, the varying the hysteresis boundary (i.e., buck converter can be regarded as a voltage-controlled oscillator is the control voltage. As shown in Fig. 3, a (VCO) where phase detector is introduced to compare the phase difference between the switching signal and a reference clock and then to tune the switching frequency. adjust the control voltage
Fig. 3. Conceptual diagram of the proposed pseudo-PWM voltage-mode hysteresis control.

Fig. 4. Waveform of the feedback voltage of the proposed buck converter.

The whole system can be regarded as a PLL which locks the switching frequency to the reference clock. For instance, when the input voltage is large, the output voltage ramps faster. Thereis set to a higher voltage to guarantee the switching fore, frequency is xed, as shown in Fig. 4. Although the designs reported in [11] and [12] proposed a similar approach to control the signal, both of them control instead of the hysteresis boundary. the switching signal via is usually very large and the ESR However, in practice, of the capacitor is desired to be relatively small. Therefore, acis not a very effective variable to control cording to (1), the switching frequency. On the other hand, can always be is more effective in conchosen with a proper value, and so trolling the frequency under a close scrutiny. With the introduced PLL, the buck converter is actually controlled by two control loops. One is the standard feedback loop

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ZHENG et al.: FAST-RESPONSE PSEUDO-PWM BUCK CONVERTER WITH PLL-BASED HYSTERESIS CONTROL 3

in PFM and uses a RC constant to set up the startup time. The details of the circuit implementation of each part will be given in the following sub-sections. A. PLL Design The switching signal is compared with a reference clock. Their phase difference is detected by the phase detector, which controls the charge pump to charge or discharge the capacitor at the output node. In this design, a variable-gain charge pump is implemented to attenuate slew-rate limit of a constant-gain charge pump. The low-pass lter (LPF) is used to integrate the . In this charge-pump current and convert it into voltage design, an active LPF is implemented to reduce the capacitor is further bounded by an output-bound size. The voltage . The details will be circuit and attenuated before generate explained later. The variable-gain charge pump with phase detector is conveyed in Fig. 7. When the phase difference between the two input signals (i.e., input and Ref) is large, the counter begins to count and increase the charge/discharge current in discrete levels. For situations such as start-up, the variable-gain charge to ramp up pump can charge with larger current, causing faster. The conventional LPF for PLL is shown in Fig. 8. Since usu, the transfer function from to is ally (3) However, in this buck-converter design, the switching frequency is relatively low (about 1 MHz). When using the is very approach shown in Fig. 8, the required value of on chip. The circuit in large and it is difcult to integrate the Low Pass Filter block shown in Fig. 6 uses a capacitance multiplying technique reported in [16] to reduce the size of . For the LPF in Fig. 6, the small-signal expressions can be written as (4) to Since the size ratio of to is also ratio of The equation can be solved as is and the drain current is obtained.

Fig. 5. Mathematically modeled transient response of the proposed pseudo-PWM voltage-mode hysteresis control buck converter.

which consists of hysteresis comparator, and the other loop is controlled by the PLL. As suggested in [13], since the duty cycle is estimated as (2) is the on-resistance of the high-side switch, and where is the series resistance in the inductor. It can be seen that is independent of hysteresis level (i.e., ). Therefore, the introduced PLL does not change the intrinsic behavior of the hysteresis comparator which provides the regulation, fast transient response and robustness. In contrast to the hysteresis comparator control loop with fast response, the PLL loop has relatively slower response, while its main usage is to regulate the switching frequency in the steady state. In Fig. 5, the load transient response of a buck converter with the proposed control scheme is modeled by a mathematical model in MATLAB. It is observed that the hysteresis comparator responses quickly and regulates the output within one switching cycle. In contrast, the PLL loop responds relatively slower. is settled after several cycles and the frequency is not locked instantaneously. During transient, the switching frequency suddenly drops for long charging period for at least one cycle, and slowly recovers eventually. Thus, the dual-loop control guarantees both fast responses in transient as well as robustness in the steady state. III. SYSTEM IMPLEMENTATION In the full-system implementation, in additional of the xedfrequency hysteresis control, or say pseudo-PWM control, a current-mode PFM control and a standby mode (STB) are also implemented and included to the buck converter. When, in lightload condition, in order to reduce switching loss, the system is taken over the control by the PFM scheme. In the ultra-light load condition, the system is switched to the standby mode. The whole system of the buck converter is illustrated in Fig. 6. The system is partitioned into power stage and drivers, zero generator, control circuit and phase-lock loop. The startup operates

(5) Compared with (3), it can be concluded that (6) Therefore, the size of is reduced by a factor of . In this is chosen to be around 200. Since, in this work, design, the system is implemented with a hybrid control scheme, in case that the pseudo-PWM mode is inactive, the output of the ) may diverge to an inappropriate value. The PLL (i.e., when slow loop response impedes prompt recovery of pseudo-PWM mode is active again. To prevent this,

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Fig. 6. Complete system of the proposed pseudo-PWM voltage-mode hysteresis control buck converter (notex : STB

= Standby Mode).

is deliberately bounded between and to generate , where and are dened by a voltage-reference circuit and . As a remark, this approach also helps to settle faster during start up. However, the output bound is expected to be active only when some inter-system transitions happen, and it will not affect the normal operation. Therefore, and are positioned far away from the normal dynamics . of The output bound circuit is shown in Fig. 9, where . When is too low, may shut off, then . The offset current is to prevent from shutting off. When will turn on and will begin to discharge the LPF by , pulling down toward . The size ratio to is designed as 2: 1 to attenuate . This of further helps to reduce the required capacitor size in LPF.

B. Control Block The pseudo-PWM control, as shown in Fig. 6, is simply a hysteresis comparator, which its lower boundary (i.e., ) is set ) is set by a voltage reference and its upper boundary (i.e., by the output of the PLL. It is noted that the control logic block will determine which control mode in the system should be used according to the loading. It is designed that when the loading current is less than around 15 mA, the system is switched to PFM mode control. In the current-mode PFM control, the node will switch to when is lower than the reference voltage. The node will switch to the ground when the sensed . In inductor current is larger than a reference current the standby mode, a hysteresis comparator with xed hysteresis and . Blocks including the clock level is used to compare generator, the PLL, the pseudo-PWM, and PFM control parts are all shut down in the standby mode to save power. The current-limit block compares the sensed inductor current signal (in voltage form: ) with the maximum allowed cur-

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ZHENG et al.: FAST-RESPONSE PSEUDO-PWM BUCK CONVERTER WITH PLL-BASED HYSTERESIS CONTROL 5

Fig. 7. Phase detector and charge pump in the PLL.

Based on the valid condition of the amplier that (7) is simplied and becomes

(8)

Fig. 8. Conventional low-pass lter.

rent. It will turn the high-side switch off in case that the inductor current is too large to avoid damage of the inductor. The deadtime block generates the non-overlapping driving signal from the input. The discontinuous-conduction-mode (DCM) control with the ground to determine whether the block compares inductor current is zero or not. When the inductor current is zero, off and the system will enter the the DCM block turns DCM. The switching signals are fed into the drivers to drive and . C. Zero Generator In general, the ESR of the output capacitor creates a left-halfplane (LHP) zero, which helps to stabilize the system. However, usually, a small ESR capacitor is desired in switched-mode power converter design to reduce the voltage spikes. In that case, the output voltage ripple is very small and the hysteresis power converter may not function properly [17]. To solve this problem, a zero generator is inserted into the feedback path. The zero generator is a typical high-pass lter with gain. It is used to amplify the ripple of the feedback voltage. and are the Fig. 10 shows the zero generator where transconductance and output resistance of the amplier, and and form the feedback network. A parasitic capacitor is added to model the gate capacitance of further stages. The small-signal equation is written as (7)

A LHP zero at is therefore created. Two LHP poles at higher frequency are also generated. One is caused by and the other is caused by . The poles limit the bandwidth of the zero generator, which should be higher than the switching frequency but should not be too high since it will degrade the phase margin of the loop gain. IV. EXPERIMENTAL RESULTS The proposed xed-frequency buck converter with voltagemode hysteresis control is fabricated using AMS 0.35- m technology. The die area is around 1900 m 2200 m. The output bound block occupies around 0.036 mm chip area and consumes around 0.3 mW during normal operation. The chip micrograph is shown in Fig. 11. Extra capacitors are added in the LPF of the PLL for tuning in the testing, and the actual capac3.3 itor utilization is only about 50%. In the chip testing, 1.8 V, 4.7 F and 4.7 H are used. V, An external reference clock of 1 MHz is used. In the real applications, the clock signal can be generated internally. The steady-state pseudo-PWM control in the continuous-conduction mode (CCM) at 200-mA loading is shown in Fig. 12. Both the switching frequency and phase is locked to the reference clock (i.e., 1 MHz). The output voltage ripple is within 40 mV. Fig. 13 shows the pseudo-PWM control in the CCM at 380-mA loading. The output voltage ripple is also within 40 mV. Although the loading current level is greatly different, the switching frequency, phase and duty cycle are kept nearly unchanged. This result reveals a fact that the voltage ripple is not changed much while the switching frequency can be xed. The buck converter operates in the DCM when the loading current is about below 50 mA. The steady-state pseudo-PWM controlled in the DCM at 25-mA loading is shown in Fig. 14. when Slight ringing is observed due to the oating node of

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Fig. 9. Circuit of the output bound.

Fig. 10. Equivalent circuit modelling of the zero generator. Fig. 12. Steady-state waveform in the CCM at 200-mA loading.

Fig. 13. Steady-state waveform in the CCM at 380-mA loading.

Fig. 11. Chip micrograph of the proposed buck converter.

the inductor current approaches to zero. However, the switching frequency still locks to the reference clock. The switching frequency at different loading conditions is measured and plotted in Fig. 15(a) for different loading currents and Fig. 15(b) for different input voltages. With average switching frequency around 1 MHz, the frequency error is within 10 kHz (i.e., 1%), while the frequency variation of

the conventional hysteresis voltage-mode buck converter could be more than 100% as stated in [15] and [18]. This measurement proves the proposed scheme can signicantly reduce the variation of switching frequency of a hysteresis voltage-mode buck converter. The load transient response between 160 and 360 mA is measured and shown in Figs. 16 and 17. Beneting from the intrinsic behavior of the hysteresis control scheme, the response time is 5 s. The measured voltage spike is about 40 mV. The efciency at different loading conditions in the pseudo-PWM mode is measured and plotted in Fig. 18. It is close to 95% up to the loading of 400-mA and drops to 75%

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ZHENG et al.: FAST-RESPONSE PSEUDO-PWM BUCK CONVERTER WITH PLL-BASED HYSTERESIS CONTROL 7

Fig. 14. Steady-state waveform in the DCM at 25-mA loading.

Fig. 16. Measured load transient response for loading changing between 160 and 360 mA.

Fig. 17. Zoom-in view of the measured load transient response for I changing from 160 to 360 mA.

Fig. 18. Measured efciency versus loading current in the pseudo-PWM mode.

V. CONCLUSION
Fig. 15. Measured switching frequency at (a) different loading currents (b) different input voltages.

when the loading is 500 mA. The drop of efciency when the loading is higher than 400 mA is due to large conduction loss occurred at the power stage. Table I summarizes the specications of design.

A pseudo-PWM buck converter with hysteresis control achieved by adjusting the hysteresis level of the comparator using a PLL has been presented in this paper. Some design techniques have been used to solve the integration and settling-speed problem of the PLL. Moreover, different control modes have been implemented and included to the buck converter. The design has been fabricated using AMS 0.35- m technology. The measured load transient response between 160

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TABLE I SUMMARY OF SPECIFICATION OF THE PROPOSED BUCK CONVERTER

[13] A. Mihalka, Fixed frequency hysteretic regulator, U.S. Patent 6 885 175, Apr. 26, 2005. [14] D. Grant, Frequency control of hysteretic power converter by adjusting hysteresis levels, U.S. Patent 6 348 780, Feb. 16, 2002. [15] Texas Instruments, Inc., Dallas, TX, Designing fast response synchronous buck regulators using the TPS5210, , TI Application Report, 1999. [16] M. Toyama, S. Dosho, and N. Yanagisawa, A design of a compact 2 GHz-PLL with a new adaptive active loop lter circuit, in IEEE Sym. VLSI Circuit Dig. Tech. Papers, , 2003, pp. 185188. [17] L. Wong and T. Man, Steady state analysis of hysteretic control buck converters, in Proc. 13th IEEE Int. Power Electron. Motion Control Conf., 2008, pp. 400404. [18] National Semiconductor Corporation, Santa Clara, CA, LM3485 hysteretic PFET buck controller, May 2002. Yanqi Zheng received the B.S. degree in microelectronic technology from the South China University of Technology, Guangzhou, China, in 2004, and the Ph.D. degree from the Department of Electronic Engineering, Chinese University of Hong Kong, Hong Kong, in 2010. From 2004 to 2006, he worked in eWave Integrated Circuit Design House Co., Ltd., GuangZhou, China, as a Design Engineer. He is now a Post-doc Fellow with the Department of Electronic Engineering, Chinese University of Hong Kong. His design interest is power management IC, especially in switching mode power converter design.

and 360 mA is 5 s. The variation of the switching frequency has been proven to be within 1%. REFERENCES
[1] P. Y. Wu, S. Y. S. Tsui, and P. K. T. Mok, Area- and power-efcient monolithic buck converters with pseudo-type III compensation, IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 14461455, Aug. 2010. [2] M. Du and H. Lee, An integrated speed- and accuracy-enhanced CMOS current sensor with dynamically-biased shunt feedback for current-mode buck regulators, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 10, pp. 28042814, Oct. 2010. [3] J. M. Rivas, Y. Han, O. Leitermann, A. D. Sagneri, and D. J. Perreault, A high-frequency resonant inverter topology with low voltage stress, IEEE Trans. Power Electron., vol. 23, no. 4, pp. 17591771, Jul. 2008. [4] R. C. N. Pilawa-Podgurski, A. D. Sagneri, J. M. Rivas, D. I. Anderson, and D. J. Perreault, Very high-frequency resonant boost converters, IEEE Trans. Power Electron., vol. 24, no. 6, pp. 16541665, Jun. 2009. [5] D. J. Skelton and R. K. Miftakhutdinov, Hysteretic regulator and control method having switching frequency independent from output lter, U.S. Patent 6 147 478, Nov. 14, 2000. [6] T. Nabeshima, T. Sato, S. Yoshida, S. Chiba, and K. Onda, Analysis and design considerations of a buck converter with a hysteretic PWM controller, in Proc. IEEE Power Electron. Spec. Conf., 2004, pp. 17111716. [7] Maxim Integrated Products, Sunnyvale, CA, MAX8576-MAX8579 3 V to 28 V input, low-cost, hysteretic synchronous step-down controllers, 2005. [8] G. Schrom, P. Hazucha, J. Hahn, D. Gardner, B. Bloechel, G. Dermer, S. Narendra, T. Karnik, and V. De, A 480 MHz, multi-phase interleaved buck DC-DC converter with hysteretic control, in Proc. IEEE Power Electron. Spec. Conf., 2004, pp. 47024707. [9] M. Castilla, L. G. de Vicuna, J. M. Guerrero, J. Miret, and N. Berbel, Simple low-cost hysteretic controller for single-phase synchronous buck converters, IEEE Trans. Power Electron., vol. 22, no. 4, pp. 12321241, Jul. 2007. [10] H.-H. Huang, C.-L. Chen, and K.-H. Chen, Adaptive window control (AWC) technique for hysteresis DC-DC buck converters with improved light and heavy load performance, IEEE Trans. Power Electron., vol. 24, no. 6, pp. 16071617, Jun. 2009. [11] C. Tso and J. Wu, A ripple control buck regulator with xed output frequency, IEEE Trans. Power Electron., vol. 1, no. 1, pp. 6163, Jan. 2003. [12] F. Su, W.-H. Ki, and C.-Y. Tsui, Ultra fast xed-frequency hysteretic buck converter with maximum charging current control and adaptive delay compensation for DVS applications, IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 815822, Apr. 2008.

Hua Chen received the B.Eng. degree in electronic engineering from the Chinese University of Hong Kong, Hong Kong, in 2010. From 2008 to 2009, he worked for an internship with Advanced Analogic Technologies Inc. as an Assistant Engineer. He is currently working with the Department of Electronic Engineering of the Chinese University of Hong Kong as a Junior Research Assistant. His current research interests include power-management IC and digital controlled power converter.

Ka Nang Leung (S02M03SM08) received the B.Eng., M.Phil., and Ph.D. degrees from The Hong Kong University of Science and Technology, Hong Kong, all in electrical and electronic engineering. His Ph.D. research area was power-management integrated circuits in CMOS technology. He joined the Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong, in September 2005 as an Assistant Professor. He was a Visiting Assistant Professor with the Department of Electrical and Electronic Engineering, The Hong Kong University of Science and Technology. His current research interests include power-management IC for wireless telecommunication systems in nano-scale CMOS technologies, ultra-low-voltage analogue IC, RFIC, and biomedical IC for health care. Prof. Leung was a recipient of a Best Teaching Assistant Award from the Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, in 1996. In 2007 and 2010, he received the Department Exemplary Teaching Awards from The Chinese University of Hong Kong. He received the 2003 Young Scientist Award of the Hong Kong Institution of Science. He is a technical paper reviewer of several IEEE journals and international conferences.