HIGH LEVEL SYNTHESIS

VIJAYA PRAKASH A M

Definition of Synthesis
• Synthesis
– A translation from behavioral description into a structural description – Also called Design Refinement, adds an additional level of detail that provides information needed for the next level of synthesis or for manufacturing of the design

• Synthesis process consist of the following task
– – – – – Compilation Minimization Technology mapping Optimization Transistor sizing

Logic synthesis

control/data flow analysis .read Verilog .timing optimization Technology Dependent Optimizations .basic logic Technology independent Optimizations restructuring .Typical Synthesis Scenario RTL to Network Transformation .physically driven optimizations .test logic insertion 4 .crude measures for goals .improve testability Test Preparation .use logic gates from targ Technology Mapping cell library .

Types of synthesis • Circuit synthesis – Generates a transistor schematic from a set of input-output current. • Logic synthesis – Translates Boolean expression into a netlist of components from a given library of logic gates. voltage and frequency characteristics or equations. b c b c d a’bc + abc + d bc + d d .

memories. (Each Components can be RT descriptions) . • System synthesis – Generates a structure of processors. controllers and interface adapters from a set of system components.Types of synthesis • Register transfer synthesis – Generates two parts  A datapath. which is a storage elements and functional units that performs the given RT  A control unit that control the sequencing of the states in the RT descriptions.

Design Representation • First step in synthesis is compilation of input behavior in into a intermediate graph representation. . Functional Storage and Interconnection Binding. • We perform high level synthesis tasks such as – – – – Scheduling. Unit Selection. Control Generation.

When 2 => A := X +3. A := X +W. End case. Control Flow Representation . 1 2 E X := X +2.Control flow Representation case c is When 1 => X := X +2. A := X +3. A := X +5. A := X +5. When others => A := X +W.

End case. A := X +5.Data flow Representation Read X Case c is When 1 => X := X +2. 1 2 E 2 + 5 3 Read W + 1 + 2 + E Read C Write X Write A Data Flow Representation . When 2 => A := X +3. When others => A := X +W.

Sequencing & Timing Read b Const 1 Read a Signal statement b <= a + 1. a <= b + 1. Statement execute concurrently Write b Write a + + Note: • we must ensure read operation precedes the write operation • • We must ensure that variable values are read before a new value is defined Conversely. a read access of a variable should not be executed before its value is defined. .

+ Write b Read b + Write a .Sequencing & Timing Read a Const 1 Variable statement b := a + 1. a := b + 1.

Compiler Transformation Const 9 Const 1 Const 10 + Write c Constant folding Write c Read a Read b Read a Read b Read a Read b + Write c + Write d Write c + Write d Redundant operator removal .

Flow Graph Transformation • Tree height reduction • CF .DF Transformation • Flattening of CF/DF graph .

Hardware .Specific Transformation • Pattern matching .

Binary Decision Diagrams (BDD) .

Contents • • • Introduction Representation How to build the BDD • • • • Reduced BDD’s Design consideration ITE Algorithm ITE_constant Algorithm .

• Efficient way to represent the formulae • BDD came in as a choice of many application . verification & testing algorithms manipulates large switching formulae.Introduction • Many synthesis.

BDD • BDD’s has penetrated every subfields in the area of Synthesis and Verification • Two properties of BDD’s – Circuit optimization. testing & equivalence checking – Effective in representing the Combinatorial large set • Which has led to stunning break through in FSM equivalence checking & in two level logic optimization. .

etc.Properties of BDDs • • • • Canonicity Compactness (with some exceptions) Fast computation (with some exceptions) Represent a variety of discrete objects – – – – Boolean functions and relations Compositional sets and subsets Partitions of states Encodings and labelings • Facilitate symbolic methods – Two-level minimization – State traversal of FSMs. .

Representation • It can represented as – Minterm – Maxterm – Canonical Form – Non-canonical form .

level representation of the some functions are too large to be practical Passing SOP to POS and vice versa is difficult as a consequence: • • Taking the complement is difficult Taking the AND of the SOP (or OR of POS) is difficult – – Since SOP and POS is non canonical forms. the formulae types known as SOP or POS have been widely used.Representation • • Canonical form makes the equivalence test easy – Has as serious drawback when the no of variables increases Non-Canonical form. answering the equivalence for two functions is difficult Further deciding whether a product of sum is satisfiable is NP .complete (tautology) . – – Two .

BDD
• BDD is DAG (Directed Acyclic Graph)

BDD
S(x) = S(x1, x2, x3)

S(x) = S(x1, x2, x3)

X1 X2
1 0

X2

1

X3

X1 X2 X3

1

0

1

0

A MUX circuit with corresponding BDD

Formal definition of BDD
• The nodes are partitioned into 3 subsets
– Every node has a label v  F – V is a set of internal nodes & its out degree is 2
• T is a Regular Edge & E is a Complement Edge • Function to compute  l(v) FT + l(v)’ FE

– 1 & 0 are terminal nodes with out degree 0

• BDD’s are canonical (for given variable ordering)

How to build the BDD for f BDDs can be built for recursive use of Boole’s expansion example F = abc + b’d + c’d ordering b  c  a  d Fb = ac + c’d Fbc = a Fbca = 1 Fbca’ = 0 Fbc’ = d Fbc’a = 1 Fbc’a’ = 0 Fb’ = d + c’d Fb’c = d Fb’c’ = d Fb’ca = 1 Fb’ca’ = 0 Fb’c’a = 1 Fb’c’a’ = 0 .

How to build the BDD for f f = abc + b’d + c’d Fb = ac + c’d T Fbc = a T b E E Fbc’ = d Fb’ = d + c’d = d c a E Fbca = 1 T Fbca’ = 0 d Fbc’d = 1 T E Fb’d = 0 1 Ordering b  c  a  d 0 .

.Reduced BDD • A non-reduce BDD can be systematically transformed into reduced one – Identification of isomorphic sub-graph – Removal of redundant nodes.

Examples a a a1 b 1 0 1 a2 b2 b1 a1 b1 a2 b2 1 0 1 0 F=a a F = ab a b 0 1 0 1 0 F = a F = a+b F=a1b1+ a2b2 F=a1b1+a2+b2 .

Known Representations • • • • Truth table SoP and PoS Decision tree Reduced decision tree – BDD – Zero-Suppressed BDD – BDD with complement edges .

and PoS x1 0 0 0 0 1 1 1 1 x2 0 0 1 1 0 0 1 1 x3 0 1 0 1 0 1 0 1 F 0 0 0 1 0 1 0 1 • Sum-of-products F = x1’x2x3 + x1x2’x3 + x1x2x3 • Product-of-sums F = (x1+x2+x3) & (x1+x2+x3’) & (x1+x2’+x3) & (x1’+x2+x3) & (x1’+x2’+x3) . SoP.Truth Table.

Truth Table and Decision Tree x1 0 x2 0 x3 0 F 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 x2 0 1 0 0 x1 1 x2 1 x3 1 0 1 0 1 x3 0 0 1 0 0 0 x3 10 1 x3 0 1 .

g.Variable Ordering – Assign arbitrary total ordering to variables • e. x1 < x2 < x3 – Variables must appear in ascending order along all paths OK Not OK x1 x2 x3 x3 x1 x3 x2 x1 x1 x1 Properties   No conflicting variable assignments along path Simplifies manipulation ..

z ) .y. Fx = F( 1.Shannon Expansion • A boolean function can be expanded with respect to any variable F( x.z ).y.z ) = x’ & Fx’ + x & Fx where Fx’ and Fx are positive (negative) cofactors Fx’ = F( 0.y.

Reduction Rule #1 Merge equivalent leaves a a a x1 x2 x3 0 0 0 x3 1 0 x3 1 0 x2 x3 1 x3 x2 x3 0 x1 x2 x3 1 x3 .

Reduction Rule #2 Merge isomorphic nodes x x x x x x y z y z y z x1 x2 x3 x3 0 x2 x3 1 x3 x2 x3 0 x1 x2 x3 1 .

Reduction Rule #3 Eliminate Redundant Tests x y y x1 x2 x3 0 x2 x3 1 0 x2 x1 x3 1 .

if variable ordering x1 < x2 < x3 < … < xn is given function Build ( F. return CreateNode ( i. i ) if ( i > n ) if (F == 0) return Node0 else return Node1. 1). v1 = Build ( Fx . v0. i+1 ). . v1 ). else v0 = Build ( Fx. i+1 ).Building Already Reduced Tree Build a reduced tree for F by calling Build( F.

Fx ) ) return the existing node. Fx ). return the new node. Fx ) if (Fx == Fx ) return Fx. Fx. Fx. Fx. . else Insert( Var. else if ( CheckExists( Var.Creating a Unique Node assuming there is a node table with functions CheckExists() and Insert() function CreateNode( Var.

the use of attribute edges should be constrained .Complement Edges • BDD edges can carry attributes • Using complementation as an attribute for edges saves BDD nodes and makes NOT a constant time operation • To maintain canonicity.

Equivalent Pairs of Functions x x x x x x x x .

Representing Circuit Functions • Functions – All outputs of 4-bit adder – Functions of data inputs A A D D S3 Cout a3 a3 b3 b 3 a2 b2 b 2 a1 b1 b 1 a0 b0 1 S2 a2 b3 b3 a2 b2 b2 a1 b1 b1 a0 b0 0 C o u t S S1 b 2 b2 a1 B S0 b 1 b1 a0 Shared Representation   Graph with multiple roots 31 nodes for 4-bit adder  571 nodes for 64-bit adder growth  Linear .

Effect of Variable Ordering a1 b1 a2 b2 a3 b3 Good Ordering a1 b1 a2 b2 a3 b3 0 1 a3 Bad Ordering a1 a2 a3 a3 a2 a3 b1 b1 b1 b1 b2 b2 b3 0 1 Linear Growth Exponential Growth .

BDD .Ordering (Better result) f = abc + b’d + c’d b T E E c T a T E T d E 1 0 Ordering b  c  a  d .

Reduced BDD f b c d a 1 0 1 a d d 0 c d 0 1 0 1 1 0 .

Reduced BDD f b c d d d 0 1 0 1 c d 0 a 1 0 1 a 1 0 .

Reduced BDD f b c d d c d 0 1 0 a 1 0 1 a 1 0 .

Reduced BDD f b c d d d 0 1 0 a 1 0 1 a 1 0 .

Reduced BDD f b c d d d 0 1 0 a 1 0 1 a 1 0 .

Reduced BDD f b c d d 1 0 1 d 0 a 1 0 .

Reduced BDD f b c a 1 0 1 d 0 1 d 0 .

Reduced BDD f = abc + b’d + c’d b T E E c T a T E T d E 1 0 .

• The size of the BDD is exponential in the number of variables in the worst case • The logical AND & OR of BDDs have the same complexity • Both satisfiability and tautology can be solved in constant time.The reduced ordered BDD (ROBDD) is a canonical form. the reduced graph for a function is unique.Properties of ROBDD • Given an ordering. • Covering problem can be solved in linear time .

if we want to implement a PLA. . Finding good ordering is not always simple. More constraint function of covering problem fall into this category • In some cases SOP/POS forms are closer to the final implementation of a circuit.Properties of ROBDD On the other side • BDD sizes depends on the ordering. For instance. we need to generate at some point a SOP or POS form. • There are functions for which the SOP or POS representation are more compact than the BDDs.

If-Then-Else Operation • Concept – Basic technique for building OBDD from logic network or formula. E   Functions over variables X Represented as OBDDs Result  OBDD representing composite function (I T)  (I  E) Implementation   Combination of depth-first traversal and dynamic programming. I T. T.  . E I X T E 1 MUX 0 Arguments I. Worst case complexity product of argument graph sizes.

F) = ITE (F. Gv’ + F’v’ .Gv’. G + F’ . Hv) + v’. G. 0) = ITE (G.Gv. H)v + v’ .H = v .G + F’. Hv).F) = F .ITE Algorithm ITE (F. ITE(Fv’. 1. Hv’) = (v. ITE(Fv. H) = F. (F . (F . G. Hv’)) Terminal case recursions are ITE (1. G + F’ . H)v’ = v . G) = ITE (0. (Fv .F. (Fv’ . Gv + F’v . F.

B2 A3.B2 A6.B2 A5.B5 A3.If-Then-Else Execution Example Argument I A1 a A2 b c A6 A3 d A4 0 1 A5 B2 d B3 0 c B5 Argument T 1 Argument E a B1 Recursive Calls A1.B3 A5.B4 • Optimizations – Dynamic programming – Early termination rules .B1 A2.B4 1 B4 A4.B2 A6.

B4 – Recursive calling structure implicitly defines unreduced BDD – Apply reduction rules bottom-up as return from recursive calls • Generates reduced graph .B2 A6.B2 A5.B2 A6.B1 A2.If-Then-Else Result Generation Recursive Calls A1.B5 A3.B2 A3.B3 A5.B4 0 d 1 b c 1 c 1 Without Reduction a With Reduction a C6 C5 b C4 c C3 d C1 0 1 C2 A4.

H) if (in_computed_table){ return(result) } v = TOP_VARIABLE(F.H).H) { (result.Gv’. Hv) E = ITE(Fv’.ITE Algorithm ITE (F. H) if (terminal_case){ return (result) } result. G. G.Gv. terminal_case) = TERMINAL_CASE(F. E) INSERT_COMPUTED_TABLE((F.G. T. Hv’) if (T = E) Return (T) R = FIND_OR_ADD_UNIQUE_TABLE(v. H) T = ITE(Fv.G. G. in_computed_table) = COMPUTED_TABLE_HAS_ENTRY(F. R) return ( R ) } } .

H).Gv. in_computed_table) = COMPUTED_TABLE_HAS_ENTRY(F.ITE_CONSTANT Algorithm ITE_CONSTANT (F. H) T = ITE_CONSTANT (Fv. terminal_case) = TERMINAL_CASE(F. G.G.Gv’. Hv’) if (T  E) return non_constant INSERT_COMPUTED_TABLE((F. T) return ( T ) } } . G. H) if (terminal_case){ return (result) } result.G. H) if (in_computed_table){ return(result) } v = TOP_VARIABLE(F.H) { (result. G. Hv) if (T  0 and T  1) Return non_constant E = ITE_CONSTANT (Fv’.

…) – Symbolic Simulation (CMU. Fujitsu. Torino. Synopsys. …) – FSM equivalence (Bull. Colorado. MCC. Bull. NTT) • Test – False path identification (TI) . …) – State minimization (UCB) – Sum-of-Products minimization (UCB. Synopsys. Utah) – Symbolic Model Checking (CMU. Motorola. Siemens. …) • Synthesis – Don’t care set representation (UCB. Fujitsu.Digital Applications of BDDs • Verification – Combinational equivalence (UCB. UCB.

What’s Good about OBDDs • Powerful Operations – Creating. manipulating. testing – Each step polynomial complexity • Graceful degradation – Maintain “closure” property • Each operation produces form suitable for further operations • Generally Stay Small Enough – Especially for digital circuit applications – Given good choice of variable ordering • Weak Competition – No other method comes close in overall strength – Especially with quantification operations .

What’s Not Good about OBDDs • Doesn’t Solve All Problems – Can’t do much with multipliers – Some problems just too big – Weak for search problems • Must be Careful – Choose good variable ordering • Critical effect on efficiency • Must have insights into problem characteristics • Dynamic reordering most promising workaround – Some operations too hard • Must work around limitations .