TMS320C6713 Assembly Language

General DSP System Block Diagram
Internal Memory
Internal Buses

External Memory

Central Processing Unit

P E R I P H E R A L S

What are the typical DSP algorithms?
The Sum of Products (SOP) is the key element in most DSP algorithms:
Algorithm Finite Impulse Response Filter Equation

y ( n) =

∑a
k =0 M

M

k

x(n − k )

Infinite Impulse Response Filter

y ( n) =

∑a
k =0

k

x ( n − k )+

∑b
k =1

N

k

y (n − k )

Convolution

y ( n) =

∑ x ( k ) h( n − k )
k =0

N

Discrete Fourier Transform

X (k ) =

∑ x(n) exp[− j(2π / N )nk ]
n =0
N −1

N −1

Discrete Cosine Transform

F (u ) =

⎡ π ⎤ c(u ). f ( x). cos ⎢ u (2 x + 1)⎥ ⎣ 2N ⎦ x =0

So let’s write the code for this algorithm and at the same time discover the C6713 architecture.Implementation of Sum of Products (SOP) It has been shown that SOP is the key element for most DSP algorithms... N Y = ∑ an * xn n = 1 = a1 * x1 + a2 * x2 +. (1) Multiplication (2) Addition Therefore two basic instructions are required . + aN * xN Two basic operations are required for this algorithm.

+ aN * xN Two basic operations are required for this algorithm..Implementation of Sum of Products (SOP) So let’s implement the SOP algorithm! The implementation in this module will be done in assembly. N Y = ∑ an * xn n = 1 = a1 * x1 + a2 * x2 +. (1) Multiplication (2) Addition Therefore two basic instructions are required ..

+ aN * xN The multiplication of a1 by x1 is done in assembly by the following instruction: MPY a1..Multiply (MPY) N Y = ∑ an * xn n = 1 = a1 * x1 + a2 * x2 +. x1..M” . Y This instruction is performed by a multiplier unit that is called “.

.M .M The .Multiply (.M unit) 40 Y = ∑ an * xn n = 1 . M unit performs multiplications in hardware MPY . Y Note: 16-bit by 16-bit multiplier provides a 32-bit result.M a1. 32-bit by 32-bit multiplier provides a 64-bit result. x1.

Addition (.?) 40 Y = ∑ an * xn n = 1 .M . prod.? MPY ADD .M .? . x1.M . prod Y.? a1. Y .

M .Add (.L a1. x1.M . prod Y. prod.M .L unit) 40 Y = ∑ an * xn n = 1 . Y RISC processors such as the C6000 use registers to hold the operands. so lets change this code. .L MPY ADD .L .

M . Y A15 32-bits Let us correct this by replacing a. prod Y. prod and Y by the registers as shown above. . a1 x1 40 Y = ∑ an * xn n = 1 . prod. x.L a1.L .A Register File A A0 A1 A2 A3 prod Y . x1.L MPY ADD . .M . .Register File .M .

L MPY ADD . a1 x1 40 Y = ∑ an * xn n = 1 . . A3.L .M . A3 A4.L A0. A1. A4 A15 32-bits The registers A0.M . . . A1. A3 and A4 contain the values to be used by the instructions.Specifying Register Names Register File A A0 A1 A2 A3 prod Y .M .

.M .Specifying Register Names Register File A A0 A1 A2 A3 prod Y .L A0. A1. A3 A4.L . a1 x1 40 Y = ∑ an * xn n = 1 . A4 A15 32-bits Register File A contains 16 registers (A0 -A15) which are 32-bits wide.M .M .L MPY ADD . A3. . .

.L .M .M . . a1 x1 Q: How do we load the operands into the registers? .L A15 32-bits .Data loading Register File A A0 A1 A2 A3 prod Y .

L . .D .L . .M . A15 32-bits Data Memory .Load Unit “.D A: The operands are loaded into the registers by loading them from the memory using the . a1 x1 Q: How do we load the operands into the registers? .D unit.D” Register File A A0 A1 A2 A3 prod Y .M .

.L . a1 x1 It is worth noting at this stage that the only way to access memory is through the .D unit.D A15 32-bits Data Memory .M . .D” Register File A A0 A1 A2 A3 prod Y .L .D .M . .Load Unit “.

M .D A15 32-bits Data Memory .L .Load Instruction Register File A A0 A1 A2 A3 prod Y . .L .D . .M . a1 x1 Q: Which instruction(s) can be used for loading operands from the memory to the registers? .

D A: The load instructions.L .M .LDW.M . . LDH. . a1 x1 Q: Which instruction(s) can be used for loading operands from the memory to the registers? .Load Instructions (LDB.L . A15 32-bits Data Memory .LDDW) Register File A A0 A1 A2 A3 prod Y .D .

Also the addresses are 32-bit wide. Data address 00000000 00000002 00000004 00000006 00000008 FFFFFFFF 16-bits . which means that each byte is represented by a unique address.Using the Load Instructions Before using the load unit you have to be aware that this processor is byte addressable.

16-bits FFFFFFFF Data a1 x1 prod Y address 00000000 00000002 00000004 00000006 00000008 .Using the Load Instructions The syntax for the load instruction is: LD *Rn.Rm Where: Rn is a register that contains the address of the operand to be loaded and Rm is the destination register.

Using the Load Instructions The syntax for the load instruction is: LD *Rn.Rm The question now is how many bytes are going to be loaded into the destination register? Data a1 x1 prod Y address 00000000 00000002 00000004 00000006 00000008 FFFFFFFF 16-bits .

Using the Load Instructions The syntax for the load instruction is: LD *Rn. is that it depends on the instruction you choose: • LDB: loads one byte (8-bit) • LDH: loads half word (16-bit) • LDW: loads a word (32-bit) • LDDW: loads a double word (64-bit) Data a1 x1 prod Y address 00000000 00000002 00000004 00000006 00000008 Note: LD on its own does not exist.Rm The answer. FFFFFFFF 16-bits .

gives A7 = 0x00000201 (3) LDW *A5. gives A7 = 0x04030201 (4) LDDW *A5.A7. A7 .A7.A7:A6. gives A7 = 0x00000001 (2) LDH *A5.Using the Load Instructions The syntax for the load instruction is: LD *Rn.Rm Example: If we assume that A5 = 0x4 then: (1) LDB *A5. gives A7:A6 = 0x0807060504030201 Data 1 0xA 0xC 0x2 0x4 0x6 0x8 0 0xB 0xD 0x1 0x3 0x5 0x7 address 00000000 00000002 00000004 00000006 00000008 FFFFFFFF 16-bits .

D unit. how can we load the register pointer Rn in the first place? Data 0xA 0xC 0x2 0x4 0x6 0x8 0xB 0xD 0x1 0x3 0x5 0x7 address 00000000 00000002 00000004 00000006 00000008 FFFFFFFF 16-bits .Using the Load Instructions The syntax for the load instruction is: LD *Rn.Rm Question: If data can only be accessed by the load instruction and the .

A5 How many bits represent a full address? 32 bits So why does the instruction not allow a 32-bit move? All instructions are 32-bit wide (see instruction opcode).? a.Loading the Pointer Rn The instruction MVKL will allow a move of a 16-bit constant into a register as shown below: MVKL (‘a’ is a constant or label) . .

A5 ah (‘a’ is a constant or label) Finally. A5 .? a. A5 a. to move the 32-bit address to a register we can use: MVKL MVKH a. MVKH .Loading the Pointer Rn To solve this problem another instruction is available: MVKH ah al x a A5 eg.

Wrong . A5 MVKH 0x1234FABC. look at the following examples: Example 1 A5 = 0x87654321 MVKL 0x1234FABC. A5 A5 = 0xFFFFFABC (sign extension) A5 = 0x1234FABC . OK Example 2 MVKH A5 = 0x12344321 0x1234FABC. A5 MVKL 0x1234FABC.Loading the Pointer Rn Always use MVKL then MVKH. A5 A5 = 0xFFFFFABC .

A4 .L . MVKL MVKH pt1. A0 *A6.M . A3. A6 pt2. A6 . A5 pt2.L *A5.L . A1 A0.M .D .D . A5 pt1. . A1. .D .D MVKL MVKH LDH LDH MPY ADD A15 32-bits pt1 and pt2 point to some locations Data Memory in the data memory.LDH. A3 A4.M . MVKL and MVKH Register File A A0 A1 A2 A3 A4 a x prod Y . .

L pt1.D . A3 A4. i. A5 pt2. A6 pt2. A4 . A5 pt1.Creating a loop So far we have only implemented the SOP for one tap only.M . A1 A0. A1. Y= a1 * x1 So let’s create a loop so that we can implement the SOP for N Taps.D . MVKL MVKH MVKL MVKH LDH LDH MPY ADD . A6 *A5.e. A0 *A6. A3.

i. Y= a1 * x1 So let’s create a loop so that we can implement the SOP for N Taps. . With the C6000 processors there are no dedicated instructions such as block repeat.Creating a loop So far we have only implemented the SOP for one tap only. The loop is created using the B instruction.e.

5. Make the branch conditional based on the value in the loop counter. Add a branch instruction. Add an instruction to decrease the loop counter. 2. . B.What are the steps for creating a loop 1. 4. Create a label to branch to. Create a loop counter. 3.

A3. A6 loop LDH LDH MPY ADD . A0 *A6.D .1. A4 .L *A5.M . A6 pt2. A1 A0. Create a label to branch to MVKL MVKH MVKL MVKH pt1. A1.D . A3 A4. A5 pt2. A5 pt1.

A5 pt2. A1 A0. A6 loop LDH LDH MPY ADD B . A6 pt2. B.D . Add a branch instruction.M .D . A1. A0 *A6.L . A4 loop . MVKL MVKH MVKL MVKH pt1. A3.2. A3 A4. A5 pt1.? *A5.

A4 loop A15 32-bits Data Memory .S .L .D MVKL MVKH loop LDH LDH MPY ADD B .M . A6 .D . A1.D . A5 pt1.D .L . A5 pt2. A3 A4.M .S .Which unit is used by the B instruction? Register File A A0 A1 A2 A3 prod Y .L . . A3. a x MVKL MVKH pt1.L .D .M .M . A1 A0.D .L . .? *A5. A0 *A6.M . A6 pt2.

A6 . .S pt1.M .S . a x MVKL .D .Which unit is used by the B instruction? Register File A A0 A1 A2 A3 prod Y .M .L . A1. A0 *A6.S MVKH . A6 pt2. A1 A0.D .L .S . .L .S loop LDH LDH MPY ADD B .M .S *A5. A3 A4. A5 pt1. A5 pt2.S MVKH . A3.D MVKL . A4 loop A15 32-bits Data Memory .D .D .M .M .D .L .L .

Register File A A0 A1 A2 A3 prod Y .3. A0 *A6. A4 loop .S MVKH .M .L .D .D .D MVKL . Create a loop counter.M . A6 pt2. .D .S loop LDH LDH MPY ADD B .D .L . . A1.S MVKL .L .M .L . A3 A4. A3. A5 pt2.S .S pt1. A6 count.S MVKH .L . A1 A0. a x MVKL .S .M .M . A5 pt1.D .S A15 32-bits B0 registers will be introduced later Data Memory . B0 *A5.

4.D .L .M .L . A3 A4.M .S MVKH . A1.L . A6 count.S MVKL .S pt1.S . A0 *A6. 1. B0 loop . A4 B0. .M .D .D MVKL .S .L .S MVKH . A6 pt2.M . A1 A0. A5 pt2. . a x MVKL .L .S .M . Decrease the loop counter Register File A A0 A1 A2 A3 prod Y .D . A3.S loop LDH LDH MPY ADD SUB B .S A15 32-bits Data Memory .D . B0 *A5. A5 pt1.D .

B0. B1.5. (2) Any instruction can be conditional. [B1] B loop Instruction Label (1) The condition can be one of the following registers: A1. .g. Make the branch conditional based on the value in the loop counter What is the syntax for making instruction conditional? [condition] e. A2. B2.

branch if B0 = 0 loop .branch if B0 != 0 Instruction Label .5. Make the branch conditional based on the value in the loop counter The condition can be inverted by adding the exclamation symbol “!” as follows: [!condition] e. [!B0] [B0] B B loop .g.

A3.S1 pt1.L . A6 MVKH . 1.D . A1.L .M . B0 loop A15 32-bits Data Memory . . A0 *A6.M .M .5. A1 A0.M .L . . A4 B0.S1 pt2.D .D .S1 pt2. a x MVKL .L .M .L . B0 loop LDH LDH MPY ADD SUB [B0] B .S *A5. A3 A4. A6 MVKL . A5 MVKH .D .S1 pt1.D MVKL .S2 count.D .S . A5 .S . Make the branch conditional Register File A A0 A1 A2 A3 prod Y .S .

S1 label Relative branch. 32-bit B Case 1: 21-bit relative address B . Label limited to +/. Therefore the label must have a dynamic range of less than 32-bit as the instruction B has to be coded.More on the Branch Instruction (1) With this processor all the instructions are encoded in a 32-bit. .220 offset.

S2 ONLY! . This will allow a dynamic range of 232.More on the Branch Instruction (2) By specifying a register as an operand instead of a label.S2 5-bit register code register Absolute branch. it is possible to have an absolute branch. 32-bit B Case 2: B . Operates on .

S1 pt1. B0 loop LDH LDH MPY However.M .S2 count.S1 pt1.S .Testing the code MVKL .D .S *A5. A4 B0. A3.D . A6 MVKL . A1 A0. 1.S1 pt2. we would like to perform: a0*x0 + a1*x1 + a2*x2 + … + aN*xN This code performs the following operations: a0*x0 + a0*x0 + a0*x0 + … + a0*x0 . B0 loop ADD SUB [B0] B . A5 MVKH . A1. A0 *A6. A6 MVKH . A3 A4.L .S1 pt2. A5 MVKL .

S2 pt1.S2 pt1.S .L . A1. B0 The solution is to modify the pointers A5 and A6. A0 *A6.S *A5.S2 pt2.D .Modifying the pointers MVKL . A4 B0.D . A1 A0.M . 1. loop LDH LDH MPY ADD SUB .S2 pt2. A3. A5 MVKL . A6 MVKH . B0 loop [B0] B . A5 MVKH .S2 count. A3 A4. A6 MVKL .

Indexing Pointers Syntax *R Description Pointer Pointer Modified No In this case the pointers are used but not modified. R can be any register .

W (32-bit). or B (8-bit).Pre-offset Pointer Modified No No No In this case the pointers are modified BEFORE being used and RESTORED to their previous values.Indexing Pointers Syntax *R *+R[disp] *-R[disp] Description Pointer + Pre-offset . [disp] specifies the number of elements size in DW (64-bit). disp = R or 5-bit constant. R can be any register. . H (16-bit).

Indexing Pointers Syntax *R *+R[disp] *-R[disp] *++R[disp] *--R[disp] Description Pointer + Pre-offset . .Pre-offset Pre-increment Pre-decrement Pointer Modified No No No Yes Yes In this case the pointers are modified BEFORE being used and NOT RESTORED to their Previous Values.

Pre-offset Pre-increment Pre-decrement Post-increment Post-decrement Pointer Modified No No No Yes Yes Yes Yes In this case the pointers are modified AFTER being used and NOT RESTORED to their Previous Values.Indexing Pointers Syntax *R *+R[disp] *-R[disp] *++R[disp] *--R[disp] *R++[disp] *R--[disp] Description Pointer + Pre-offset . .

H.size in DW. .Indexing Pointers Syntax *R *+R[disp] *-R[disp] *++R[disp] *--R[disp] *R++[disp] *R--[disp] Description Pointer + Pre-offset . or B. W. R can be any register. disp = R or 5-bit constant.Pre-offset Pre-increment Pre-decrement Post-increment Post-decrement Pointer Modified No No No Yes Yes Yes Yes [disp] specifies # elements .

A1 A0. B0 loop [B0] B . A6 MVKL . + aN*xN loop LDH LDH MPY ADD SUB .D .L . A0 *A6++.D . A5 MVKH .S1 pt2.S .S1 pt2. B0 This code now performs the following operations: a0*x0 + a1*x1 + a2*x2 + . A3.Modify and testing the code MVKL .S1 pt1. A6 MVKH .S1 pt1.S2 count. A3 A4..M . A1.S *A5++. A5 MVKL .. A4 B0. 1.

B0 This code now performs the following operations: a0*x0 + a1*x1 + a2*x2 + .D ..S1 pt2. A1 A0. A3 A4.L .S1 pt1. A6 MVKH . A1. A4 B0. + aN*xN loop LDH LDH MPY ADD SUB .S2 count.M .S .S .Store the final result MVKL . A0 *A6++. A3.S1 pt2. A5 MVKL .. A6 MVKL . *A7 [B0] B STH .S1 pt1. B0 loop A4.D . A5 MVKH .D *A5++. 1.

B0 loop A4.S1 pt2.S .D *A5++. 1.S .S1 pt2. A6 MVKL .S2 count.S1 pt1. A3. A5 MVKH .S1 pt1. A5 MVKL . A1 A0. A4 B0. A3 A4. *A7 [B0] B STH .M .D .L . A0 *A6++. A6 MVKH . A1. B0 loop The Pointer A7 has not been initialised.Store the final result MVKL . LDH LDH MPY ADD SUB .D .

L . A4 B0. *A7 The Pointer A7 is now initialised. A7 count. B0 *A5++.S1 .S1 pt2. A5 MVKL .M . A5 MVKH . 1. A7 pt3.S1 pt1.D . . A3.S . A3 A4.S . A1 A0.D pt3.S1 . A6 MVKL MVKH MVKL loop LDH LDH MPY ADD SUB [B0] B STH . A0 *A6++.S1 pt2.Store the final result MVKL . A1.S2 .S1 pt1. B0 loop A4. A6 MVKH .D .

A3.S .What is the initial value of A4? MVKL . A1. A5 MVKH .L . A4 B0.S . so it needs to be reset to zero. A5 MVKL . B0 loop A4. A3 A4. A7 pt3. B0 A4 *A5++.D .M . A1 A0.S1 . A7 count. A0 *A6++. A6 MVKL MVKH MVKL ZERO LDH LDH MPY ADD SUB [B0] B STH .L .S1 pt2.S2 .D pt3.S1 pt1.D . 1.S1 pt2. A6 MVKH .S1 .S1 pt1. loop . *A7 A4 is used as an accumulator.

.D1 How can we add more processing power to this processor? Data Memory .L1 .D1 . .L1 .S1 . A15 32-bits .M1 .M1 .S1 .Increasing the processing power! Register File A A0 A1 A2 A3 A4 .

S1 .S1 .M1 .D1 Data Memory . .M1 (1) Increase the clock frequency. (2) Increase the number of Processing units. . A15 32-bits .L1 .Increasing the processing power! Register File A A0 A1 A2 A3 A4 . .L1 .D1 .

S1 .D2 .M2 . B15 Data Memory .M1 . .S1 .L1 .S2 .D1 . this processor has two sides (A and B or 1 and 2) Register File A A0 A1 A2 A3 A4 . .M1 .M2 .D1 . .D2 32-bits Register File B B0 B1 B2 B3 B4 . .L2 .L2 .L1 .S2 .To increase the Processing Power. A15 32-bits .

1. decrement loop count .D1 40. *A7 = Y Note: Assume that A4 was previously cleared and the pointers are initialised. A2 loop A4.L1 . . Y = Y + A3 . loop count . branch . A4 A2. A4.S1 . A1. A1 = x(n) . *A7 . A2 *A5++.M1 . A0 = a(n) .D1 . A2 = 40.S1 . A3 A3. A0 *A6++. A3 = a(n) * x(n) .Code Review (using side A only) Y = ∑ an * xn n = 1 40 MVK loop: LDH LDH MPY ADD SUB [A2] B STH .L1 . if A2 ≠ 0.D1 . A1 A0.

S units.L and . .Let us have a look at the final details concerning the functional units. Consider first the case of the .

32-bit registers.Operands . 40-bit Registers.32/40-bit Register. we have seen that registers are only 32-bit. However. So where do the 40-bit registers come from? . 5-bit Constant Operands can be: 5-bit constants (or 16-bit for MVKL and MVKH).

The registers must be consecutive. The first register must be even and the second odd. . However. there are 3 conditions that need to be respected: The registers must be from the same side. 5-bit Constant A 40-bit register can be obtained by concatenating two registers.32/40-bit Register.Operands .

32/40-bit Register.Operands . 5-bit Constant All combinations of 40-bit registers are shown below: 40-bit Reg odd 8 40-bit Reg odd 8 : even 32 : even 32 A1:A0 A3:A2 A5:A4 A7:A6 A9:A8 A11:A10 A13:A12 A15:A14 B1:B0 B3:B2 B5:B4 B7:B6 B9:B8 B11:B10 B13:B12 B15:B14 .

<dst> 32-bit Reg 5-bit Const < src > 32-bit Reg < src > 40-bit Reg . <dst> instr .L or .S < dst > 32-bit Reg 40-bit Reg .unit <src>.Operands . <src>.32/40-bit Register. <src>. 5-bit Constant instr .unit <src>.

unit <src>.unit <src>. <src>.L or . <src>. 5-bit Constant instr .S < dst > 32-bit Reg 40-bit Reg . <dst> instr . <dst> 32-bit Reg 5-bit Const < src > 32-bit Reg < src > 40-bit Reg .Operands .32/40-bit Register.

unit <src>. <dst> instr .L1 A0. A2 32-bit Reg 40-bit Reg .Operands .unit <src>. 5-bit Constant instr .L or . <dst> 32-bit Reg 5-bit Const < src > 32-bit Reg < src > 40-bit Reg . <src>. <src>. A1.S < dst > OR.32/40-bit Register.

Operands - 32/40-bit Register, 5-bit Constant
instr .unit <src>, <src>, <dst> instr .unit <src>, <src>, <dst> 32-bit Reg 5-bit Const
< src >

32-bit Reg
< src >

40-bit Reg

.L or .S
< dst >

OR.L1 ADD.L2

A0, A1, A2 -5, B3, B4

32-bit Reg

40-bit Reg

Operands - 32/40-bit Register, 5-bit Constant
instr .unit <src>, <src>, <dst> instr .unit <src>, <src>, <dst> 32-bit Reg 5-bit Const
< src >

32-bit Reg
< src >

40-bit Reg

.L or .S
< dst >

OR.L1 ADD.L2 ADD.L1

A0, -5, A2,

A1, B3, A3,

A2 B4 A5:A4

32-bit Reg

40-bit Reg

Operands - 32/40-bit Register, 5-bit Constant
instr .unit <src>, <src>, <dst> instr .unit <src>, <src>, <dst> 32-bit Reg 5-bit Const
< src >

32-bit Reg
< src >

40-bit Reg

.L or .S
< dst >

32-bit Reg

40-bit Reg

OR.L1 ADD.L2 ADD.L1 SUB.L1

A0, -5, A2, A2,

A1, A2 B3, B4 A3, A5:A4 A5:A4, A5:A4

A2 -5. 5-bit Constant instr . B4 A2.L1 SUB.L2 ADD. A1. B3.L or . <dst> instr .32/40-bit Register. A3. B9:B8. B9:B8 .unit <src>.L2 A0.Operands .S < dst > 32-bit Reg 40-bit Reg OR. <src>.L1 ADD.unit <src>. <src>. A5:A4 A2.L1 ADD. A5:A4. A5:A4 3. <dst> 32-bit Reg 5-bit Const < src > 32-bit Reg < src > 40-bit Reg .

B7 To move the content of a control register to another register (A or B) or vice-versa use the MVC instruction.: MVC MVC IFR. e.g. e.: MV MV A0. A0 A0. B0 B6. IRP .Register to register data transfer To move the content of a register (A or B) to another register (B or A) use the move “MV” Instruction.g.

TMS320C6000 Instruction Set .

L Unit ABS ADD AND CMPEQ CMPGT CMPLT LMBD MV NEG NORM NOT OR SADD SAT SSUB SUB SUBC XOR ZERO ADDSP ADDDP SUBSP SUBDP INTSP INTDP SPINT DPINT SPRTUNC DPTRUNC DPSP MPYSP MPYDP MPYI MPYID IDLE .S .D Unit ADD NEG ADDAB (B/H/W) STB (B/H/W) ADDAD SUB LDB (B/H/W) SUBAB (B/H/W) LDDW ZERO MV No Unit Used Note: Refer to the 'C6000 CPU Reference Guide for more details.M ADD ADDK ADD2 AND B CLR EXT MV MVC MVK MVKL MVKH NEG NOT OR SET SHL SHR SSHL SUB SUB2 XOR ZERO ABSSP ABSDP CMPGTSP CMPEQSP CMPLTSP CMPGTDP CMPEQDP CMPLTDP RCPSP RCPDP RSQRSP RSQRDP SPDP ‘C67x .' C6700: Superset of Fixed-Point (by unit) .S .S Unit .M Unit MPY MPYH MPYLH MPYHL NOP SMPY SMPYH .L .M .D . .L .D .

D2 .L2 .'C6x System Block Diagram Memory Internal Buses EMIF .M1 .D1 .S1 .M2 .L1 .S2 Control Regs Ext’l Memory P E R I P H E R A L S Regs (A0-A15) Regs (A0-A15) Regs (B0-B15) Regs (B0-B15) CPU .

Async P E R I P H E R A L S Regs (A0-A15) Regs (A0-A15) Regs (B0-B15) Regs (B0-B15) CPU .D2 .'C6x System Block Diagram Program RAM Addr Internal Buses D (32) EMIF Data Ram .M2 .Sync .S2 Control Regs Ext’l Memory .L1 .S1 .L2 .M1 .D1 .

M . Which support memory loads/stores? .S . How many can perform an ADD? Name them. b.D .Module 1 Exam 1.L . Functional Units a.

Which instructions can be conditional? .2. Which registers can be used as cond’l registers? b. Conditional Code a.

Coding Problems a.3. Move contents of A0-->A1 .

Move contents of A0-->A1 b. Clear register A5 . Coding Problems a. Move contents of CSR-->A1 c.3.

. A2 = A0 * A1 + 10 g.3. Load an unsigned constant (19ABCh) into register A6. If (B1 ≠ 0) then B2 = B5 * B6 f. A2 = A02 + A1 e. Coding Problems (cont’d) d.

Load A7 with contents of mem1 and postincrement the selected pointer. . Coding Problems (cont’d) h.3.