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After drawing it lot o f qestions on that ckt will be asked. 2. Transistor sizing for given rise time and fall time. How do you size it for e qual rise and fall time. 3. Given a function whose inputs are dependent on its outputs. Design a sequenti al circuit. 4. Design a finite state machine to give a modulo 3 counter when x=0 and modulo 4 counter when x=1. 5. Given a boolean equation minimize it. 6. Given a boolean equation draw the transistor level minimum transistor circuit . 7. What is the function of a D-flipflop, whose inverted outputs are connected to its input ? 8. What will you do if you want to drive a large capacitance ? Layout related questions: 1. asked me to layout the 3 input nand gate. 2. Later he asked me to modify it to consume as much less space as we can. 3. He also asked me about the transistor sizing. . What is the difference between a latch and a flip flop. For the same input, ho w would the output look for a latch and for a flip-flop. 2. Finite state machines: (2.1)Design a state-machine (or draw a state-diagram) to give an output '1' when the # of A's are even and # of B's are odd. The input is in the form of a seria l-stream (one-bit per clock cycle). The inputs could be of the type A, B or C. A t any given clock cycle, the output is a '1', provided the # of A's are even and # of B's are odd. At any given clock cycle, the output is a '0', if the above c ondition is not satisfied. (2.2). To detect the sequence "abca" when the inputs can be a b c d. 3. minimize a boolean expression. 4. Draw transistor level nand gate. 5. Draw the cross-section of a CMOS inverter. 6. Deriving the vectors for the stuck at 0 and stuck at 1 faults. 7. Given a boolean expression he asked me to implement just with muxes but nothi ng else. 8. Draw Id Vds curves for mosfets and explain different regions. 9. Given the transfer characteristics of a black box draw the circuit for the bl ack box.

10. Given a circuit and its inputs draw the outputs exact to the timing. 11. Given an inverter with a particular timing derive an inverter using the prev ious one but with the required timing other than the previous one. 12. Change the rise time and fall time of a given circuit by not changing the tr ansistor sizes but by using current mirrors. 13. Some problems on clamping diode s.

What is the output of AND gate in the circuit below, when A and B are as in wav eform? Tp is the gate delay of respective gate.

Explain why & how a MOSFET works Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with incre asing Vgs (b) with increasing transistor width (c) considering Channel Length Mo dulation Explain the various MOSFET Capacitances & their significance Draw a CMOS Inverter. Explain its transfer characteristics Explain sizing of the inverter How do you size NMOS and PMOS transistors to increase the threshold voltage? What is Noise Margin? Explain the procedure to determine Noise Margin Give the expression for CMOS switching power dissipation What is Body Effect? Describe the various effects of scaling Give the expression for calculating Delay in CMOS circuit What happens to delay if you increase load capacitance? What happens to delay if we include a resistance at the output of a CMOS circuit ? What are the limitations in increasing the power supply to reduce delay? How does Resistance of the metal lines vary with increasing thickness and increa sing length? You have three adjacent parallel metal lines. Two out of phase signals pass thro ugh the outer two metal lines. Draw the waveforms in the center metal line due t o interference. Now, draw the signals if the signals in outer metal lines are in phase with each other What happens if we increase the number of contacts or via from one metal layer t o the next? Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, whi ch one would you place near the output? Draw the stick diagram of a NOR gate. Optimize it For CMOS logic, give the various techniques you know to minimize power consumpti on What is Charge Sharing? Explain the Charge Sharing problem while sampling data f rom a Bus Why do we gradually increase the size of inverters in buffer design? Why not giv

e the output of a circuit to one large inverter? In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transisto r with large width? Given a layout, draw its transistor level circuit. (I was given a 3 input AND ga te and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates) Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram Why don't we use just one NMOS or PMOS transistor as a transmission gate? For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD Draw a 6-T SRAM Cell and explain the Read and Write operations Draw the Differential Sense Amplifier and explain its working. Any idea how to s ize this circuit? (Consider Channel Length Modulation) What happens if we use an Inverter instead of the Differential Sense Amplifier? Draw the SRAM Write Circuitry Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes? How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM 's performance? What's the critical path in a SRAM? Draw the timing diagram for a SRAM Read. What happens if we delay the enabling o f Clock signal? Give a big picture of the entire SRAM Layout showing your placements of SRAM Cel ls, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lin es? Why? How can you model a SRAM at RTL Level? What s the difference between Testing & Verification? For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic) What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up? Infineon: 43. How do you tackle coupling when design deep submicron SRAM memories? 44 . Power Optimization Techniques for deep sub micron? Digital Design Interview Questions Give two ways of converting a two input NAND gate to an inverter Given a circuit, draw its exact timing response. (I was given a Pseudo Random Si gnal Generator; you can expect any sequential ckt) What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit? Give a circuit to divide frequency of clock cycle by two Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock) Suppose you have a combinational circuit between two registers driven by a clock . What will you do if the delay of the combinational circuit is greater than you r clock signal? (You can't resize the combinational circuit transistors) The answer to the above question is breaking the combinational circuit and pipel ining it. What will be affected if you do this? What are the different Adder circuits you studied? Give the truth table for a Half Adder. Give a gate level implementation of the s ame.

Draw a Transmission Gate-based D-Latch. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Witho ut inverting the output) How do you detect if two 8-bit signals are same? How do you detect a sequence of "1101" arriving serially from a signal line? Design any FSM in VHDL or Verilog.

Identify the circuit below, and its limitation.

What is the current through the resistor R1 (Ic) ?

Referring to the diagram below, briefly explain what will happ en if the propagation delay of the clock signal in path B is much too high compa red to path A. How do we solve this problem if the propagation delay in path B c an not be reduced ?

What is the function of a D flip-flop, whose inverted output i s connected to its input ?

Design a circuit to divide input frequency by 2.

Design a divide-by-3 sequential circuit with 50% duty cycle.

Design a divide-by-5 sequential circuit with 50% duty cycle.

What are the different types of adder implementations ?

Draw a Transmission Gate-based D-Latch.

Give the truth table for a Half Adder. Give a gate level imple mentation of it.

What is the purpose of the buffer in the circuit below, is it necessary/redundant to have a buffer ?

What is the output of the circuit below, assuming that value o f 'X' is not known ?

Consider a circular disk as shown in the figure below with two sensors mounted X, Y and a blue shade painted on the disk for an angle of 45 de gree. Design a circuit with minimum number of gates to detect the direction of r otation.

Design an OR gate from 2:1 MUX.

Design an XOR gate from 2:1 MUX and a NOT gate

What is the difference between a LATCH and a FLIP-FLOP ?

Latch is a level sensitive device while flip-flop is an edge sensitive device. Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to gli

tches. Latches take less gates (also less power) to implement than flip-flops. Latches are faster than flip-flops.

Design a D Flip-Flop from two latches.

Design a 2 bit counter using D Flip-Flop.

What are the two types of delays in any digital system ?

Design a Transparent Latch using a 2:1 Mux.

Design a 4:1 Mux using 2:1 Muxes and some combo logic.

What is metastable state ? How does it occur ?

What is metastability ?

Design a 3:8 decoder

Design a FSM to detect sequence "101" in input sequence.

Convert NAND gate into Inverter, in two different ways.

Design a D and T flip flop using 2:1 mux; use of other compone nts not allowed, just the mux.

Design a divide by two counter using D-Latch.

Design D Latch from SR flip-flop.

Define Clock Skew , Negative Clock Skew, Positive Clock Skew.

What is Race Condition ?

Design a 4 bit Gray Counter.

Design 4-bit Synchronous counter, Asynchronous counter.

Design a 16 byte Asynchronous FIFO.

What is the difference between an EEPROM and a FLASH ?

What is the difference between a NAND-based Flash and a NOR-ba sed Flash ?

You are given a 100 MHz clock. Design a 33.3 MHz clock with an d without 50% duty cycle.

Design a Read on Reset System ?

Which one is superior: Asynchronous Reset or Synchronous Reset ? Explain.

Design a State machine for Traffic Control at a Four point Jun ction.

What are FIFO's? Can you draw the block diagram of FIFO? Could you modify it to make it asynchronous FIFO ?

How can you generate random sequences in digital circuits?

- digital
- 2012_EC21103
- EE120 Exercise 1
- VLSI Design
- 18
- Lecture05 Gatelevel Layout
- CEN214_Chapter6.ppt
- EC1312 Model Key
- II & III Units
- PART 15-Elec Buk(Final)
- ANALYSIS OF FACTS
- Data Sheet
- Lecture1 Overview
- ch4
- Chapter 4
- 1bit Comparator 90n CMOS Layout Design
- 206 C1 Lab Report
- VTU LD Lab Manual
- 10.1.1.60
- Chapter 6
- Vlsi Lab Mannual
- A3_001B_GIT0754_ZAKIAH
- Basic Gate
- Transistor Sizing
- Lecture1 Overview
- Introduction 2
- Ces 522 Lecture 1 Hierarchical Design
- Gates
- Pre Labs Digital Logic Design
- Digital Electronics Selfnotes

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