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uit.circuit whose output depend on present input as well as previos output is known assequential circuit .

One way of deterniming that a combinital circuit is working properly or not. We apply to circuit all possible input combinitation and compare the resultant output with either the corresponding truth table .or a fault free version of the same circuit .any deviation indicates the presence of some fault .such exaustivetest are very long and detect fault within a circuit or even to locate them by shorter tests . Such tests are referred to as either fault-detection or fault-location tests.

Fault detection:
If test just reveal the presence of a fault.

Fault location test:


If not only reveal the presence of a fault but also locate it. Two technical words are commonly used in the respect of faults. They are a) stuck at zero(s-a-0) b) stuck at one(s-1-0) in desighning fault detection test we shall be considerd only with those faults that cause any wire to be stuck at zero or stuck at one . This restriction for this class of faults can be justified technically.

Since most circuits failures fall in this class.

Fault Detection:
Let x1,x2,x3................xn be the inputs to a combinational circuit in the presence of fault k. As an example consider the circuit may be either stuck at zero (s-a-0) or stuck at one (s-a-1). We shall denote by m0 and m1 the faults of wire m s-a-0 and s-a-1 respectively. Similar notation is used for the other wires. The truth table for this circuit is shown in figure(b). Where coulmn f denotes the fault free output while, for example coulmns f(m0) and f(m1) corresponed ,respectively to the circuit output in the presence of faults m0 and m1 and so on. An input combination is referred to as a test for fault fk if , in response to that input combination, the output of the correctly operating circuit is different from that of the circuit impaired by fault fk . Hence , for example ,the input combination 111 is the only test for detecting the fault , f(m0) in the circuit of figure(c) . Since it is the only input combination for which the value in the coulmn f and f(m0///0 are different . n the other hand , fault f(q1) can be detected by the tests 001,011,and 101 and so on,for other faults. More precisely , an input combination a1,a2,a3,a4.....aN is a test for detecting fault fk if and only if f(a1,a2,a3....aN) fk(a1,a2,a3,.....aN)=1 where f (a1,a2,a3..aN) and fk(a1,a2,a3,.........aN) denote respectively the fault free output and the incorrect output in response to the input a1,a2,a3,....aN .Thus in order to determine all the tests that detect a fault fk , it is necessary to take the modulo-2 sum of coulmn f and fk in the truth table. In the truth table shown in fig (b),we observe that colmn f(m0), f(n0) and f(p0) are identical , and so are coulmns f(p1) and f(q1). In other words , the circuit output in the presence of fault is identical with the output in the presencs of f(q1). Hence there is no input combination which can differentiate fault f(p1). Such faults are called equivalent faults.In general , two faults f1 and f2 are said to equivalent faults if the function realised by the circuit with fault f1, is identical with function realised by the same circuit with fault f2. Faults that are not equivalent are said to be distinguishable faults. The truth table can usually be simplified by combining the coulmn that

correspond to every set of equivalent faults.In the foregoing example coulmn f(p1) and f(q1) may be combined and similarly coulmn f(m0) coulmn f(n0) and f(p0) may be combined . In some situation it may occur that a coulmn fk is identical with the fault free coulmn f. As a result the modulo-2 some of f X-Orfkwill be zero for every input combination and consequently , fault fk can not be detected . Undetectable usually occur in redundant circuit & they may be detected from truth table . If the combine equivalent faults and take and take the modulo-2 sum of coulmn f with all other coulmn which correspond to incorrect outputs ,we obtain the fault table shown in fig(c).A fault table is the table in which there is a row for every possible tests(i.e. input combination) and a coulmn for every fault . A1 is entered at the intersection of the ith row and the jth coulmn can be detected by ith test. The problem of finding a minimal set of rows so that every coulmn has a 1 in tree in at least row of the set. Such a set of rows will be said to cover the fault table .It is evident that the problem of findin a minimal set of rows which cover a fault table is identical with the prime- implicant.

Covering the fault table:


The fault table can now be for the simplified by the removal of unneccessary rows and columns. A column I is said to dominate column I if 1 in at least every row in which j has 1. The dominating column I may be removed ,since any test which detects fault j will also detect fault i. For example , the column corresponding to p1 q1 of fig(c) may be eliminated since it correspond to a test that can always be replaced by test I. Thus for example ,row 010and similarly ,rows 010 100 can be removed because they are equivalent to and hence dominate by row 000 . Clearly row 110 correspond to a test which does not detect any fault and can therefore be removed from table. In order to find smallest cover of the simplified fault table ,the techniques of finding the minimal switching expression may be employed. The essential test are determined by observing which fault can be detected by just a single test additional teat are added until a minimal cover is obtain . In our example there are three essential test, 011,101 and 111 , which detect all faults except q0. A fourth test 000 detect q0 and thus complete

the set of test that detect all single fault in the circuit being tested to a single applicationpf value to the input terminal and a fault detection experiment, which refers to a set of test leading to a definite conclusion as to whether or not the circuit operate correctly for all input combination . In our example the experiment consist of 4 tests as follows (throgh not neccessarily in the order): 1.Apply 011: If the output is T=1 circuit is faulty and the experiment may be stopped ; If T=0 ,apply second test. 2.Apply 101: If T=1,circuit is faulty ; otherwise, apply next test. 3.Apply 111: If T=0 circuit is faulty ; otherwise ,apply next test. 4.Apply 000: If T=0 circuit is faulty ; If T=1 circuit operate correctly.

Fault-Location Expriments:
Distinguished from all other non equivalent faults . we now consider adaptive experiment which are also known as sequential decision procedures , and in which the selection of the next test to be appiled is determined by the circuit response to the previous tests. A convenient way to describe adaptive experiments is by means of adaptive tree.

Adaptive tree:
The adaptive tree is a directed graph whose correspond to the various tests and whose branches correspond to the differnt responses to these test. In particuler , one of the branches emanating from some node Tj is associated with the correct. circuit response to that tests Tj while the other branches is associated with an incorrect response to that tests. these branches will be lable P to indicate pass or correct response and F to indicate failure . the initial branch that enters the first node is associted with all possible faults fo,f1, f3..........fp) where for simplicity we refer to f0,fault free circuit the branches emanating from the first node is associated with subset of fault that may affect the circuit depending on the output of the first test. There

are disjoint subset whose union includes the entire initial set of fault associated with the branch entering in a given node is divided into two disjoint subset associated with the branches leaving that node each such subset contains those faults that failed . The tree terminates when all its end branches starting at the initial branch and terminating at the end branch , is referred to as path in the path . Each path describes a seqence of tests which when applied to the circuit , identifies and locate the fault in its end branch.

Desighing adaptive experiments:


A technical word heuristic should be explained here . Heuristic means taking decision on past experiences .For designing adaptive experiments heuristic approach is applied. Consider the fault table shown in fig(d). If we add to this table a column corresponding to the fault free output . Following the heuristic approach we may choose either t2 or t6 as the first test , since each of theserows has three 1s and four 0s. The tree corresponding to test , t2 taking as first test. In this case the initial set of faults (f0,f1,f2,f3,f4,f5,f6)is divided into two subsets (f1,f3,f5) and (f0,f2,f4,f6). (f1,f3,f5) is the subset that correspond to a test that fails . (f0,f2,f6) is the subset of possible faults. In the second step it is necessary to diffentiate between these two subsets. To differentiate between f1,f3 & f5. We need a test that divides these faults into two subsets.

Fault Tolerant Design:


After detection of fault our next step is to improve reliability of logic networks & to design it so that for special classes of faults , it becomes self-checking or even self-correcting.

The problem:

physical devices used as switching component have non zero probability of failure . As a result in many applications where high reliability is of at most importance, in addition to the selection of high reliable components , special procedures must be employed in order to increase the mean failure time . In many cases digital system cant be repaired , during too short intervals for economic strategic or physical (e.g. system in space) regions, on other hand since recent technologies have contributed towards making component cast & size of design techniques as the use of redundancy & automatic self checking. It seems clear that if a logic network is to perform its logical function & at the same time correct errors , there must be some redundancy either in the inputs to the network is the existence of parity & error correcting digits which do not carry any information . Another way of arriving at circuit with error detection & correction capabilities is by using multiplexing as a basic principle where by each gate is provided by multiple inputs. These inputs must be generated independently so that in one need not imply others. Consequently, redundant, independent logic circuits must exists to generate these inputs. there are several possible strategies to increase the reliability of system . In general these strategies can be subdivided into two basic approaches.

Self-Checking System
In this system is continuously checked for faults . If a fault is detected a stand by unit is activated, replacing faulty one. SYSTEM WITH FAULT MASKING CAPABILITIES In this the fault is masked by additional hardware.

Outline Of Possible Stratigies:


The simplest approach to increase the reliability of circuit is, to test it often enough so that a fault is detected as soon as it hs occured. This can be accomplished either by using error-detecting codes or by attaching to the circuit a special sub-circuit called a checker which automatically checks the circuit as it performs its computation. After fault has been diagonosed & located, it must be isolated to prevent it from aeffecting the entire computation. at this state either a stnd by spare sub system replaces the faulty one, then we say that the system is self-correcting. Another approach, in which,original system is recognised to by pass the faulty module, usually involves some degradation in the perfomance of system, & hence is reffered to as graceful degradation & the corresponding system is called a fail soft system.A fail soft system do not require redundant hardware but they r very difficult to design since they must possess two important prop. First , they must enable rapid fault detection & location ; second they must have the ability to recongrifurate themselves so that the faulty module will be isolate while the degradation in performance will be minimal. In many practical situation one type of failure is more criticalthen another type .eg .If a traffic light control system fails , red lights are preferable to green ones in both directions. The design of system in which no single fault will produce the critical output is reffered to as fail safe design. Whenever a system must not malfunction even in the presence of some faults it become necessary to use fault-tolerant systems . A symple approach to fault tolerant design is to duplicate the system & to compare the outputs

of the two systems . The two systems receive the same data, but only one of the them is controlling the operation while the other serves as a stand by & used for checking purposing only.the outputs of the two systems are fed into a matching circuit which in its simplest form can be an EXCLUSIVE-OR gate . If a mismatch occurs which indicates a fault , the gate produces a signal s which in turn activates diagnostic programs to determine the location of the fault . The fault free unit becomes then the controlling one while the faulty unit is being repaired .

Restoring Organs:
A restoring organ is a logical syructure which st ructure which receives redundant input information & generates more reliable output information & generates more reliable output information . Its main task is to check the redundant inputs & to generate the desired number of independent outputs. A simple restoring organ is a logical structure which receives redundant input information & generates more reliable output information . Its main task is to check the redundant inputs & to generate the desired number of independent outputs . A simple restoring organs which uses straight forward multiplexing is shown in figure . the decesiohn element may be a simple majority gate a vote taker , or a threshold device. It receives R versions of the same inputs & is design to compute R identical versions of the outputs. When the redundancy R element . In this case three identical version of inputs X namely X1,X2 & X3 are fed into majority circuit fault in any one of these input channels will not propagate to the output lines, & thus accepts for fault with in the decision element it self. This scheme corrects

any single circuit failure . Not fault correction is possible e.g. a modulo-2 gate can be used to detect the existence of different inputs. The next obvious step is to improve the reliability of the decision elements themselves by using R identical copies as shown in figure2. The application of this scheme to the design of redundant circuit for f=ab+ab is shown in fig 3. I n practice it is important that the error correction mechnism will not just correct error but will also produce a warning indicating that an error has occured . This can be done by disagreement detector or dissent circuit , as show in fig 5. The circuit produces an output d which is equal to one for all inputs combination except when X1,X2,X3 & M assumes identical values. Thus , d=1 indicates the existence of an error where d=(X1+X2+X3+M)*(X1+X2+X3+M)

Hybrid Redundancy:
A more reliable system organization is the hybrid redundancy. This system in its most general form consists of N=2n+1 identical units and the voter with threshold , which is equal to n+1. Thus the voter produces an output according to the majority of its inputs. In addition , the system consist of spsre stand by units such that , when one of the active units fails a spare is automatically used to replace the faulty one. The swiching out of faulty units and the swiching out of faulty units and the swiching in and swiching units. A hybrid redundancy with triple modular redundancy (TMR) core units and two standby units is in fig6. The disagreement detector associated with each core unit detect if the core unit is different from the output of the voter.

Bibliography1) IEEE transaction on computer , 1972.

Internet Resources1) webopedia.com 2) cc.georgia.edu