You are on page 1of 29

1. What is the maximum size of the memory that can be used in a 16-bit computer and 32 bit computer?

The maximum size of the memory that can be used in a 16-bit computer is 216=64K memory locations. The maximum size of the memory that can be used in a 32-bit computer is 232 =4G memory locations.

2. Define memory access time? The time required to access one word is called the memory access time. Or it is the time that elapses between the initiation of an operation and the completion of that operation.

3. Define memory cycle time? It is the minimum time delay required between the initiation of two successive memory operations. Eg. The time between two successive read operations.

4. When is a memory unit called as RAM? A memory unit is called as RAM if any location can be accessed for a read or write operation in some fixed amount of time that is independent of the locations address.

5. What is MMU? MMU is the Memory Management Unit. It is a special memory control circuit used for implementing the mapping of the virtual address space onto the physical memory.

6. Define memory cell? A memory cell is capable of storing one bit of information. It is usually organized in the form of an array.

7. What is a word line? In a memory cell, all the cells of a row are connected to a common line called as word line.

8. Define static memories? Memories that consists of circuits capable of retaining their state as long as power is applied is called Static memories.

9.What are the Characteristics of semiconductor RAM memories?


They are available in a wide range of speeds. Their cycle time range from 100ns to less than 10ns. They replaced the expensive magnetic core memories. They are used for implementing memories.

10.Why SRAMs are said to be volatile? Because their contents are lost when power is interrupted. So SRAMs are said to be volatile.

11.What are the Characteristics of SRAMs?


SRAMs are fast. They are volatile. They are of high cost. Less density.

12.What are the Characteristics of DRAMs?


Low cost. High density. Refresh circuitry is needed.

13.Define Refresh Circuit? It is a circuit which ensures that the contents of a DRAM are maintained when each row of cells are accessed periodically.

14.Define Memory Latency? It is used to refer to the amount of time it takes to transfer a word of data to or from the memory.

15.what are asynchronous DRAMs? In asynchronous DRAMs, the timing of the memory device is controlled asynchronously. A specialised memory controller circuit provides the necessary control signals RAS and CAS that govern the timing.The processor must take into account the delay in the response of the memory. such memories are asynchronous DRAMs .

16.what are synchronous DRAMs? Synchronous DRAMs are those whose operation is directly synchronized with a clock signal.

17.Define Bandwidth? When transferring blocks of data, it is of interest to know how much time is needed to transfer an entire block. since blocks can be variable in size it is useful to define a performance measure in terms of number of bits or bytes that can be transferred in one second. This measure is often referred to as the memory bandwidth.

18. What is double data rate SDRAMs?

Double data rates SDRAMs are those which can transfer data on both edges of the clock and their bandwidth is essentially doubled for long burst transfers.

19.What is motherboard? Mother Board is a main system printed circuit board which contains the processor. It will occupy an unacceptably large amount of space on the board. 20.What are SIMMs and DIMMs? SIMMs are Single In-line Memory Modules. DIMMs are Dual In-line Memory Modules. Such modules are an assembly of several memory chips on a separate small board that plugs vertically into a single socket on the motherboard.

21.What is memory Controller? A memory controller is a circuit which is interposed between the processor and the dynamic memory. It is used for performing multiplexing of address bits.It provides RAS-CAS timing. It also sends R/W and CS signals to the memory. When used with DRAM chips , which do not have self refreshing capability , the memory controller has to provide all the information needed to control the refreshing process.

22. Differentiate static RAM and dynamic RAM? Static RAM Dynamic RAM They are fast They are slow They are very expensive They are less expensive They retain their state indefinitely They do not retain their state indefinitely They require several transistors They require less no transistors. Low density High density

23. What is Ram Bus technology? The key feature of Ram bus technology is a fast signaling method used to transfer information between chips. Instead of using signals that have voltage levels of either 0 or V supply to represent the logic values, the signals consist of much smaller voltage swings around a

reference voltage, vref. Small voltage swings make it possible to have short transition times, which allows for a high speed of transmission.

24.What are RIMMs? RDRAM chips can be assembled in to larger modules called RIMMs. It can hold upto 16 RDRAMs.

25. What are RDRAMs? RDRAMs are Rambus DRAMs. Rambus requires specially designed memory chips. These chips use cell arrays based on the standard DRAM technology. Multiple banks of cell arrays are used to access more than one word at atime. Circuitry needed to interface to the Rambus channel is included on the chip. Such chips are known as RDRAMs.

26.What are the special features of Direct RDRAMs?


It is a two channel Rambus.. It has 18 data lines intended to transfer two bytes of data at a time. There are no separate address lines.

27. Define ROM? It is a non-volatile memory. It involves only reading of stored data.

28.What are the features of PROM?


They are programmed directly by the user. Faster Less expensive More flexible.

29.Why EPROM chips are mounted in packages that have transparent window?

Since the erasure requires dissipating the charges trapped in the transistors of memory cells. This can be done by exposing the chip to UV light .

30.What are the disadvantages of EPROM? The chip must be physically removed from the circuit for reprogramming and its entire contents are erased by the ultraviolet light.

31.What are the advantages and disadvantages of using EEPROM? The advantages are that EEPROMs do not have to be removed for erasure.Also it is possible to erase the cell contents selectively. The only disadvantage is that different voltages are needed for erasing, writing and reading the stored data.

32.What is cache memory? It is a small, fast memory that is inserted between the larger, slower main memory and the processor. It reduces the memory access time.

33. Differentiate flash devices and EEPROM devices. EEPROM devices Flash devices It is possible to read the contents of a single cell, but it is only possible to write an entire block of cells. Relatively lower density Greater density which leads to higher capacity. Lower cost per bit. Relatively more cost. It is possible to read and write the contents of a single cell.

Consumes less power in their operation and makes it more attractive for use in portable equipments that is battery driven.

Consumes more power.

34.Define flash memory? It is an approach similar to EEPROM technology. A flash cell is based on a single transistor controlled by trapped charge just like an EEPROM cell.

35. What is locality of reference? Analysis of programs shows that many instructions in localized areas of the program are executed repeatedly during some time period., and the remainder of the program is accessed relatively infrequently. This is referred to as locality of reference. This property leads to the effectiveness of cache mechanism.

36. What are the two aspects of locality of reference?. Define them. Two aspects of locality of reference are temporal aspect and spatial aspect. Temporal aspect is that a recently executed instruction is likely to be executed again very soon. The spatial aspect is that instructions in close proximity to a recently executed instruction are also to be executed soon.

37. Define cache line. Cache block is used to refer to a set of contiguous address locations of some size. Cache block is also referred to as cache line.

38.What are the two ways in which the system using cache can proceed for a write operation?

Write through protocol technique. Write-back or copy back protocol technique.

39. What is write through protocol? For a write operation using write through protocol during write hit: the cache location and the main memory location are updated simultaneously. For a write miss: For a write miss, the information is written directly to the main memory.

40.When does a readmiss occur? When the addressed word in a read operation is not in the cache, a read miss occur.

41. What is write-back or copy back protocol? For a write operation using this protocol during write hit: the technique is to update only the cache location and to mark it as updated with an associated flag bit, often called the dirty or modified bit. The main memory location of the word is updated later, when the block containing this marked word is to be removed from the cache to make room for a new block. For a write miss: the block containing the addressed word is first brought into the cache, and then the desired word in the cache is overwritten with the new information.

42.What is load-through or early restart? When a read miss occurs for a system with cache the required word may be sent to the processor as soon as it is read from the main memory instead of loading in to the cache. This approach is called load through or early restart and it reduces the processors waiting period.

43.What are the mapping technique?


Direct mapping Associative mapping Set Associative mapping

44.What is a hit? A successful access to data in cache memory is called hit.

45.Define hit rate? The number of hits stated as a fraction of all attempted access .

46.What are the two ways of constructing a larger module to mount flash chips on a small card?

Flash cards Flash drivers.

47.Describe the memory hierarchy?

48.Define miss rate? It is the number of misses stated as a fraction of attempted accesses.

49.Define miss penalty? The extra time needed to bring the desired information into the cache.

50.Define access time for magnetic disks? The sum of seek time and rotational delay is called as access time for disks. Seek time is the time required to move the read/write head to the proper track. Rotational delay or latency is the amount of time that elapses after the head is positioned over the correct track until the starting position of the addressed sector passes under the read/write head.

51.What is phase encoding or Manchestor encoding? It is one encoding technique for combining clocking information with data. It is a scheme in which changes in magnetization occur for each data bit. It s disadvantage is poor bit-storage density.

52.What is the formula for calculating the average access time experienced by the processor? tave=hc +(1-h)M Where h =Hit rate M=miss penalty C=Time to access information in the cache.

53. What is the formula for calculating the average access time experienced by the processor in a system with two levels of caches? tave =h1c1(1-h1)h2c2+(1-h1)(1-h2)M where h1=hit rate in L1 cache h2=hit rate in L2 cache C1=Time to access information in the L1 cache. C2=Time to access information in the L2 cache.

54.What are prefetch instructions? Prefetch Instructions are those instructions which can be inserted into a program either by the programmer or by the compiler.

55.Define system space? Management routines are part of the operating system of the computer.It is convenient to assemble the OS routines into a virtual address space.

56.Define user space? The system space is separated from virtual address space in which the user application programs reside. The letter space is called user space.

57.What are pages? All programs and data are composed of fixed length units called pages.each consists of blocks of words that occupies contiguous locations in main memory.

58.What is replacement algorithm? When the cache is full and a memory word that is not in the cache is referenced, the cache control hardware must decide which block should be removed to create space for the new block that contains the reference word .The collection of rules for making this decision constitutes the replacement algorithm.

59.What is dirty or modified bit? The cache location is updated with an associated flag bit called dirty bit.

60.What is write miss?

During the write operation if the addressed word is not in cache then said to be write miss.

61.What is associative research? The cost of an associative cache is higher than the cost of a direct mapped cache because of the need to search all 128 tag patterns to determine whether a given block is in the cache. A search of this kind is called an associative search.

62.What is virtual memory? Techniques that automatically move program and datablocks into the physical main memory when they are required for execution are called as virtual memory.

63.What is virtual address? The binary address that the processor used for either instruction or data called as virtual address.

64.What is virtual page number? Each virtual address generated by the processor whether it is for an instruction fetchis interpreted as a virtual page.

65.What is page frame? An area in the main memory that can hold one page is called as page frame.

66.What is Winchester technology? The disk and the read/write heads are placed in a sealed air-filtered enclosure called Winchester technology.

67.What is a disk drive? The electromechanical mechanism that spins the disk and moves the read/write heads called disk drive.

68.What is disk controller? The electronic circuitry that controls the operation of the system called as disk controller.

69.What is main memory address? The address of the first main memory location of the block of words involved in the transfer is called as main memory address.

70.What is word count? The number of words in the block to be transferred.

71.What is Error checking? It computes the error correcting code (ECC)value for the data read from a given sector and compares it with the corresponding ECC value read from the disk.

72.What is booting? When the power is turned on the OS has to be loaded into the main memory which takes place as part of a process called booting.To initiate booting a tiny part of main memory is implemented as a nonvolatile ROM.

73.What are the two states of processor?


Supervisor state User state.

74.What is lockup-free? A cache that can support multiple outstanding misses is called lockup-free.

75.Draw the static RAM cell?

PART-B

1. Write notes on semiconductor RAM memories.


Internal organization of memory chips Static memories Asynchronous DRAMs Synchronous DRAMs Structure Of Larger Memories Memory System Considerations Rambus Memory

2. Write notes on various types of ROMs.


ROM PROM EPROM EEPROM Flash Memory

3. What are the various types of cache mapping mechanisms? Explain in detail.

Direct mapping Associative mapping Set Associative mapping

4. Write notes on secondary storage devices.


Magnetic hard disks Floppy disks Optical disks DVD Magnetic tape systems

5. Write notes on Virtual memories.


Address Translation Diagram Explanation

6. What are the various techniques used to improve the performance of cache. Explain it.

Reducing the miss rate Reducing the miss penalty Reducing the miss rate or miss penalty using parallelism Reducing the time to hit in a cache

7. Explain with neat diagram the internal organization of bit cells in a memory chip.

Hints: Memory cells are usually organized in the form of an array, in which each cell is capable of storing one bit of information. Each row consists a memory word, and all cells of a row are connected to a common line referred to as word line, which is driven by he address decoder on the chip.

8. Discuss the virtual memory management technique in detail

Hints: The data is to be stored in physical memory locations that have addresses different from those specified by the program. The memory control circuitry translates the address specified by the program into an address that can be used to access the physical memory.

9. What is memory interleaving? Explain with neat diagram.

Hints: The main memory of a computer is structure as a collection of physically separate modules each with its own address buffer register and data buffer register, memory access operations may proceed in more than one module at the same time. Thus the aggregate rate of transmission of words to and from the main memory system can be increased.

10.Write brief notes on Optical Disks

CD Technology CD-ROM CD-Recordables CD-Rewritables DVD Technology DVD-RAM

11. Explain in detail Magnetic Hard Disks

Organization And Accessing Of Data On A Disk Access Time Typical Disks Data Buffer/Cache Disk Controller Software And Operating System Implications

Floppy Disks Raid Disk Arrays Commodity Disk Considerations

12. Write notes on Performance Considerations

Interleaving Hit Rate And Miss Penalty Caches On Processor Chip Other Enhancements

16 Marks 1. Write notes on semiconductor RAM memories. Internal organization of memory chips Static memories Asynchronous DRAMs Synchronous DRAMs Structure Of Larger Memories Memory System Considerations Rambus Memory

2. Write notes on various types of ROMs. ROM PROM EPROM EEPROM

Flash Memory

3. What are the various types of cache mapping mechanisms? Explain in detail. Direct mapping Associative mapping Set Associative mapping

4. Write notes on secondary storage devices. Magnetic hard disks Floppy disks Optical disks DVD Magnetic tape systems

5. Write notes on Virtual memories. Address Translation Diagram Explanation

6. What are the various techniques used to improve the performance of cache. Explain it.

Reducing the miss rate Reducing the miss penalty Reducing the miss rate or miss penalty using parallelism Reducing the time to hit in a cache

7. Explain with neat diagram the internal organization of bit cells in a memory chip.

Hints: Memory cells are usually organized in the form of an array, in which each cell is capable of storing one bit of information. Each row consists a memory word, and all cells of a row are connected to a common line referred to as word line, which is driven by he address decoder on the chip.

8. Discuss the virtual memory management technique in detail

Hints: The data is to be stored in physical memory locations that have addresses different from those specified by the program. The memory control circuitry translates the address specified by the program into an address that can be used to access the physical memory.

9. What is memory interleaving? Explain with neat diagram.

Hints: The main memory of a computer is structure as a collection of physically separate modules each with its own address buffer register and data buffer register, memory access operations may proceed in more than one module at the same time. Thus the aggregate rate of transmission of words to and from the main memory system can be increased.

10.Write brief notes on Optical Disks

CD Technology CD-ROM CD-Recordables CD-Rewritables DVD Technology DVD-RAM

11. Explain in detail Magnetic Hard Disks

Organization And Accessing Of Data On A Disk Access Time Typical Disks Data Buffer/Cache Disk Controller Software And Operating System Implications Floppy Disks Raid Disk Arrays Commodity Disk Considerations

12. Write notes on Performance Considerations

Interleaving Hit Rate And Miss Penalty Caches On Processor Chip Other Enhancements

User Comments.....

Read more: CS2253 - COMPUTER ARCHITECTURE - Anna University Engineering Question Bank 4 U http://www.questionbank4u.com/index.php?action=view&listid=60&subject=20&semester=9#ix zz1GANbaqT2 Under Creative Commons License: Attribution Enter to win a free tech book 101 Free Tech Books UNIT-II 1.What are called memory-mapped I/O devices? When I/O devices and the memory share the same address space the arrangement is called memory-mapped I/O devices. 2.What constitutes the devices interface circuit? The address decoder, the data and the status registers, and the control circuitry required to coordinate I/O transfers constitute the devices interface circuit. 3.What are the two important mechanisms for implementing I/O operations? There are two commonly used mechanisms for implementing I/O operations. They are interrupts and direct memory access. 4.What are known as interrupts? In the case of interrupts, the synchronization is achieved by having the I/O device send a special signal over the bus whenever it is ready for a data transfer operation. 5.What do you mean by direct memory access?

Direct memory access is a technique used for high speed I/O devices. It involves having the device interface transfer data directly to or from the memory.

6.What do you mean by an interrupt- request line? The bus control line is also known as an interrupt-request line. 7.What do you mean by an interrupt acknowledge signal? The processor must inform the device that its request has been recognized so that it may remove its interrupt-request signal. This may be accomplished by an interrupt acknowledge signal. 8.What is a subroutine? A subroutine performs a function required by the program from which it is called. 9.What is interrupt latency? Saving registers also increases the delay between the time an interrupt request is received and the start of execution of the interrupt-service routine. This delay is called interrupt latency. 10.What is known as real-time processing? The concept of interrupts is used in operating systems and in many control applications where processing of certain routines must be accurately timed relative to external events .The latter type of application is referred to as real-time processing. 11.What is known as a edge triggered line? The processor has a special interrupt-request line for which the interrupt handling circuit responds only to the leading edge of a signal .such a line is called a edge-triggered line. 12.What is known as an interrupt vector? The location pointed to by the interrupting device is used to store the starting address of the interrupt-service routine .The processor reads this address ,called the interrupt vector. 13.What is known as a debugger? System software usually includes a program called a debugger, which helps the programmer find errors in a program. 14.What is an exception? The term exception is often used to refer to any event that causes an interruption. 15.What are known as privileged instructions? To protect the operating system of a computer from being corrupted by user programs, certain instructions can be executed only while the processor is in the supervisor mode. These are called privileged instructions.

16.What is known as multitasking? Multitasking is a mode of operation in which a processor executes several user programs at the same time. 17.What is known as time slicing? A common OS technique that makes multitasking possible is known as time slicing. 18.What is a process? A program, together with any information that describes its current state of execution, is regarded by the OS as an entity called a process. 19.What is a device driver? A self contained module that encapsulates all software pertaining to a particular device is known as a device driver. 20.What is data abort? Data abort arises from an error in reading or writing data. 21.What is known as prefetch abort? Prefetch abort arises from an error when prefetching instructions from the memory. 22.What are banked registers? The registers that replace user mode registers are called banked registers. 23.What is known as direct memory access? A special control unit may be provided to allow transfer of a block of data directly between an external device and the main memory, without continuous intervention by the processor. This approach is called direct memory access, or DMA. 24.What is known as a DMA controller? DMA transfers are performed by a control circuit that is part of the I/O device interface. This circuit is known as DMA controller. 25.What is known as cycle stealing? The processor originates most memory access cycles, the DMA controller can be said to steal memory cycles from the processor. Hence ,this interweaving technique is usually called cycle stealing. 26.What is known as block/burst mode? The DMA controller may be given exclusive access to the main memory to transfer a block of data without interrupt. This is known as block/burst mode. 27.What is called a bus master?

The device that is allowed to initiate data transfers on the bus at any given time is called the bus master.

28.What is known as distributed arbitration? Distributed arbitration means that all devices waiting to use the bus have equal responsibility in carrying out the arbitration process, without using a central arbiter 29.What is a strobe? Strobe captures the values of the data given instant and store them into a buffer. 30.What is meant by handshake? Handshake is used between the master and the slave for controlling data transfers on the bus. 31. What is known as full handshake? A change of state in one signal is followed by a change in the other signal. This is known as a full handshake. 32.What is a bitrate? The speed of transmission is known as a bit rate. 33.What is a initiator? A master is called an initiator in PCI technology. 34.What is called a target? The addressed device that responds to read and write commands is called a target. 35.What is a transaction? A complete transfer operation on the bus involving an address and a burst of data ,is called a transaction. 36.What are sectors? Data are stored on a disk in blocks called sectors. 37.What are known as asynchronous events? The event of pressing a key is not synchronized to any other event in a computer system.the data generated by the keyboard are called asynchronous. 38.What are known as isochronous events? The sampling process yields a continuous stream of digitized samples that arrive at regular intervals,synchronized with the sampling clock. 39.What is known as plug- and- play? The plug-and play feature means that a new device ,such as an additional speaker, can be connected at any time while the system is operating.

40.What is called a hub? Each node of the tree has a device called a hub which acts as an intermediate control point between the host and the I/O devices. 41.What is a root hub? At the root of a tree, a root hub connects the entire tree to the host computer. 42.What are called functions in USB terminology? The leaves of the tree are the I/O devices being served which are called functions of the USB terminology. 43.What are called pipes? The purpose of the USB software is to provide bi-directional communication links between application software and I/O devices. These links are called pipes. 44.What are called endpoints? Locations in the device to or from which data transfer can take place ,such as status, control, and data registers are called endpoints. 45.What is a frame? Devices that generate or receive isochronous data require a time reference to control the sampling process. To provide this reference, transmission over the USB is divided into frames of equal length. 46.What is the length of a frame? A frame is 1 ms long for low-and full-speed data. CS2253 - COMPUTER ARCHITECTURE - Anna University Engineering Question Bank 4 U http://www.questionbank4u.com/index.php?action=view&listid=61&subject=20&se mester=9#ixzz1GAOI7gws Under Creative Commons License: Attribution Enter to win a free tech book 101 Free Tech Books 16 Marks 1. Explain the various methods available to handle multiple devices using interrupts? Vectored interrupt Interrupt nesting Simultaneous requests 2. Write notes on interrupts in operating system? Explanation 3. Explain DMA and the different types of bus arbitration mechanisms.

Diagram Explanation Centralized arbitration Decentralized arbitration 4. Explain the accessing of I/O devices. Computers use a single bus arrangement. It consists of 3 lines to carry address, data and control signals. Each I/O device is assigned a set of unique addresses.

When the I/O devices and the memory share the same address space, the arrangement is called memory-mapped I/O. With memory-mapped I/O, any machine that can access memory can be used to transfer data. The address decoder enables the device to recognize its address when it appears on the address lines. The data reg. holds the data to be transferred to the processor. The status register contains information relevant to the operation of I/O device The address decoder, the data and status reg. and the control circuitry required to coordinate I/O transfers constitute the devices interface circuits. 5.Explain Synchronous and Asynchronous bus. Synchronous bus o In a Synchronous bus all devices derive timing information from a common clock line. o Each interval constitutes a bus cycle,during which one data transfer can take place. o Explain with an example. o The clock speed must be chosen such that it accommodates the longest delays on the bus and the slowest interface. Asynchronous bus o An alternative scheme for controlling data transfers on the bus is based on the use of a handshake between the processor and the device being addressed.

o The common clock is eliminated. o The clock line is replaced by two timing control lines, which we refer to as Ready and Accept. o Explain with an example. 6.Explain the Interface circuits. The I/O interface consists of the circuitry required to transfer data between the computer bus and an I/O device. On one side of the interface we have the bus signals for the address, data and control. On the other side we have a data path with its associated controls, which enables transfer of data between the interface and the I/O device. This side is device-independent. It can be classified as (i) parallel interface and (ii) serial interface. Parallel Interface o A parallel interface transfers data in the form of one or more bytes simultaneously to or from the device. o Explain an example with suitable diagrams. Serial Interface o A Serial interface is used to connect the processor to I/O devices that require transmission of data one bit at a time. o The key feature of a serial interface is a circuit capable of communicating in bit-serial fashion on the device side and in bit-parallel fashion on the bus side. o Transformation between parallel and serial formats is achieved with shift registers that have parallel access capability. o The most common use of the serial interface is in connecting the computer to devices that are a considerable distance away. o The speed of transmission gives the bit rate. 7.Explain the Peripheral Component Interconnect (PCI) Bus. The PCI bus is a good example of a system bus that grew out of the need for Standardization. Devices connected to the PCI bus appear to the processor as if they were connected directly to the processor bus. They are assigned addresses in the memory address space of the processor. The PCI was developed as a low cost bus that is truly processor independent. An important feature that PCI pioneered is a plug-and-play capability for connecting I/O devices. At any time, one device is the bus master. A master is called an initiator in PCI terminology. This is either a processor or a DMA controller. The addressed device That responds to read and write commands is called a target.

A complete transfer operation on the bus,involving an address and a burst of data is called a transaction. Individual word transfers within a transaction are called phases. When an I/O device is connected to a computer several actions are needed to configure both the device and the software that communicates with it. Explain an example. 8.Explain the SCSI Bus. SCSI stands for Small Computer System Interface. It refers to a std. bus defined by the ANSI. The SCSI bus standard has undergone many revisions, and its data transfer capability has increased very rapidly. A SCSI bus may have 8 data lines, in which case it is called a narrow bus and transfers data only one bit at a time. A wide SCSI bus has 16 data lines and transfers 16 bits at a time. Devices connected to the SCSI bus are not part of the address space of the processor in the same way as devices connected to the processor bus. Data are stored on a disk in blocks called sectors, where each sector may contain several hundred bytes. A controller connected to a SCSI bus is one of two types-an initiator or a target. An initiator has the ability to select a particular target. The initiator establishes a logical connection with the intended target. Explain the sequence of events that take place when the processor sends a command to the SCSI controller. 9.Explain Universal Serial Bus (USB). The USB supports two speeds of operation, called low-speed(1.5 megabits/s) and fullspeed(12 megabits/s). The most recent revision of the bus specification introduced a third operation, called high-speed (480 megabits/s). The USB is quickly gaining acceptance in the market place. To add new ports, a user must open the computer box to gain access to the internal expansion bus and install a new interface card. The kinds of devices that may be connected to a computer cover a wide range of functionality. The sampling process yields a continuous stream of digitized samples that arrive at regular intervals, synchronized with the sampling clock. Such a data stream is called isochronous. A signal must be sampled quickly enough to track its highest-frequency components.

An important requirement in dealing with sampled voice or music is to maintain precise timing in the sampling and replay processes. A high degree of jitter is unacceptable. User Comments..... Read more: CS2253 - COMPUTER ARCHITECTURE - Anna University Engineering Question Bank 4 U http://www.questionbank4u.com/index.php?action=view&listid=61&subject=20&semest er=9#ixzz1GAOrtwM4 Under Creative Commons License: Attribution Enter to win a free tech book 101 Free Tech Books