Professor A. K. Majumdar

Metal-Oxide Semiconductor (MOS) Field Effect Transistors

Computer Science and Engineering Department Indian Institute of Technology, Kharagpur
NMOS enhancement mode transistor

Induced Channel in NMOS Transistor

Current – Voltage characteristics of NMOS transistors

Enhancement mode NMOS transistor with VGS>0 showing induced channel

NMOS Transistor Analysis
• Induced Channel Charge / Unit Area Q(x) = - COX [ VGS – V(x) – Vth] Where COX = εOX/ tOX capacitance per unit area due to gate oxide Drain current IDS = vn(x) Q(x)W vn(x) = drift velocity of electron • • • • •

NMOS Transistor Analysis Contd
vn(x) = - μn E(x) = μn dV/dx μn = Mobility of electrons Hence IDS = - μn Q(x)W dV/dx Substituting for Q(x), IDS dx = μn COX W[VGS– V(x) – Vth] dV Integrating • IDS= μn COX W/L[(VGS - Vth ) - VDS /2 ] VDS • IDS = ηn [(VGS - Vth ) - VDS /2 ] VDS




reduction in effective channel length increases IDS • More accurate representation • IDS = ηn/2.W/L where μn is the mobility of electron.(VGS–Vth)2 where the gain factor ηp = (μpεox/tox). the transistor does not operate as a perfect current source. • Transconductance in saturation region • gm = ηn (VGS – Vth) MOS-SLIDES-AKM 9 Current – Voltage Relationship of NMOS Transistor • The drain-to-source current-voltage dependence for a NMOS transistor is given by the following equations • IDS = 0 • IDS = ηn/2.(VGS – Vth)2 for VDS < Vth (off) for 0 < VDS – Vth < VDS (saturation) • IDS = ηn(VGS – Vth – VDS/2)VDS for VGS > Vth and VGS – Vth≥ VDS (linear) ηn = (μnεox/tox). and VDS < VGS–Vth IDS = ηp/2.(Vgs – Vth)2 ( 1 + λVDS) MOS-SLIDES-AKM 11 Current – Voltage Relationship of PMOS Transistor • Cut off VGS > Vth IDS = 0 • Linear Region: VGS ≤ Vth and VDS > VGS – Vth IDS = ηp(VGS – Vth – VDS/2)VDS • Saturation region VGS ≤ Vth. and tox is the thickness of the oxide.e.Vth)) NMOS Transistor Analysis in Linear Region • Transconductance of NMOS transistor • gm = (dIDS/ dVGS)│ VDS = constant In linear region gm = ηn VDS MOS-SLIDES-AKM 7 MOS-SLIDES-AKM 8 NMOS Transistor Analysis Saturation Region • VDS ≥ VGS – Vth • Channel is pinched off • Assuming voltage difference over induced channel from source to pinch off point fixed at VGS – Vth • IDS = ηn /2 (VGS – Vth)2 • In saturation region. • Since IDS α 1/L. i. VDS2 /2 can be ignored and IDS depends linearly on VDS • Rlinear = 1/ (ηn (VGS . IDS is not independent of VDS • As VDS is increased beyond (VGS– Vth) effective channel length decreases. MOS-SLIDES-AKM 10 Channel Length Modulation • In saturation region.NMOS Transistor Analysis in Linear Region • kn =μn COX = μn εOX/ tOX is called process transconductance parameter • ηn = kn(W/L) is called gain factor • For small VDS .W/L and μp is mobility of holes MOS-SLIDES-AKM 12 MOS-SLIDES-AKM 2 . MOS transistor acts as a constant current source. εox is the permittivity of the oxide material.

current in both pull up and pull down transistors must be same. Current Voltage Characteristics of NMOS Inverter MOS-SLIDES-AKM 17 MOS-SLIDES-AKM 18 MOS-SLIDES-AKM 3 . • With no current drawn from output.Lateral diffusion of source and drain regions MOSFET Capacitances Lateral diffusion = Ld Effective channel length Leff = L -2 Ld MOS-SLIDES-AKM 13 MOS-SLIDES-AKM 14 MOS transistor gate capacitances for three operating regions NMOS Inverter Capacitance CGB CGS CGD Cutoff Linear Saturation CoxW Leff 0 0 Cox W Ld CoxW Ld + ½ CoxW Leff CoxW Ld + 2/3 CoxW Leff Cox W Ld CoxW Ld + ½ CoxW Leff CoxW Ld MOS-SLIDES-AKM 15 MOS-SLIDES-AKM 16 Pull Up and Pull Down transistors • The depletion mode transistor is a pull up device. It is always on (Vgs = 0) • The enhancement mode transistor is the pull down device.

pull up offers lower resistance to charge capacitive load. MOS-SLIDES-AKM 19 NMOS Inverter • With NMOS Depletion Mode transistor • High Dissipation: When VIN is high current flows through both the devices. MOS-SLIDES-AKM 20 CMOS INVERTER CMOS Inverter N Well VDD 2λ VDD PMOS PMOS In Out In Polysilicon Contacts Out Metal 1 NMOS NMOS GND MOS-SLIDES-AKM 21 MOS-SLIDES-AKM 22 CMOS Fabrication CMOS Fabrication MOS-SLIDES-AKM 23 MOS-SLIDES-AKM 24 MOS-SLIDES-AKM 4 .NMOS Inverter • The points of intersection of the pull up (for Vgs =0 ) and pull down curves give points on the transfer characteristics for the inverter • As Vin exceeds VTpd (pull down transistor threshold) current will flow and Vout falls. Further increase in Vin will cause pull down transistor to be out of saturation and will behave as resistor • Pull up device is initially resistive when pull down is turned on • The point at which Vin = Vout is called Vinv • Vinv can be shifted by variation of ratios of pull up and down resistances – determined by the length to width ratio of the transistor. • Degrades 0 value : Low output value is determined by pull down resistance. • Output switching: occurs when Vin exceeds Vthpd • During fall 1→ 0 transition.

• Region R2: Vthn< Vin< VDD . CMOS Inverter Characteristics MOS-SLIDES-AKM 27 MOS-SLIDES-AKM 28 Static Analysis of CMOS Inverter Current – Voltage Relationship of NMOS transistor : VGSn = Vin .Current Voltage Characteristics CMOS INVERTER –VOLTAGE TRANSFER CHARACTERISTICS MOS-SLIDES-AKM 25 MOS-SLIDES-AKM 26 CMOS INVERTER . NMOS transistor in saturation.|Vthp| and Vin .(VDD – Vout) ηp = (μp ε/tox) (W/L)n Cut-off (Vin > VDD . Vout > Vin – Vthn): IDS = ηn/2(VGSn – Vthn)2 MOS-SLIDES-AKM 29 Linear (Vin ≤ VDD . • Region R3: Vthn<Vin<VDD . and PMOS transistor still in the linear region.|Vthp|) and (Vout ≤ Vin +|Vthp|) :IDS = ηp/2(VGSn – |Vthp|)2 MOS-SLIDES-AKM 30 MOS-SLIDES-AKM 5 . VDSp = . • Region R4: Vthn < Vin< VDD – |Vthp| and Vout < Vin .(VDD – Vin).Vthn ≤ Vout ≤ Vin + |Vthp|. NMOS in the linear region. NMOS transistor is off. • Region R5: VDD – |Vthp| < Vin < VDD. VDSn = Vout ηn = (μn ε/tox) (W/L)n Cut-off (Vin ≤ Vthn) : IDS = 0 Current – Voltage Relationship of PMOS transistor VGSp = . PMOS transistor in cut-off. NMOS transistor is in the linear region and PMOS remains in saturation.Vthn. PMOS device operates in the linear region.|Vthp|) and (Vout >Vin +|Vthn|) : IDS = ηn(VGSp – |Vthp| –VDSp/2)VDSp Saturation (Vin ≤ VDD . both the transistors are in saturation.CONTD • Region R1: 0 < Vin < Vthn.|Vthp|) : IDS = 0 Linear (Vin – Vthn ≥ Vout) : IDS = ηn(VGSn – Vthn – VDSn/2)VDSn Saturation ( Vthn ≤ Vin.|Vthp| and Vin + |Vthp| < Vout ≤ VDD.

• (W/L)n / (W/L)p = μp/μn ≈ 1/2.5 (W/L)n MOS-SLIDES-AKM 31 Static Analysis of CMOS InverterContd • • • • • • VIL = (2Vout + Vthp – VDD + βVthn) / (1 + β) β = 1.5 • (W/L)p ≈ 2. and Vthn = │Vthp│. VIH = (5VDD – 2Vthn) /8 • • • • MOS-SLIDES-AKM 32 NOISE MARGINS Switching Characteristics of a CMOS Inverter • NML = VIL – VOL = VIL • NMH = VOH – VIH = VDD – VIH Parasitic capacitances in a cascaded CMOS inverter MOS-SLIDES-AKM 33 MOS-SLIDES-AKM 34 Switch model of a static CMOS inverter Propagation delay times and rise and fall times of an inverter MOS-SLIDES-AKM 35 MOS-SLIDES-AKM 36 MOS-SLIDES-AKM 6 .Static Analysis of CMOS InverterContd VOH = VDD VOL = 0 Vinv = [ Vthn + (1/√β)(VDD + Vthp)] / (1 + 1/√β) β = ηn/ηp =[μn(εox/tox)n (W/L)n ]/ [μp(εox/tox)p(W/L)p] • for β = 1. and Vthn = │Vthp│ VIL = 1/8 (3VDD +2 Vthn) VIH = [VDD + Vthp + β(2 Vout + Vthn)] / (1 + β) with β = 1.

• τpHL2 = η n (V DD ⎡ ⎛ 4V thn ⎞ ⎤ CL ⎟⎥ ⎢ ln ⎜ 3 − − V thn ) ⎣ ⎜ V DD ⎟ ⎦ ⎝ ⎠ MOS-SLIDES-AKM 38 MOS-SLIDES-AKM 37 Propagation Delay Estimation – Contd.5 (W/L)n MOS-SLIDES-AKM 39 MOS-SLIDES-AKM 40 Power Dissipation in CMOS Inverter • Dynamic Power Consumption Charging and Discharging Capacitors Dynamic Power Consumption • Short Circuit Currents Short Circuit Path between Supply Rails during Switching • Leakage Leaking diodes and transistors E-charge = CL VDD2 E-discharge = ½ CL VDD2 Average Power dissipation PAvg= 1/T CL VDD2 = CL VDD2 f MOS-SLIDES-AKM 41 MOS-SLIDES-AKM 42 MOS-SLIDES-AKM 7 .CMOS inverter equivalent circuit during high-to-low and low-to-high output transitions Propagation Delay Estimation • High to Low Transition • τpHL = τpHL1 + τpHL2 • τpHL1 = the period during which Vout drops from VDD to VDD – Vthn. • Low to High Transition • τpLH = ηp(VDD−|Vthp |)⎢(VDD−|Vthp |) ⎣ CL ⎡ 2|Vthp | ⎢ ⎛ 4|Vthp | ⎞⎤ ⎜ ⎟⎥ + ln⎜3− VDD ⎟⎥ ⎝ ⎠⎦ Typical input . • τpHL1 = 2 CLVthn / ηn (VDD – Vthn)2 • τpHL2 = the period during which Vout drops from VDD – Vthn to VDD /2. (W/L)p ≈ 2.output and load capacitor current waveforms in a CMOS inverter • For τpHL = τpLH .

dd IDL = JS × A Reverse leakage Current of a p-n junction Ireverse= A JS(e Reverse saturation current Density JS = 10-100 pA/μm2 JS doubles for every 9 deg C! qVbias/kT - 1) at 25 deg C for 0. • To reduce short circuit power dissipation input/output rise and fall times should be of same order = τ PAvg(short-circuit) = 1/12[k τ f (VDD.Contd • When node transition rate is slower than clock rate • PAvg = α T CL VDD2 f • where α T is the node transition factor (effective number of power consuming transition per cycle) • Energy Delay Product EDP = PDP τp = ½ CL VDD2 τp MOS-SLIDES-AKM 44 Short Circuit Current in CMOS Inverter Short Circuit Current • Short circuit current is large if output load capacitance is low and input rise/fall time is large. MOS-SLIDES-AKM 43 Switching Power Dissipation .Vthn -|Vthp|)3] MOS-SLIDES-AKM 45 MOS-SLIDES-AKM 46 Sub Threshold Leakage Reverse-Biased Diode Leakage ReverseGATE p+ N p+ Reverse Leakage Current + V . PDP = Pavg τp For f = fmax. PDP = CL VDD2 fmax τp = ½ CL VDD2 Note: average switching power dissipation of a CMOS inverter is independent of transistor sizes and characteristics provided there is full voltage swing Analysis is valid when output node of the gate undergoes one transition (0 to VDD) in a clock cycle.25μm CMOS. MOS-SLIDES-AKM 47 MOS-SLIDES-AKM 48 MOS-SLIDES-AKM 8 .Switching Power Dissipation in CMOS Inverter • • • • fmax = 1/2τp Power Delay Product.

off MOS-SLIDES-AKM 53 MOS-SLIDES-AKM 54 MOS-SLIDES-AKM 9 .…InN) NMOS Circuit PUN … κCox Cg/κ ηκ E IDS/κ 2 P/κ PD τ /κ κCox Cg/κ ηκ κE IDSκ Pκ 3 PDκ 2 τ /κ Static Complementary CMOS Circuit MOS-SLIDES-AKM 51 MOS-SLIDES-AKM 52 … COMPLEMENTARY CMOS NAND GATE CMOS NAND GATE • With both input A =1.In2. • NMOS pull down transistors create conducting path.Advantages of CMOS Inverter • The high and low output voltages are equal to Vdd and ground respectively so that the voltage swing is the same as the supply voltage. • The logic levels are not dependent on the relative device sizes and hence the size of the transistors can be minimized. be designed to have a low input impedance. making it less sensitive to noise. and B = 1 • PMOS pull up transistors are in cut off. MOS-SLIDES-AKM 49 Technology Scaling • Full Scaling (Constant Field Scaling) • Constant Voltage Scaling Parameter Channel Length (L) Channel Width (W) Gate oxide thickness (tox) Supply voltage VDD Junction depth (Xj) Threshold voltage (Vth) Doping densities – ND (NA) Full Scaling Constant-Voltage Scaling L/κ L/ κ W/κ W/κ tox /κ tox /κ VDD /κ Xj/κ Vth/κ NDκ (NAκ) VDD Xj/κ Vth NDκ (NAκ ) 50 2 2 MOS-SLIDES-AKM Effects of scaling on MOS transistor characteristics Parameter Gate Area (A = WL) Oxide capacitance (Cox) Gate capacitance Cg (= CoxWL) Transconductance/Gain factor (η) Electric field (E) Drain current (IDS) Power dissipation (P) Power density ( PD = P/area) Gate delay (τ) Full Scaling 2 A/κ Constant-Voltage Scaling 2 A/κ COMPLEMENTARY CMOS DESIGN VDD In1 In2 InN In1 In2 InN PDN PMOS Circuit OUT= F(In1. • The CMOS inverter has a very high input resistance and draws no dc input current as the gate of a MOS transistor is virtually a perfect insulator. • For other input combinations one of the pull up PMOS transistors will be on and NMOS network will be cut. therefore.. The inverter can. • There is always a finite resistance between the output and either Vdd or ground in the steady state.

A = (W/L)p.A = (W/L)p. To have same pull-down delay as the minimum sized inverter the NMOS devices in the PDN of the NAND gate should be twice as wide. i.CMOS NAND GATE • Taking (W/L) to be same for each type of transistors.69 Rn(C1+2C2+3C3+4CL) •Propagation delay deteriorates rapidly as a function of fan-in – quadratically Layout MOS-SLIDES-AKM 57 MOS-SLIDES-AKM 58 2-input NOR gate CMOS NOR GATE • VOL = 0 and VOH =VDD • Switching Threshold Computation Assume (W/L) to be same for each type of transistors.69 Rp CL when one input goes low.e. MOS-SLIDES-AKM 56 4-Input NAND gate CMOS TWO INPUT NAND GATE LAYOUT Stick Diagram Elmore Delay Model: tpHL = 0. MOS-SLIDES-AKM 55 Lumped parameter switching model of a two input CMOS NAND gate •Delay is dependent on the input pattern : tpLH =0. i.A = (W/L)n. VA = VB Neglect body effect for PMOS transistors MOS-SLIDES-AKM 59 MOS-SLIDES-AKM 60 MOS-SLIDES-AKM 10 . for Vinv = VDD/2.B Vinv = [Vthn + 2 sqrt(ηp / ηn) (VDD – |Vthp|)] / (1+ 2 sqrt(ηp / ηn)) • Assuming Vthn = |Vthp| . tpHL = 0.e.69 * 2 Rn CL for low to high transition of both inputs. (W/L)n. (W/L)n.e.A = (W/L)n.B both input voltage switch simultaneously.B and (W/L)p. one should select ηn = 4 ηp .B and (W/L)p. i. tpLH = 0.69 Rp/2 CL for low to high output transition when both inputs go low.

for Vinv = VDD/2. VOL = GND • Low output impedance • Very high input resistance • Logic levels independent of relative device sizes . one should select ηp = 4 ηn . of the NMOS and PMOS transistors : ratioless •With proper sizing .CMOS NOR GATE • At switching Threshold VA = VB = Vout = Vinv • NMOS transistors are in saturation (since VGS= VDS) • Lower PMOS transistor (with A-input) is in linear region. rise and fall times are of same order MOS-SLIDES-AKM 63 MOS-SLIDES-AKM 64 Pass Transistor Pass Transistor • NMOS pass transistor : Passes 0 (low ) well but degrades 1 (high) Maximum value of output is VDD – Vthn • PMOS pass transistor Passes 1 without any degradation Low value is degraded to Vthp MOS-SLIDES-AKM 65 MOS-SLIDES-AKM 66 MOS-SLIDES-AKM 11 . MOS-SLIDES-AKM 61 XOR Gate MOS-SLIDES-AKM 62 CMOS realization of a switching function F = (A+D) B + CD Features of Complementary CMOS Design • No static power consumption • High noise margins : VOH = V DD . the upper PMOS (B-input) is in saturation • Vinv = [Vthn + sqrt(ηp /4 ηn) (VDD – |Vthp|)] / (1+ sqrt(ηp /4 ηn)) • Assuming Vthn = |Vthp| .

•Pass transistor gates should not be cascaded MOS-SLIDES-AKM 68 COMPLEMENTARY PASS TRANSISTOR LOGIC CMOS Transmission Gate Logic • With CMOS transmission gates : No signal degradation • Equivalent resistance of a CMOS transmission gate is almost independent of the output voltage. but degrades VOH to VDD –Vthn . MOS-SLIDES-AKM 71 MOS-SLIDES-AKM 72 MOS-SLIDES-AKM 12 . Q1 is turned on and input B is copied to the output Z.PROBLEMS • NMOS pass transistor passes 0V(VOL) correctly. MOS-SLIDES-AKM 69 MOS-SLIDES-AKM 70 CMOS transmission gate realization of XOR function. • Compared to the corresponding static CMOS realization the transmission gate realization would have speed advantage. Six transistor CMOS transmission gate realization of the XOR function.e. MOS-SLIDES-AKM 67 •Signal level degradation can be remedied by insertion of a CMOS inverter or by the usage of suitable level restoration circuits. •PMOS pass transistor passes 1 i. • If A is low. VDD correctly but degrades 0 to |Vthp| • When the input A is high. the pass transistor Q2 is turned on and passes 0 to Z.PASS TRANSISTOR LOGIC PASS TRNASISTOR LOGIC . • The transistor Q2 offers low impedance path to the supply rails even when A is low.

The dynamic design is non-ratioed. On the other hand. The output is conditionally discharged depending upon the inputs and the topology of the PDN . and the mode of operation is determined by the clock signal CLK MOS-SLIDES-AKM 73 DYNAMIC CMOS DESIGN ADVANTAGES The number of transistors required is (N + 2) in dynamic CMOS as compared to 2N for static design. The dynamic gates have reduced load capacitance because of a fewer number of transistors and hence faster switching speeds. it would offer a low resistance path between out and the ground.Dynamic CMOS Design DYNAMIC CMOS LOGIC OPERATION When CLK = 0. MOS-SLIDES-AKM 74 The circuit operates in two phases. the output is pre-charged to VDD by the transistor Qp. The size of the CMOS pre-charge transistor is not important for proper realization of the gate and hence can be increased to improve the low-tohigh transition time. Once the node out is discharged. Thus during the evaluation phase the inputs can make not more than just one transition. the evaluation Qe is turned on while the pre-charge transistor Qp is turned off. if the PDN is turned off.if the PDN is conducting. MOS-SLIDES-AKM 75 Dynamic CMOS realization of the Boolean function F=AB+BD+CD MOS-SLIDES-AKM 76 Charge sharing in a dynamic CMOS Circuit CHARGE SHARING PROBLEMS WITH DYNAMIC LOGIC MOS-SLIDES-AKM 77 MOS-SLIDES-AKM 78 MOS-SLIDES-AKM 13 . For CLK = 1. The evaluation NMOS transistor Qe remains off during this time thus disabling the pull-down path. pre-charge and evaluation. the pre-charged value will remain stored in the output capacitance CL . it cannot be charged again till the next pre-charge begins.

. output of the dynamic gate is charged up to VDD through Qp which is ON and Inverter output is Low. Y. Evaluation phase: CLK=High. Kang. “ Digital Integrated Circuits”. 2003. The buffer output can never make 1 to 0 transition during the evaluation phase for any combination of the input values. else output of dynamic gate will remain charged (high) and the poutput of domino gate will remain low. The inverter output voltage can make at most one transition from 0 to 1 during the evaluation phase. Pre-charge phase: CLK=Low. MOS-SLIDES-AKM 81 MOS-SLIDES-AKM 82 MOS-SLIDES-AKM 83 MOS-SLIDES-AKM 14 . M. Qp turns off.H.Chandrakasan A. inverter output can change for Low to High depending on the inputs – if PDN conducts. REFERENCES 1. and Nikolic B. 2004.E and Eshraghlan. dynamic gate will discharge and inverter output will become high. McGraw Hill Pub. Sung-Mo and Leblebici.Hall of India.. Rabaey J.. 2003 Weste N. Hence a domino gate can only implement non-inverting logic.Cascading problem in dynamic CMOS gates DOMINO LOGIC MOS-SLIDES-AKM 79 MOS-SLIDES-AKM 80 DOMINO LOGIC OPERATION A static inverter (buffer) follows an n-type dynamic logic block. 3. K: Principles of CMOS VLSI Design. Pearson Education. Prentice..: CMOS Digital Integrated Circuits. 2.