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Input Impedance Analysis of Single-Phase PFC Converters

Jian Sun
Department of Electrical, Computer, and Systems Engineering Rensselaer Polytechnic Institute, Troy, NY 12180-3590, USA Telephone: (518) 276-8297; Fax: (518) 276-6226; E-mail: jsun@rpi.edu
Abstract-Input impedance of single-phase boost power factor corrected (PFC) ac-dc converters is modeled and analyzed in this paper. A large-signal model is presented for the input impedance which overcomes the limitations of traditional piece-wise linearized models. The model is valid at frequencies ranging from the crossover frequency of the output voltage loop to half the switching frequency of the converter. Experimental results from a boost single-phase PFC converter are provided to validate the model. Input characteristics of typical boost PFC converter designs, such as input impedance dipping, leading phase of the input current, and responses to distorted lines are studied by using the model. A simple compensation technique to reduce the dipping in the input impedance thereby improving converter performance and minimizing the potential for undesirable interactions with the input EMI filter is also presented.

I. INTRODUCTION Dynamic interactions of converters with their input filters are a common problem in systems involving switching power converters. For dc-dc converters, a systematic approach based on averaging and linearization has been developed for analyzing such interactions and their effects on interconnected system stability. Specifically, the input impedance of a dc-dc converter at a given steady-state operating point can be determined through linearization of the nonlinear averaged model of the converter. The Nyquist criterion can then be applied to the ratio of the filter output impedance to the converter input impedance to determine the stability of the interconnected converter-filter system [1]. Linearization is a credible approach in this case because most dc-dc converters can be assumed to operate with constant input and output such that a steady-state operating point can always be identified. Filter-converter interaction also exists in systems employing power factor corrected (PFC) ac-dc converters as the front end. For example, [2] demonstrated that the interaction between a PFC converter and the source impedance of a generator may lead to voltage instability. There is, however, a lack of systematic method for analyzing and characterizing such interactions. A fundamental difficulty here is the sine wave input voltage to single-phase PFC converters, which prevents, in theory, the application of conventional small-signal linearization techniques. At frequencies below the line fundamental frequency, the time-varying switching-cycle averaged model of the converter power stage can be averaged again over a line cycle to eliminate its dependency on time (due to time-varying

input) [3]. The resulting nonlinear, time-invariant, line-cycle averaged model can then be linearized and combined with controller models to predict the input impedance in the low frequency region [4]. The resulting low-frequency model can be further simplified by assuming ideal current control, i.e., by assuming that the inductor current follows perfectly the reference current [5]. However, since most converter-filter interactions occur at high frequencies, typically around the crossover of the current loop and/or the corner frequency of the input EMI filter, the low-frequency model is not sufficient for system stability analysis. The traditional approach to high-frequency modeling of single-phase PFC converters relies on the assumption of quasistationary operation, i.e., by assuming that the converter operates in a quasi steady state at different points along the sine wave input. Under this assumption, the nonlinear, switchingcycle averaged model of the converter power stage can be linearized at different points along the sine wave input. This results in a set of linear models each being valid for a particular point along the sine wave. From a practical point of view, it might be plausible to use these piece-wise linear models to assist in the design and stability analysis of PFC converter control loops. For example, if the piece-wise linear models indicate instability of the current loop under a particular input voltage (lower than the peak of the ac line), one could arguably infer that the converter would also have stability problems when operating from the ac line. This has indeed been the approach used in previous works on control design for single-phase PFC converters [6]. The piece-wise linear models have also been used to determine the input impedance of single-phase PFC converters above the line fundamental frequency, see, e.g., [7]. Despite some degree of correlation between model predictions and experimental measurements reported in the literature, this approach has a fundamental deficiency in its theory, i.e., there is no clear physical interpretation for the piece-wise linear input impedance calculated under different dc input voltages and its correlation to the actual input impedance of a PFC converter under sine wave inputs. For example, the input impedance of a PFC converter at three times the line frequency is, by definition, equal to the ratio of a (small) third harmonic voltage
. However, stability of the converter with a sinusoidal input is not guaranteed even if the piece-wise models predict stability at all points along the sinusoidal input waveform.

0-7803-7768-0/03/$17.00 (C) 2003 IEEE

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superimposed onto the ac line and the resulting third harmonic input current. A third harmonic input voltage introduces a perturbation to the converter operation along the entire fundamental cycle, not just at a particular point of the ac line. Hence the input impedance predicted by the piece-wise linear model for a particular dc input voltage is theoretically meaningless when the converter operates with a sine wave input. A new approach to high-frequency (above half the line frequency) input impedance modeling of boost single-phase PFC converters is presented in this paper. The high-frequency model, which complements the existing low-frequency model [5], is derived by assuming that the output voltage is constant, i.e., by ignoring the dynamics of the voltage loop above half the line frequency, under which the switching-frequency averaged model of the boost power stage becomes linear. The resulting impedance model is valid for large-signal operation and can be used to predict not only the input impedance of the converter but also its input characteristics under different lines. The high-frequency impedance model described in this paper was originally obtained as a by-product of a research effort on input current zero-crossing distortion in single-phase PFC converters [9]. During the preparation of the current paper, the author came across references [10] and [11] which reported similar high-frequency models. In comparing the two approaches, it was found that the derivation in [10] and [11] assumed small-signal operation of the converter, and the results were actually for the input impedance of the boost stage, i.e., excluding the front-end rectifier bridge. In contrast, this paper uses a large-signal approach to determine the input impedance at the ac side directly. Additionally, the models in [10] and [11] were verified indirectly by measurements of the current loop gain, while direct measurements of the input impedance are provided in this paper for model validation. II. HIGH-FREQUENCY IMPEDANCE MODEL This section presents the development of the high-frequency input impedance model for boost single-phase PFC converters with average current control. The basic converter circuit and control is shown in Fig. 1. There, it is assumed that the inductor current is sensed by using a resistor. Other current sensing methods can also be used, and the model presented in the following is applicable in general. Reference iref for the inductor current is generated by a multiplier with three inputs: k mv a v in i ref = -------------------2 v ff where 1) va is the output of the output voltage compensator, and 2) vff is generated by a low-pass circuit and represents the rms value of the line voltage for input feedforward control [8]. The crossover frequency of the output voltage loop in singlephase PFC converters is usually well below the line frequency [8]. Hence the output of the voltage compensator, va, can be

assumed constant when calculating the input impedance at high frequencies. Similarly, the input voltage feedforward loop [8] can be ignored in the high-frequency region. As such, the reference current, iref, can be expressed as i ref = g v in (1)

in the high-frequency region, where g is a constant. In steady state and under ideal control, the input current (rms) and power of the converter are related to the parameter g by follows: gV in R I in = ---------------l , Rs
2 gV in R l P in = V in I in = ---------------- . Rs

(2)

The pulse-width modulator in Fig. 1 is assumed to use leading-edge modulation such that the off-time duty ratio, d ' = 1 d , of the switch is proportional to the output of the current amplifier, vc. Assuming that the PWM signal has a peak-to-peak value equal to Vm, the modulator has a gain of 1/ Vm, and the off-time duty ratio of the switch can be written as vc d' = 1 d = -----Vm (3)

where d is the on-time duty ratio of the switch. It is known that leading-edge modulation can reduce the output voltage ripple of the PFC converter when its load is a trailing-edge modulated dc-dc converter [13]. Derivation of the high-frequency impedance model follows the modeling procedure outlined in the [9]. First, with standard average current control, the current compensator output, vc, can be written as V c(s) = [ R s i L R l I ref(s) ]H c(s) iL D1 D2 + |vin| _ Rl Rs Cp |vin| va vff km|vin|va iref vff2 Rl
Fig. 1. Simplified boost single-phase PFC converter circuit for the derivation of input impedance at high frequencies. The converter uses leading-edge modulation and standard average current control.

(4)

+ S d(t) vs _

D C

D3 iin

D4 +_ vin

Rz _ +

Cz vc d(t) PWM

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Load

+ V0 _

where H c(s) is the current compensator transfer function: Kc( 1 + s z ) H c(s) = -------------------------------- , s ( 1 + s p) with Cp + C z 1 1 K c = ---------------------------- , z = ----------- , p = ------------------ . CzRz ( C p + C z )R l Cp Cz Rz Since the pulse-width modulator can be modeled by a constant gain under average current control [12], the off-time duty ratio of the switch can be expressed as 1 D'(s) = ------ [ R s i L R l I ref(s) ]H c(s) . Vm To model the boost power stage, we further assume that 1) all components in the circuit are ideal, 2) the boost inductor operates in the continuous conduction mode (CCM) over the entire line cycle, and 3) the sensing resistor, Rs, is small such that the voltage across it can be ignored when modeling the power stage. Based on these and the assumption that the output voltage is constant, an average model can be written for the boost inductor current, iL: di L L ------ = v in d'V 0 . dt Since i in = sgn ( v in ) i L , (7) can be rearranged to di in L -------- = v in sgn ( v in ) d'V 0 . dt (8) (7) (6) (5)

R l V 0 V m1 H c(s)Iref(s) V in(s) I in(s) = ----------------------------------------------- + ---------------------------------------------1 H (s) Ls + R s V 0 V m1 H c(s) Ls + R s V 0 V m c

(10)

Defining n = RsV0 Kc ----------------- , LV m s2 s p(s) = 1 + ----- + -----2 z n (11)

and assuming that the effects of the current compensator pole, p , on the input impedance can be ignored, i.e., Kc( 1 + s z ) H c(s) -------------------------------- , s transfer function (10) can be simplified to s1 + ----R l I ref(s) z V in(s) s I in(s) = ------------------ -------------- + ------------- -------- . 2 Rs p(s) L n p(s) (12)

(13)

Considering (1), the input impedance of the converter can be determined from (13) as follows: Rs V in(s) p(s) Z in(s) = ------------- = ------- ------------------------------------------------gR l Rs I in(s) 1 1 + s ----- + ------------------ gR L 2
z l n

(14)

On the other hand, multiplying both sides of equation (6) by the sign function, sgn(vin), yields 1 sgn ( v in ) D'(s) = ------ [ R s i in R l I ref(s) ]H c(s) . Vm (9)

Equations (8) and (9) indicate that the input current dynamics of the boost single-phase PFC converter can be represented by the block diagram shown in Fig. 2, based on which a transfer function can be derived for the input current in response to the input voltage and the reference:

Note that (14) gives directly the input impedance of the PFC converter at the ac side. It is also a large-signal model since small-signal operation is not assumed in the derivation. A small filter capacitor is usually placed on the dc side of the rectifier bridge, as shown in Fig. 3, to reduce high-frequency noises in the rectified dc voltage. This capacitor should be as small as possible in order not to cause significant phase shift at the fundamental frequency, which would otherwise lead to high zero-crossing distortion of the input current [9]. Yet the effect of this capacitor on the input impedance, especially at high frequencies, may not be negligible. When considering this capacitor as well as the commonly used ac-side filter capacitor, Cac, the total input impedance of the converter can be written as follows where Z in(s) is defined by (14): Z in(s) Z in'(s) = -----------------------------------------------------1 + ( C dc + C ac )sZ in(s) + vin Cac Cdc Boost Stage (15)

Vin(s)

1 sL

Iin(s)

V0 Vm Hc(s)

Rs
_

RlIref(s)
Fig. 3. Boost single-phase PFC converter with an ac and a dc filter capacitor. . This is justified as p is usually placed at half the switching frequency to attenuate high-frequency noise in the control loop.

Fig. 2. Block diagram representing high-frequency dynamics of boost single-phase PFC converters.

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III. MODEL VALIDATION The boost single-phase PFC converter described in [13] was measured under various operating conditions to verify the impedance model (14). Following are the major parameters of this converter (refer to Fig. 1): boost inductor L = 1 mH, steady state output voltage V0 = 385 V, sensing resistor Rs = 0.25 , PWM signal peak-peak voltage Vm = 4 V, Rl = 4 k, Rz = 12 k, Cz = 1.2 nF, and Cp = 270 pF, switching frequency fs = 100kHz. With the given compensator parameters, the zero, z, is calculated to be z = 69444 rad/sec, while its dc gain is Kc = 170068. Then, using (11), n can be calculated as follows: n = R s V 0K c ----------------- = LV m 0.25 385 170068 ------------------------------------------------- = 63970.8 10 3 4

Input impedance measurement of the converter was conducted by injecting, through a power amplifier and an isolation transformer, a sinusoidal perturbation to the input voltage and measuring the resulting perturbation in the input current. Fig. 4 shows the input impedance responses of the converter at 50 Hz input. The input voltage was 115 V (rms), and the input power was 53W (corresponds to g = 0.25 10 6 ). The dashed lines represent the experimental measurement results, while the solid lines are predicted from (15). A 30 nF capacitor was used on the dc side of the rectifier
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in this measurement, but no ac-side filter capacitor was used. As can be seen, the measurement results agree with the model prediction over the entire frequency range (10 Hz to 100 kHz). The measurement error around 50 Hz was due to the fact that the frequency of the injected signal in this region is equal or close to the fundamental frequency of the line so that it cannot be distinguished from the fundamental. It shall be pointed out that averaged models, such as the input impedance models (14), are usually useful in predicting frequency responses up to 1/3 of the switching frequency. The input impedance of the experimental boost converter above 30 kHz is dominated by the effect of the 30 nF dc side filter capacitor mentioned above, so that the agreement between the measured and predicted responses above 30 kHz in Fig. 4 should be interpreted as a proof of the accuracy of the total input impedance expression (15), not as an indication that (14) is valid beyond 1/3 of the switching frequency. Fig. 5 shows the input impedance response of the converter at 400 Hz input, which is the standard ac bus frequency on most of todays commercial jet airplanes. The input power in this case is 106 W (corresponds to g = 0.5 10 6 ). Good agreement between experimental measurements and model predictions can again be seen. The measurement error around 400 Hz is again due to the inability of the network analyzer to distinguish the injected signal from the fundamental component of the line. Furthermore, Fig. 6 shows the total input impedance
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Fig. 4. Input impedance of the boost single-phase PFC converter at 50 Hz, 53 W input. Solid lines: predicted; dashed lines: measured.

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Fig. 5. Input impedance of the boost single-phase PFC converter at 400 Hz, 106 W input. Solid lines: predicted; dashed lines: measured.

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Fig. 6. Input impedance of the boost PFC converter with an ac side capacitor Cac = 1.5mF, a dc side capacitor Cdc = 30 nF, and at 400 Hz, 106 W input. Solid lines: predicted responses; dashed lines: measured responses.

Frequency (Hz)
Fig. 7. Input impedance responses of the boost PFC converter without filter capacitors Cdc and Cac. The two sets of plots correspond to g = 0.5x10-6 (dashed lines) and g = 0.25x10-6 (solid lines), respectively.

of the converter with a 1.5 F filter capacitor placed at the ac side of the rectifier bridge. The measurements were taken at 400 Hz input, with 106 W input power. The close correlation between experimental measurements and model predictions proved the accuracy of the presented input impedance model. IV. INPUT IMPEDANCE ANALYSIS The impedance responses in the previous section were measured under small-signal operation conditions. The input impedance model (14) is, however, valid for large-signal operation as well and can be used to study characteristics of the converter to different inputs. The impedance plots in Fig. 4-5 included the effects of Cdc, the capacitor on the dc side of the rectifier bridge, see Fig. 3. Since this capacitor is not part of the essential function of the converter and can have very different values in different designs, frequency-domain responses of Zin (without Cdc) are plotted using (14) in Fig. 7 for the example boost converter with g = 0.25 10 6 and 0.5 10 6 , respectively. The input voltage is 115 V (rms) in both cases. A. Input Impedance Dipping The most noticeable feature of the plots in Fig. 7 is the dipping of the input impedance in the frequency region ranging from 1 kHz to about 30 kHz. This is caused by the pole

1 Rs 1 s p = ----- + ------------------ gR L 2 z l n

(16)

in Zin(s). As can be seen, this pole is always smaller than the zero, z , of the current compensator and moves to lower frequency as g decreases (so does the input power). The maximum dipping happens at a frequency corresponding to the resonant frequency of p(s), from which the impedance starts to rise. For the measured boost PFC converter, this happens at about 10 kHz, as can be seen from Fig. 7. The amount of maximum dipping in the input impedance is also affected by the characteristics of the zeros of p(s), especially its damping factor, , defined by n 1 R sV 0Kc = -------- = -------- ----------------- . 2 z LVm 2 z To maximize the current loop gain, the common design practice is to place the zero, z, of the current compensator at the crossover frequency, c, of the current loop [8]. Since the duty ratio to inductor current transfer function of the boost converter in the high frequency region is given by V 0 ( sL ) , see Fig. 1, unity gain of the current loop at c = z implies that [9]
. It will be shown later that the second-order function p(s) is always underdamped in conventional designs so that it has two complex conjugate poles.

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2K R s V 0 Rs V0 H c(j c) ------ --------- ------------c ------ --------- = 1 . c V m cL V m cL

(17)

Using this, the damping factor of p(s) can be calculated as follows: 1 c 1 R sV 0K c = -------- ----------------- = -------- ------ = 0.42 (18) 2 c 4 2 2 z LV m Therefore, the two zeros of p(s) (hence zeros of the input impedance) are under-damped, which causes an undershoot at the resonant frequency of p(s) and further adds to the dipping in the input impedance. Fig. 8 shows the magnitude response of p(s) for the measured boost converter with g = 0.25 10 6 . As can be seen, there is about 3 dB undershoot at 8 kHz which contributes to the dipping in the input impedance. Stability of a PFC converter connected with an input EMI filter requires that the impedance ratio, Z 0(s) Z in(s) , meets the Nyquist criterion, where Z 0(s) is the output impedance of the filter. To provide sufficient attenuation for the switchingfrequency ripple, the corner frequency of the EMI filter is usually designed to be 1/10 of the switching frequency, which would be 10 kHz for the measured boost PFC converter. Since the output impedance of the EMI filter peaks at the corner frequency, a dipping in the input impedance of the PFC converter in the same frequency region can greatly increase the potential for instability or deteriorated performance of the converter. The analytical input impedance model derived here can be used to guide the converter and EMI filter design to avoid undesirable interactions, see Subsection C.
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approaches the pole of Zin(s). Additionally, the input current starts to lead the input voltage as the line frequency goes up, and the leading phase of the input current becomes significant (e.g., at 1 kHz) even before the change in magnitude becomes appreciable. Furthermore, the plots in Fig. 7 suggest that these effects are more significant under light load conditions when g is small. The leading phase of the input current also causes harmonic distortion in the input current around the zero crossing of the input voltage, as explained in [9]. The input impedance model can also be used to predict response of the converter to distorted lines. In particular, dipping of the input impedance at high frequencies imply that an x percent harmonic voltage at these frequencies will generate more than x percent harmonic current. For example, the magnitude plot in Fig. 4 shows a maximum of 15 dB dipping (from 48 dB at 200 Hz and below to 33 dB at 9 kHz). This implies that, with reference currents having the same amplitude, i.e., the same value of g, an input voltage at 9 kHz would generate a current that is 5.6 times (15 dB = 5.6234) of the current generated by the same voltage at 200 Hz or lower frequency. In other words, assuming the line frequency is under 200 Hz, 1% harmonic voltage at 9 kHz would generate as much as 5.6% harmonic current at the same frequency. This can be a major concern for PFC converters that have to meet harmonic current limits under distorted lines, such as the recently issued DO-160D for airborne equipment. C. Performance Improvement The two causes discussed in Subsection A for the dipping in the input impedance, namely, the low-frequency pole and the under-damped zeros of Zin(s), also point to possible ways for reducing the dipping. First, (14) indicates that it is possible to redesign the reference current generation circuit to make Zin(s) purely resistive over the entire frequency range (i.e., up to 1/3 of the switching frequency in which the average model is valid). This can be achieved by adding a phase shift circuit to the |vin| input pin of the multiplier shown in Fig. 1. Assuming the transfer function of this circuit is Q(s), the reference current becomes then I ref(s) = gQ(s)V in(s) . Based on (13), a transfer function Q(s) that will result in complete cancellation of the pole and zeros of Zin(s) is determined to be Rs 1 s2 1 + s ----- ------------------ + ----- gR L 2 2 z l n n Q(s) = -------------------------------------------------------------- . 1 + s z

Magnitude (dB)

65 60 55 50 45 100 1000 10000 100000.

Frequency (Hz)
Fig. 8. Frequency response of function p(s) defined by (11). Shown here is the magnitude response with g = 0.25x10-6.

B. Response to Different Lines The large-signal nature of the input impedance model (14) also allows it to be used to study the response of the converter to input voltages at different frequencies. As can be seen from Fig. 7, when the line frequency is well below the pole of Zin(s), the actual input current will be in phase with the input voltage, with a magnitude determined by the control parameter g according to (2). However, the decrease of the input impedance with frequency (beyond 500 Hz) implies that the same value of g will result in higher input current when the line frequency

(19)

As can be seen, this transfer function is dependent of control parameter g. Therefore, its realization would require an adaptive filter and is best implemented using digital circuits, which is beyond the scope of this paper. A simplified version of it, as given below
. DO-160D requires that, for every 1% of individual voltage harmonic, the equipment shall not demand harmonic current greater than 1.25% above the limit for the corresponding harmonic current with undistorted input.

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1 Q(s) -------------------1 + s z

(20)

V. CONCLUSIONS A large-signal model is presented for predicting input impedance response of single-phase boost PFC converter with average current control. The model complements previously published low-frequency impedance models and is directly verified by impedance measurements from a prototype converter. It is also used to study input characteristics of boost single-phase PFC converters in general. A particular issue discussed is the dipping in the input impedance and its impacts on converter performance. Based on the analyses, a simple phase compensation method is proposed and its effectiveness in reducing input impedance dipping demonstrated. ACKNOWLEDGMENTS The experimental results were taken at Rockwell Collins, Inc. where the author worked until August 2002. Continuation of the work at RPI was supported in part by Rockwell Collins through the Center for Power Electronics Systems (CPES), an Engineering Research Center of the National Science Foundation. The author also wants to thank Mr. James Noon of Texas Instruments for providing the UCC3817 single-phase PFC evaluation boards used for the experiments. REFERENCES
[1] R. D. Middlebrook, Input filter considerations in design and application of switching regulators, Proceedings of IEEE Industry Applications Society Annual Meeting, pp. 366-382, 1976. [2] C. D. Davidson and R. Szasz, Compatibility of switchmode rectifiers with engine generators, in Proceedings of 2000 International Telecommunications Energy Conference (INTELEC2000), pp. 626-631. [3] V. J. Thottuvelil, D. Chin, and G. C. Verghese, Hierarchical approaches to modeling high-power-factor ac-dc converters, in IEEE Transactions on Power Electronics, vol. 6, no. 2, pp. 179-187, 1991. [4] R. B. Ridley, Average small-signal analysis of the boost power factor correction circuit, in VPEC Proceedings, 1989, pp. 108-120. [5] V. Rajasekaran and J. Sun, Practical design issues for PFC converters with input filters, Proceedings of 2000 High Frequency Power Conversion Conference (HFPC00), October 2000, Boston, pp. 97-107. [6] C. Zhou and M. Jovanovic, Design trade-offs in continuous currentmode controlled boost power-factor-correction circuits, in Proceedings of 1992 High Frequency Power Conversion Conference, pp. 209-220. [7] R. Redl and A. Kislovski, Source impedance and current-control loop interaction in high-frequency power-factor correctors, in Records of IEEE PESC92, pp. 483-488, 1992. [8] P. C. Todd, UC3854 controlled power factor correction circuit design, Unitrode Application Note U-134. [9] J. Sun, Demystifying zero-crossing distortion in single-phase PFC converters, in Proceedings of 2002 IEEE Power Electronics Specialists Conference, pp., June 2002. [10] G. Spiazzi, L. Rossetto and J. A. Pomilio, Analysis of EMI filter induced instabilities in boost power factor preregulators, in Reconds of PESC '98, pp. 1048-1053, 1998. [11] G. Spiazzi and J. A. Pomilio, Interaction between EMI filter and power factor preregulators with average current control: analysis and design considerations, in Records of PESC '99, pp. 382-388, 1999. [12] J. Sun and R. M. Bass, Modeling and practical design issues for average current control, in Proceedings of 1999 IEEE Applied Power Electronics Conference (APEC99), pp. 980-986. [13] Texas Instruments, UCC3817 BiCMOS Power Factor Preregulator Evaluation Board - Users Guide, July 2001. [14] Environmental conditions and test procedures for airborne equipment DO-160D, Ch 16.

can be used instead for analog implementation. Fig. 9 compares the input impedance responses of the boost PFC converter [13] before and after a phase shift circuit described by (20) is added. The plots correspond to an input power of 53 W ( g = 0.25 10 6 ), and the measurement was taken with 400 Hz input. As can be seen, the model predicts that inclusion of the phase shift circuit would reduce the maximum input impedance dipping by as much as 5 dB, while actual measurement shows a 3 dB reduction due to imperfect experimental setup. The phase shift circuit described by (20) was used in [9] as a means to compensate for the leading phase of the input current so as to reduce the associated input current zero-crossing distortion. Practical implementation of the circuit and its other benefits were also discussed there. It was also noted in [10] that adding a phase shift, such as the one described by (20), to the reference current can improve the stability of the current loop in the interconnected EMI filter-PFC converter system, which is an indirect proof of the effect of reference current phase shift in reducing the dipping of converter input impedance. Furthermore, the analysis in the previous subsection indicates that reducing the dipping in the input impedance would also improve the response of the converter to distorted line voltages.
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Fig. 9. Reduction of input impedance dipping by phase shifting the reference current. a) Input impedance response predicted by the model with phase shift; b) measured input impedance with phase shift; c) predicted input impedance response when the phase shift is not present.

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