ADSD Fall2011 13 Multipliers Reduced Partial Products | Multiplication | Theory Of Computation

ADSD Fall 2011

Lecture # 13

Dr. Rehan Hafiz

<rehan.hafiz@seecs.edu.pk>

Course Website for ADSD Fall 2011
2
Furthermore, Material from the following sources has been consulted/used in these slides: 1. Stanford University:EE 486 lecture 7: Integer Multiplication M. J. Flynn 2. University of Minnesota : EE 5324 - VLSI Design II - Lectures Slides by Kia Bazargan, Spring 2006 3. Above reference uses slides from following: 1. [WE92] N. H. E. Weste, K. Eshraghian“Principles of CMOS VLSI Design: A System Perspective” Addison-Wesley, 2nd Ed., 1992. 2. [Rab96] J. M. Rabaey “Digital Integrated Circuits: A Design Perspective” Prentice Hall, 1996. 3. [Par00] B. Parhami “Computer Arithmetic: Algorithms and Hardware Designs” Oxford University Press, 2000.

http://lms.nust.edu.pk/

Acknowledgement: Material from the following sources has been consulted/used in these slides: 1. [CIL] Advanced Digital Design with the Verilog HDL, M D. Ciletti 2. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan 3. [STV] Advanced FPGA Design, Steve Kilts 4. Ercegovac’s Book: “Digital Arithmetic” 2004 5. Dr. Shoab A Khan’s CASE Lectures on Advanced Digital System Design
Material/Slides from these slides CAN be used with following citing reference: Dr. Rehan Hafiz: Advanced Digital System Design 2010 Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.

Lectures: Contact: Office:

Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm By appointment/Email VISpro Lab above SEECS Library

This Lecture
3

  

Canonical Sign Digit Multiplication by a Constant Modified BOOTH Recoding for reduction of Partial Products

Fast Multipliers
4

We have seen how to optimize the process of accumulation of partial products in a multiplier Can we reduce the number of partial products as well ???? No. of Partial Products depend upon the number of ONES in Multiplier

Multiplier

Multiplication

Formation of Partial Products

Addition of Partial Products (Reduction)

Final Addition Stage

Product

5

Lets reduce the number of ones in the multiplier

Canonic Signed Digit
6

 

Encoding a binary number such that it contains the fewest number of non-zero bits is called canonic signed digit(CSD). On average, CSD numbers contains about 33% fewer non-zero bits than two’s complement numbers. So, it should decrease the partial products We need to see which technique is giving us the canonic representation

String Property
7

Results in a radix-2 signed-digit representation of the multiplier Allowed Symbols {1,0,1}

Policy/ Algorithm
Look for string of ones in a binary number  For every string

Replace the Least Significant 1 by -1. Denoted as 1  Replace the remaining 1(s) with 0  Put a 1 after the MSB position of string

Examples
 

15 = 16-1
 

1111 = 10000-1 = 10001

110
(01101110)2 = (110)10  10110010  2^7-2^5+2^4-2

Canonical Sign Representation <Applying string property again & again to reach Canonical Sign Digit Representation>

00111101101111011101 00111101101111100101 00111101110000100101

String
String String String

00111110010000100101
01000010010000100101
Hence the number of 1(s) has reduced from 14 to 6. Both have the same value. (Calculated offline) -For multiplication with constant

Using this reduced digit form to reduce the number of Partial Products
9

 

This radix-2 signed-digit representation is Calculated Offline Hence used for Multiplication by a constant Strategy
 Apply

the String Property on a Multiplier offline to get the CSD representation  Use the modified representation if it has less no. of ones – Else use the original multiplier

Booth Recoding
Useful only for Multiplication with Constant
 

Uses String Property Apply the String Property on a Multiplier offline to get the CSD representation Use the modified representation if it has less no. of ones – Else use the original multiplier

Booth Multiplier: an Introduction
11

Recode each 1 in multiplier as “+2-1”

Might reduce the number of 1’s

0

0

1

1

1

1

1

1

0

0

+1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1
0 1 0 0 0 0 0 -1
Spring 2006

0

0

EE 5324 - VLSI Design II - © Kia Bazargan

Booth Multiplier: Recoding (Encoding) Example
12

0

1

1

0

1

1

1

0

0

0

1

0

(+1 -1) (+1 -1) +1

(+1 -1) (+1 -1) (+1 -1) 0 0 -1 0

(+1 -1)

0

-1 +1

0 +1 -1

0

If you use the last row in multiplication, you should get exactly the same result as using the first row (after all, they represent the same number!)
EE 5324 - VLSI Design II - © Kia Bazargan

13

Booth Recoding: Multiplication Example
Sign extension

1

1

0 0 0 0 0 0 0

1

1 0 0 1 1

0 0 0 1 +1 0 0 0 1 0 0 0 0 0 1 0 0 1

1 1 0 0 1 0

1 1 -1 0 0

0 0 0 0

6x 14

(-6)

0 1 0 0
Spring 2006

84

EE 5324 - VLSI Design II - © Kia Bazargan

Booth Algorithm - Example

Worst Case Booth Example

Booth Recoding: Advantages and Disadvantages

Potential advantage: might reduce the # of 1’s in multiplier Performance increase depends on the type of constant operand Disadvantage
 Uncertainty

of usefulness

What else we can do ?
17

Booth Recoding
 We

decreased the partial products by decreasing the number of ONES of Multiplier

Moving to higher Radix
 Radix-2

{0,1}  Radix-4 {0,1,2,3}

What else can we do ?

1 0 1

0 1

1 0 1

1 1

0 1 2

1 0

1
1 1 0 1 0 1

0
1 0

1
1 1

1
0

0
1

1

0

This way we are guaranteed to no. of reduce partial to half Any issue ?

But what about this case ?
19

1 0

0 1

1 0

1 1

0 1

1 1

1

1

3

We have a 3 which is difficult to be handled Simple shifting can’t be performed to handle it Because if we get 3, it means 2+1 hence resulting in 2 partial products

So, we have a problem moving to higher Radices
20

Not every bit combination is useful
 Example-

11,011,111

What is useful:
 1:

“001” - Simply Add  2: “010” - Shift Left & Add  4: “100” - Double Shift Left & Add

Numbers are required to be in this form
 (-2,

-1, 0, +1, +2)

Modified Booth Recoding
21

 

  

A modified version of BOOTH Recoding Makes intelligent use of String Property to represent bits in the following form (-2, -1, 0, +1, +2) Gets rid of 3s in the BOOTH Recoding This technique reduces number of pps into half Can be employed for variables as well

Modified Booth Multiplier: Idea
22

Group pairs, leaving –2, -1, 0, 1, 2
 Grouping reduces #

of partial products by half  Gets rid of 3’s (sequences of 1’s in general)
0 1 1 0 1 1 1 0 0 0 1 0

(+1 -1) (+1 -1) +1 0 +2

(+1 -1) (+1 -1) (+1 -1) 0

(+1 -1)

-1 +1 -1

0

0

-1 0 -2

0 +1 -1 0 +1 -2
[©Hauck]

Modified Booth Multiplier: Paper & Pen Process
23

  

First Apply String Property Then make pairs of two Denote each 2 bit pair as a single value defined by the proper weights (21 20)

0

1

1

0

1

1

1

0

0

0

1

0

(+1 -1) (+1 -1) +1 0 +2

(+1 -1) (+1 -1) (+1 -1) 0

(+1 -1)

-1 +1 -1

0

0

-1 0 -2

0 +1 -1 0 +1 -2
[©Hauck]

Radix-4 Modified Booth Multiplier
24

0 +1

1 0

1

0

1 0

1 0

1 -1

0 0

0

0

1

0 0

-1 +1

0 +1 -1

+2

-1

0

-2

+1

-2

(+2)(45) + (-1)(44) + (0)(43) + (-2)(42) + (+1)(41) + (-2)(40)

Modified Booth Multiplier Encoding Table & Explanation
25

i+1 0 0 0 0 1 1 1 1

i 0 0 1 1 0 0 1 1

i-1 0 1 0 1 0 1 0 1

add 0*M 1*M 1*M 2*M –2*M –1*M –1*M 0*M

Explanation No string of 1’s in sight End of a string of 1’s Isolated 1 End of a string of 1’s Beginning of a string of 1’s End one string, begin new one Beginning of a string of 1’s Continuation of string of 1’s
[Par] p. 160

Requirement for Modified BOOTH
26

Considering a x b, where
a

multiplicand  b multiplier

Modified BOOTH requires us to develop the mechanism to pre-compute & than use–2a, -1a, 0, 1a and 2a

(Modified) Booth Multiplier: Example
27

Retire two bits per shift operation 0 0 1 1 0 1
1 1 1 0 1 0

13 -6

i+1 0 0 0 0 1 1 1 1

i 0 0 1 1 0 0 1 1

i-1 0 1 0 1 0 1 0 1

add 0*M 1*M 1*M 2*M –2*M –1*M –1*M 0*M

1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 0 0 0 0 0 0
1 1 1

0 -1 -2

1 1 1 0 1 1 0 0 1 0

© Kia Bazargan

Modified Booth Algorithm: Unsigned numbers
1. 2.

Pad the LSB with one zero Pad the MSB
 

Even Numbers  Two Zeros Odd Numbers One Zero

3. 4. 5. 6.

Divide the multiplier into overlapping groups of 3-bits Determine partial product scale factor from modified Booth-2 encoding table Compute the multiplicand multiplies Sum partial products

http://etd.gsu.edu/theses/available/etd-12012006-104849/unrestricted/thankachan_shibi_p_200608_ms.pdf

Modified Booth
 1.

Example: Pad LSB with 1 zero
b7 b6 b5 b4 b3 b2 b1 b0 0

2.

n is even then pad the MSB with two zeros
0 0 b7 b6 b5 b4 b3 b2 b1 b0 0

3.

Form 3-bit overlapping groups for n=8 we have 5 groups
0 0 0 0 0 1 0 1 0 0 0

0

0

b7

b6

b5

b4

b3

b2

b1

b0

0

Modified Booth
4.

Determine partial product scale factor from modified booth 2 encoding table.
0 0 0 0 1 0 1 0 0 0 bi+1 0 0 Groups Coding 0 bi 0 0 1 bi-1 0 1 0 Action 0×a 1×a 1×a

0

0
0 0 0 0

0
1 1 0 0

0
0 0 0 0

0×a
1×a 1×a 0×a 0×a

0
1 1 1 1

1
0 0 1 1

1
0 1 0 1

2×a
-2 × a -1 × a -1 × a 0×a

Modified Booth
5.

Compute the Multiplicand Multiples (& all the partial products)
000001000 Groups Coding 0 0 0 0 0×a 1×a 1×a 0×a ×000010100 00000000001000 000000001000 0000000000 00000000 8 20 1×a 1×a

0 0 0 0

0 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0×a

0×a 0×a

0

0

0

0×a

Modified Booth
6.

Sum Partial Products
000001000 ×000010100 00000000001000 +000000001000 0000000000 00000000 8 20 1×a 1×a

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0×a

0×a 0×a

0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 160

Modified Booth Algorithm: Signed numbers
1. 2.

Pad the LSB of multiplier with one zero. MSB Padding
1. 2.

If n is even don’t pad the MSB ( n/2 PP’s) if n is odd sign extend the MSB by 1 bit ( n+1/2 PP’s)

3.

4.

5. 6.

Divide the multiplier into overlapping groups of 3bits. Determine partial product scale factor from modified Booth-2 encoding table Compute the multiplicand multiplies Sum Partial Products

http://www.stanford.edu/class/ee486/doc/lecture8.pdf

34

Proof that BOOTH Recoding handles 2’s complement numbers
http://people.wallawalla.edu/~curt.nelson/ engr434/project/booth_sec3.11.pdf

Modified Booth
 1.

Example: Pad LSB with 1 zero
b7 b6 b5 b4 b3 b2 b1 b0 0

2.

n is even then do not pad the MSB
b7 b6 b5 b4 b3 b2 b1 b0 0

3.

Form 3-bit overlapping groups for n=8 we have 4 groups 0 1 1 0 1 0 0 1 0
b7 b6 b5 b4 b3 b2 b1 b0 0

Modified Booth
4.

Determine partial product scale factor from modified booth 2 encoding table.
0 1 1 0 1 0 0 1 0 bi+1 bi bi-1 Action

0
0 0 0 1 1 1 1

0
0 1 1 0 0 1 1

0
1 0 1 0 1 0 1

0×a
1×a 1×a 2×a -2 × a -1 × a -1 × a 0×a

Groups 0 1 1 0 1 0 0 1 0 0 1 1

Codin g 1×a -2 × a -1 × a 2×a

Modified Booth
5. 6.

Compute the Multiplicand Multiples ADD
1 00 10 1 01 × 0 11 01 0 01 Codin g 0 1×a -107 105 1×a -2 × a -1 × a

Groups 0 1

1111111110010101
00 00 0 01 10 10 11 0 00 00 0 11 01 01 1 11 00 1 01 01 0

1 1
0

0 0
1

0 1
1

-2 × a -1 × a
2×a

2×a

1 1 0 1 0 1 0 0 0 0 0 1 1 1 0 1 -11235

Correction Vector Computation for Modified BOOTH Recoding

Here we divide the Correction Vector into two parts FIXED PART
 

Known in advanced Added to compensate sign extension & sign-bit inversion

Variable PART

Variable since depends upon the chosen action

Action = Multiplication with ZERO, ONE, -2 or 2

1 0 01 01 01 × 0 1 10 10 01

-107 105 1×a -2 × a -1 × a 2×a

1 11 11 11 11 0 01 01 01 0 00 00 01 10 1 01 10

000001101011
1 10 01 01 01 0

1 1 0 1 0 1 0 0 0 0 0 1 1 1 0 1 -11235

Correction Vector <Fixed Part>

To multiply with an n-bit multiplicand; we need to compute (n+1) bit partial products (-2a,-a,0,a,2a) with sign extension to accommodate multiplication by a 2-bit number (00,01,10)
1 0 0 1 0 1 0 1 × 0 1 1 0 1 0 0 1 -107 105

1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1
0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 0 0 0 0 1 1 1 0 1

1×a -2 × a -1 × a 2×a -11235

Correction Vector <Fixed Part>

Sign bit is the (n+1)th bit

1 0 0 1 0 1 0 1 × 0 1 1 0 1 0 0 1

-107 105

1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1
0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 0 1 0 1 0 1 0

1×a -2 × a -1 × a 2×a

Correction Vector <Fixed Part>

For correction vector we need to invert the sign bit & add one

1 0 0 1 0 1 0 1 × 1 1 1 1 1 1 0 0 1 0 1 0 1
0 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 0 1 0 1 0

-107 105

0 1 1 0 1 0 0 1

1×a -2 × a -1 × a 2×a

Correction Vector <Fixed Part>

Extend with all ONES

1 0 0 1 0 1 0 1 × 1 1 1 1 0 1 1 0 1 0 0 1

-107 105

1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1
1 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 1 0 0 1 1 0 1 0 1 1 1 1 0 0 1 0 1 0 1 0

1×a -2 × a -1 × a 2×a

Correction Vector <Variable Part>

This part depends on the sign of generated partial product

1 0 0 1 0 1 0 1 × 1 1 1 1 0 1 1 0 1 0 0 1

-107 105

1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1

1×a

1 1 1 1 1 0 1 1 0 1 0 1 1 0

-2 × a

1 1 1 0 0 1 1 0 1 0 1 1

-1 × a

1 1 0 0 1 0 1 0 1 0

2×a

Correction Vector <Variable Part>

This part depends on the sign of generated partial product <Blue Shade> Underlined text shows the bits that are the result of the complement operation -2a
  

1 0 0 1 0 1 0 1 × 1 1 1 1 0 1 1 0 1 0 0 1

-107 105

1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 0 1 0 1

1×a

-2 × a

Invert Add 1 Shift Left

-a
 

-1 × a

Invert Add 1

0 1 1 1 0 0 1 0 1 0 1 0 0 0
2×a

Correction Vector <Variable Part>
1 0 0 1 0 1 0 1 ×
bi+1 bi bi-1 Action CV

-107 105

0 1 1 0 1 0 0 1 1

1

1

1

0

0

0

0a

00

0 0
0 1 1 1 1

0 1
1 0 0 1 1

1 0
1 0 1 0 1

1a 1a
2a -2 a -1 a -1 a 0a

00 00
00 10 01 01 00

1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 0 1 0 1

1×a

-2 × a

-1 × a

0 1 1 1 0 0 1 0 1 0 1 0 0 0
2×a

Modified BOOTH With & Without Correction Vector
46

1 0 0 1 0 1 0 1 × 0 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 1 1 × 1

1 0 0 1 0 1 0 1 0 1 1 0 1 0 0 1

1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 0 0

0 0 0 0 0 0 1 1 0 1 0 1 1 0

1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0

0 0 0 0 0 1 1 0 1 0 1 1

1 1 1 1 1 0 0 1 0 1 0 1

0 1 1 1 0 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0 0 0
1 1 0 1 0 1 0 0 0 0 0 1 1 1 0 1

1 1 0 1 0 1 0 0 0 0 0 1 1 1 0 1

Correction Vector Computation for Modified BOOTH Recoding

Here we divide the Correction Vector into two parts

FIXED PART
 

Known in advanced Added to compensate sign extension & sign-bit inversion Variable since depends upon the chosen action

Variable PART

Action = Multiplication with ZERO, ONE, -2 or 2

Modified Booth Multiplier Hardware Implementation

Modified Booth HW Planning: Signed numbers
 

Pad the LSB with one zero. MSB Padding  If n is even don’t pad the MSB ( n/2 PP’s)  if n is odd sign extend the MSB by 1 bit ( n+1/2 PP’s) Divide the multiplier into overlapping groups of 3-bits. Pre-Compute all the n+1 bit partial products that are possible due to all the possible actions: -2a,-a,0,a,2a Pre-Compute the Variable Part of Correction Vector for all the possible actions: 00, 01,10

 

  

Determine partial product factor from table
SELECT the appropriate PP & Variable Correction Vectors Sum All the Partial Products

Modified BOOTH With Correction Vector in H.W
50

1 0 0 1 0 1 0 1 × 1 1 1 1 0 1 1 0 1 0 0 1

-107 105
bi+1 bi bi-1 Action CV

0 1×a 0 0 -2 × a 0 1 0 0

0 0 1 1 0

0 1 0 1 0

0a 1a 1a 2a -2 a

00 00 00 00 10

1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1

1 1 1 1 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 0 1 0 1

1
-1 × a 1 1 2×a

0
1 1

1
0 1

-1 a
-1 a 0a

01
01 00

0 1 1 1 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 0 0 0 1 1 1 0 1

Coding the Booth Recoder
<Determine partial product factor from table>
51

begin
case(recoderIn) 3'b000: RECODERfn = 3'b000; 3'b001: RECODERfn = 3'b001; 3'b010: RECODERfn = 3'b001;

Xi+1

Xi

Xi-1 Action

0 0
0 0 1 1 1 1

0 0
1 1 0 0 1 1

0 1
0 1 0 1 0 1

0×a 1×a
1×a 2×a -2 × a -1 × a -1 × a 0×a

3'b011: RECODERfn = 3'b010; 3'b100: RECODERfn = 3'b110; 3'b101: RECODERfn = 3'b111; 3'b110: RECODERfn = 3'b111; 3'b111: RECODERfn = 3'b000; default: RECODERfn = 3'bx;
endcase end

Code Snippet Taken from: Adv. Digital Design By Dr. Shoab A. Khan CASE

Selecting Correct PPs & Variable CV
52

Xi+1
0 0 0 0 1 1 1 1

Xi
0 0 1 1 0 0 1 1

Xi-1 Action
0 1 0 1 0 1 0 1 0×a 1×a 1×a 2×a -2 × a -1 × a -1 × a 0×a

3'b000: begin ppi = {1'b1,zeros}; correctionVector = 2'b00; end 3'b001: begin ppi = a; correctionVector = 2'b00; end 3'b010: begin ppi = _2a; correctionVector = 2'b00; end 3'b110: begin ppi = _2a_n; correctionVector = 2'b10; end 3'b111: begin ppi = a_n; correctionVector = 2'b01; end default: begin ppi = 'bx; correctionVector = 2'bx; end

Code Snippet Taken from: Adv. Digital Design By Dr. Shoab A. Khan CASE

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