ADSD Fall 2011

Lecture # 12

Dr. Rehan Hafiz

<rehan.hafiz@seecs.edu.pk>

Course Website for ADSD Fall 2011
2

http://lms.nust.edu.pk/
Acknowledgement: Material from the following sources has been consulted/used in these slides: 1. [CIL] Advanced Digital Design with the Verilog HDL, M D. Ciletti 2. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan 3. [STV] Advanced FPGA Design, Steve Kilts 4. Ercegovac’s Book: “Digital Arithmetic” 2004 5. Dr. Shoab A Khan’s CASE Lectures on Advanced Digital System Design
Material/Slides from these slides CAN be used with following citing reference: Dr. Rehan Hafiz: Advanced Digital System Design 2010
Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.

Lectures: Contact: Office:

Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm By appointment/Email VISpro Lab above SEECS Library

Lecture Overview
3

Last Lecture

Multi-Operand Addition

This Lecture
 Binary

Multiplication
Numbers

 Signed/Unsigned
 Architecture  Q format

Multiplication  Correction Vector

Binary Multiplication
4

Addition of multiple terms
 Sequential –

[CIL]

using a single adder  Combinational Logic – using compression trees

Sequential Multiplier-1
5

How Right Shifting the Accumulator Register helps ?
6

If Multiplying bit is 1 ADD Multiplicand & Shift If Multiplying bit is 0 Just Shift

http://www.parl.clemson.edu/~walt/ece327/mult.v

Sequential Multiplier-2
7

Sequential Multiplier-2
8

Add 0 or Add 1

Can we further save a register

Sequential Multiplier-3
9

Make use of Product Register

Sequential Multiplier-3 Example
10

Fractional Numbers
11

Multiplication of two numbers Qm.n & Qo.p result into a product with Q(m+o).(n+p) bits.  Taking 2’s complement of fractional number

 Same

as for usual integer binary numbers

 Take Bitwise Complement
 Add 1

Don’t Get Confused by Book Example 

-

Signed Number Multiplication
12

(Incorrect; result should be –1)

Negative Multiplicand, Positive Multiplier Sign Extend the Multiplicand equal to the product bits before the multiplication process
13

Signed Multiplicand, Positive Multiplier [Fractional Number] Align the bits & then forget about the fractional dot ! Sign Extend the Multiplicand equal to the product bits before the multiplication process
14

Positive Multiplicand, Negative Multiplier Sign Extend the Multiplier equal to Multiplicand bit Last Partial Product needs to be subtracted OR Add 2’s complement
15

Positive Multiplicand, Signed Multiplier [Fractional Number] Align the bits & then forget about the fractional dot ! Sign Extend the Multiplier equal to Multiplicand bit Last Partial Product needs to be subtracted OR Add 2’s complement
16

Signed Multiplicand, Signed Multiplier Sign Extend the Multiplier Last Partial Product needs to be subtracted OR Add 2’s complement
17

Signed Negative Multiplicand, Signed Negative Multiplier (Fractional Number) Align the bits & then forget about the fractional dot ! Sign Extend the Multiplier Last Partial Product needs to be subtracted OR Add 2’s complement
18

Signed Multiplier
19

We can adjust the previous algorithm to work with signed integers
 make

sure each shift is an arithmetic shift

 right shift – extend the

sign bit (keep the MS bit the same instead of shifting in a 0).

Example (-1 * -1)
20

At each addition… Perform 4 bit addition, Discard Carry out & Shift Right while replicating MSB
1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1

P Add = S Add =

0 1 1 1 1 1

0 1 1 1 1 1

0 1 1 1 1 1

0 1 1 1 1 0

S Add
= S

1 1
1 1

1 1
1 1 0 0

1 1
1 1 0 0

1 1
0 1 1 0

0
0 0

1
1 0

1
1 1

0
0 1

Add(2’s 0 ) = 0

0

0

1

1

S

0

0

0

0

0

0

1

Example (-1 * -5) (1111*1011)
21

P Add = S Add =

0 1 1 1 1 1

0 1 1 1 1 1

0 1 1 1 1 1

0 1 1 1 1 0

1 1 1 1

0 0 1 1

1 1 0 0

1 1 1 1

S Add
= S

1 0
1 1

1 0
1 1 0 0

1 0
1 1 0 0

1 0
1 1 1 0

0
0 1

1
1 0

1
1 1

0
0 1

Add(2’s 0 ) = 0

1

0

1

1

S

0

0

0

0

0

1

0

1

Example (1 * -5) (0001*1011)
22

P Add = S Add =

0 0

0 0

0 0

0 1 1

1

0

1

1

1 1 1 1

S Add
= S Add(2’s 1 ) = 1 1 1 1 1 1 1

1
1 0

1
1 1 1

0

1

1

S

1

1

1

1

1

0

1

1

Complexities & special cases Sign Extension, 2’c Complement
23

Two things have to be done dynamically
 

Sign Extension <Dependent> 2’s Complement <Dependent>

What can be done ?

What can we do about Sign Extension
24

Rather than following a selective sign extension for signed numbers we follow a common policy for all (+ve & -ve) numbers Policy
 Complement the

sign bit  Always extend with ONEs  Add ONE to the sign bit
B is positive (S=0) B=0 0 0 0 0 0 . 1 1 0 1 0 1 1 B=1 1 1 1 1 0 . 1 1 0 1 0 1 1 + 1 000000.1101011 B is negative (S=1) B=1 1 1 1 1 1 . 1 1 0 1 0 1 1 B=1 1 1 1 1 1 . 1 1 0 1 0 1 1 1 + 111111.1101011

Example-Sign Extension
25

(.)

(.)

(.)

(.)

(.)
1 1 1 1 1 1 1 (.) 1 1 1 (.) (.) 1 1 (.) (.) (.) 1 (.) (.) (.) (.) 1

(.)
(.) (.) (.)

(.)
(.) (.)

(.)
(.)

Policy Complement the sign bit Add ONE to the sign bit Always extend with ONEs

Can we do something about 2’s complement & its sign extension
26

Do 2’s Complement

(.)(.)(.)(.) 1+

Than do Sign Extension

1(.)(.)(.)(.) 1 1+
 So

the MSB is complemented two times; first due to 2’s complement & secondly due to sign extension. Since complement of complement is the original bit. MSB needs not to be complemented

ExampleSign Extension & 2’s Complement
27

(Carries) (3) 1 1 (2) 1 1 (1) 1 1 (1) 1 (.)

(.) (.) (.) (.)

(.) (.) (.) (.)

(.) (.) (.) (.)

(.) (.) (.)

1
1

1
(.) 1

(.)
(.) 1 0

(.)
(.) 1 1

(.)
(.) 1 1 0

(.)
Due to 2s complement

1

0

0

0

0 Correction Vector for multiplication of TWO 4-bit signed numbers

Exercise: -2 * -2 or -2 *2

2’s Complement Example
28

1 (1) (1) (2) (2) 0 1 1 1

1 1 0 1

1 1 0 0

0 0 0

0
1 1 0 0 0 0 0 0

1
0 1 0

1
1 0 0

0
0 1 0 0 0 0

2’s Complement Example
29

1 (1) (1) (2) (2) 0 1 1 1

1 1 0 1

1 1 0 0

0 0 0 Add

0
1 1 0 0 0 0 0 0

1
0 1 0

1
1 0 0

0
0 1 0 0 0 0

Output

Correction Vector Examples
30

Discard the carries after the MSB Note the different Correction Vectors for +ve & -ve numbers

Benefit of Correction Vector
31

Reduced Logic Generalized Algorithms

Designing a Fast Multiplier (Single Cycle Multiplication)
32

Formation of Partial Products
 Sign

Multiplier

Multiplication

extension OR Generation of Correction Vector

Formation of Partial Products

Addition of PP
 Wallace/Dada

Addition of Partial Products (Reduction)

Compression Tree
Final Addition Stage

Final Addition using any fast Ripple Carry Adder

Product

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