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TP3054 TP3057 Enhanced Serial Interface CODEC Filter COMBO Family

August 1994

TP3054 TP3057 Enhanced Serial Interface CODEC Filter COMBO Family


General Description
The TP3054 TP3057 family consists of m-law and A-law monolithic PCM CODEC filters utilizing the A D and D A conversion architecture shown in Figure 1 and a serial PCM interface The devices are fabricated using Nationals advanced double-poly CMOS process (microCMOS) The encode portion of each device consists of an input gain adjust amplifier an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz Also included are auto-zero circuitry and a companding coder which samples the filtered signal and encodes it in the companded m-law or A-law PCM format The decode portion of each device consists of an expanding decoder which reconstructs the analog signal from the companded m-law or A-law code a low-pass filter which corrects for the sin x x response of the decoder output and rejects signals above 3400 Hz followed by a single-ended power amplifier capable of driving low impedance loads The devices require two 1 536 MHz 1 544 MHz or 2 048 MHz transmit and receive master clocks which may be asynchronous transmit and receive bit clocks which may vary from 64 kHz to 2 048 MHz and transmit and receive frame sync pulses The timing of the frame sync pulses and PCM data is compatible with both industry standard formats

Features
Y

Y Y Y Y Y Y Y Y Y Y Y

Complete CODEC and filtering system (COMBO) including Transmit high-pass and low-pass filtering Receive low-pass filter with sin x x correction Active RC noise filters m-law or A-law compatible COder and DECoder Internal precision voltage reference Serial I O interface Internal auto-zero circuitry m-law 16-pin TP3054 A-law 16-pin TP3057 Designed for D3 D4 and CCITT applications g 5V operation Low operating power typically 50 mW Power-down standby mode typically 3 mW Automatic power-down TTL or CMOS compatible digital interfaces Maximizes line interface card circuit density Dual-In-Line or surface mount packages See also AN-370 Techniques for Designing with CODEC Filter COMBO Circuits

Connection Diagrams
Dual-In-Line Package Plastic Chip Carriers

TL H 5510 1

Top View Order Number TP3054J or TP3057J See NS Package Number J16A Order Number TP3054N or TP3057N See NS Package Number N16A Order Number TP3054WM or TP3057WM See NS Package Number M16B
TL H 5510 10

Top View Order Number TP3057V See NS Package Number V20A

COMBO and TRI-STATE are registered trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation TL H 5510 RRD-B30M125 Printed in U S A

Block Diagram

FIGURE 1

TL H 5510 2

Pin Description
Symbol VBB GNDA VFRO VCC FSR Function Negative power supply pin VBB e b5V g 5% Analog ground All signals are referenced to this pin Analog output of the receive power amplifier Positive power supply pin VCC e a 5V g 5% FSX MCLKX Symbol Function should be synchronous with MCLKX for best performance When MCLKR is connected continuously low MCLKX is selected for all internal timing When MCLKR is connected continuously high the device is powered down Transmit master clock Must be 1 536 MHz 1 544 MHz or 2 048 MHz May be asynchronous with MCLKR Best performance is realized from synchronous operation Transmit frame sync pulse input which enables BCLKX to shift out the PCM data on DX FSX is an 8 kHz pulse train see Figures 2 and 3 for timing details The bit clock which shifts out the PCM data on DX May vary from 64 kHz to 2 048 MHz but must be synchronous with MCLKX The TRI-STATE abled by FSX PCM data output which is en-

Receive frame sync pulse which enables BCLKR to shift PCM data into DR FSR is an 8 kHz pulse train See Figures 2 and 3 for timing details DR Receive data input PCM data is shifted into DR following the FSR leading edge BCLKR CLKSEL The bit clock which shifts data into DR after the FSR leading edge May vary from 64 kHz to 2 048 MHz Alternatively may be a logic input which selects either 1 536 MHz 1 544 MHz or 2 048 MHz for master clock in synchronous mode and BCLKX is used for both transmit and receive directions (see Table I) MCLKR PDN Receive master clock Must be 1 536 MHz 1 544 MHz or 2 048 MHz May be asynchronous with MCLKX but 2

BCLKX

DX TSX GSX VFXIb VFXI a

Open drain output which pulses low during the encoder time slot Analog output of the transmit input amplifier Used to externally set gain Inverting input of the transmit input amplifier Non-inverting input of the transmit input amplifier

Functional Description
POWER-UP When power is first applied power-on reset circuitry initializes the COMBO and places it into a power-down state All non-essential circuits are deactivated and the DX and VFRO outputs are put in high impedance states To power-up the device a logical low level or clock must be applied to the MCLKR PDN pin and FSX and or FSR pulses must be present Thus 2 power-down control modes are available The first is to pull the MCLKR PDN pin high the alternative is to hold both FSX and FSR inputs continuously low the device will power-down approximately 1 ms after the last FSX or FSR pulse Power-up will occur on the first FSX or FSR pulse The TRI-STATE PCM data output DX will remain in the high impedance state until the second FSX pulse SYNCHRONOUS OPERATION For synchronous operation the same master clock and bit clock should be used for both the transmit and receive directions In this mode a clock must be applied to MCLKX and the MCLKR PDN pin can be used as a power-down control A low level on MCLKR PDN powers up the device and a high level powers down the device In either case MCLKX will be selected as the master clock for both the transmit and receive circuits A bit clock must also be applied to BCLKX and the BCLKR CLKSEL can be used to select the proper internal divider for a master clock of 1 536 MHz 1 544 MHz or 2 048 MHz For 1 544 MHz operation the device automatically compensates for the 193rd clock pulse each frame With a fixed level on the BCLKR CLKSEL pin BCLKX will be selected as the bit clock for both the transmit and receive directions Table 1 indicates the frequencies of operation which can be selected depending on the state of BCLKR CLKSEL In this synchronous mode the bit clock BCLKX may be from 64 kHz to 2 048 MHz but must be synchronous with MCLKX Each FSX pulse begins the encoding cycle and the PCM data from the previous encode cycle is shifted out of the enabled DX output on the positive edge of BCLKX After 8 bit clock periods the TRI-STATE DX output is returned to a high impedance state With an FSR pulse PCM data is latched via the DR input on the negative edge of BCLKX (or BCLKR if running) FSX and FSR must be synchronous with MCLKX R TABLE I Selection of Master Clock Frequencies BCLKR CLKSEL Clocked 0 1 Master Clock Frequency Selected TP3057 2 048 MHz 1 536 MHz or 1 544 MHz 2 048 MHz TP3054 1 536 MHz or 1 544 MHz 2 048 MHz 1 536 MHz or 1 544 MHz ASYNCHRONOUS OPERATION For asynchronous operation separate transmit and receive clocks may be applied MCLKX and MCLKR must be 2 048 MHz for the TP3057 or 1 536 MHz 1 544 MHz for the TP3054 and need not be synchronous For best transmission performance however MCLKR should be synchronous with MCLKX which is easily achieved by applying only static logic levels to the MCLKR PDN pin This will automatically connect MCLKX to all internal MCLKR functions (see Pin Description) For 1 544 MHz operation the device automatically compensates for the 193rd clock pulse each frame FSX starts each encoding cycle and must be synchronous with MCLKX and BCLKX FSR starts each decoding cycle and must be synchronous with BCLKR BCLKR must be a clock the logic levels shown in Table 1 are not valid in asynchronous mode BCLKX and BCLKR may operate from 64 kHz to 2 048 MHz SHORT FRAME SYNC OPERATION The COMBO can utilize either a short frame sync pulse or a long frame sync pulse Upon power initialization the device assumes a short frame mode In this mode both frame sync pulses FSX and FSR must be one bit clock period long with timing relationships specified in Figure 2 With FSX high during a falling edge of BCLKX the next rising edge of BCLKX enables the DX TRI-STATE output buffer which will output the sign bit The following seven rising edges clock out the remaining seven bits and the next falling edge disables the DX output With FSR high during a falling edge of BCLKR (BCLKX in synchronous mode) the next falling edge of BCLKR latches in the sign bit The following seven falling edges latch in the seven remaining bits All four devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode LONG FRAME SYNC OPERATION To use the long frame mode both the frame sync pulses FSX and FSR must be three or more bit clock periods long with timing relationships specified in Figure 3 Based on the transmit frame sync FSX the COMBO will sense whether short or long frame sync pulses are being used For 64 kHz operation the frame sync pulse must be kept low for a minimum of 160 ns The DX TRI-STATE output buffer is enabled with the rising edge of FSX or the rising edge of BCLKX whichever comes later and the first bit clocked out is the sign bit The following seven BCLKX rising edges clock out the remaining seven bits The DX output is disabled by the falling BCLKX edge following the eighth rising edge or by FSX going low whichever comes later A rising edge on the receive frame sync pulse FSR will cause the PCM data at DR to be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode) All four devices may utilize the long frame sync pulse in synchronous or asynchronous mode In applications where the LSB bit is used for signalling with FSR two bit clock periods long the decoder will interpret the lost LSB as to minimize noise and distortion

Functional Description
TRANSMIT SECTION

(Continued) (due to encoding delay) which totals 290 ms Any offset voltage due to the filters or comparator is cancelled by sign bit integration RECEIVE SECTION The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter clocked at 256 kHz The decoder is A-law (TP3057) or m-law (TP3054) and the 5th order low pass filter corrects for the sin x x attenuation due to the 8 kHz sample hold The filter is then followed by a 2nd order RC active post-filter power amplifer capable of driving a 600X load to a level of 7 2 dBm The receive section is unity-gain Upon the occurrence of FSR the data at the DR input is clocked in on the falling edge of the next eight BCLKR (BCLKX) periods At the end of the decoder time slot the decoding cycle begins and 10 ms later the decoder DAC output is updated The total decoder delay is E 10 ms (decoder update) plus 110 ms (filter delay) plus 62 5 ms ( frame) which gives approximately 180 ms

The transmit section input is an operational amplifier with provision for gain adjustment using two external resistors see Figure 4 The low noise and wide bandwidth allow gains in excess of 20 dB across the audio passband to be realized The op amp drives a unity-gain filter consisting of RC active pre-filter followed by an eighth order switched-capacitor bandpass filter clocked at 256 kHz The output of this filter directly drives the encoder sample-and-hold circuit The A D is of companding type according to m-law (TP3054) or A-law (TP3057) coding conventions A precision voltage reference is trimmed in manufacturing to provide an input overload (tMAX) of nominally 2 5V peak (see table of Transmission Characteristics) The FSX frame sync pulse controls the sampling of the filter output and then the successive-approximation encoding cycle begins The 8-bit code is then loaded into a buffer and shifted out through DX at the next FSX pulse The total encoding delay will be approximately 165 ms (due to the transmit filter) plus 125 ms

Absolute Maximum Ratings


If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications VCC to GNDA VBB to GNDA Voltage at any Analog Input or Output 7V
b 7V

VCC a 0 3V to VBBb0 3V

VCC a 0 3V to GNDAb0 3V b 25 C to a 125 C Operating Temperature Range b 65 C to a 150 C Storage Temperature Range Lead Temperature (Soldering 10 seconds) 300 C ESD (Human Body Model) 2000V Latch-Up Immunity e 100 mA on any Pin limits printed in BOLD characters are guaranteed for VCC

Voltage at any Digital Input or Output

Electrical Characteristics Unless otherwise noted

e 5 0V g 5% VBB e b 5 0V g 5% TA e 0 C to 70 C by correlation with 100% electrical testing at TA e 25 C All other limits

are assured by correlation with other production tests and or product design and characterization All signals referenced to GNDA Typicals specified at VCC e 5 0V VBB e b5 0V TA e 25 C Symbol DIGITAL INTERFACE VIL VIH VOL Input Low Voltage Input High Voltage Output Low Voltage DX IL e 3 2 mA SIGR IL e 1 0 mA TSX IL e 3 2 mA Open Drain DX IH eb3 2 mA SIGR IH eb1 0 mA GNDAsVINsVIL All Digital Inputs VIHsVINsVCC DX GNDAsVOsVCC 24 24
b 10 b 10 b 10

Parameter

Conditions

Min

Typ

Max 06

Units V V V V V V V

22 04 04 04

VOH IIL IIH IOZ

Output High Voltage Input Low Current Input High Current Output Current in High Impedance State (TRI-STATE) Input Leakage Current Input Resistance Output Resistance Load Resistance Load Capacitance Output Dynamic Range Voltage Gain Unity Gain Bandwidth Offset Voltage Common-Mode Voltage Common-Mode Rejection Ratio Power Supply Rejection Ratio Output Resistance Load Resistance Load Capacitance Output DC Offset Voltage Power-Down Current Power-Down Current Power-Up Active Current Power-Up Active Current

10 10 10

mA mA mA

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES) IIXA RIXA ROXA RLXA CLXA VOXA AVXA FUXA VOSXA VCMXA CMRRXA PSRRXA RORF RLRF CLRF VOSRO ICC0 IBB0 ICC1 IBB1
b 2 5V s V s a 2 5V VFXI a or VFXI b b 2 5V s V s a 2 5V VFXI a or VFXI b b 200

200 1 3 50

nA MX X kX pF V V V MHz

10 10
b2 8

Closed Loop Unity Gain GSX GSX GSX RLt10 kX VFXI a to GSX 5000 1
b 20

28 2 20 25

mV V dB dB

CMRRXA l 60 dB DC Test DC Test Pin VFRO VFRO e g 2 5V

b2 5

60 60 1 600 500
b 200

ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES) 3 X X pF mV mA mA mA mA 200 05 0 05 50 50 15 03 90 90

POWER DISSIPATION (ALL DEVICES) No Load (Note) No Load (Note) No Load No Load

Note ICC0 and IBB0 are measured after first achieving a power-up state

limits printed in BOLD characters are guaranteed for VCC e 5 0V g 5% VBB e b5 0V g 5% TA e 0 C to 70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and or product design and characterization All signals referenced to GNDA Typicals specified at VCC e 5 0V VBB e b5 0V TA e 25 C All timing parameters are measured at VOH e 2 0V and VOL e 0 7V See Definitions and Timing Conventions section for test methods information Symbol 1 tPM Parameter Frequency of Master Clocks Conditions Depends on the Device Used and the BCLKR CLKSEL Pin MCLKX and MCLKR MCLKX and MCLKR MCLKX and MCLKR 485 BCLKX and BCLKR BCLKX and BCLKR MCLKX and MCLKR MCLKX and MCLKR First Bit Clock after the Leading Edge of FSX Long Frame Only VIH e 2 2V VIL e 0 6V Long Frame Only Short Frame Only Long Frame Only Load e 150 pF plus 2 LSTTL Loads Load e 150 pF plus 2 LSTTL Loads CL e 0 pF to 150 pF CL e 0 pF to 150 pF 50 20 160 160 100 100 160 160 0 0 80 0 140 140 165 165 488 Min Typ 1 536 1 544 2 048 50 50 15725 50 50 Max Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Timing Specifications Unless otherwise noted

tRM tFM tPB tRB tFB tWMH tWML tSBFM tSFFM tWBH tWBL tHBFL tHBFS tSFB tDBD tDBTS tDZC tDZF

Rise Time of Master Clock Fall Time of Master Clock Period of Bit Clock Rise Time of Bit Clock Fall Time of Bit Clock Width of Master Clock High Width of Master Clock Low Set-Up Time from BCLKX High to MCLKX Falling Edge Set-Up Time from FSX High to MCLKX Falling Edge Width of Bit Clock High Width of Bit Clock Low Holding Time from Bit Clock Low to Frame Sync Holding Time from Bit Clock High to Frame Sync Set-Up Time from Frame Sync to Bit Clock Low Delay Time from BCLKX High to Data Valid Delay Time to TSX Low Delay Time from BCLKX Low to Data Output Disabled Delay Time to Valid Data from FSX or BCLKX Whichever Comes Later Set-Up Time from DR Valid to BCLKR X Low Hold Time from BCLKR X Low to DR Invalid Set-Up Time from FSX R to BCLKX RLow Hold Time from BCLKX R Low to FSX R Low Hold Time from 3rd Period of Bit Clock Low to Frame Sync (FSX or FSR) Minimum Width of the Frame Sync Pulse (Low Level)

tSDB tHBD tSF tHF tHBFl

50 50 Short Frame Sync Pulse (1 Bit Clock Period Long) Short Frame Sync Pulse (1 Bit Clock Period Long) Long Frame Sync Pulse (from 3 to 8 Bit Clock Periods Long) 64k Bit s Operating Mode 50 100 100

ns ns ns ns ns

tWFL

160

ns

Timing Diagrams

7
TL H 5510 3

FIGURE 2 Short Frame Sync Timing

Timing Diagrams (Continued)

8
TL H 5510 4

FIGURE 3 Long Frame Sync Timing

Transmission Characteristics Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e 5 0V g 5% VBB e b5 0V g 5% TA e 0 C to 70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and or product design and characterization GNDA e 0V f e 1 02 kHz VIN e 0 dBm0 transmit input amplifier connected for unity gain non-inverting Typicals specified at VCC e 5 0V VBB e b 5 0V TA e 25 C
Symbol Parameter Conditions Min Typ Max Units AMPLITUDE RESPONSE Absolute Levels (Definition of Nominal Gain) tMAX Virtual Decision Valve Defined Per CCITT Rec G711 Transmit Gain Absolute Nominal 0 dBm0 Level is 4 dBm (600X) 0 dBm0 Max Overload Level TP3054 (3 17 dBm0) TP3057 (3 14 dBm0) TA e 25 C VCC e 5V VBB eb5V Input at GSX e 0 dBm0 at 1020 Hz TP3054 57 f e 16 Hz f e 50 Hz f e 60 Hz f e 200 Hz f e 300 Hzb3000 Hz f e 3300 Hz f e 3400 Hz f e 4000 Hz f e 4600 Hz and Up Measure Response from 0 Hz to 4000 Hz Relative to GXA Relative to GXA Sinusoidal Test Method Reference Level eb10 dBm0 VFXI a eb40 dBm0 to a 3 dBm0 VFXI a eb50 dBm0 to b40 dBm0 VFXI a eb55 dBm0 to b50 dBm0 TA e 25 C VCC e 5V VBB eb5V Input e Digital Code Sequence for 0 dBm0 Signal at 1020 Hz TP3054 57 f e 0 Hz to 3000 Hz f e 3300 Hz f e 3400 Hz f e 4000 Hz Relative to GRA Relative to GRA Sinusoidal Test Method Reference Input PCM Code Corresponds to an Ideally Encoded PCM Level eb 40 dBm0 to a 3 dBm0 eb 50 dBm0 to b 40 dBm0 eb 55 dBm0 to b 50 dBm0 RL e 600X

1 2276 2 501 2 492

Vrms VPK VPK

GXA

b 0 15

0 15
b 40 b 30 b 26 b0 1

dB dB dB dB dB dB dB dB dB dB dB dB

GXR

Transmit Gain Relative to GXA

b1 8 b 0 15 b 0 35 b0 7

0 15 0 05 0 b 14 b 32 01 0 05

GXAT GXAV GXRL

Absolute Transmit Gain Variation with Temperature Absolute Transmit Gain Variation with Supply Voltage Transmit Gain Variations with Level

b0 1 b 0 05

b0 2 b0 4 b1 2

02 04 12

dB dB dB

GRA

Receive Gain Absolute

b 0 15 b 0 15 b 0 35 b0 7 b0 1 b 0 05

0 15 0 15 0 05 0 b 14 01 0 05

dB dB dB dB dB dB dB

GRR

Receive Gain Relative to GRA

GRAT GRAV GRRL

Absolute Receive Gain Variation with Temperature Absolute Receive Gain Variation with Supply Voltage Receive Gain Variations with Level

b0 2 b0 4 b1 2 b2 5

02 04 12 25

dB dB dB V

VRO

Receive Output Drive Level

Transmission Characteristics (Continued) Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e 5 0V g 5% VBB e b5 0V g 5% TA e 0 C to 70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and or product design and characterization GNDA e 0V f e 1 02 kHz VIN e 0 dBm0 transmit input amplifier connected for unity gain non-inverting Typicals specified at VCC e 5 0V VBB e b5 0V TA e 25 C
Symbol Parameter Conditions Min Typ Max Units ENVELOPE DELAY DISTORTION WITH FREQUENCY DXA DXR Transmit Delay Absolute Transmit Delay Relative to DXA f e 1600 Hz f e 500 Hz 600 Hz f e 600 Hz 800 Hz f e 800 Hz 1000 Hz f e 1000 Hz 1600 Hz f e 1600 Hz 2600 Hz f e 2600 Hz 2800 Hz f e 2800 Hz 3000 Hz f e 1600 Hz f e 500 Hz 1000 Hz f e 1000 Hz 1600 Hz f e 1600 Hz 2600 Hz f e 2600 Hz 2800 Hz f e 2800 Hz 3000 Hz
b 40 b 30

290 195 120 50 20 55 80 130 180


b 25 b 20

315 220 145 75 40 75 105 155 200

ms ms ms ms ms ms ms ms ms ms ms ms ms ms

DRA DRR

Receive Delay Absolute Receive Delay Relative to DRA

70 100 145

90 125 175

NOISE NXC NXP NRC NRP NRS PPSRX Transmit Noise C Message Weighted Transmit Noise P Message Weighted Receive Noise C Message Weighted Receive Noise P Message Weighted Noise Single Frequency Positive Power Supply Rejection Transmit Negative Power Supply Rejection Transmit Positive Power Supply Rejection Receive TP3054 TP3057 PCM Code is Alternating Positive and Negative Zero TP3054 PCM Code Equals Positive Zero TP3057 f e 0 kHz to 100 kHz Loop Around Measurement VFXI a e 0 Vrms VFXI a e b50 dBm0 VCC e 5 0 VDC a 100 mVrms f e 0 kHz 50 kHz (Note 2) VFXI a e b50 dBm0 VBB eb5 0 VDC a 100 mVrms f e 0 kHz 50 kHz (Note 2) PCM Code Equals Positive Zero VCC e 5 0 VDC a 100 mVrms Measure VFR0 f e 0 Hz 4000 Hz f e 4 kHz 25 kHz f e 25 kHz 50 kHz PCM Code Equals Positive Zero VBB eb5 0 VDC a 100 mVrms Measure VFR0 f e 0 Hz 4000 Hz f e 4 kHz 25 kHz f e 25 kHz 50 kHz 12
b 74

15
b 67

dBrnC0 dBm0p

8
b 82

11
b 79 b 53

dBrnC0 dBm0p dBm0

40

dBC

NPSRX

40

dBC

PPSRR

40 40 36

dBC dB dB

NPSRR

Negative Power Supply Rejection Receive

40 40 36

dBC dB dB

10

Transmission Characteristics (Continued) Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e 5 0V g 5% VBB e b5 0V g 5% TA e 0 C to 70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and or product design and characterization GNDA e 0V f e 1 02 kHz VIN e 0 dBm0 transmit input amplifier connected for unity gain non-inverting Typicals specified at VCC e 5 0V VBB e b5 0V TA e 25 C
Symbol SOS Parameter Spurious Out-of-Band Signals at the Channel Output Conditions Loop Around Measurement 0 dBm0 300 Hz to 3400 Hz Input PCM Code Applied at DR 4600 Hz 7600 Hz 7600 Hz 8400 Hz 8400 Hz 100 000 Hz Min Typ Max
b 30

Units dB

b 30 b 40 b 30

dB dB dB

DISTORTION STDX STDR Signal to Total Distortion Transmit or Receive Half-Channel Sinusoidal Test Method (Note 3) Level e 3 0 dBm0 e 0 dBm0 to b 30 dBm0 eb 40 dBm0 XMT RCV eb 55 dBm0 XMT RCV 33 36 29 30 14 15
b 46 b 46

dBC dBC dBC dBC dBC dBC dB dB dB

SFDX SFDR IMD

Single Frequency Distortion Transmit Single Frequency Distortion Receive Intermodulation Distortion Loop Around Measurement VFX a eb4 dBm0 to b21 dBm0 Two Frequencies in the Range 300 Hz 3400 Hz

b 41

CROSSTALK CTX-R CTR-X Transmit to Receive Crosstalk 0 dBm0 Transmit Level Receive to Transmit Crosstalk 0 dBm0 Receive Level f e 300 Hz 3400 Hz DR e Quiet PCM Code f e 300 Hz 3400 Hz VFXI e Multitone (Note 2) ENCODING FORMAT AT DX OUTPUT TP3054 m-Law VIN (at GSX) e a Full-Scale VIN (at GSX) e 0V VIN (at GSX) ebFull-Scale 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 TP3057 A-Law (Includes Even Bit Inversion) 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0
b 90 b 90 b 75 b 70

dB dB

Note 1 Measured by extrapolation from the distortion test result at b 50 dBm0 Note 2 PPSRX NPSRX and CTR-X are measured with a b 50 dBm0 activation signal applied to VFXI a Note 3 Devices are measured using C message weighted filter for m-Law and psophometric weighted filter for A-Law

11

Applications Information
POWER SUPPLIES While the pins of the TP305X family are well protected against electrical misuse it is recommended that the standard CMOS practice be followed ensuring that ground is connected to the device before any other connections are made In applications where the printed circuit board may be plugged into a hot socket with power and clocks already present an extra long ground pin in the connector should be used All ground connections to each device should meet at a common point as close as possible to the GNDA pin This minimizes the interaction of ground return currents flowing through a common bus impedance 0 1 mF supply decoupling capacitors should be connected from this common ground point to VCC and VBB as close to the device as possible For best performance the ground point of each CODEC FILTER on a card should be connected to a common card ground in star formation rather than via a ground bus This common ground point should be decoupled to VCC and VBB with 10 mF capacitors RECEIVE GAIN ADJUSTMENT For applications where a TP305X family CODEC filter receive output must drive a 600X load but a peak swing lower than g 2 5V is required the receive gain can be easily adjusted by inserting a matched T-pad or q-pad at the output Table II lists the required resistor values for 600X terminations As these are generally non-standard values the equations can be used to compute the attenuation of the closest practical set of resistors It may be necessary to use unequal values for the R1 or R4 arms of the attenuators to achieve a precise attenuation Generally it is tolerable to allow a small deviation of the input impedance from nominal while still maintaining a good return loss For example a 30 dB return loss against 600X is obtained if the output impedance of the attenuator is in the range 282X to 319X (assuming a perfect transformer)

T-Pad Attenuator

R1 e Z1

N

N2 a 1 2b1

b 20Z1 Z2

N

N
2b1

R2 e 20Z1 Z2

N

N
2b1

Where N e and Se

POWER IN POWER OUT

0Z2
Z1

Also Z e 0ZSC  ZOC Where ZSC e impedance with short circuit termination and ZOC e impedance with open circuit termination

q-Pad Attenuator

TL H 5510 5

R3 e

Z1 Z2 2

N2 b 1 N

J J

N2 b 1 R3 e Z1 N2 b 2NS a 1 Note See Application Note 370 for further details

12

Applications Information (Continued)


TABLE II Attentuator Tables for Z1 e Z2 e 300X (All Values in X) dB 01 02 03 04 05 06 07 08 09 10 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 20 R1 17 35 52 69 85 10 4 12 1 13 8 15 5 17 3 34 4 51 3 68 84 100 115 379 143 156 168 180 190 200 210 218 233 246 R2 26k 13k 8 7k 6 5k 5 2k 4 4k 3 7k 3 3k 2 9k 2 6l 1 3k 850 650 494 402 380 284 244 211 184 161 142 125 110 98 77 61 R3 35 69 10 4 13 8 17 3 21 3 24 2 27 7 31 1 34 6 70 107 144 183 224 269 317 370 427 490 550 635 720 816 924 1 17k 1 5k R4 52k 26k 17 4k 13k 10 5k 8 7k 7 5k 6 5k 5 8k 5 2k 2 6k 1 8k 1 3k 1 1k 900 785 698 630 527 535 500 473 450 430 413 386 366

Typical Synchronous Application

TL H 5510 6

Note 1 XMIT gain e 20 c log

R1 a R2 R2

where (R1 a R2) l 10 KX

FIGURE 4

13

Connection Diagrams (Continued)


Plastic Chip Carrier

TL H 5510 7

Top View Order Number TP3057V See NS Package Number V20A

14

Physical Dimensions inches (millimeters)

Cavity Dual-In-Line Package (J) Order Number TP3054J or TP3057J NS Package Number J16A

Molded Small Outline Package (WM) Order Number TP3054WM or TP3057WM NS Package Number M16B

15

TP3054 TP3057 Enhanced Serial Interface CODEC Filter COMBO Family

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N) Order Number TP3054N or TP3057N NS Package Number N16A

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