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Experiment No.

- 4(a)
Batch: EC-A2 Date:

Aim:
FF0h.

a) Write a assembly language program to exchange the content of FFh and

Software tool used: Keil vision v 4.02 Logical description:

Here, FFh and FF0h are memory address of external ROM. For accessing the external ROM instruction MOVX A,@DPTR is used. First load the address FF0h in dptr and by using above equation load the data of FF0h in accumulator then store it temporarily in another register. Now as above process data stored in FFh can be loaded in accumulator. To send this data to FF0h Dptr sets to FF0h again and by instruction MOV @DPTR,A the data can be stored back to the external memory address FF0h. For FFh, load the temporarily register data in accumulator and by using above instruction the data can be stored back to FFh. This way we can exchange the data of FFH and FF0h. Here MOVX instruction works only with accumulator, so it is necessary to load content in accumulator which u want to copy in external memory.

Memory address FF0 h

Accumulator

Memory address FF h

Register B

Process 1: Process 2: Process 3:

ALP code for 8051 (p4.lst):


A51 MACRO ASSEMBLER P4 04/17/2011 08:19:15 PAGE

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN p4.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE p4.a51 SET(SMALL) DEBUG EP LOC 0000 0000 0003 0004 0006 0009 000A 000D 000E 0010 0013 OBJ LINE SOURCE org 00h mov dptr,#0ff0h movx a,@dptr mov b,a mov dptr,#0ffh movx a,@dptr mov dptr,#0ff0h movx @dptr,a mov a,b mov dptr,#0ffh movx @dptr,a end 2

1 900FF0 2 E0 3 F5F0 4 9000FF 5 E0 6 900FF0 7 F0 8 E5F0 9 9000FF 10 F0 11 12 _A51 MACRO ASSEMBLER P4 04/17/2011 08:19:15 PAGE SYMBOL TABLE LISTING ------ ----- ------N A M E B. . . . . . . . . T Y P E D ADDR

V A L U E 00F0H A

ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)

Output:
i) Register used: A 00h 44h B 00h 44h

Register used Register value before executing Register value after executing

ii)

Program status word: CY 0 0 AC 0 0 RS1 0 0 RS1 0 0 AC 0 0 OV 0 0 UD 0 0 P 0 0

Psw Psw value before executing Psw value after executing iii)

Memory location used:

External memory used: Memory locations used value before executing 0FFh 33h 0FF0h 44h

Value after executing

44h

33h

Experiment No. - 4(b)


Batch: EC-A2 Date:

Aim: b) Write a assembly language program to store the higher nibble of R7 into
both nibbles of R6.

Software tool used: Keil vision v 4.02 Logical description:


For getting the higher nibble of R7, first load F0h to accumulator and do AND operation with R7. This gives answer in accumulator which has higher nibble of R7 and lower nibble is equal to zero. Now store the data of A in R6, as per our problem we get lower nibble. For higher nibble swap the data of accumulator and do OR operation with R6 and copy the answer of accumulator in R6. That gives the higher nibble of R7 into both nibbles of R6.

R7 (85h)

AND operation with F0h (80h)

Store A in R6 (80)

Swap A (08h)

(Here 85h is stored in R7)

OR operation between A and R6 (88h)

Store A in R6 (88h)

ALP code for 8051 (p4b.lst):


A51 MACRO ASSEMBLER P4B 04/16/2011 01:47:37 PAGE

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN p4b.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE p4b.a51 SET(SMALL) DEBUG EP LOC 0000 0000 0002 0004 0006 0007 0008 0009 000A OBJ 7F85 7E32 74F0 5F FE C4 4E FE LINE 1 2 3 4 5 6 7 8 9 10 SOURCE org 00h mov r7,#85h mov r6,#32h mov a,#0f0h anl a,r7 mov r6,a swap a orl a,r6 mov r6,a end

_A51 MACRO ASSEMBLER P4B 04/16/2011 01:47:37 PAGE SYMBOL TABLE LISTING ------ ----- ------N A M E T Y P E

V A L U E

ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)

Output:
i) Register used: R6 32h 88h R7 85h 85h A 00h 88h

Register used Register value before executing Register value after executing

ii) Psw

Program status word: CY 0 0 AC 0 0 RS1 0 0 RS1 0 0 AC 0 0 OV 0 0 UD 0 0 P 0 0

Psw value before executing Psw value after executing

Practical No: 05(A)


Batch: EC-A2 Date:

Aim: Develop assembly language code: Read R6, R7 & R4, R5 as two 16-bit registers perform subtraction between them store the result in 20th lower byte & 21st higher byte. Tools used: keil vision 4.02 Logical description:

For this instruction SUBB is used which subtract to content considering the carry flag. For 16 bit register first subtract the data of R7 and R5. The accumulator having the answer, store it to 20h address of internal RAM. Now subtract the data of R6 and R4. If the carry flag is set then instruction consider carry and do subtraction with using that carry. Store that answer in 21h. At the end we get full answer stored in 20h to 21h. Process 1: R6 R4 A SUBB A,R4 send Memory address 20h

Process 2: R7 R5 A SUBB A,R5 send Memory address 21h

ALP code for 8051 (5tha.lst):


A51 MACRO 04/02/2011 12:10:47 PAGE ASSEMBLER 1 5THA

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN 5tha.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE SET (SMALL) DEBUGS EP LOC OBJ 0000 0000 0002 0004 0006 0008 0009 000A 000C 000D 000E 7E10 7F40 7CFF 7D30 EE 9C F520 EF 9D F521 LINE 1 2 3 4 5 6 7 8 9 10 11 SOURCE org 0000h mov r6,#10h mov r7,#40h mov r4,#0ffh mov r5,#30h mov a,r6 subb a,r4 mov 20h,a mov a,r7 subb a,r5 mov 21h,a 12 end ASSEMBLER 2

5tha.a51

A51 MACRO 04/02/2011 12:10:47 PAGE SYMBOL TABLE LISTING ------ ----- ------N A M E T Y P E

5THA

V A L U E

ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERRORS(S)

Output:
i) Register used: A 00h 0Fh R4 00h FFh R5 00h 30h R6 00h 10h R7 00h 40h

Register used Register value before executing Register value after executing

ii)

Program status word: CY 0 0 AC 0 0 RS1 0 0 RS1 0 0 AC 0 1 OV 0 0 UD 0 0 P 0 0

Psw Psw value before executing Psw value after executing


iii)

Memory locations used:

Microcontroller memory used: Memory locations used Values before execution Values after execution 20h (lower byte) 00h 11h 21h (higher byte) 00h FFh

Experiment No. - 5(b)


Batch: EC-A2 Date:

Aim: Develop an assembly language code: divide the content of R0 by R1 and store
the result in R2 and store reminder in R3, and then restore original content in R0.

Software tool used: Keil vision v 4.02 Logical description:


For division DIV A,B is used. After the execution of instruction answer is stored in accumulator and reminder is stored in B. Here DIV instruction works with only A and B, so first move the content of R0 and R1 in to A & B respectively. Then using the above instruction divide both. After division A will be having answer and B will having the reminder. Store answer( in A) in R2, and reminder( in B) in R3. R0 has its original content.

R0

R1

MUL AB Send A in R2 Store B in R3

ALP code for 8051 (prgm.lst):


A51 MACRO 04/05/2011 15:58:37 PAGE ASSEMBLER 1 PRGM

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN prgm.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE SET (SMALL) DEBUGEP LOC 0000 0000 0002 0003 0005 0007 0008 000A OBJ 7852 E8 7905 89F0 84 ABF0 FA LINE SOURCE org mov mov mov mov div mov mov end 2 0000h r0,#52h a,r0 r1,#05h b,r1 ab r3,b r2,a ASSEMBLER

prgm.a51

1 2 3 4 5 6 7 8 9 A51 MACRO 04/05/2011 15:58:37 PAGE SYMBOL TABLE LISTING ------ ----- ------N A M E B. . . . . . . . .

PRGM

T Y P E V A L U E D ADDR 00F0H A

ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)

Output:
1) Register used: Register used Register value before executing Register value after executing A 00h 10h B 00h 02h R0 00h 52h R1 00h 05h R2 00h 10h R3 00h 02h A 00h 10h

2) Program status word: Psw Psw value before executing Psw value after executing CY 0 0 AC 0 0 RS1 0 0 RS1 0 0 AC 0 0 OV 0 0 UD 0 0 P 0 1

Experiment No. - 6
Batch: EC-A2 Date:

Aim: Write a assembly language program to transfer the block of data from 20h to
30h to external location 1020h to 1030h.

Software tool used: Keil vision v 4.02 Logical description:


We have to transfer the data of 20h to 30h to the external memory 1020h to 1030h. Here 20h t0 30h is memory of internal RAM and 1020h to 1030h is memory of external RAM. Here register R0 is used as variable that contains the address between 20h to 30h and another variable is DPTR which contains address of external memory. Program contains loop which first checks that if data address (R0) is between 20 to31, then it copy the data from respected address to accumulator and then copy the data of accumulator to the external memory. In the end it increases one byte of data (R0) address and DPTR. This process goes until the data address is not between the 20h to 30h and program stop to copy the data and end the program.

20 h 21h 30h

Inc DPTR

1020h 1021h 1030h

ALP code for 8051(exp6.lst):

A51 MACRO ASSEMBLER EXP6 04/04/2011 19:37:36 PAGE

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN exp6.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE exp6.a51 SET(SMALL) DEBUG EP LOC 0000 0000 0003 0005 0008 000A 000B 000C 000D 000E 0010 OBJ LINE SOURCE org 0000h mov dptr,#1020h mov r0,#20h again:cjne r0,#31h,l1 sjmp l2 l1:mov a,@r0 movx @dptr,a inc r0 inc dptr sjmp again l2: end 2

1 901020 2 7820 3 B83102 4 8006 5 E6 6 F0 7 08 8 A3 9 80F5 10 11 12 _A51 MACRO ASSEMBLER EXP6 04/04/2011 19:37:36 PAGE SYMBOL TABLE LISTING ------ ----- ------N A M E AGAIN. . . . . . . L1 . . . . . . . . L2 . . . . . . . . T Y P E C ADDR C ADDR C ADDR

V A L U E 0005H 000AH 0010H A A A

ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)

Output:

i) Register used: Register used Register value before executing Register value after executing ii) Program status word: Psw Psw value before executing Psw value after executing CY 0 0 AC 0 0 RS1 0 0 RS1 0 0 AC 0 0 OV 0 0 UD 0 0 P 0 0 R0 00h 31h A 00h dptr 0000h 1031h

iii) Memory location used: Microcontroller memory used:


20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E Memory locations used (Hexadecimal) 10 11 12 13 14 15 16 17 18 19 20 value before executing (Hexadecimal) 10 11 12 13 14 15 16 17 18 19 20 value before executing (Hexadecimal) 21 22 23 24 2F

25

21

22

23

24

25

External memory used:

Memoy locations used value before executing value before executing

1020 h 00 h 10 h

1020 h 00 h 11 h

1022 h 00 h 12 h

1023 h 00 h 13 h

1024 h 00 h 14 h

1025 h 00 h 15 h

1026 h 00 h 16 h

1027 h 00 h 17 h

CONTINUE

1028h CONTINUE 00h 18h

1029h 00h 19h

102Ah 00h 20h

102Bh 00h 21h

102Ch 00h 22h

102Dh 00h 23h

102Eh 00h 24h

102F h 00h 25h

Experiment No. - 7

Batch: EC-A2

Date:

Aim: Write a assembly language program to find out how many equals bytes between
two memory box 10h to 20h and 20h to 30h.

Software tool used: Keil vision v 4.02 Logical description:


The logic of program is very simple depend upon the nested loop. There are two blocks first is 10h to 20h and second is 20h to 30h. In program data of one register of first block (10h to 20h) is compared with data of all registers of second block (20h to 30h).after this second register (12h) is compared with data of all registers. If the bytes are same than counter will increment. This process will continue until all data are compared with each other. Most important thing for program is clear the carry flag when conditions of address is check than if address is small than carry flag will be set and that affect the instruction SUBB gives wrong answer, so it is necessary to clear carry after every comparison and subtraction.

ALP code for 8051(p7.lst):

A51 MACRO ASSEMBLER P7 04/16/2011 00:27:31 PAGE

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN p7.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE p7.a51 SET(SMALL) DEBUG EP LOC 0000 0000 0002 0004 0006 0007 0009 000C 000E 000F 0012 0013 0014 0016 0017 0018 001A 001B 001D 001E 001F 0020 0022 OBJ 7811 7921 7C00 C3 7921 B82102 8014 C3 B93104 C3 08 80F0 C3 E6 87F0 97 7001 0C C3 09 80EC LINE SOURCE org 00h mov r0,#11h mov r1,#21h mov r4,#00h head: clr c mov r1,#21h cjne r0,#21h,l1 sjmp l3 l1: clr c cjne r1,#31h,l4 clr c inc r0 sjmp head l4: clr c mov a,@r0 mov b,@r1 subb a,@r1 jnz l2 inc r4 l2: clr c inc r1 sjmp l1 l3: end 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 _A51 MACRO ASSEMBLER P7 04/16/2011 00:27:31 PAGE

SYMBOL TABLE LISTING

------ ----- ------N A M E B. . HEAD L1 . L2 . L3 . L4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T Y P E D C C C C C ADDR ADDR ADDR ADDR ADDR ADDR V A L U E 00F0H 0006H 000EH 001EH 0022H 0016H A A A A A A ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)

Output:

i)

Register used: R0 11h 21h R1 21 h 21 h R4 00 h 10 h A 00 h 10 h B 00h 00h

Register used Register value before executing Register value after executing ii) Program status word: CY 0 0 AC 0 0 RS1 0 0 RS1 0 0

Psw Psw value before executing Psw value after executing iii)

AC 0 0

OV 0 0

UD 0 0

P 0 1

Memory location used:

Microcontroller RAM memory used: Memory locations used* value before executing* value before executing* Memory locations used* value before executing* value before executing* 1 1 1 0 1 0 1 2 1 0 1 0 1 3 1 0 1 0 1 4 1 0 1 0 1 5 1 0 1 0 1 6 1 0 1 0 1 7 1 0 1 0 1 8 1 0 1 0 1 9 1 0 1 0 1A 1B 1C 1D 1E 1F 10 10 10 10 10 10 10 10 10 10 10 10 20 10 10

2 1 1 0 1 0

2 2 0 0 0 0

2 3 0 0 0 0

2 4 0 0 0 0

2 5 0 0 0 0

2 6 0 0 0 0

2 7 0 0 0 0

2 8 0 0 0 0

2 9 0 0 0 0

2A 2B 2C 2D 2E 2F 00 00 00 00 00 00 00 00 00 00 00 00

30 00 00

*all values are in HEXADECIMAL

Experiment No. - 8

Batch: EC-A2

Date:

Aim: Write a program in assembly language to find out bytes from blocks of 100h to
200h are greater than content of R2 and less than content of R3. Store the count in R4.

Software tool used: Keil vision v 4.02 Logical description:


This program is to check the data of 100h to 200h, whether it is greater than R2 and less than R3. Total number of memory is 100h. Microcontroller can count only up to FFh, for this we use nested loop for counting purpose. In program R1, R5 contains 00h and 00h. As nested loop first R1 increased with increment of dptr, as the r1 become 0FFh then the register R5 will be increased it value so we cannot use 0FFh in program as address counter. Here R1 for 0FEh times so to makes address counter counts 100h times R5 should count 02h times. As it becomes 02h the program will end. In short we take difference between to memory address and use it as address counter. Now, when address is between 100h to 200h. First load the data in accumulator. By using SUBB instruction it is decided that whether it is greater than R2 if it is than greater than R2 then carry flag is 0. If it is less than R2 then it jumps to end of the program and increment address counter and dptr. For greater than R2 it will further check by SUBB whether the data is smaller than R3. If carry flag is 1 than it is smaller than R3 and the datacounter (R4) counts, than it increment dptr and address counter. If the carry is 0 then it directly jumps to L3 (label).

ALP code for 8051(p82.lst):

A51 MACRO ASSEMBLER P82 04/16/2011 12:23:39 PAGE

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN p82.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE p82.a51 SET(SMALL) DEBUG EP LOC 0000 0000 0002 0004 0006 0008 000B 000E 0011 0013 0014 0015 0016 0018 0019 001A 001B 001D 001E 001F 0020 0023 0024 0026 0027 0029 OBJ 7A32 7B50 7900 7D00 900100 B9FF05 BD0202 8016 C3 E0 9A 4006 C3 E0 9B 5001 0C C3 A3 B9FF03 0D 80E5 09 80E2 LINE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SOURCE org 00h mov r2,#32h mov r3,#50h mov r1,#00h mov r5,#00h mov dptr,#0100h head:cjne r1,#0ffh,l1 cjne r5,#02h,l1 sjmp l4 l1: clr c movx a,@dptr subb a,r2 jc l2 clr c movx a,@dptr subb a,r3 jnc l2 inc r4 l2: clr c inc dptr cjne r1,#0ffh,l3 inc r5 sjmp head l3: inc r1 sjmp head l4: end 2

_A51 MACRO ASSEMBLER P82 04/16/2011 12:23:39 PAGE

SYMBOL TABLE LISTING

------ ----- ------N A M E HEAD L1 . L2 . L3 . L4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T Y P E C C C C C ADDR ADDR ADDR ADDR ADDR V A L U E 000BH 0013H 001EH 0026H 0029H A A A A A ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)

Output:

i)

Register used: R1 00h 0ffh R2 32h 32h R3 50h 50h R4 00h 07h R5 00h 02h A 00h E3h Dptr 0100h 0201h

Register used Register value before executing Register value after executing ii)

Program status word: CY 0 0 AC 0 0 RS1 0 0 RS1 0 0 AC 0 0 OV 0 0 UD 0 0 P 0 1

Psw Psw value before executing Psw value after executing iii)

Memory location used:

External memory used: Memory locations used value before executing value before executing 100h 101h 102h 103h 104h 14Ch 17Fh 181h 200h

33h 10h

55h 11h

66h 12h

33h 13h

32h 14h

35h 15h

33h 16h

40h 17h

33h 18h

Other memory except given above between 100h to 200h are 00h,which is less than R2.

Experiment No. - 9

Batch: EC-A2

Date:

Aim: Write the assembly language program for given problem:


Crystal frequency is given as 12 MHz. make a subroutine that will generate delay Exact 1 ms. Use this delay to generate square waves of 50 Hz on pin P2.0.

Software tool used: Keil vision v 4.02 Logical description:


For given program the square waves frequency is 50 Hz. By calculating time for 1 full cycle time required is 20 ms. For one half cycle time is 10 ms. For program 10 ms time delay should be generated. After each 10 ms second the output will be complement thus gives square wave on pin p2.0. 1 ms time delay will be generated by using register R2. Register R2 contains FAh (250). Program contains subroutine of 1 ms. this subroutine is repeated for 10 times generates 10 ms. For this register R1 contains 0Ah. After delay the output will be complemented and another time delay of 10 ms is generated. This process goes on continuously until the programs ends manually. For 1ms we use two NOP instruction having delay of 2 s and DJNZ so total delay is 4 s. This should be done for 250 time gives 1ms time delay. In program R1 contains 10. After each call delay program decrement the R1 and check whether it zero, it is not then re-call the delay so as per program delay subroutine called 10 times generate time delay of 10 ms. After this the pin P2.0 is complemented this process repeated f= 50MHz, T=1/f = 20 ms 20 ms So, delay should be generated of 10 ms. After 10 ms output will Complemented.

10 ms

ALP code for 8051(p9.lst):

A51 MACRO ASSEMBLER P9 04/15/2011 22:38:11 PAGE

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN p9.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE p9.a51 SET(SMALL) DEBUG EP LOC 0000 0000 0002 0004 0006 0008 000A 000C 000D 000E 0010 OBJ B2A0 790A 110A D9FC 80F6 7AFA 00 00 DAFC 22 LINE SOURCE org 00h again: cpl p2.0 mov r1,#0ah l1: acall delay djnz r1,l1 sjmp again delay: mov r2,#0fah l2: nop nop djnz r2,l2 ret end 2

1 2 3 4 5 6 7 8 9 10 11 12 _A51 MACRO ASSEMBLER P9 04/15/2011 22:38:11 PAGE SYMBOL TABLE LISTING ------ ----- ------N A M E AGAIN. DELAY. L1 . . L2 . . P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T Y P E C C C C D ADDR ADDR ADDR ADDR ADDR

V A L U E 0000H 000AH 0004H 000CH 00A0H A A A A A

ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)

Output:

i)

Register used: R1 0Ah 0Ah R2 FAh FAh

Register used Register value before executing Register value after executing

ii)

Program status word: CY 0 0 AC 0 0 RS1 0 0 RS1 0 0 AC 0 0 OV 0 0 UD 0 0 P 0 0

Psw Psw value before executing Psw value after executing iii) Ports:

At t=0 s, Port P2: FFh

At, t = 10 ms, Port P2: FEh

Experiment No. - 10
Batch: EC-A2 Date:

Aim: Develop a program in assembly to count number of interrupts arriving on


external interrupt in INT1, stop when counter overflows & disable the interrupt .give the indication of P0.0 .

Software tool used: Keil vision v 4.02 Logical description:

To enable interrupt IE is set to 84h. Here we want to cont the interrupt so we need to use edge triggered interrupt for this Tcon.2 should be set. It means when input at pin P3.4 become 1 to 0 at that moment interrupt generated and counter count. The counter initially set to zero. In interrupt subroutine program condition checks whether the counter is overflows, so condition is to check that counter is 00h or not. If it is than program disable all the interrupt and store the 01h in R2 return to the main program. In main program if checks the data of R2, if it is 01h then program ends and if it is 00h than program counter jumps to HERE (label) and re check the data of R2.

ALP code for 8051(pp4.lst):

A51 MACRO ASSEMBLER PP4 04/05/2011 13:40:07 PAGE

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN pp4.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE pp4.a51 SET(SMALL) DEBUG EP LOC OBJ LINE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SOURCE org 00h sjmp main org 0030h main:mov ie,#84h mov p0,#00h setb tcon.2 mov r1,#00h here: cjne r2,#01h,l4 sjmp l3 l4: sjmp here org 0003h inc r1 cjne r1,#00h,l2 mov ie,#00h mov r2,#01h setb p0.0 sjmp l2 l2:reti l3: end

0000 0000 802E 0030 0030 0033 0036 0038 003A 003D 003F 0003 0003 0004 0007 000A 000C 000E 0010 0011 75A881 758000 D288 7900 BA0102 80D2 80F9 09 B90009 75A800 7A01 D280 8000 32

_A51 MACRO ASSEMBLER PP4 04/05/2011 13:40:07 PAGE

SYMBOL TABLE LISTING ------ ----- -------

N A M E HERE IE . L2 . L3 . L4 . MAIN P0 . TCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

T Y P E C D C C C C D D ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR

V A L U E 003AH 00A8H 0010H 0011H 003FH 0030H 0080H 0088H A A A A A A A A

ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)

Output:

i)

Register used: R1 00h 00h R2 Tcon 00h 04h 01h 04h IE 84h 84h

Register used Register value before executing Register value after executing

ii) Psw

Program status word: CY 0 0 AC 0 0 RS1 0 0 RS1 0 0 AC 0 0 OV 0 1 UD 0 0 P 0 0

Psw value before executing Psw value after executing

iii)

Ports: Port P0 ( after overflag): 01h

Port P0 ( before overflag): 00h

Experiment No. - 11
Batch: EC-A2 Date:

Aim: Write a assembly language program to continuously scan port p0 if data is other
than FFh write a subroutine that will multiply it with 10d and send it to port P1,P2.

Software tool used: Keil vision v 4.02 Logical description:


As per our program we have to check the port P0 continuously by looping when the data do not equal to the FFh then call function call the subroutine that will multiply the term of port P0 with 10d. In this MUL AB instruction is used the last 8 bit data is stored in register A and another 8 bit data are in register B. Flowchart :

Start

Check if P0 = FFh

Yes

No Multipliy with 10 d

Send A to P1, Send B to p2

Stop

ALP code for 8051(ffff.lst):

A51 MACRO ASSEMBLER FFFF 04/15/2011 21:04:56 PAGE

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN ffff.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE ffff.a51 SET(SMALL) DEBUG EP LOC 0000 0000 0002 0005 0007 0009 000B 000E 000F 0011 0014 OBJ E580 B4FF02 8002 110B 80F5 75F00A A4 F590 85F0A0 22 LINE 1 2 3 4 5 6 7 8 9 10 11 12 SOURCE org 00h head: mov a,p0 cjne a,#0ffh,l1 sjmp l2 l1: call subroutine l2: sjmp head subroutine: mov b,#0ah mul ab mov p1,a mov p2,b ret end 2

_A51 MACRO ASSEMBLER FFFF 04/15/2011 21:04:56 PAGE SYMBOL TABLE LISTING ------ ----- ------N A M E B. . . . . HEAD . . . L1 . . . . L2 . . . . P0 . . . . P1 . . . . P2 . . . . SUBROUTINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T Y P E D C C C D D D C ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR

V A L U E 00F0H 0000H 0007H 0009H 0080H 0090H 00A0H 000BH A A A A A A A A

ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. WARNING(S), 0 ERROR(S)

Output:

i)

Register used: A 00h 87h B 00h 05h

Register used Register value before executing Register value after executing

ii)

Program status word: CY 0 0 AC 0 0 RS1 0 0 RS1 0 0 AC 0 0 OV 0 1 UD 0 0 P 0 1

Psw Psw value before executing Psw value after executing iii) Ports:

Port P0 (input): 32h

Port P2(output): 01h

Port P1(output): F4h

Experiment No. - 12
Batch: EC-A2 Date:

Aim: write a assembly language program to generate a delay of 500 ms using


software instruction.

Software tool used: Keil vision v 4.02 Logical description:


By using software instruction we can generate time delay by using register changing the value and waste the time of microcontroller to get the desired delay. We can use NOP to waste time of microcontroller. Here we use main program portion having time delay of 1 ms which is repeated by 500 time to generate time delay of 500 ms. Register R2 contains FAh (250) to generate the time delay of 1 ms. The other register R1 contains FAh (250). So the 1 ms time delay generated for 250 times generates 250 ms and the last register R0 contain 02h which generate delay of 250 ms for 2 times gives total time delay of 500 ms.

ALP code for 8051(p-12.lst):

A51 MACRO ASSEMBLER P_12 04/15/2011 21:15:42 PAGE

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN p-12.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE p-12.a51 SET(SMALL) DEBUG EP LOC 0000 0000 0002 0004 0006 0007 0008 000A 000C OBJ LINE SOURCE org 00h mov r0,#02h l3:mov r1,#0fah l2:mov r2,#0fah l1:nop nop djnz r2,l1 djnz r1,l2 djnz r0,l3 end 2

1 7802 2 79FA 3 7AFA 4 00 5 00 6 DAFC 7 D9F8 8 D8F4 9 10 _A51 MACRO ASSEMBLER P_12 04/15/2011 21:15:42 PAGE SYMBOL TABLE LISTING ------ ----- ------N A M E L1 . . . . . . . . L2 . . . . . . . . L3 . . . . . . . . T Y P E C ADDR C ADDR C ADDR

V A L U E 0006H 0004H 0002H A A A

ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)

Output:

i)

Register used: R0 02h 00h R1 FAh 00h R2 FAh 00h

Register used Register value before executing Register value after executing

ii) Psw

Program status word: CY 0 0 AC 0 0 RS1 0 0 RS1 0 0 AC 0 0 OV 0 1 UD 0 0 P 0 1

Psw value before executing Psw value after executing iii)

States: 501507 Delay time: 0.501507 s

Experiment No. - 13
Batch: EC A2 Date:

Aim: Generate the delay of 500ms using timer 0 in mode 1 (frequency 11.059 MHz). Software tool used: Keil vision v 4.02 Logical description:
As per our problem we have to generate the time delay of 500 ms second using timer0 in mode 1.we have clock frequency of 11.059 Hz so as per calculation of time for one machine cycle is 1.085 s, so we can get maximum time delay by timer is 65536*1.085 s = 71.10 ms, So we have to repeat the timer 500/71.10 = 7.03 is approximately 7 times. That gives us time delay of 499.9 ms. Calculation:

ALP code for 8051(pp5.lst):


A51 MACRO ASSEMBLER PP5 04/05/2011 12:56:55 PAGE 1

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN pp5.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE pp5.a51 SET(SMALL) DEBUG EP LOC 0000 0000 0002 0005 0008 000B 000D 0010 0012 0014 OBJ 7807 758901 758A00 758C00 D28C 308DFD C28D C28C D8EF LINE SOURCE org mov mov l1: 00h r0,#07h tmod,#01h mov tl0,#00h mov th0,#00h setb tr0 again: jnb tf0,again clr tf0 clr tr0 djnz r0,l1 end 2

1 2 3 4 5 6 7 8 9 10 11 _A51 MACRO ASSEMBLER PP5 04/05/2011 12:56:55 PAGE SYMBOL TABLE LISTING ------ ----- ------N A M E AGAIN. L1 . . TF0. . TH0. . TL0. . TMOD . TR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T Y P E C C B D D D B ADDR ADDR ADDR ADDR ADDR ADDR ADDR

V A L U E 000DH 0005H 0088H.5 008CH 008AH 0089H 0088H.4 A A A A A A A

ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)

Output:
i) Register used:

Register used Register value before executing Register value after executing

R0 07h 00h

Tmod 01h 01h

Th0 00h 00h

Tl0 00h 00h

ii) Psw

Program status word: CY 0 0 AC 0 0 RS1 0 0 RS1 0 0 AC 0 0 OV 0 0 UD 0 0 P 0 0

Psw value before executing Psw value after executing

iii)

States: 458832 Delay time: 0.49788 s

Experiment No. - 14
Batch: EC-A2 Date:

Aim: Write a program to find seven segments code of given 8 bit data using lookup
table method and create interfacing diagram of 8051 family microcontroller and common cathode seven segment devise. Simulate the diagram any EDA tool.

Software tool used: Keil vision v 4.02 , Multisim v11 Logical description:
Here we have to find the seven segment code for given 8 bit data which is given on port P1. The seven segment code is got from port P0. Which can be easily detect by seven segment display on port p2. The look up table for seven segments for common cathode configuration is given below with individual code for 0-9 decimal number. Decimal number 0 1 2 3 4 5 6 7 8 9 Port P1 input 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h Seven segment code 3F h 06 h 5B h 4F h 66 h 6D h 7D h 07 h 7F h 6F h

Table 14.1: Lookup table for seven segment common cathode configuration

This seven segment code will be stored in internal ROM by using directives db. This code is in memory so it can be accessed by instruction MOVC A,@A+DPTR. Dptr contains address of initial seven segment code of 0. (Here there is no external ROM is used so we cannot use MOVX instruction). This instruction copy content of address A+Dptr in accumulator. According to data of accumulator it selects value from lookup table. For example if A=05h then above instruction gives code 6Dfrom lookup table. From the accumulator the data (code) is send to the port P2.if the input is given out of 00-09 then no seven segment code will get from port P2.

Figure 14.2: Block diagram of seven segment display interfacing with 8051 using multisim.

Here as shown in diagram input is given to Port 1 and at Port 2 seven segment display (U2) is connected. In multisim, there are two methods to do simulation by including PLD in schematic diagram: 1. Create MCU module and make MCU work space project in which u directly load HEX file which is created by software like keil vision. 2. Create MCU module and make MCU work space project in which u can select standard project type and programming language and create a project and write and run program and simulate it. For this experiment, second method is adopted for the simulation. The brief procedure is given below:

1. Click Show machine code for simulation location on disk. Windows Explorer opens in the folder where the output file will be located. In the screen capture below, project2 of 8051workspace is selected in the MCU Code Manager. Project2 has the Hi-tech C51-Lite compiler selected as the tool. This is a C compiler which compiles and links code in order to produce an output machine code file (*.hex), and is more advanced than the Metalink assembler. It has three tabs (General, C/Assembly, and Library) to configure its build settings.

The assembler or compiler type determines the type of output target files that you can generate. In the screen capture above, the Hi-Tech C51 Lite compiler is chosen. Consequently, there are two types of target files that you can create: a machine code file and a library file. If you choose a library file, the compiler generates object files from the source files and places them in the specified library file instead of creating a machine code file. The library file is configured in the Library tab. There is a C/Assembly tab (see below) in addition to the Library tab available to allow you to configure the Hi-Tech tools further. One of the advanced features of the Hi-Tech tools is that intermediate and output files generated by the Hi-Tech C51 Lite can be redirected - therefore the Intermediate files and Output files paths are enabled in the General tab.

The above shows the MCU Code Manager for MCU U1 in the MCU Code Manager Overview section. The C/Assembly tab of the Hi-Tech C51 Lite compiler for project2 is displayed. The Project options edit box contains the compiler line options for the C51 Lite compiler. The default settings are normally sufficient to build an 8051 Hi-Tech C program but you can customize the options based on the Hi-Tech C51 Lite documentation. Refer to the Documentation for Supported Tools section for more information.

The Libraries edit box is where you can specify pre-existing libraries to be linked into the final build. In the above screen capture, one library file will be linked into the final build. Use the Add library file button to display a file browse window to find the library that should be linked into the build and automatically add the library file path to the Libraries edit box. The Library tab, as shown below, is enabled only if the output target selected in the General tab is a library. The Project options edit box in the Library tab displays the command line options used when the Hi-Tech tools generate the library. The figure below shows that the Library options are disabled since the output selected for project2 is a hex file. The Hi-Tech compiler documentation includes details on it command line options. Refer to the Documentation for Supported Tools section for more information. The above figure shows the MUC Code Manager for MUC U1 in the MUC Code Manager Overview section. The Library tab of Hi-Tech C51 Lite compiler for project2 is displayed. The tabs for the other assembler/compiler files are all similar except that the command line options in the C/Assembly and Library tabs are different for each tool. Refer to the assembler/compiler documentation for each tool for more information on the options that can be used with them. Refer to the Documentation for Supported Tools section for more information.

The tab that was not shown in the above example is the Link tab. The Hi-Tech compilers have the ability to pass on the command line options to their linker tool from the compiler. This means that the command line options for both the compiler and the linker can be specified all at once in the command line options for the compiler, which is when no Link tab is required. The Microchip relocatable assembler requires the Link tab to configure the command line options for MPLINK, its linker. The C/Assembly tab for the Microchip tools displays the options for the compiler, MPASM. The figure below shows an example of the C/Assembly tab for the Microchip assembler.

Use the Link tab for the Microchip assembler to add any libraries that need to be linked into the final build and the linker options that have to be passed to MPLINK. The next figure shows an example of the Link tab. Note: The Microchip assembler has both absolute and reloadable assembler. To use MPASM in reloadable assembler mode, you must add the /o option to the Project options edit box in the C/Assembly tab shown above, to generate the object files (*.o) used in the linking stage. Otherwise the object files do not generate and only the machine code file (*.hex) will be generated as the output file. You must also write your code in a reloadable fashion using the CODE directive before the code can be assembled in reloadable mode.

The Link tab for the Microchip MPLINK tool displays command line options in the Project options edit box and provides a way of specifying the libraries that should be linked into the final build.

ALP code for 8051(p14.lst):


A51 MACRO ASSEMBLER P14 04/19/2011 08:26:06 PAGE 1

MACRO ASSEMBLER A51 V8.02 OBJECT MODULE PLACED IN p14.OBJ ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\A51.EXE p14.a51 SET(SMALL) DEBUG EP LOC OBJ LINE SOURCE

0100 1 org 0100h 0100 3F065B4F 2 db 3fh,06h,5bh,4fh,66h,6dh,7dh,07h,7fh,6fh 0104 666D7D07 0108 7F6F 0000 3 org 00h 0000 900100 4 mov dptr,#0100h 0003 E590 5 mov a,p1 0005 540F 6 anl a,#0fh 0007 93 7 movc a,@a+dptr 0008 F5A0 8 mov p2,a 9 end _A51 MACRO ASSEMBLER P14 04/19/2011 08:26:06 PAGE 2 SYMBOL TABLE LISTING ------ ----- ------N A M E P1 . . . . . . . . P2 . . . . . . . . T Y P E D ADDR D ADDR V A L U E 0090H 00A0H A A ATTRIBUTES

REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE. 0 WARNING(S), 0 ERROR(S)

Output:
i) Register used: A 05h 6Dh Dptr 0100h 0100h

Register used Register value before executing Register value after executing

ii)

Program status word: CY 0 0 AC 0 0 RS1 0 0 RS1 0 0 AC 0 0 OV 0 0 UD 0 0 P 0 1

Psw Psw value before executing Psw value after executing iii)

Memory location used:

Internal ROM memory used: Memory locations used value before executing value before executing iv) 100h 3Fh 3Fh 101h 06h 06h 102h 5Bh 5Bh 103h 4Fh 4Fh 104h 66h 66h 105h 6Dh 6Dh 106h 7Dh 7Dh 107h 07h 07h 108h 7Fh 7Fh 109h 6Fh 6Fh

Ports: Port P2 (output): 6Dh

Port P1 (input): F5h

Conclusion: