Maximizing High Speed Data Converter Performance through Clocking, Power, and SNRBoost Maximizing High Speed Data

Converter Performance through Clocking, Power, and SNRBoost

Vera Mao Texas Instruments

Agenda
• Sampling Theory
– Nyquist Rate – Aliasing – Under-sampling

• Real World Clocking Solutions
– Clock Jitter impact to Data Converter Performance – Jitter Impact as Related to Input Frequency – TI High Performance Clocking Solutions – Clock Improvement Techniques

• Analog Signal Chain Interface - ADC
– Passive Transformer Interface – Buffer vs. Non-buffered Device – Active Op-Amp Interface

• Power Supply Considerations
– Utilizing DC-DC Converters for Efficient Supplies – Power Supply Noise Reduction Techniques

• Analog Signal Chain Interface - DAC
– Proper Load for Current Sink DACs – Interface Network to Quadrature Modulator – Low Pass Filter Design Techniques

• Special Section: China Export Restrictions and SNRBoost
– Current Export Restrictions – SNRBoost3G noise shaper – ADS58C48 – Out of band noise gain in SNRBoost

• DAC Special Features
– – – – Interpolation Filters Digital Signal Adjustments (QMC) NCO option DAC3283 Example Diagram

Sampling Theory
• The Nyquist Rate is the minimum sampling rate required to avoid aliasing
– Nyquist rate is simply twice the highest frequency

“1st Nyquist”

“2nd Nyquist”

“3rd Nyquist”

“4th Nyquist”

“etc……..”

Fs/2 = 45
‘Nyquist’

67.5

Fs=90M

112.5

135

180

SAMPLE/CLOCK RATE

What is Aliasing?
• Aliasing - two different sinusoids give the same digital samples
– – – – – If Fs is the Sampling Frequency (clock rate) a high frequency Fred = 10/9 * Fs and a low frequency at Fblue = 1/9 * Fs = Fred – Fs Both look like 1/9 * Fs to the ADC Thus one might say,
• “the frequency at Fred is aliased down, or under-sampled, to be at frequency Fblue at the ADC digital outputs in the spectral domain” • Or better yet, “the ADC can’t tell the difference”

example: Wikipedia.org

Under-sampling (Aliasing)
• We just down-converted a signal from a high frequency to a lower frequency – that sounds useful
– This is called Under-sampling

• This usually requires an analog frequency mixer • What is not always clear in the definition of the Nyquist Rate is that it refers to the bandwidth of the signal, not the frequency
– In the example given, the bandwidth of each signal is practically zero – these are discrete tones at 1/9 and 10/9 of Fs – But signals with no bandwidth contain little information and are therefore not usually very useful for communication systems – So let’s look at aliasing with some bandwidth involved….

or Down-Converting.5 Fs=90M 122.Bad Aliasing (graphically speaking) As drawn here. centered at 100MHz Input to ADC Sampling at 90MSPS Fs/2 = 45 ‘Nyquist’ 12.5 Output of ADC Sampling at 90MSPS Fs/2 = 45 32. . this is 1 modulated carrier with a BW = 45MHz. 45MHz of Bandwidth Notice that the ‘red’ spectrum aliased on top of part of the ‘gray’ spectrum.5 ‘Nyquist’ Fs=90M After Aliasing. while the gray did not This would NOT be okay – a digital down-converter (DDC) would not be able to recover the information. Notice also that the red horizontally inverted.5 77.

Notice that the color is not horizontally inverted – this is because we used an ‘odd’ nyquist zone (the 3rd). so all the energy is in one ‘Nyquist Zone’ Input to ADC Sampling at 90MSPS Fs/2 = 45 ‘Nyquist’ 67. If we had used an ‘even’ zone. and money . centered at 112.5 Fs=90M 112.5 After Aliasing. 45MHz of Bandwidth Notice that the spectrum is still continuous.Good Aliasing As drawn here. this is 1 modulated carrier with a BW = 45MHz. or Down-Converting.5 Fs/2 = 45 ‘Nyquist’ 67. This is not a bad thing. power. Many radio designs take full advantage of ‘good aliasing’ to eliminate an entire analog frequency down-conversion stage – saving board space.5 135 Output of ADC Sampling at 90MSPS 22.5 Fs=90M 112.5MHz. the color would reverse – it is spectrally inverted. but might need to be known in order to process the band.

5 Fs=90M 112. centered at 112. this is 1 modulated carrier with a BW = 22. or Down-Converting.5 Fs/2 = 45 ‘Nyquist’ 67.5 Fs/2 = 45 ‘Nyquist’ 67.5 135 Output of ADC Sampling at 90MSPS After Aliasing. you need to bandpass filter the signal before going into the ADC so that frequency content outside of your signal of interest is not aliased into the ADC and adding noise – and BPF’s aren’t a brickwall – they require some room for proper roll-off As drawn here.Practical Aliasing Example In the real world. and money . 22.5MHz (Fs / 4).5 Fs=90M 112.5 45MHz of Bandwidth This is perfect – a digital down-converter (DDC) can recover the information with room for further practical digital filtering and digital frequency mixing – usually to baseband. power. Many radio designs take full advantage of ‘good aliasing’ to eliminate an entire analog frequency down-conversion stage – saving board space.5MHz (it could be multiple sub-carriers in the same BW) PF gB alo An Input to ADC Sampling at 90MSPS 22.

could sample input frequencies up to 2GHz (carrier. with a 2GHz Input Bandwidth. which are sometimes called Nyquist Converters. not BW) at 500MSPS – but the performance is frequency dependent • There are ADCs that cannot under-sample.Can all ADCs Under-sample? • Pipeline ADCs are usually designed to have Input Bandwidth that exceeds the intended operating range or ‘Performance Bandwidth’ • The ADS5463. and are usually high precision and have much slower sample rates .

Agenda • Sampling Theory – Nyquist Rate – Aliasing – Under-sampling • Real World Clocking Solutions – Clock Jitter impact to Data Converter Performance – Jitter Impact as Related to Input Frequency – TI High Performance Clocking Solutions – Clock Improvement Techniques • Analog Signal Chain Interface .DAC – Proper Load for Current Sink DACs – Interface Network to Quadrature Modulator – Low Pass Filter Design Techniques • Special Section: China Export Restrictions and SNRBoost – Current Export Restrictions – SNRBoost3G noise shaper – ADS58C48 – Out of band noise gain in SNRBoost • DAC Special Features – – – – Interpolation Filters Digital Signal Adjustments (QMC) NCO option DAC3283 Example Diagram .ADC – Passive Transformer Interface – Buffer vs. Non-buffered Device – Active Op-Amp Interface • Power Supply Considerations – Utilizing DC-DC Converters for Efficient Supplies – Power Supply Noise Reduction Techniques • Analog Signal Chain Interface .

particularly at high-IF – They are passive devices.Transformers • Benefits – Isolated Input\Output – does not pass DC! – Common Mode can be applied to the center tap to bias ADC inputs – Can provide voltage step-up or step down – Can provide Single-ended to differential conversion – Provides best AC performance. no noise added • Limitations – – – – Phase Balance Amplitude balance Flatness of bandwidth Frequency Bandwidth .

Transformers Example • Dual transformer – Better balance of single ended to differential • Transformer is automatically AC coupled – Can use VCM to bias at center tap. or at termination • Balun is not AC coupled. need AC coupling external to balun .

Non-buffered • TI BiCMOS ADCs are generally buffered – Input buffer presents high input impedance – Prevents noise from sampling caps from getting out – Often have internal biasing to VCM • TI CMOS ADCs are often non-buffered (but not always) – Input is *not* constant impedance (i. not constant effective input capacitance vs.e.Input Circuit – Buffered vs. frequency) – Sampling caps emit noise back onto the input signal at every edge of the sample clock – Sampling glitch noise will have both single ended and common mode components • External filtering is often recommended to swallow up the sampling glitches – External R-C-R filter across inputs • Put pole of the filter higher than highest desired input frequency – Low impedance termination to VCM to hold more tightly to VCM • Ex: Two 25 Ohm terminations to VCM to terminate single 50 Ohm input – Problem: Higher ratio transformers or amplifiers desire higher termination or load imp. tuned RLC circuit across inputs • Sampling glitches may wreak havoc with amplifier stability – Same amplifier and filter that worked well with ADS5483 was unstable with ADS62P49 . – Effect of inadequate filtering of sampling glitches => loss of SFDR – Trick: for specific input frequencies and sample rates.

such that unwanted noise is also band-limited – Excellent performance can be achieved up to at least 100MHz or so of analog input • Amp + ADC *will* have worse AC performance than ADC itself – Must decide on target specs and design amp/filter to meet it . the input bandwidth should be limited.Amplifiers • Reasons to use an op-amp Provide the gain needed for driving the ADC at its full dynamic range Used in DC or time domain applications Used in baseband applications!! The CM input of the op-amp can be used to level shift the signal to the right level for the ADC – Used for SE to differential conversion – – – – • Considerations when using an op-amp – For best overall performance.

but amp + filter can degrade it • SFDR – SFDR of amp + filter combine with ADC linearly in voltage .Amplifiers • Filter – Follow amp with bandpass filter if possible • Input bandwidth of the ADC might be 2GHz or more – Might represent many Nyquist zones • Noise floor will fold back many times • SNR – SNR of amp + filter combine with ADC by rms sum of powers • Can never get better SNR than ADC data sheet numbers.

Non-buffered Device – Active Op-Amp Interface • Power Supply Considerations – Utilizing DC-DC Converters for Efficient Supplies – Power Supply Noise Reduction Techniques • Analog Signal Chain Interface .DAC – Proper Load for Current Sink DACs – Interface Network to Quadrature Modulator – Low Pass Filter Design Techniques • Special Section: China Export Restrictions and SNRBoost – Current Export Restrictions – SNRBoost3G noise shaper – ADS58C48 – Out of band noise gain in SNRBoost • DAC Special Features – – – – Interpolation Filters Digital Signal Adjustments (QMC) NCO option DAC3283 Example Diagram .ADC – Passive Transformer Interface – Buffer vs.Agenda • Sampling Theory – Nyquist Rate – Aliasing – Under-sampling • Real World Clocking Solutions – Clock Jitter impact to Data Converter Performance – Jitter Impact as Related to Input Frequency – TI High Performance Clocking Solutions – Clock Improvement Techniques • Analog Signal Chain Interface .

Proper Load for Current Sink DACs • Max Current = 20 mA • Max Voltage Swing = 1Vpp each leg • Rload = 50 ohms .

3V Vcm Modulator like TRF370333 – Two resistor network (per leg) – No insertion loss • Case 2: Utilizing a Modulator with Vcm < 3.3V like TRF370317 – 3 resistor network (per leg) – Insertion loss dependant on delta common mode voltage Case 1 Case 2 .Interface Network to Quadrature Modulator • Case 1: Utilizing 3.

2 s Marker 2 [T1 ] -40. R2. R2.4 MHz .13 dBm 83.889230769 MHz Marker 1 [T1 ] -60. and R4 * RBW 10 kHz Ref 10 10 dBm * Att 20 dB VBW 30 kHz SWT 6. R3.44 MHz/ Stop 614.10 307.639589572 Marker 3 [T1 ] -80. R3 • Filter Load impedance is set by R4 • DAC Load impedance is set by R1.57 120.Low Pass Filter Design Technique • Typically utilize LPF to eliminate high frequency noise and clock images • Filter source impedance is set by R1.200000000 0 1 AP CLRWR dBm MHz dBm MHz A -10 -20 -30 2 -40 -50 1 -60 -70 3 -80 -90 Start 0 Hz 61.

639589572 Marker 3 [T1 ] -80.DAC Filter Design Example * RBW 10 kHz • Zin. Zout = 50 ohms SE • 5th order Butterworth Filter • Desired Corner Frequency = 70 MHz • Designed Corner Frequency > 70 MHz – account for filter roll-off due to Q limitation of the inductors 1 AP CLRWR Ref 10 10 dBm * Att 20 dB VBW 30 kHz SWT 6.2 s Marker 2 [T1 ] -40.13 dBm 83.200000000 0 dBm MHz dBm MHz A -10 -20 -30 2 -40 -50 1 -60 -70 3 -80 -90 Start 0 Hz 61.4 MHz • Modify to differential topology .44 MHz/ Stop 614.57 120.10 307.889230769 MHz Marker 1 [T1 ] -60.

DAC Filter Example Schematic .

Non-buffered Device – Active Op-Amp Interface • Power Supply Considerations – Utilizing DC-DC Converters for Efficient Supplies – Power Supply Noise Reduction Techniques • Analog Signal Chain Interface .DAC – Proper Load for Current Sink DACs – Interface Network to Quadrature Modulator – Low Pass Filter Design Techniques • Special Section: China Export Restrictions and SNRBoost – Current Export Restrictions – SNRBoost3G noise shaper – ADS58C48 – Out of band noise gain in SNRBoost • DAC Special Features – – – – Interpolation Filters Digital Signal Adjustments (QMC) NCO option DAC3283 Example Diagram .ADC – Passive Transformer Interface – Buffer vs.Agenda • Sampling Theory – Nyquist Rate – Aliasing – Under-sampling • Real World Clocking Solutions – Clock Jitter impact to Data Converter Performance – Jitter Impact as Related to Input Frequency – TI High Performance Clocking Solutions – Clock Improvement Techniques • Analog Signal Chain Interface .

– Also get benefits of higher oversample rates which can improve SNR.e. (processing gain) • The Cost – High speed logic to generate the interpolation filters . lower data clock rate) – get more distance between the signal of interest and the images.Interpolation • Additional samples are created on-chip provided sampling at >2x on the input data • Benefits – Run the interface slower (i. resulting in easier filtering.

must window in practice .Interpolation Filters • We can use a digital filter to “create” accurate interpolated samples between the actual input sample • Convolving with the SINC function can create nearly perfect values • Ideal SINC function is infinite.

Interpolation Filter Implementation data_in clk_1x clk_2x b0 b2 b4 limit round 1 -1 limit 1 0 highpass 0 data_out • Utilize efficient shift and add circuitry. • The filters are designed with the minimum number of add and subtract operations to minimize hardware .

Special Features • QMC Adjustments – DC Offset Adjustment • Used to minimize LO Feedthrough – QMC Gain • Adjust digital gain of the signal • Adjust for I/Q amplitude imbalance – QMC Phase • Adjust for I/Q phase imbalance – QMC Delay • Adjust for I/Q delay imbalance • Coarse Mixer – Adjust output to fs/2 or fs/4 to move signal to higher IF • NCO – Numerically Controlled Oscillator – Used to adjust output frequency to any arbitrary frequency – Programmable and adjustable on-the-fly – Not limited to binary divisions of clock rate .

100 100 100 100 Pattern Test CLKVDD18 De-interleave 8 Sample FIFO ALARM_SDO SDIO SDENB SCLK TXENABLE RESETB Coarse Mixer Fs/4. -Fs/4. Fs/2 DIGVDD18 VFUSE QMC Phase and Gain DACVDD18 DAC Block Diagram (DAC3283) GND Programmable Delay (0-3T) .

Non-buffered Device – Active Op-Amp Interface • Power Supply Considerations – Utilizing DC-DC Converters for Efficient Supplies – Power Supply Noise Reduction Techniques • Analog Signal Chain Interface .DAC – Proper Load for Current Sink DACs – Interface Network to Quadrature Modulator – Low Pass Filter Design Techniques • Special Section: China Export Restrictions and SNRBoost – Current Export Restrictions – SNRBoost3G noise shaper – ADS58C48 – Out of band noise gain in SNRBoost • DAC Special Features – – – – Interpolation Filters Digital Signal Adjustments (QMC) NCO option DAC3283 Example Diagram .ADC – Passive Transformer Interface – Buffer vs.Agenda • Sampling Theory – Nyquist Rate – Aliasing – Under-sampling • Real World Clocking Solutions – Clock Jitter impact to Data Converter Performance – Jitter Impact as Related to Input Frequency – TI High Performance Clocking Solutions – Clock Improvement Techniques • Analog Signal Chain Interface .

Clock Jitter Impact to Data Converters • Random variation of the clock position compared to its ideal position with respect to time • As clock position varies. the position of the sampling point varies • Sampling at imprecise locations yield SNR degradation • Theoretical limit of SNR due to jitter: SNR j = −20 ⋅ log(2πf in ⋅τ j ) where: fin = input frequency τj = clock jitter .

SNR degrades as input frequency increases SNR j = −20 ⋅ log(2πf in ⋅τ j ) • Higher sampling rates indirectly lead to more stringent jitter requirements .Jitter Impact with respect to Frequency • SNR is independent of sampling rate • SNR is dependent on input frequency – For a given amount of jitter.

Phase Noise • Jitter is related to the integrated phase noise performance over a specified BW Φ N [dBc] = ∫ L( f ) ⋅ df f0 f1 2 ⋅10 τ j [sec] = 2πf clk ΦN 10 Where: L(f) = SSB noise power spectral density ΦN= Phase Noise f0. f1= frequency limits of integration τj = clock jitter • Phase Noise = Sum of the area under the curves .Clock Jitter vs.

Total Data Converter SNR Performance • SNR contributions – Quantization noise: • 6 * N{# of bits} + 1.76 dB – Clock jitter • Jitter or Phase Noise Performance – Aperture jitter • Value extracted from the datasheet – Thermal Noise • Value estimated from SNR performance from the datasheet at lowest IF • Total jitter is determined by rms sum of all individual contributions τT = ∑ [τ ] i i 2 • Total SNR is vector sum of all individual SNR contributions .

com/litv/zip/slac133 .Determining Clocking Requirements • Given SNR target from customer or standards • Given ADC aperture jitter from device datasheet • Given center frequency from customer specifications • Calculate the clock jitter requirement • Jitter Calculator Worksheet: http://www.ti.

00 MHz Aperture Jitter 170.49 fs rms SNR 62.59 dBc • Clock Jitter: (CDCE72010) • SNR : Input Frequency Aperture Jitter Ext Clock Jitter Total Jitter SNR 450.00 fs rms Ext Clock Jitter 200.36 MHz fs rms fs rms fs rms dBc 200 fs 62.ADS61B49 (14-bit 250 MSPS) Example • Aperture Jitter: • Fin: • SNR (from DS): 170 fs 450 MHz 66 dB Calculate Jitter-limited SNR Input Frequency 450.00 66.00 fs rms Total Jitter 262.00 170.6 dB Calculate Jitter-limited SNR Input Frequency 450.00 fs rms Total Jitter 262.00 fs rms Ext Clock Jitter 200.59 dBc .00 170.49 fs rms SNR 62.00 0.00 MHz Aperture Jitter 170.

ADS61B49 at 450 MHz IF Measurements match predicted values within 0.5 dB .

TI Clocking Solutions for Data Converters • CDCM7005 • External VCXO Ultra Low Jitter • 5 output channels • Programmable divider outputs • CDCE72010 • External VCXO Ultra Low Jitter • 10 output channels • Extended Programmable divider outputs • CDCE62005 • Integrated Low Jitter Frequency Synthesizer • 5 output channel • Wide range of programmable divider outputs • CDCE52005 • Integrated Dual PLL Ultra Low Jitter Synthesizer .

TI Clocking Solutions for Data Converters – CDC7005 – CDCE7005 • Jitter: ~180 – 250 fs • Internal VCO Dependent – CDCE62005 • Jitter: ~ 660 fs – CDCE52005 • Jitter: ~220 fs CDCE62005 CDCE72010 • VCXO Dependent With 400kHz PLL BW .

5 dBc .84 MHz (from standards) Pout = -7.7 dBm (at 70 MHz) Alt-ACPR [dBc] = 86.DAC3283 ACPR/NSD Example • NSD (Noise Spectral Density) Relationship to ACPR (Adjacent Channel Power Ratio) – ACPR [dBc] = Pout – (NSN [dBc/Hz] * 10*log(BW)) – Example • • • • NSN = -160 dBc/Hz (from datasheet) BW = 3.

29 dB 24.38 dB -79.29 dB -30 24.55 MHz/ Center 25.84 MHz Power Lower Upper Lower Upper * RBW 30 kHz * VBW 300 kHz * SWT 2 s -7.78 dB 3.84 MHz 5 MHz 3.74 dB Bandwidth Spacing -76.84 MHz Power Lower Upper Lower Upper * RBW 30 kHz * VBW 300 kHz * SWT 2 s -7.23 dBm -74.08 dB -79.84 MHz 5 MHz 3.84 MHz 5 MHz 3.000000000 MHz Marker 1 [T1 ] -105.84 MHz 10 MHz -82.14 dBm -81.000000000 MHz -40 1 RM * CLRWR -50 -60 -70 -80 -90 1 2 -100 -110 2.95 dB Tx Channel Bandwidth Adjacent Channel Bandwidth Spacing Alternate Channel W-CDMA 3GPP FWD 3.000000000 MHz 20 MHz CDC Clock A -40 1 RM * CLRWR -50 -60 -70 -80 -90 -100 -110 Center 20 MHz Ext Clock Tx Channel Bandwidth Adjacent Channel Bandwidth Spacing Alternate Channel Bandwidth Spacing W-CDMA 3GPP FWD 3.84 MHz Power Lower Upper Lower Upper -9.26 dBm -76.6 dBm -20 -30 * Att 10 dB Marker 2 [T1 ] -103.55 MHz/ Span 25.320000000 MHz Ref -14.80 dB Bandwidth Spacing -84.5 MHz Span 20 MHz 2.84 MHz 10 MHz .84 MHz 10 MHz -77.WCDMA ACPR Performance (DAC3283 EVM) over Frequency and Clock Jitter using External Clock and CDCE62005 Ref -12.37 dB 3.78 dB -83.73 dB 255.58 dB 255.73 dB -30 255.320000000 MHz -40 1 RM * CLRWR -50 -60 -70 -80 * Att 10 dB 259 MHz -40 1 RM * CLRWR -50 -60 -70 -80 -90 CDC Clock A Ext Clock NOR -90 1 2 -100 -110 2.55 MHz/ Span 25.00 dB Tx Channel Bandwidth Adjacent Channel Bandwidth Spacing Alternate Channel W-CDMA 3GPP FWD 3.71 dB 24.52 dB Marker 2 [T1 ] -103.84 MHz Power Lower Upper Lower Upper -9.55 MHz/ Center 25.21 dB -84.32 2.37 dB -78.70 dB -79.5 dBm Marker -20[T1 ] 1 -103.5 dBm Marker 1 [T1 ] -20 -104.5 MHz 1 2 -100 -110 Center 259.71 dB 24.76 dB -76.320000000 MHz 3.65 dB 3.84 MHz 10 MHz Ref -14.5 MHz 1 2 NOR * Att 10 dB * RBW 30 kHz * VBW 300 kHz * SWT 2 s Marker 2 [T1 ] -105.5 MHzMHz Span 259.88 dB -74.320000000 MHz Marker 1 [T1 ] -103.58 dB 255.5 dBm -20 -30 * Att 10 dB * RBW 30 kHz * VBW 300 kHz * SWT 2 s Marker 2 [T1 ] -104.000000000 MHz Ref -12.32 MHz Tx Channel Bandwidth Adjacent Channel Bandwidth Spacing Alternate Channel Bandwidth Spacing W-CDMA 3GPP FWD 3.14 dBm -80.84 MHz 5 MHz 3.

88 MHz Expected SNR Performance with SNR_Boost1 = ~72 dBFS (1) Extrapolated from SNR contour plots and expected SNR Boost improvement . Fclk = 122.Example ADC SNR with Different CDC Devices • Test with ADC62C17 (11-bit) – – – – Engage SNR Boost Measurement BW = ~ 20 MHz Fin = 150 MHz.

Performance with Subpar Clock • CDCE62005 – Jitter = ~650 fs – SNR (20 MHz BW) = 62.4 dBFS .

Performance with Realistic Clock • CDCE72010 – Jitter: ~300 fs – SNR = 71.3 dBFS .1 dBFS • Dual PLL – Jitter: ~220 fs – SNR = 72.

Clock Thermal Noise Impact to SNR • Thermal noise causes random variations in clock amplitude • Random variations alter zero-crossings or transition boundary location with respect to time (similar to jitter) • These variations yield SNR degradation. .

Sinusoidal Clock Amplitude • Maximizing the clock amplitude increases the slope of the sinusoidal clock signal at the transition boundaries and reduces thermal noise impact .

Band Limit Clock Phase Noise • Clock jitter performance integrated over entire clock input BW – Input BW can be up to 1 GHz for high speed converters – Some band limiting filter needed • For very sensitive jitter requirements. add narrow band Crystal filter on output – Requires CMOS output or amplifier to overcome insertion loss – Crystal Filter BW around 14 kHz – Small SMT devices available .

Non-buffered Device – Active Op-Amp Interface • Power Supply Considerations – Utilizing DC-DC Converters for Efficient Supplies – Power Supply Noise Reduction Techniques • Analog Signal Chain Interface .DAC – Proper Load for Current Sink DACs – Interface Network to Quadrature Modulator – Low Pass Filter Design Techniques • Special Section: China Export Restrictions and SNRBoost – Current Export Restrictions – SNRBoost3G noise shaper – ADS58C48 – Out of band noise gain in SNRBoost • DAC Special Features – – – – Interpolation Filters Digital Signal Adjustments (QMC) NCO option DAC3283 Example Diagram .ADC – Passive Transformer Interface – Buffer vs.Agenda • Sampling Theory – Nyquist Rate – Aliasing – Under-sampling • Real World Clocking Solutions – Clock Jitter impact to Data Converter Performance – Jitter Impact as Related to Input Frequency – TI High Performance Clocking Solutions – Clock Improvement Techniques • Analog Signal Chain Interface .

but normally <20mV ok • Traditionally an LDO regulator is used for each supply voltage – “Safe” approach – Still need good design.Power Supply • Most ADCs have separate supplies for analog and digital circuitry – Analog supply must be kept ‘clean’ – Check PSSR in datasheet. and bypassing – Degrades efficiency – must dissipate power in LDO • Migrating toward use of DC-DC converters – – – – New converters are very small (smaller than LDOs) Improved efficiency High switching frequencies yield to smaller inductors and easier filtering Yield good performance . layout.

3V Output 1. Drop out voltage of LDO 3.7V (5V) 34% 45% 1.5V (3.Traditional ADC Power Supply Typical LDO drop out voltage ~0.5V (with DC/DC) Often LDO connected directly to the input rail Ideal loss in the LDO Tradeoff between number of regulators and efficiency Best efficiency is to minimize drop across LDO But lowest device count may be to drop from existing next highest voltage rail.5V 13% 22% 1V 26% 36% 1.8V Output 0.3V) .

LDO. ADS42xx.DC-DC Power Supplies • Included on EVMs for newer lower power ADCs – ADS41xx. ADS58C48 • Option to compare DC-DC supply. and bench supply • Optimize power supply for max power efficiency while maintaining performance .

25 MHz • Standard “ADC ferrite” provides higher impedance at higher frequencies – Useful for providing isolation from RF signals LF202 ~75Ω at switching frequency Standard ferrite beat on ADC EVMs .Ferrite Bead Choice? • Ferrite bead after DC-DC (or LDO) provides filtering and supply isolation • LF202 ferrite provides highest impedance at switching frequency – TPS62590 switching frequency is 2.

ADC ferrite DCDC .LF202 90 LDO .ADC ferrite SNR (dBFS) vs Fin (MHz) @ 250Msps 72 71.ADC ferrite DCDC .5 1.3 dB SNR hit at 300 MHz IF • Ferrite bead choice is critical SFDR (dBc) vs Fin (MHz) @ 250Msps 95 1.ADC ferrite 85 80 75 69 70 0 50 100 150 200 250 300 68.5 70 69.8V Lab Supply DCDC .LF202 LDO .5 Fin (MHz) 0 50 100 150 200 250 300 Fin (MHz) .Power Supply Comparisons ADS4149 at 250MSPS • Negligible SFDR degradation with DC-DC • Negligible SNR degradation below 170 MHz • Only 0.5 71 70.8V Lab Supply DCDC .

ADC – Passive Transformer Interface – Buffer vs.DAC – Proper Load for Current Sink DACs – Interface Network to Quadrature Modulator – Low Pass Filter Design Techniques • China Export Restrictions and SNRBoost – Current Export Restrictions – SNRBoost3G noise shaper – ADS58C48 – Out of band noise gain in SNRBoost • DAC Special Features – – – – Interpolation Filters Digital Signal Adjustments (QMC) NCO option DAC3283 Example Diagram .Agenda • Sampling Theory – Nyquist Rate – Aliasing – Under-sampling • Real World Clocking Solutions – Clock Jitter impact to Data Converter Performance – Jitter Impact as Related to Input Frequency – TI High Performance Clocking Solutions – Clock Improvement Techniques • Analog Signal Chain Interface . Non-buffered Device – Active Op-Amp Interface • Power Supply Considerations – Utilizing DC-DC Converters for Efficient Supplies – Power Supply Noise Reduction Techniques • Analog Signal Chain Interface .

Europe. military system needs Supplier and government inputs Multi-national negotiation (US.What are the export restrictions for ADCs? Resolu Max Fs tion 9 500 11 200 12 105 The export restrictions are updated periodically as data converter technology improves Takes into account commercial vs. Japan) lengthens process .

– New.32 MSPS) for 3G wireless technology – Features flat noise performance inband.3M from Fs/4 40M: Center frequency adjustable in 9 steps in 6.1W Selectable DDR LVDS or CMOS output. optimized wideband modes (up to 60M @ 184.ADS58C48 Quad channel 11 Bit 200 MSPS withSNRBoost3G – TI PATENTED TECHNOLOGY • New and Improved SNRBoost3G: – SNRboost3G is the 3rd generation ADC from TI. 11-Bit resolution. the total Power Dissipation =1. Pin control of SNRboost 80 pin QFP • Specs and Features: – – – – – NDA Protected Material . – TI invented and patented SNRboost technology. • SNRBoost3G Bandwidth modes – – – – 60M: Center frequency adjustable in 7 steps in 5. 200MSPS Ultra-low power technology: all 4ch on.5M from Fs/4 30M: Center frequency adjustable in 10 steps in 7M from Fs/4 20M: Center frequency adjustable in 10 steps in 8M from Fs/4 Quad.

Strictly Private” or similar placed here if applicable 55 .88M. BW=40M More total power for 65% occupied BW than for 43% occupied BW 2010/8/8 “TI Proprietary Information .32M. BW=40M Case #2 FS=184.Total Out of Band Noise Increases with % BW of Nyquist BW Case #1 FS=122.

quantization has a maximum of 0.Noise Gain in SNR Boost 30 Noise Shaping Circuit 25 20 Value 15 10 5 0 Current Sample 0 5 10 T ap 15 20 25 Past quantization errors Filter FFT 60 Filter taps Noise shaping INCREASES noise during shaping process With no noise shaping.5 output LSBs Noise shaping peak value increases by SUM(ABS(filter taps)) 12 dB Suppression 40 Response (dB) 20 0 -20 Increased headroom needed to avoid saturation with noise shaping added to input signal -40 0 20 40 60 Frequency (MHz) 80 .

05 40 29.13 60 171 0.76 .Noise Gain in SNR Boost More filter taps and larger total sum required for higher BW/Fs ratios and filters offset from mid-band Example at 184.7 0.4 0.03 30 11.9 0.32 MSPS Noise shaped signal without ADC input signal 1000 800 600 40 MHz centered Code 400 200 0 -200 -400 -600 -800 -1000 0 1 2 Sample 3 4 x 10 5 4 60 MHz centered 60 MHz offset 10 MHz ADC input headroom required to prevent saturation BW (MHz) Filter Sum Headroom (dB) 20 6.

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