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PGS.TS L Tin Thng Nguyn Thanh Phng Phan Trng B Quyn 111400044 111400051
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1.Tm tt 4 2. Gii thiu ....................................................................................................4 3. DSP v FPGA .............................................................................................4 3.1 Digital Signal Processing ....................................................................4 3.2 Field Programmable Gate Arrays ........................................................6 4. Kt hp DSP trn FPGA .............................................................................8 4.1 Tch hp cng .....................................................................................9 4.2 Tch hp mm.....................................................................................10 5. So snh DSP-FPGA vi DSP-ASIC .......................................................... 11 6. nh gi .................................................................................................... 12 6.1 u im ............................................................................................ 12 6.2 Nhc im ...................................................................................... 12 7. Kt lun .. 13 8.Ti liu tham kho .. 14
1.Tm tt
Trong project ny chng ta s nghin cu v s lin kt gia DSP v FPGA, cc u, khuyt im cng nh ng dng ca s lin kt ny trong thc t.
2. Gii thiu
S t ph mnh m trong cng ngh bn dn v nhu cu cao v ng dng a phng tin trn mng khng dy thc y vic nghin cu v pht trin cc php ton x l tn hiu mnh cho h thng vin thng trn FPGA cng nh trn cc mch tch hp chuyn dng (ASIC). Nhng bc tin ny cng dn n mt lot cc gii php mi cho vn v x l tn hiu, m ra th trng c hi v xu hng mi. Thng thng th cc ng dng c trng cho x l tn hiu c sn trong cc b x l tin hiu s (DSP). Song song , cc gii thut dng trn nhng b x l c tp lnh phc tp (VLIW) kh kh khan v thng khng mang li mt gii php ti u. V thm vo l nhng t ph gn y v tc , mt , v gi thnh ca cc b x l FPGA dn n c thm mt la chn rt hp dn cho vic x l tn hiu tc cao. So snh trong nhiu thit k, s kt hp DSP vo FPGA cho kt qu vt tri so vi cc b x l vi tp lnh phc tp.
3. DSP v FPGA
3.1 Digital Signal Processing
X l tn hiu s (DSP) l s dng cc bin i hoc iu khin tn hiu s trong sut thi gian di. DSP tr thnh mt nn tng cng ngh v thay th cho h thng x l tn hiu truyn thng trong nhiu ng dng. DSP c nhiu im mnh, chng hn nh khng thay i theo nhit , tui th, v thm vo , cc thit k s c hiu sut cao, cng sut thp, gi thnh r hn so vi cc thit k tng t. Ta d dng bt gp mt h thng c s dng DSP hu ht cc thit b cng ngh by gi, PC hoc in thoi di ng chng hn. DSP c s dng kh rng ri trong nhiu lnh vc i sng cng nh khoa hc k thut. Ta c th t rt ra tm quan trng ca DSP trong cc h thng ng dng. Kh m tng tng c nu th gii khng tn ti DSP, cng ngh s khng th pht trin c nh hin ti, cng nh s khng tn ti ca kh nhiu tin ch cuc sng v khng c g h tr to nn cc ng dng kh quen thuc vi chng ta. Bng tm lc di y s cho ta ci nhn tng quan v cc ng dng ca DSP.
GII THUT DSP Lc v nhn chp, lc thch nghi, nhn din v so snh, nh gi ph, phn tch ph v bin i Fourier. M ho v gii m, nhn dng v tng hp ting ni, nhn din ngi ni, loi b ting vng, x l tn hin trong cy tai. M ho v gii m Hi-Fi, loi b nhiu, cn bng m thanh, m phng m thanh xung quanh, trn v hiu chnh m thanh, tng hp m thanh. Nn v gii nn nh, xoay, truyn v phn gii nh, nhn dng nh, nng cp nh, x l tn hiu trong cy vng mc. Th m thanh, fax, b iu ho, mng in thoi, iu ch v gii iu ch, cn bng ng dy, m ho v gii m d liu, truyn thng s v mng LAN, mng khng dy, v tuyn v truyn hnh, y sinh. iu khin Server, a, my in, ng c, iu khin nh hng, iu khin dao ng, iu khin h thng cng sut, robot. ng dn chm, my quan st sng, phn tch in p, phn tch trng thi bn vng, h thng nh v.
X l ting ni
X l m thanh
X l nh
iu khin
Thit b o
Hnh 1 trnh by mt ng dng c trng ca h thng DSP dng thc thi mt ng dng tng t. tn hiu vo tng t i qua b tin lc kh nhiu cho tn hiu th ban u, ta c c tn hiu tng t trn tru, vi tn s ly mu fs ta thu c cc mu tn hiu ri rc, tn hiu c ly mu qua b bin i tn hiu tng t sang s (ADC - Analog to Digital Converter) thu c tn hiu s. Lc ny, tn hiu s qua h thng DSP v tn hiu ra c th dng s hoc qua b bin i s sang tng t (DAC - Digital to Analog Converter) c c tn hiu ra tng t.
Hnh 2 m t kin trc bn trong mt FPGA thng thng, ta c th thy gm c 3 thnh phn: I/O Cell(I/O pads), Logic Block, v Wire Segments (Routing Channels). Routing Channels c th c xem nh rng, s ng dy. Cc li vo I/O khp vi chiu cao ca mt dng hoc rng ca mt ct trong mng, c nhim v kt ni theo mun bt k mt ng dy no vi knh bn cnh. Cu trc mt Logic Block c xem xt hnh 3.
Mt khi Logic c in bao gm mt Look up table 4-input (LUT), mt flip-flop, nh c biu din hnh 3, khi ny c th thc hin bt k hm logic no t 4input. Cng vi s pht trin cng ngh, s u vo c th tng ln 6-input LUT hoc hn. Hnh 4 cho thy cu trc bn trong ca mt bn tra c 4 u vo A-B-C-D.
DSP tch hp cng trn FPGA ngha l mt chip DSP c tch hp ln h thng FPGA.
Hnh 5 cho thy mt cch trc quan h thng gm 2 thnh phn FPGA v DSP, DSP c tch hp ln FPGA nh mt ngoi vi ca FPGA. Tt nhin trong h thng ng dng khng ch c 2 thnh phn ny thi.
Hnh 6 l mt sn phm ca Altera, Altera DSP Development Kit Stratix II, h tr mt FPGA Stratix II EP2S60F1020C4, b DSP c tn DK-DSP-2S60N (vi phin bn Professional c thm DK-DSP-2S180N), mt DC-VIDEO-TVP5146 ng vo x l video,. Hnh 7 l mt sn phm ca Xilinx, ZestET1 GigE TOE and FPGA, h tr mt FPGA Xilinx Spartan-3A XC3, cc chun Internet IPv4, TCP, UDP,.
Vic tch hp cng DSP trn h thng FPGA cho mt hiu qu lm vic tt. Tc x l, tnh ton s tng hn nhiu ln so vi mt h thng khng c DSP. Nhc im ca vic tch hp cng l DSP b t cht trong h thng nn kh c kh nng cp nht, h thng x l ph thuc nhiu vo DSP ny, hn ch v kh nng nng cp ng dng. ta khng th mong mun thay i mt chip x l m thanh c h tr cng thay vo bng mt chip x l nh m board khng h tr.
4.2 Tch hp mm
Mt DSP tch hp mm tht cht l mt IP vit bng ngn ng HDL v cng c thit k s trin khai IP xung FPGA. Vi Altera chnh l Nios, Nios II, cn trong Xilinx l Picoblaze, Microblaze. Hnh 8 ch ra mt DSP nm trong FPGA, ng ngha vi DSP l mt IPcore c nhng trn FPGA.
Vi mt DSP c tch hp mm, hn ch ln nht ca n chnh l tiu tn kh nhiu ti nguyn FPGA, nu bn c mt h thng DSP phc tp th vn s dng ti nguyn cn phi c tnh ton hp l sao cho ti u nht cho ng dng ca bn. h tr cho vic thc hin cc ng dng ln c thun tin hn, tn thi gian vit nhn hn, cc hng cng cung cp mt s IP core v x l tn hiu s, l cc th vin, v d nh: Xilinx FFT Library, Polyphase DFT, FIR Filters,.
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Tt nhin vic tch hp mm cng c u im ni tri ca n, chnh l kh nng cp nht. y s l la chn tt cho cc ng dng m thng c s thay i nhanh trong thut ton x l (hoc nng cp thng xuyn). Th hnh dung, nu bn c mt ng dng cn th nghim, vi mt DSP tch hp mm, hm nay bn lm DSP ny, ngy mai bn cm thy DSP khc hiu qu hn v mun thay i n, vic cu hnh li FPGA s cho php bn thc hin iu mt cch d dng. Chng hn nh bn thit k mt h thng ca nhn din ch nh v t ng m kho khi xc nh ng l ch. Bn dng DSP x l nh nhn din c i tng, mt thit k DSP mm c s dng v phn FPGA lm cng vic iu khin. Nu dng y th nhiu ngi s ni rng nhng h thng trc kia vn c th lm c, nhng nu ti mun thit k thm tnh nng iu khin ca t kho bng ging ni th sao? Vi thit k truyn thng, ti phi thay i phn cng cc k gian nan, so vi vic np thm mt IPcore DSP x l ting ni v thm mt s module iu khin vo FPGA, qu l mt tri mt vc, thit k tch hp ny t ra vt tri hn hn.
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Thm mt li th ca FPGA so vi ASIC. Ta xt trong cc trng hp nghin cu khoa hc hoc qun s chng hn, ASIC khng cn l s la chn u tin na. n gin l v i hi v mt gii thut mi hoc mt ci tin t ph mi s loi b suy ngh v ASIC, v h cn s mi m hon ton, v h s nh n mt s sng to trn FPGA. D ASIC a dng n u th cng s c gii hn, cn FPGA tuy l chip trng, nhng c kh nng bin chuyn v cng. Da vo yu cu ng dng cn tnh linh ng hay chuyn dng, m ta s c la chn DSP ASIC hay DSP FPGA.
6. nh gi
6.1 u im
Kt hp c kh nng ca c FPGA v DSP to nn mt h thng u th v tc x l so vi cc thit k trn cc vi x l thng thng. Cc thit k thng thng, chng hn nh vic vit m x l trn cc vi x l, cng vic ny hn ch bi bn thn chip khng h tr bt c DSP no ti u ho tc . Tit kim v hao ph thi gian, cng sut khi thit k ra h thng c s dng DSP. Vi nhng DSP tch hp sn, ta khng phi thc hin thao tc kt ni mt b DSP ngoi vo h thng nh trc y, hoc vit mt chng trnh x l trn chip thng thng, m DSP tr thnh mt phn trong h thng. Vi kh nng cu hnh li, chng rt linh ng trong thit k. Kh tin li cho nghin cu pht trin ng dng.
6.2 Nhc im
V c im ca FPGA l ti cu hnh li mi khi reset, d rng hin c mt s FPGA h tr t cu hnh, nhng y vn l mt nhc im ng ni ca hng pht trin DSP-FPGA. Tnh linh ng trong thit k lm cho DSP-FPGA tr nn kh tip cn vi ngi dng bnh thng. Chng ch ph hp vi gii nghin cu, dn k thut. V linh ng nn cng sinh ra mt hn ch, l khng chuyn dng. Ngi thit k phi am hiu v ngn ng HDL cng nh nhiu kin thc khc, mi c th thc hin c. Gi thnh kh cao, nn s tip cn DSP-FPGA cng hn ch phn no.
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7. Kt lun
Qua cc ni dung c trnh by trn, chng ta c th thy c ti sao ngi ta li lin kt DSP vi FPGA. Tuy nhin y mi ch l l thuyt, cn thc t c ng dng ra sao th do thi gian c hn nn chng em cha trnh by y. Trong tng lai, nu c iu kin, chng em s trnh by cc ng dng thc t c th lm r hn vn ny.
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