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Junction Field Effect Transistor A semiconductor device that operates by altering the conductivity of a region of the semiconductor (the channel) between two contacts (source and drain) by application of a voltage to a third terminal (gate). The current flow between source and drain is controlled by the gate voltage. In a JFET device, the gate voltage is applied to the channel across a P-N junction, in contrast to its application across an insulator in a conventional MOSFET. JFETs are of both P-channel and N-channel types.

Structure of an N-channel JFET See also FET, MOSFET. Meanwhile, AMS has a good JFET tutorial page here.

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Page author: Eric Seale This page was last updated on July 11, 2003 This work is licensed under a Creative Commons License.

Top Electronic Tutorials Semiconductor Theory - Table Of Contents Chapter 5 - Junction Field-Effect Transistors

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Introductio n

A transistor is a linear semiconductor device that controls current with the application of a lower-power electrical signal. Transistors may be roughly grouped into two major divisions:bipolar and fi eld-effect. In the last chapter we studied bipolar transistors, which utilize a small current to control a large current. In this chapter, we'll introduce the general concept of the field-effect transistor -- a device utilizing a small voltage to control current -- and then focus on one particular type: the junction field-effect transistor. In the next chapter we'll explore another type of fieldeffect transistor, the insulated gate variety. All field-effect transistors are unipolar rather than bipolar devices. That is, the main current through them is comprised either of electrons through an N-type semiconductor or holes through a Ptype semiconductor. This becomes more evident when a physical diagram of the device is seen:

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In a junction fieldeffect transistor, or JFET, the controlled current passes from source to drain, or from drain to source as the case may be. The controlling voltage is applied between the gate and source. Note how the current does not have to cross through a PN junction on its way between source and drain: the path (called a channel) is an uninterrupted block of semiconductor material. In the image just shown, this channel is an N-type semiconductor. P-type channel JFETs are also manufactured:

Generally, N-channel JFETs are more commonly used than P-channel. The reasons for this have to do with obscure details of semiconductor theory, which I'd rather not discuss in this chapter. As with bipolar transistors, I believe the best way to introduce field-effect transistor usage is to avoid theory whenever possible and concentrate instead on operational characteristics. The only practical difference between Nand P-channel JFETs you need to concern yourself with now is biasing of the PN junction formed between the gate material and the channel. With no voltage applied between gate and source, the channel is a wideopen path for

electrons to flow. However, if a voltage is applied between gate and source of such polarity that it reverse-biases the PN junction, the flow between source and drain connections becomes limited, or regulated, just as it was for bipolar transistors with a set amount of base current. Maximum gate-source voltage "pinches off" all current through source and drain, thus forcing the JFET into cutoff mode. This behavior is due to the depletion region of the PN junction expanding under the influence of a reversebias voltage, eventually occupying the entire width of the channel if the voltage is great enough. This action may be likened to reducing the flow of a liquid through a flexible hose by squeezing it: with enough force, the hose will be constricted enough to completely block the flow.

Note how this operational behavior is exactly opposite of the bipolar junction transistor. Bipolar transistors are normally-off device s: no current through the base, no current through the collector or the emitter. JFETs, on the other hand, are normally-on device s: no voltage applied to the gate allows maximum current through the source and drain. Also take note that the amount of current allowed through a JFET is determined by a voltage signal rather than a current signal as with bipolar transistors. In fact, with the gate-source PN junction reversebiased, there should be nearly zero current through the gate connection. For this reason, we classify the JFET as a voltagecontrolled device, and the bipolar transistor as a current-controlled device.

If the gate-source PN junction is forwardbiased with a small voltage, the JFET channel will "open" a little more to allow greater currents through. However, the PN junction of a JFET is not built to handle any substantial current itself, and thus it is not recommended to forward-bias the junction under any circumstances. This is a very condensed overview of JFET operation. In the next section, we'll explore the use of the JFET as a switching device. Lessons In Electric Circuits copyright (C) 2000-2002 Tony R. Kuphaldt, under the terms and conditions of the Design Science License

JFET Basics 1 by Kenneth A. Kuhn Nov. 3, 2001, rev. Oct. 30, 2008 Introduction A junction field-effect transistor (JFET) consists of a semiconducting channel whose conductance is controlled by an electric field. The terminals at either end of the channel

are called source (S) and drain (D). The control electrode that applies the electric field is called the gate (G) and is made of the opposite type of semiconductor material than the channel. Thus, there is a PN junction between the gate and the channel. This PN junction is always reverse biased in normal operation. Figure 1 shows the basic structure. Figure 1: JFET construction and conduction channel controlled by depletion zone JFETs are known as depletion mode devices because the channel conducts with zero bias voltage applied (i.e. the depletion region has zero width). Applying a reverse bias increases the width of the depletion region which in turn reduces the conduction of the channel. This is the basis for making an amplifier. The channel conduction resembles a resistor for low voltage drops (ohmic region) and becomes a constant current for higher voltage drops (saturation region). The mathematical models we use are based on the saturation region and will provide incorrect results if used in the ohmic region. The model for a field effect transistor is a voltage controlled current source. Many JFETs are so symmetrical in their construction that it makes little if any difference if the source and drain terminals are swapped. There are two channel types of JFETs. One type is n-channel and the other type is pchannel. Both types operate exactly the same way but the terminal voltages and currents are inverted. This discussion is for n-channel devices.JFET Basics 2

The main feature of JFETs is extremely high input resistance usually at least several hundred megohms. This feature enables the power gain of a JFET amplifier to be huge. Development of analytic equations for JFET bias condition The following discussion is about n-channel JFETs. p-channel JFETs operate the same way except that the polarity of the terminal voltages and currents is inverted. There are two parameters that describe the operation of a JFET: IDSS is the drain saturation current at VGS = 0. VP is the gate-source voltage, VGS, that causes the channel conduction to drop to zero (actually, the drain current does not go all the way to zero but ceases to decrease below a very small current). IDSS and VP have a rough proportional relationship. A high IDSS generally has a higher magnitude VP. However, because the relationship is dependent on the manufacturing geometry of the JFET there is not a singular proportionality constant. The interpretation of this is that for the spread of IDSS and VP provided on the data sheet for a specific part that low values of one parameter tend to correlate with low values of the other parameter with the same holding true for higher values. Some data sheets show a typical plot of this relationship. The drain current is zero when VGS = VP and is IDSS when VGS = 0. The relationship in the saturation region follows a square law as shown in Equation 1. For normal operation,

VGS is biased to be somewhere between VP and 0. Equation 1 gives the approximate drain current, ID, for a given bias point. This approximation is generally good to within about ten percent and is the accepted equation for all JFET calculations. The more exact model is discussed later. ID = IDSS * [1 - (VGS/VP)] 2 Eq. 1 Equation 1 is valid only if the JFET is operating such that VGS is between 0 and VP and that VDS is greater than (VGS - VP) , i.e. the saturation region. Note that the drain current, ID, will be between 0 and IDSS. Figure 2 illustrates an example transfer function for a JFET that has an IDSS of 12 mA and a VP of -6 volts. The drain current will be less if the transistor is operating in the ohmic region. Although the transfer curve continues into the positive bias region we do not normally operate the JFET there except for very small signals.JFET Basics 3 Transfer Curve of a Typical JFET 0.000 0.001 0.002 0.003 0.004

0.005 0.006 0.007 0.008 0.009 0.010 0.011 0.012 0.013 0.014 0.015 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 VGS DI Figure 2: Transfer Curve of a Typical JFET showing ID versus VGS Figure 3 shows the family curves for a typical JFET. For amplifiers we normally operate the JFET in the saturation region to the right of the dotted parabola curve that separates the ohmic region from the saturation region. Note that that the dotted curve is the solution to VDS = (VGS VP). In the ohmic region the device acts similarly to a voltage controlled resistor and in the saturation region the device acts as a voltage controlled current source. The slight tilt of the lines in the saturation region is an extension of the model that includes the effective shunt resistance of the current source. That model is not

discussed here. All of the mathematics developed later assumes these lines are perfectly horizontal. It should be noted that for VDS near zero volts (within plus or minus a few tenths of a volt at most) the channel acts as a voltage variable resistor that is linear with voltage. This useful effect continues through zero for small negative voltages across the channel.JFET Basics 4 FET Family Curves 0.000 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.010 0.011 0.012 0.013 0.014 0.015 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

VDS DI VGS=0 VGS=-1 VGS=-2 VGS=-3 VGS=-4 VGS=-5 VGS=-5.5 Knee for IDSS = 12 mA and VP = -6 Ohmic_region Saturation_region Figure 3: FET Family Curves Note: VGS is negative the minus sign may not show on some systems It is desirable to have the solution to every possible permutation of knowns. The next task is to solve Equation 1 for VGS if ID is known. This is an exercise for the student but the result is: VGS = VP * [1 - sqrt(ID/IDSS)] Eq. 2 Equations 1 and 2 tell us about the DC bias point operation of the JFET for any combination of knowns. Development of gain equations for the JFET Since the JFET is a voltage controlled current source, the gain is the change in drain current divided by the change in gate voltage. This is called the transconductance gain (abbreviated as gm) of the JFET and has units of conductance which is measured in

Siemens. The gain value is very low (typically between 0.0001 and 0.02 but remember that what matters is power gain and that is very high for a JFET) and is often expressed in mS. The gain is found by taking the derivative of Equation 1 with respect to VGS. gm = |2 * (IDSS/VP) * [1 - (VGS/VP)]| Eq. 3JFET Basics 5 The absolute value is used because gm is always positive. This is done because sign information is lost when terms are squared as in Equation 1. The ratio, IDSS/VP, will always be negative since VP is negative for n-channel JFETS and IDSS is negative for pchannel JFETS. Note from Equation 3 that gm is a linear function of VGS. When VGS is equal to VP (i.e. ID is zero) then gm is zero. When VGS is equal to zero (i.e. ID = IDSS) then gm is at the maximum value. The maximum value of gm is known as gmo and is obtained by setting VGS to zero in Equation 3. gmo = |2 * (IDSS/VP)| Eq. 4 At this point it should seem obvious that if high gain is desired then the JFET should be biased as close as practical to IDSS. Equation 4 gives us the ultimate gain possible. Equation 3 gives us the gm if VGS is known. For some problems, ID is known instead. Although VGS can be calculated if ID is known, it is convenient to have an equation that directly gives us gm when ID is known. Simple substitution of Equation 1 into Equation 3 (an exercise for the student) gives: gm = |2 * sqrt(ID * IDSS) / VP| Eq. 5

Equation 5 can be expressed in another way that might be convenient for some problems gm = gmo * sqrt(ID/IDSS) Eq. 6 All three ways of computing gm give exactly the same answer. The one to use depends on what the knowns at the moment are. It must be remembered that all of these equations assume the JFET is operating in the saturation region. They do not apply in the ohmic region. The user must always take care in using these equations. The scale factor of 2 in Equations 3 through 5 is nominal. According to the National Semiconductor FET Handbook (1977), that factor can range from about 1.1 to 2.5 but is typically near 2. Keep in mind that we use a model of a JFET based on a simplified quadratic equation. Equations 1 and 2 can be expressed in a normalized form as ID/IDSS = [1 (VGS/VP)] 2 Eq. 7 VGS/VP = 1 sqrt(ID/IDSS) Eq. 8JFET Basics 6 An equation for the normalized gm can be developed by dividing Equation 3 by Equation 4 producing gm/gmo = 1 VGS/VP Eq. 9 By substituting Equation 8 into Equation 9 we can also write gm/gmo = sqrt(ID/IDSS) Eq. 10 Figure 4 is a plot of Equations 7 and 9. The linear relationship between VGS and gm is

clearly seen. Figure 5 is a plot of Equation 10. Normalized ID/IDSS and gm/gmo versus VGS/VP 0.000 0.100 0.200 0.300 0.400 0.500 0.600 0.700 0.800 0.900 1.000 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 VGS/VP DI / DI SS ID/IDSS gm/gmo Figure 4: Normalized FET plotJFET Basics 7 gm/gmo versus ID/IDSS 0.000 0.100 0.200 0.300 0.400

0.500 0.600 0.700 0.800 0.900 1.000 0.000 0.100 0.200 0.300 0.400 0.500 0.600 0.700 0.800 0.900 1.000 ID/IDSS gm g/ mo Figure 5: Normalized gm/gmo ComparingExactandApproximate JFET Models In the text, Engineering Electronics, A Practical Approach, by Robert Mauro (copyright 1989 by Prentice-Hall, Inc., Englewood Cliffs, NJ 07632) on pages 209 to 211 there is a development of a more accurate mathematical model for the JFET. The result of that development is: [ (VGS) (VGS) 3/2 ] ID = IDSS * [ 1 3 * (-----) + 2 * (-----) ] Eq. 11 [ ( VP ) ( VP ) ] A commonly used and more convenient approximate model was presented in Equation 1 and is expanded here for comparison: [ (VGS) (VGS) 2

] ID = IDSS * [ 1 2 * (-----) + (-----) ] Eq. 12 [ ( VP ) ( VP ) ]JFET Basics 8 Figure 6 is a plot of both equations in normalized form. Observe that the error of the approximate model is not very large and that the approximate model predicts a somewhat higher current than the actual. Observealsothattheslopeoftheexactcurveissteeper thus leading to a higher gm. Comparing "Exact" versus Approximate JFET Models 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 VGS/VP No mr alized DI ID approx ID exact ID error

Figure6:ComparingExactversusApproximateJFETModels Figure 7 shows the normalized transconductance for both models. Observe that the exactmodelhasahighergmo than the approximate model. This is one reason that on data sheets the stated value of gmo is often higher than what one would calculate using the given IDSS and VP parameters.JFET Basics 9 Comparing "Exact" gm versus Approximate gm JFET Models 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 VGS/VP No mr alized gm

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