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How fast is your personal computer? When people ask this question, they are typically referring to the frequency of a minuscule clock inside the computer, a crystal oscillator that sets the basic rhythm used throughout the machine. In a computer with a speed of one gigahertz, for example, the crystal "ticks" a billion times a second. Every action of the computer takes place in tiny steps, each a billionth of a second long. A simple transfer of data may take only one step; complex calculations may take many steps. All operations, however, must begin and end according to the clock's timing signals. The use of a central clock also creates problems. As speeds have increased, distributing the timing signals has become more and more difficult. Present day transistors can process data so quickly that they can accomplish several steps in the time that it takes a wire to carry a signal from one side of the chip to the other. Keeping the rhythm identical in all parts of a large chip requires careful design and a great deal of electric al power. Wouldn't it be nice to have an alternative? Clockless approach, which uses a technique known as asynchronous logic, differs from conventional computer circuit design in that the switching on and off of digital circuits is controlled individually by specific pieces of data rather than by a tyrannical clock that forces all of the millions of the circuits on a chip to march in unison. It overcomes all the disadvantages of a clocked circuit such as slow speed, high power consumption, high electromagnetic noise etc. For these reasons the clockless technology is considered as the technology which is going to drive majority of electronic chips in the coming years.
2. A BRIEF HISTORY
CONCEPT OF CLOCKS The clock is a tiny crystal oscillator t hat resides in the heart of every microprocessor chip. The clock is what which sets the basic rhythm used throughout the machine. The clock orchestrates the synchronous dance of electrons that course through the hundreds of millions of wires and transistors of a modern computer. Such crystals which tick up to 2 billion times each second in the fastest of today’s desktop personal computers, dictate the timing of every circuit in every one of the chips that add, subtract, divide, multiply and move the ones and zeros that are the basic stuff of the information age. Conventional chips (synchronous) operate under the control of a central clock, which samples data in the registers at precisely timed intervals. Computer chips of today are synchronous: they contain a main clock which controls the timing of the entire chips. One advantage of a clock is that, the clock signals to the devices of the chip when to input or output. This functionality of the synchronous design makes designing the chip much easier. There are problems that go along with the clock, however. Clock speeds are now in the
Dept. of CSE, BRECW
As we see in the figure. With a gigahertz clock powering a c hip. One possible solution is a second clock. The most disturbing thing about this is that the clock serves no direct computational use. Mobile electronics are the target for many chips. Therefore. A synchronous circuit looks for a particular signal of the clock. but this will incur overhead and power consumption. so t his is a poor solution. BRECW 2 . These chips need to be even more conservative with power consumption in order to have a reasonable battery lifetime. New problems with speeding up a clocked chip are just around t he corner. Especially when transferring the data on to the registers the computations settle down and wait for the next leading edge of the clock to occur. the other parts of the chip are forced to sit idle. The figure gives a clear idea of how conventional chips operate under the control of a central clock. speedup up the clock frequency could become disastrous. At this point. The only thing the designers have to think about is how to complete one operation during a single tick of the clock. is to eliminate the source of these headaches: the clock. if one part of the chip is especially slow. PROBLEMS OF SYNCHRONOUS CIRCUITS One problem is speed. so does the power used by the clock. signals barely have enough time to make it across the chip before the next clock tick. which samples data in the registers at precisely timed intervals. This wasted computing time is obviously detrimental to t he speed of the chip. Then only the data will be transferred to the next register. A clock does not perform operations on information. therefore blindly trying to increase chip speed by increasing frequency without considering other options is foolish. New problems with power consumption are arising. power consumption becomes an even more crucial topic.Clockless Chip gigahertz range and there is not much room for speedup before physical realities start to complicate things. This is when a chip that is not constricted by clock speeds could become very valuable. all actions in this circuit take place only on the leading edge of the clock cycle. When we get to the point where the clock cannot drive the entire chip. Clock frequencies are getting so fast that signals can barely cross the chip on one clock cycle. the circuit is looking for the leading edge of the clock pulse. Therefore. The other major problem with a clocked design is power consumption. Dept. As the number of transistors on a chip increases. The natural solution to the above problems. It is extremely import ant to design the circuits in such a fashion that all the computations must settle down and be ready for the next logical operation before the next clock tick. It is also important to note that doubling the frequency of the clock does not double the chip speed. as you may have guessed. we'll be forced to come up with a solution. as we design more complicated chips. of CSE. WORKING OF A SYNCHRONOUS CIRCUIT This is the working model of a particular synchronous circuit. it simply orchestrates the computational parts of the computer. In this case. The clock consumes more power than another other component of the chip. A chip can only work as fast as its slowest component.
By throwing out the clock. The next part is about various types of implementation. The figure below gives an idea of working of an asynchronous circuit. data moves instead under the control of local " handshake" signals (lines below) that indicate when work has been completed and is read y for t he next logic operation. without needing to wait for everything else.Clockless Chip CONCEPT OF CLOCKLESS CHIPS The main concept behind a clockless design is evident from the name itself. So there must be some control mechanism which should synchronize the components inside a clockless chip to ensure correct working of the chip. Clockless chips draw power only when t here is useful work to do. The clockless chips rely up on handshaking signals. The control signal is encoded within the data that is being transferred. By contrast. of CSE. a clocked c hip can run no faster than its most slothful piece of logic. for example. This control signals act as handshaking and handoff signals which indicates when the component is ready for the next logical operation. The result? Instead of the entire chip running at the speed of its slowest components. an asynchronous-chip-based pager marketed by Philips Electronics. chip makers will be able to escape from the problems of the synchronous circuits. self timed or event driven) chips dispense with the timepiece. As we can see above there is the usual logical circuitry and instead of a clock signal which controls the circuit. The faster t he clock. there are two lines on the top and bottom. clocked chips. they don’t have a global clock which synchronizes it s actions. Another advantage of clockless chips is that they give off very low levels of electromagnetic noise. the more difficult it is to prevent a device from interfering with other devices. handoff signals & sometimes a local clock to synchronize the actions. the transistors on an asynchronous chip can swap information independently. dispensing with the clock all but eliminates this problem. Dept. it can run at the average speed of all components. enabling a huge savings in battery-driven devices. In this particular scheme (which is called a duel rail circuit which will be discussed later). Like a team of horses that can only run as fast as its slowest member. The wires are used to transfer the data bits and the control bits together. this approach has led to prototype chips that run two to three times faster than comparable products using conventional circuitry. runs almost twice as long as competitors' products. That is. BRECW 3 . WORKING OF ASYNCHRONOUS CIRCUIT Clockless (also called asynchronous. There are different ways to implement an asynchronous circuit. which use conventional. the answer isn't guaranteed until every part completes its work. So there is no separate control signal going across the circuit. At both Intel and Sun.
as opposed to DATA in the set phase. the gates do not need to be clocked because they do their computation as soon as possible. then the output of the gate is DATA. without an error. As a result. BOUNDED DELAY METHOD 2. This signal is an indication given by the c ompletion detection circuit for the signal to pass to the next step. in Bounded-Delay design we [censored] use that we know the largest amount of time for each component to perform its task. NULL CONVENTIONAL LOGIC (NCL) The simplest implementation of asynchronous design is the Bounded-Delay method. When t he combinational logic is done with the input signal. This design is very similar to synchronous design. of CSE. This is the actual logic which does all the calculation. Attached to this logic circuit is the completion detection unit which helps the circuit to proceed in a controlled fashion i. This convention uses a NULL state when data is in the reset phase. Once the gate gets all its inputs. Knowing the bounds of the delay time allows for computations to be sped up. The theory behind NCL is simple. They are the following: 1. that are all its inputs are DATA.Clockless Chip TYPES OF IMPLEMENTATIONS There are mainly three kinds of implementations of an asynchronous circuit. If a gate has any inputs that are NULL. The input signal in the combinational logic part and the go signal in the completion detection circuit reach the unit simultaneously. BOUNDED DELAY Prototype delay Done GoEarly? Combinational logic Input Output Dept. does not assume any bounds on time. This completion detection unit indicates when the circuit has completed its action and when it is ready for the next action. handshaking is needed between components. Another way of implementing an asynchronous design is to use NULL Convention Logic (NCL). In this way. DELAY INSENSITIVE METHOD 3.e. a done signal is produced by the completion detection circuit. THE GENERAL MODEL Completion Detection Done GoLogic Circuit Input Output The general model of an asynchronous design implementation is shown above. In this circuit we can see a logic circuit which does the same operation as in the synchronous circuit. which is quite the opposite of Bounded-Delay. BRECW 4 . then this gate has an output which is NULL. In some cases the done signal acts as the go signal to the completion detection circuit of the next stage. The Delay-Insensitive e method.
Data not ready. So this is kept in mind while designing an asynchronous circuit. There are many ways in which a delay insensitive method can be done. In the circuit we can see that. comparing with the general model. of CSE. XH=1 XL=1 -. a component is considered to have finished its working when the introduced delay is over. OR & NOT gates are shown below. The most popular and efficient method is the duel-rail encoding method. XH=1 XL=0 -. XH=0 XL=1 -. The AND.Logical 1. Here we are assuming t he maximum time taken and this is introduced as the delay. So the input will consist of a total of four wires and t he output will consist of two wires. But this kind of implementation has a disadvantage. In bounded delay method we assume that we know the maximum time a component takes to complete its working. i. DELAY-INSENSITIVE METHOD Contrary to the bounded delay method which assumes bounds on time. Bounded delay method is quite similar to the design of synchronous circuits. This is done with the help of handshake and hand off signals. The encoding scheme is shown below: XH=0 XL=0 -.Logical 0. AH AH AL AL CH=AH*BH CH=AH+BH CL=AL+BL CL=AL*BL BH BH 0 XH Dept.Not used. In one method each signal X is encoded with two wires XH & XL. each wire in the logical circuit will now need two wires to implement a duel-rail circuit. To do this we introduce the maximum time which a circuit takes as the prototype delay. As we see from the coding above. Therefore communication between independent components is essential. Signals of both the channels together indicate the control and data signals. Thus special kind of gates would be required to implement the logics.e. the delay-insensitive method doesn’t assume any bounds on time. That is. the circuit which introduces the prototype delay acts as the completion detection circuit in bounded delay method. So it is not possible to do early completion even if the circuit doesn’t take the maximum time. BRECW 5 . So it is forced to wait until the delay is over. In this method separate channels are open for data and control signals. These signals indicate when the job of a component is over.Clockless Chip The above circuit shows the working model of a bounded delay circuit. the circuit is designed in such a way that the control will be transferred to the next circuit only when the previous component completes its work.
CH=XL & CL=XH.e. BRECW 6 . Dept. I. of CSE.Clockless Chip 1 CH 0 CL XL 1 NOT gate can be implemented simply as the only thing we need to do is to reverse the wires.
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