© Bryan J. Mealy 2011

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1 Chapter ....................................................................................................................................................... 9 1.1 Introduction.................................................................................................................................. 9 1.2 Approach and Motivation ............................................................................................................ 9 1.3 The Approach We’ll be Taking ................................................................................................... 11 1.4 Analog Things and Digital Things ............................................................................................... 12 1.5 The “Modeling” Approach to Anything and Everything ............................................................. 14 1.6 The Black Box Model in Digital Design...................................................................................... 17 1.7 Digital Design Overview ............................................................................................................. 23 1.8 The Digital Design Paradigm....................................................................................................... 24 1.9 Computer Science vs. Electrical Engineering .............................................................................. 27 1.10 One Final Comment ..................................................................................................................... 28 Chapter Summary....................................................................................................................................... 29 Chapter Exercises ....................................................................................................................................... 30 Chapter 2.1 2.2 2.3 Two .............................................................................................................................................. 31 Introduction.................................................................................................................................. 31 Number System Basics ................................................................................................................ 31 Number Systems and Binary Numbers ........................................................................................ 32 2.3.1 Common Digital Radii................................................................................................... 34 2.4 Juxtapositional Notation and Numbers ........................................................................................ 34 2.5 Digital Design .............................................................................................................................. 36 2.5.1 Defining the Problem..................................................................................................... 37 2.5.2 Describing the Solution ................................................................................................. 39 2.5.3 Implementing the Solution ............................................................................................ 42 2.6 Representing Functions................................................................................................................ 44 2.6.1 DeMorgan’s Theorems .................................................................................................. 44 2.7 Timing Diagrams ......................................................................................................................... 46 Examples .................................................................................................................................................... 51 Design Examples ........................................................................................................................................ 56 Chapter Summary....................................................................................................................................... 59 Chapter Exercises ....................................................................................................................................... 60 Design Problems ........................................................................................................................................ 63 Chapter 3.1 3.2 3.3 Three ............................................................................................................................................ 64 Introduction.................................................................................................................................. 64 More Standard Logic Gates ......................................................................................................... 64 Representing Functions................................................................................................................ 67 3.3.1 Minterm & Maxterm Representations ........................................................................... 67 3.3.2 Compact Minterm & Maxterm Function Forms ............................................................ 69 3.3.3 Reduced Form Representation: Karnaugh-Maps ........................................................... 70 3.3.4 Karnaugh-Maps and Incompletely Specified Functions ................................................ 76 3.3.5 Karnaugh-Maps and XOR/XNOR Functions ................................................................ 78 3.4 Function Form Transfer Matrix ................................................................................................... 79 Design Examples ........................................................................................................................................ 81 Chapter Summary....................................................................................................................................... 87 Chapter Exercises ....................................................................................................................................... 88 Design Problems ........................................................................................................................................ 93

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Chapter Four .............................................................................................................................................. 94 4.1 Introduction.................................................................................................................................. 94 4.2 Circuit Forms ............................................................................................................................... 94 4.2.1 The Standard Circuit Forms........................................................................................... 95 4.3 Minimum Cost Concepts ............................................................................................................. 99 4.4 Programmable Logic Devices ...................................................................................................... 100 4.4.1 Digital Design: Twenty Years Back .............................................................................. 100 4.4.2 Digital Design: The Early 1990’s .................................................................................. 101 Chapter Summary....................................................................................................................................... 107 Chapter Exercises ....................................................................................................................................... 108 Chapter Five ............................................................................................................................................... 112 5.1 Chapter Overview ........................................................................................................................ 112 5.2 Number Systems .......................................................................................................................... 112 5.2.1 Hexadecimal Number System ....................................................................................... 112 5.2.2 Octal Number System .................................................................................................... 113 5.3 Number System Conversions ....................................................................................................... 114 5.3.1 Any Radix to Decimal Conversions .............................................................................. 114 5.3.2 Decimal to Any Radix Conversion ................................................................................ 115 5.3.3 Binary ↔ Hex Conversions ........................................................................................... 118 5.3.4 Binary ↔ Octal Conversions ......................................................................................... 119 5.4 Other Useful Codes ...................................................................................................................... 120 5.4.1 Binary Coded Decimal Numbers (BCD) ....................................................................... 120 5.4.2 Unit Distance Codes (UDC) .......................................................................................... 122 5.5 Signed Binary Number Representations ...................................................................................... 123 5.5.1 Representing Signed Numbers in Binary Notation ........................................................ 123 5.5.2 Sign Magnitude Notation (SM): .................................................................................... 124 5.5.3 Diminished Radix Complement (DRC) ......................................................................... 125 5.5.4 Radix Complement (RC): .............................................................................................. 126 5.5.5 Number Ranges in SM, DRC, and RC Notations .......................................................... 128 5.6 Binary Addition and Subtraction ................................................................................................. 129 5.6.1 Binary Subtraction ......................................................................................................... 130 5.6.2 Operations on Unsigned Binary Numbers ..................................................................... 130 5.6.3 Operations on Signed Binary Numbers ......................................................................... 131 5.7 The Big Digital Design Overview ............................................................................................... 135 Design Examples ........................................................................................................................................ 137 Chapter Summary....................................................................................................................................... 142 Chapter Exercises ....................................................................................................................................... 143 Chapter Design Problems ........................................................................................................................... 147 Chapter 6.1 6.2 6.3 6.4 Six ................................................................................................................................................ 148 Chapter Overview ........................................................................................................................ 148 VDHL in Modern Digital Design ................................................................................................ 148 VHDL Introduction...................................................................................................................... 150 6.3.1 Primary Uses of VHDL ................................................................................................. 150 6.3.2 The Golden Rules of VHDL .......................................................................................... 151 VHDL Invariants ......................................................................................................................... 152 6.4.1 Case Sensitivity ............................................................................................................. 152 6.4.2 White Space ................................................................................................................... 153 6.4.3 Comments ...................................................................................................................... 153 6.4.4 Parenthesis ..................................................................................................................... 154 6.4.5 VHDL Statement Termination ...................................................................................... 154 6.4.6 Control Constructs: if, case, and loop Statements ......................................................... 154 6.4.7 Identifiers....................................................................................................................... 155

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6.4.8 Reserved Words............................................................................................................. 156 6.4.9 VHDL General Coding Style......................................................................................... 156 6.5 Basic VHDL Design Units........................................................................................................... 157 6.5.1 The Entity ...................................................................................................................... 158 6.5.2 The Architecture ............................................................................................................ 161 6.5.3 The Architecture Body .................................................................................................. 162 6.6 Simple VHDL Models: entity and architecture............................................................................ 162 Chapter Summary....................................................................................................................................... 166 Chapter Exercises ....................................................................................................................................... 167 7 Chapter Seven ............................................................................................................................................ 170 7.1 Chapter Overview ........................................................................................................................ 170 7.2 Modular Digital Design ............................................................................................................... 170 7.3 VHDL Structural Modeling ......................................................................................................... 171 7.3.1 VHDL and Programming Languages: Exploiting the Similarities ................................ 172 7.4 Structural Modeling Design Overview ........................................................................................ 173 7.5 Practical Considerations for Structural Modeling ........................................................................ 181 Chapter Summary....................................................................................................................................... 185 Chapter Exercises ....................................................................................................................................... 186 Chapter Eight ............................................................................................................................................. 189 8.1 Chapter Overview ........................................................................................................................ 189 8.2 More Introduction-Type Verbage ................................................................................................ 190 8.2 The VHDL Programming Paradigm ............................................................................................ 190 8.2.1 Concurrent Statements ................................................................................................... 191 8.2.2 The Signal Assignment Operator: “<=”......................................................................... 193 8.2.3 Concurrent Signal Assignment Statements.................................................................... 194 8.2.4 Conditional Signal Assignment ..................................................................................... 199 8.2.5 Selected Signal Assignment .......................................................................................... 201 8.2.6 The Process Statement ................................................................................................... 203 8.2.6.1 Sequential Statements...................................................................................... 205 8.2.6.2 Signal Assignment Statements ........................................................................ 205 8.2.6.3 IF Statements ................................................................................................... 206 8.2.6.4 Case Statements............................................................................................... 208 8.2.6.5 Caveats Regarding Sequential Statements ...................................................... 210 8.3 Standard Models in VHDL Architectures .................................................................................... 211 8.3.1 VHDL Dataflow Style Architecture .............................................................................. 211 8.3.2 VHDL Behavior Style Architecture .............................................................................. 212 8.3.3 Behavioral vs. Dataflow ................................................................................................ 212 8.4 Truth-table-based Decoder Implementations ............................................................................... 213 8.4.1 Selective Signal Assignment for Generic Decoders ...................................................... 213 8.4.2 Conditional Signal Assignment for Generic Decoders .................................................. 215 8.4.3 Process Statement for Generic Decoders ....................................................................... 216 8.4.4 Generic Decoders Implementations ............................................................................... 218 Chapter Summary....................................................................................................................................... 223 Chapter Exercises ....................................................................................................................................... 226 Chapter Nine .............................................................................................................................................. 229 9.1 Chapter Overview ........................................................................................................................ 229 9.2 Design Techniques ....................................................................................................................... 229 9.3 Standard Digital Modules ............................................................................................................ 230 9.3.1 Multiplexors .................................................................................................................. 230 9.3.2 Comparators .................................................................................................................. 236

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9.3.3 Comparators via VHDL Modeling ................................................................................ 239 9.4 Digital Design Oddities................................................................................................................ 242 9.5 Modular-Based Digital Design .................................................................................................... 244 Design Examples ........................................................................................................................................ 245 Chapter Summary....................................................................................................................................... 257 Chapter Problems ....................................................................................................................................... 258 Design Problems ........................................................................................................................................ 259 10 Chapter Ten ................................................................................................................................................ 261 10.1 Chapter Overview ........................................................................................................................ 261 10.2 Real Digital Devices .................................................................................................................... 261 10.3 Timing Diagrams Again .............................................................................................................. 262 10.4 Gate Delays and Gate Delay Modeling ........................................................................................ 262 10.4.1 Timing Diagram Annotation.......................................................................................... 264 10.4.2 The Simulation Process ................................................................................................. 265 10.5 Glitches in Digital Circuits .......................................................................................................... 266 10.5.1 Static Logic Hazards...................................................................................................... 266 Chapter Summary....................................................................................................................................... 271 Chapter Exercises ....................................................................................................................................... 272 Chapter Eleven ........................................................................................................................................... 276 11.1 Chapter Overview ........................................................................................................................ 276 11.2 Standard Decoders ....................................................................................................................... 276 11.3 Parity Generators and Checkers ................................................................................................... 284 11.4 Map Entered Variables ................................................................................................................ 288 11.4.1 Karnaugh Map Compression ......................................................................................... 290 11.5 Implementing Functions Using MUXes ...................................................................................... 293 Chapter Summary....................................................................................................................................... 296 Chapter Exercises ....................................................................................................................................... 297 Chapter Design Problems ........................................................................................................................... 302 Chapter 12 .................................................................................................................................................. 304 12.1 Chapter Overview ........................................................................................................................ 304 12.2 Mixed Logic................................................................................................................................. 304 12.2.1 Mixed Logic Basics ....................................................................................................... 305 Chapter Summary....................................................................................................................................... 319 Design Examples ........................................................................................................................................ 320 Chapter Exercises ....................................................................................................................................... 322 Design Problems ........................................................................................................................................ 324 Chapter Thirteen......................................................................................................................................... 326 13.1 Chapter Overview ........................................................................................................................ 326 13.2 Sequential vs. Combinatorial Circuit ........................................................................................... 327 13.3 Sequential Circuit: The Whole Story ........................................................................................... 328 13.3.1 The NOR Latch ............................................................................................................. 334 13.3.2 State Diagrams............................................................................................................... 334 13.3.3 PS/NS Tables ................................................................................................................. 336 13.3.4 Excitation Tables ........................................................................................................... 336 13.3.5 The NAND Latch .......................................................................................................... 337 13.3.6 NOR and NAND Latch Summary ................................................................................. 338 13.4 Gated Latches .............................................................................................................................. 340 13.5 Flip-flops...................................................................................................................................... 342 4

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13.5.1 The D Flip-Flop ............................................................................................................. 343 13.5.2 The T Flip-Flop ............................................................................................................. 344 13.5.3 The JK Flip-Flop ........................................................................................................... 345 13.5.4 The Big D, T, and JK Flip-Flop Summary .................................................................... 347 13.6 VHDL Models for Basic Sequential Circuits............................................................................... 347 13.6.1 Simple Storage Elements Using VHDL ........................................................................ 348 13.6.2 Synchronous and Asynchronous Flip-Flop Inputs ......................................................... 350 13.6.3 Flip-flops with Multiple Control Inputs......................................................................... 354 13.6.4 Inducing Memory: Dataflow vs. Behavior Modeling .................................................... 357 Chapter Overview ...................................................................................................................................... 359 Chapter Exercises ....................................................................................................................................... 360 Design Problems ........................................................................................................................................ 366 14 Chapter Fourteen ........................................................................................................................................ 368 14.1 Chapter Overview ........................................................................................................................ 368 14.2 Finite State Machines (FSMs)...................................................................................................... 368 14.3 High-Level Modeling of Finite State Machines........................................................................... 369 14.4 FSM Analysis .............................................................................................................................. 372 14.5 FSM Design ................................................................................................................................. 383 14.6 Timing Diagrams: Mealy vs. Moore FSM ................................................................................... 395 14.6.1 Timing Diagrams and State Diagrams ........................................................................... 396 14.7 FSM Illegal State Recovery ......................................................................................................... 404 14.8 Modeling Counters with VHDL .................................................................................................. 407 Chapter Summary....................................................................................................................................... 411 Chapter Exercises ....................................................................................................................................... 412 Chapter Fifteen ........................................................................................................................................... 425 15.1 Chapter Overview ........................................................................................................................ 425 15.2 Engineering Notation ................................................................................................................... 425 15.3 Clocking Waveforms ................................................................................................................... 427 15.3.1 The Period ..................................................................................................................... 427 15.3.2 The Frequency ............................................................................................................... 428 15.3.3 Periodic with Attributes ................................................................................................. 429 15.4 Practical Flip-Flop Clocking ........................................................................................................ 430 15.5 Maximum Clock Frequencies of FSMs ....................................................................................... 431 Chapter Summary....................................................................................................................................... 434 Chapter Drill Problems .............................................................................................................................. 435 Chapter Sixteen .......................................................................................................................................... 439 16.1 Chapter Overview ........................................................................................................................ 439 16.2 FSMs Using VHDL Behavioral Modeling .................................................................................. 439 16.3 VHDL Topics: One-Hot Encoding in FSM Behavioral Modeling .............................................. 451 16.4 Shift Registers .............................................................................................................................. 453 16.5 Universal Shift Registers ............................................................................................................. 457 Chapter Summary....................................................................................................................................... 462 Chapter Seventeen ...................................................................................................................................... 469 17.1 Chapter Overview ........................................................................................................................ 469 17.2 The Big FSM Picture ................................................................................................................... 469 17.3 The FSM: An Intuitive Over-Review .......................................................................................... 471 17.3.1 The State Bubble ........................................................................................................... 472 17.3.2 The State Diagram ......................................................................................................... 473 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17.3.3 Conditions Controlling State Transitions ...................................................................... 474 17.3.4 External Outputs from the FSM .................................................................................... 475 17.3.5 The Final State Diagram Summary ............................................................................... 478 17.4 Sequence Detectors Using FSMs ................................................................................................. 480 17.4.1 Sequence Detector Post-Mortem ................................................................................... 484 17.5 Timing Diagrams: The Mealy and Moore-type Output Story ...................................................... 484 17.6 FSM Design Examples ................................................................................................................ 486 Chapter Summary....................................................................................................................................... 508 Design Problems ........................................................................................................................................ 509 18 Chapter Eighteen ....................................................................................................................................... 515 18.1 Chapter Overview ........................................................................................................................ 515 18.2 FSM Modeling using New Techniques........................................................................................ 515 18.2.1 Motivation for the New FSM Techniques ..................................................................... 516 18.2.2 New Technique Motivation: D Flip-flops ..................................................................... 517 18.2.3 New Technique Motivation: T Flip-flops ...................................................................... 518 18.2.4 New Technique Motivation: JK Flip-flops .................................................................... 519 18.2.5 The Clark Method for the New FSM Techniques ......................................................... 521 18.3 State Variable Encoding .............................................................................................................. 525 18.3.1 Binary and One-Hot Encoding of State Variables ......................................................... 525 Chapter Summary....................................................................................................................................... 532 Chapter Exercises ....................................................................................................................................... 533 Appendix .................................................................................................................................................... 538 Appendix A: ............................................................................................................................................... 539 Appendix B: ............................................................................................................................................... 540 B.1 Logical Operators .......................................................................................................... 540 B.2 Relational Operators ...................................................................................................... 540 B.3 Shift Operators............................................................................................................... 541 B.4 All the other Operators .................................................................................................. 541 B.5 The Concatenation Operator .......................................................................................... 542 B.6 The Modulus and Remainder Operators ........................................................................ 542 Appendix C: ............................................................................................................................................... 544 Appendix D: ............................................................................................................................................... 545 D.1 Types of Data Objects ................................................................................................... 545 D.2 Data Object Declarations ............................................................................................... 545 D.3 Variables and the Assignment Operator “:=” ................................................................ 546 D.4 Signals vs. Variables...................................................................................................... 546 D.5 Data Types ..................................................................................................................... 547 D.6 Commonly Used Types ................................................................................................. 547 D.7 Integer Types ................................................................................................................. 547 D.8 The std_logic Type ........................................................................................................ 548 Appendix E: ............................................................................................................................................... 551 E.1 for and while Loops ....................................................................................................... 551 E.1.1 for Loops ......................................................................................................... 552 E.1.2 while Loops ..................................................................................................... 553 E.2 Loop Control: next and exit Statements ........................................................................ 553 E.2.1 The next Statement .......................................................................................... 553 E.2.2 The exit Statement ........................................................................................... 554 Appendix F:................................................................................................................................................ 555 F.1 RET D Flip-flop (Behavioral Model) ............................................................................ 555 F.2 FET D Flip-flop w/ Active-low Asynchronous Preset (Behavioral Model) ........................................................................................................................... 556 F.3 8-Bit Register with Load Enable (Behavioral Model) ................................................... 556

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Synchronous Up/Down Counter (Behavioral Model) ................................................... 557 Shift Register with Synchronous Parallel Load (Behavioral Model)............................. 557 8-Bit Comparator (Behavioral Model) .......................................................................... 558 BCD to 7-Segment Decoder (Dataflow Model) ............................................................ 558 4:1 Multiplexor (Behavioral Model).............................................................................. 559 4:1 Multiplexer (Dataflow Model) ................................................................................ 559 3:8 Standard Decoder .................................................................................................... 560

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1 Chapter

1.1

Introduction

We’re at the point where for some reason you’ve opted to read this text. This is the point in most texts where high-level motivating words of motivation are offered; and so here they go… the first step in doing the digital design thing is to get some lingo and basic design approaches out of way. As with everything, digital design is probably easier than you may think. This chapter starts with defining what is digital and what is design. You won’t be doing any digital design in this chapter, but you’ll learn about “digital” and will be doing some real design. The approach taken to learning “design” is substantial in that it can be applied to designing anything including bowling paraphernalia.

**Main Chapter Topics
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APPROACH AND MOTIVATION: This text takes a different approach than the historical approach to digital design. This chapter describes the major differences between the historical approach to digital design and the approach taken in this text. DIGITAL DESIGN OVERVIEW: The basic digital design problem is straight-forward. This chapter establishes the “model” of digital design that is used throughout this text. ”MODELING” AS A DESIGN TOOL: The concept of modeling is introduced as the most basic tool for understanding just about anything, particularly digital design. DIGITAL DESIGN PARADIGM: The modern approach to digital design is well structured. This chapter describes hierarchical design and its relation to digital design described in this text. ANALOG AND DIGITAL: Understanding digital design requires an understanding of the inherent differences between “analog” and “digital”. This chapter outlines these differences.

(Bryan Mealy 2011 ©)

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Approach and Motivation

It was truly a different world when I was first introduced to digital logic (sometime in the mid-1800s). At that time, my digital design world revolved around the knowledge and topics presented in the course text. Back in those days, there was no laboratory associated with the digital design course. Because of this lack of academic sponsored hands-on experience, and the fact that the digital hardware involved was somewhat crude and the test/development equipment was priced massively out of reach, I could count on nothing more than the course text to gather my digital knowledge (the instructor didn’t know much about digital design either). Computers were expensive and not commonly available to students, there was no internet, and software used to aid the digital designer either did not exist or was once again too expensive to be practical for the average digital design student. In other words, both the knowledge and equipment associated with actual digital design was well outside the realm of the average students. As a consequence of all of these factors, the digital design courses were severely limited and centered primarily upon what was presented in the course text (which, even to this day, still suck badly). As a further consequence of this, the instructors associated with the digital design course simply presented whatever was present in the

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Digital McLogic Design

Chapter 1

text. Any “designs” that were actually done were merely “paper designs1”. You could argue that this approach worked fine way back then; but it simply does not work today (though the illusion of it working still exists at fine institutions such as Stanford). Despite the fact that digital technology has advanced significantly in the recent past, the course texts associated with introductory digital design have remained in the dark ages of both engineering and educational technology. And despite these drawbacks, we’ve seen nothing but a steady increase in the price of introductory digital design textbooks accompanied by a steady decline in their quality2. As digital technology progressed (more computers, more hardware, more software, and more knowledge sources), more resources became available to both digital design instructors and students. These technological advances made both the purpose and content of digital design textbooks somewhat less absolutely defined. Although the ultimate goal of transferring knowledge from the text to the student has remained the same, it is not exactly clear what knowledge is important and thus should be included in the text. What I do know is that the average digital design textbook contains way too much detail and thus can do no better than present the material in a manner that is sure to put even a die-hard caffeine junky into immediate slumber. The problem with the typical introductory digital design text is that it is written from a standpoint of presenting digital concepts in a manner that supports asking questions on exams that have nothing to do with actual design. In other words, there are lots of topics to test you on but not too much actual design going on. Let’s face it folks: actual design problems are harder to grade and are thus rarely found on exams. The current approach to digital design is outdated; it was fine when there were no computers or software available. With all this, it’s a real mystery why the price of digital design textbooks has been rising3. The goal of this text is to present digital design in such a way as to gradually take the reader to the land of digital design pretenders and make the reader into actual digital designers. The theme of this textbook is to travel lightly so that you can travel farther and faster. Topics that don’t represent major steps toward the ultimate goal of becoming a viable digital designer are not covered or are covered only briefly. Not covering many of the less useful digital-like topics saves valuable time which is then dedicated to generating true digital design skills4. I freely and openly acknowledge that advanced digital designers or instructors who read this text may feel that some topics and/or standard approaches to topics have been left out of this text. But once again, the goal of this text was to eject some of the less useful topics in favor of learning true digital design. With the knowledge contained in this text, you can easily pick up a standard digital design textbook and gather in all the full details without a lot of extra effort. One of the many nice things about digital design is that the basics do not change much through the years. That means that textbooks from twenty years ago contain many of the fine details of digital design. And because publishers typically generate new versions of these textbooks in an effort to keep instructors from using used books (which are significantly cheaper than new books5), there are plenty of excellent older textbooks are available from used book websites6. The prices are generally excellent7, especially based on the amount of valuable and interesting information they provide. You should strongly consider purchasing a few of these textbooks and using

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A paper design was something you tried hard to convince someone else that it actually would work if it were actually implemented. The person you were trying to convince was often your instructor. 2 The digital design texts published by professors at Cal Poly are known for their innate crappiness. 3 The truth is that some digital design texts written by Cal Poly instructors are so crappy, the authors should be paying you to pretend like you’re using them. 4 I have proven this many times by asking some of the brightest intermediate and advanced digital design students about some of the topics typically taught in CPE 129. Although these students were currently well on their way to becoming great digital designers, they had completely forgotten the extraneous material presented in the typical introductory digital design course. Why? Because they never had a need to use these concepts anywhere other than a quiz or exam in their introductory course. Bummer! 5 This is not true at El Corral; their monopoly is so strong that used books generally cost more than new books. I could not write this if it were not true. 6 Check out your local library, www.half.com, or www.addall.com for availability and/or pricing of these books. Many websites also include reviews of these books in order to help you narrow your selection. 7 Seriously, a two-inch thick textbook for under $5!

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The process of designing. The other form of digital design was working for a company that designed those ICs. also known as “chips”. The question naturally arises that if you can’t really define the term. then how are you going to teach it? The answer to this question is that we have decided that one approach is viable (and maybe even good.Digital McLogic Design Chapter 1 them in conjunction with the one you’re currently pretending to read. having students hand-wire circuits is a waste of time that could be better spent delving deeper into true digital design topics and wanking around with your cell phone things. and relatively inexpensive circuit development boards. These are those black rectangles with silver feet appearing on printed circuit boards. the term “modern digital design” is tough to define. With the use of an HDL. Both of these forms of design were primarily paper-driven: the circuit was designed on paper (by hand) and then transferred (primarily by hand) to either a printed circuit board (PCB) or to the integrated circuit form. most digital designs comprised of some sort of paper design which would eventually be somehow magically made into a circuit. 9 8 11 . a digital circuit can be modeled9 relatively quickly. no company plans on paying an engineer to hand-wire circuits grunt work such as that was outsourced to off-shore child prison labor many years ago. Our approach is to start with basic digital fundamentals and quickly apply those fundamentals in an actual design. In the end. The use of the word “model” is extremely important in digital design (and all engineering fields for that matter). digital design could either be classified as board-level design or integrated circuit design. simulating. Keeping in mind that the ultimate goal is to teach digital design. it’s either not covered or covered only lightly. Thirty years ago. the same model can be used to actually implement the circuit on a device such as a PLD. If all is well. The availability of inexpensive computers drove the revolution of modern digital design. our approach is relatively straightforward: we maintain our focus on material that going to help you develop and improve your digital design skills while paying less attention to the out-of-date topics covered in other digital design texts.3 The Approach We’ll be Taking Generating a concise definition for “modern digital design” is somewhat tough due to the recent advances in digital technology. implementing. and testing the implementation was tedious and time consuming and therefore not overly feasible in the short span of an introductory digital design course. you’ll find that most of the book is filled with interesting stuff but not too much of it is going to help you become a better digital designer. computer aided design (CAD) tools (no need to settle for only paper designs). The primary tool in modern digital design is the use of a Hardware Description Language (HDL). some of the early methods were quite crude by today’s standard. the HDL model can also be used to simulate the operation of the circuit. The ICs used in this form of design contained pre-designed digital circuits of varying levels of complexity. Board level design comprised of buying off-the-shelf integrated circuits (ICs8) and assembling them in such a way as to generate a meaningful result. We’ll use the term model extensively throughout this text. Be forewarned that if you actually peruse a standard digital design book. In other words. Use of HDLs creates unique learning opportunities for today’s digital design students. The technology used to design those circuits changed considerably over the years. The days of hand-wiring circuits are over. As an added bonus. but don’t get your hopes up) and we will follow that approach throughout this text. The mechanism that allows us to directly apply these digital concepts in an actual design is VHDL (Very High Speed Integrated Circuit Hardware Description Language) and PLDs (programmable logic devices). As a result of all this new technology. and the growing complexity of off-the-shelf digital ICs has made modern digital design arguably the most dynamic field in the area of electrical engineering. The advent of the internet (free information and free crap). A model is nothing more than a description of something (such as a digital circuit) in terms that highlights the important and relevant information while hiding some of less useful information. if a concept isn’t directly applicable to a digital design. Before the advent of HDLs. 1.

4 Analog Things and Digital Things After talking about “digital” for the last few pages. which is not necessarily good. Unfortunately. it’s now time to provide some type of definition for it. not programming a computer12. VHDL is an amazing and powerful tool. The on/off nature is a hallmark of digital in general while the infinite number of intensity levels is typically associated with analog. The most important concept you can grasp now is that VHDL is not a programming language: it is a hardware description language. you’ll be sure to appreciate VHDL because modeling digital circuits with VHDL is not programming! Once again. Worst of all. Did you know the flunk rate in CSC 101 hovers around 50%? It must be the student’s fault! 12 There is a huge difference (but subtle similarities). So what is the better approach?13 Example 2: Many buildings around campus have both wheelchair ramps and stairs leading to the buildings. If you’re one of those people who have a fear of programming11. we now have many discrete levels (one for each of the stairs). they provide both light and a significant amount of heat). in the context of engineering. many students do fear programming. The stairs. if you’re using VHDL. In other words. They also generate electromagnetic fields that are more likely than not hazardous to your health. Later chapters present more details regarding VHDL and the hardware description language paradigm. they are a primary food source for student eating robots. it’s not just another throwaway syntactical language you must learn in order to obtain your engineering degree. While both options lead you to your ultimate destination. Being able to model digital circuits and simulate them using VHDL is a valuable and marketable skill. The discreteness of things is the hallmark of digital while the continuousness of things is the hallmark of analog. is how to characterize an escalator? The answer: Digalog. they do so in distinctly different way. continuous (for the ramp). we’ll be going over the details in a later chapter. 13 Rhetorical question! What we’re really interested in is the intensity level characteristics of these two types of lights. this text opts to use VHDL. The two major HDLs in use today are VHDL and Verilog. But I’ve arrived at a dilemma: while the CF lights generally use less power. you’re modeling digital circuits. the CF light is either all the way on. These discrete levels are the hallmark of digital things. on the other hand. 11 10 12 . Example 1: In an effort to save the planet and do the sustainability thing. I’ve been installing compact fluorescent (CF) lights and dimmers for my incandescent lights in my house. The thing to note now is that VHDL is your friend. I do have the ability to save energy by using the dimmer to adjust the lights to the intensity level that I require at any given moment. Generally speaking. It’s actually a giant scam anyways… CF lights are hazardous waste once they burn out (due to their mercury content). The introduction you obtain in this text provides you with the foundation necessary to become a top-notch digital designer.Digital McLogic Design Chapter 1 This text uses VHDL as for modeling digital circuits10. In other words. Never lose sight of this fact. the intensity of light they provide is not adjustable. the concept of “digital” is best understood when it is presented along side the definition of “analog”. This example differs from the previous example in the instead of having two discrete levels for the CF bulb (on and off). 1. which is of course understandable based on their horrible experiences by taking computer programming courses from “computer scientists” and not actual engineers. only have a few discrete levels I can stop at which each of these levels being the individual stairs. while incandescent lights require more energy to operate (that is. What’s really bugging me. though. They burn out more quickly than stated due to their lack of ability to dissipate heat if not optimally positioned. The big difference here is discrete (for the stairs) vs. This means that I can hypothetically stop at any one of an infinite number of levels from along this path on my way to the building. The wheelchair ramp can be considered a continuous path the building. Here are a few quick examples. or all the way off. I am hypothetically able to adjust the dimmer to provide an infinite number of intensity levels (but only one intensity level at a time). But then again.

17 And protecting yourself from robots. The importance of the analog vs. A digital logic circuit is an electronic circuit that provides you with some desired result and is implemented using digital logic devices. the guitar provides a discrete set of pitches it can play while the violin provides a continuous number of pitches. digital is generally thought of as the describing something in the continuous domain vs. Some budding digital designers are scared off by the notion of “voltage” so we generally discuss digital design at a level of abstraction that enables us to ignore the reality that “voltage” is the lifeforce of digital circuits. we primarily model the inputs and outputs of our digital circuit using 1’s and 0’s. For the problem of the lights. BLACK-WHITE. Although there are many ways to implement a functional electronic circuit. there are many analog portions of a computer such as the power supply. understanding digital design is the unstated first step in communicating with computers. REPUBLICAN-DEMOCRAT. The frets only allow the string to vibrate at a set of discrete string lengths (generally 19-22 on a typical guitar)14. once we get closer to performing actual design. you’re probably wondering how this all relates to digital design. the incandescent light that is controlled by a dimmer can effectively provide anyone of a number of a virtually endless set of light intensities dependent upon the position of the dimmer control. has no frets. fretless bass guitars) you change the pitch of the vibrating string by placing your fingers at different positions on the fingerboard. 15 14 13 . So long as you choose to live in this world. As you’ll see later. but these are really boring when compared to the digital parts. In other words. The concept of analog vs. The starting point for this journey is learning digital design17. digital. With each passing day. GOOD-BAD. realm. the basis of all digital logic is the use of circuit elements whose inputs and outputs can only be one of two values. etc. bass guitars) and violins (or violas. digital concept relates directly to digital logic design. Since there are no in-between options for the CF light. on the other hand. the discrete domain. The difference between these instruments is that guitars have frets on the neck while violins do not. The continuous realm of the incandescent light are then considered analog because of their continuous nature while the CF lights are considered digital because they only operate at discrete values. the approach taken in this course is to implement circuits using digital logic. EECSC. 16 The fun parts of a computer are digital. Stringed instruments created sound by way of a vibrating string which vibrates between two fixed points. “low” forming the digitalness of this approach. CAT-DOG. the CF lights provide only a finite set of options. or digital. we’re still all living in an analog world. As you’ll see later. On the other hand. HIGH-LOW. So why do I want to design digital circuits in order to solve my problems? The last time I looked. On instruments such as guitars (or mandolins.Digital McLogic Design Chapter 1 Example 3: This is an example for the musically inclined out there. the world we purportedly live in becomes more and more controlled by digital devices. This range of intensities is considered continuous over the basic ON (full light) or OFF (no light) settings of the dimmer. it’s best that you understand digital devices and work with these devices at something other than a user level. TRUE-FALSE. While the incandescent lights effectively can provide an infinite range of light intensities. We’re of course not considering using your fingers to stretch the string (which changes the frequency of the note). Since a computer is nothing more than a giant digital circuit16. respectively. Despite these wildly interesting examples. so you can effectively play an infinite number of pitches on a given string. the CF light is only capable of providing two light intensities: ON or OFF. The actual digital circuits themselves are driven by either “high voltage” or “low voltage” but we generally choose to model our circuits using more general terms with the “high” vs. cellos. ADMINISTATOR-TEACHER. Understanding digital design is also the first step towards designing computers. So how does this relate to digital logic design? Because the characteristics of these examples nicely describe the concept of analog vs. the set of options is represented by two discrete values: ON and OFF. which are nothing more than generic placeholders for the actual high and low voltage values15. The violin. These two values can be modeled as OFF-ON. The problem we face is that the ubiquitous computer is only capable of operating in the discrete.

The concept of model should be nothing new to you. 2. 1): a representation of something. the word “model” and “modeling” has already been used many times in this short chapter. model (def. 3. Listed below are a couple of examples that may give you an idea of what you’re missing. So. In this case. Each of the two definitions contains a varying amount of wording. with comments sure to follow. but in the absolute sense. 1. no one model is better than another. And if you have created a good model. The different models can provide varying amounts and levels of information. you may be asking yourself something like: “Why should I care?” The reason you should care is that models in digital design have only one general purpose: models transfer information to the entity reading the model. we can apply software that will use this model to automatically generate a working circuit on a programmable logic device. anything that presents information by representing or describing something can therefore be considered a model. then your model will promote an understanding of the thing being modeled. There is no one “correct” model for anything. these two definitions provide two different levels of detail regarding the definition of a model. These people 14 . 2): a description of something in terms that highlights the relevant information while hiding some of less useful information.Digital McLogic Design Chapter 1 1. your teacher. or your pet raccoon. there are many subtleties that are worth mentioning regarding these definitions. This implies that there can be many different “valid” models of the same thing. the entity in question could be a piece of software. out there in the real world. and thus detail. In other words. Although these definitions seem simple. 1. This implies that there is no one correct form of a model. The idea of differing levels of detail is extremely important in the notion of modeling. Generally speaking. there are endless things out there are representing something without really being something (and some of these things actually transfer information to you). If we model our digital circuits correctly using a useful description (such as VHDL). your lab partner. what exactly is a model? I could look up the term in the dictionary. If you think about. This is because most everything we do in digital design (and engineering in general) is a matter of generating the correct model for a digital circuit. The other implication here is that some models are more “useful” than others. Example 1: Runway Models – We’ve all seen them: emaciated men and women wearing bizarre clothing and sporting unique hairstyles strutting down the runway. The model is used to represent or describe something. Listed below are my two best definitions of the word. What the definitions do not state is the exact nature of how the model is represented. so I used two. The truth is that the use of models is so useful that we somewhat forget that we’re actually using or relying on them. These are the most useful definitions that I can think of. I could not clearly define the word with one definition.5 The “Modeling” Approach to Anything and Everything In case you haven’t noticed. model (def. but that may not give me a digital design flavor of the word. So now that we’ve defined the crap out of the poor word.

2. they’re nothing more than models of the items. etc. or it’s not useful because its inherent description is provided in such a way as to effectively provide you with nothing useful. the device interacts with the model to make something meaningful happen when the button is actuated. Guns in real life are actually much louder and smell funny when you fire them. Unfortunately. 15 . but the entire genre is a model of real and/or imaginary life. Keep in mind as you read these model types that there is no one correct model of a given thing. but probabilistically speaking. The concept of models in digital design comes in two different broad flavors: Design a digital circuit: Unless you start grabbing transistors in order to create some actually digital devices. you are generally expected to come up with your own “model” of a digital circuit that performs some specific task. so you need to understand it before you are able to successfully use it. We’ll start using these special digital models in a later chapter. Everything you see in the game is a model of something you can relate to in real life. The main model types used in digital design are listed below18. Remember. Example 5: Video Games – Not that I play video games. digital design only generally uses a few types of models. use it in your digital design: In this case. But all is not lost. Here’s a model of something. we sometimes are disappointed when a more accurate description of our role models appears in the news and/or the police blotter. There’s not really a button there though there is a health dose of button-on-button action. 18 Not listed here are Finite State Machine state diagrams. sliders. Either the model is useful because it helps you design or understand something. There is nothing to stop the storm from drastically changing its path and not having rain the next week. you’ll probably be using models while you’re in the act of “digital designing”. they’re handing you a description of something. In this case. These items are not really what they’re trying to mimic. While we do know some features about these models (probably the good features which is why they are role models). Example 3: The Weather Report (weather prediction) – So how is it we know that it’s going rain next week? The satellite images indicate there is a storm somewhere. Some pixels on a display are used to model a button. elevator bars. Example 4: Graphical User Interfaces (GUIs) – Practically every computer-type device uses some type of GUI. These GUIs generally contain graphical representations of items such as button.Digital McLogic Design Chapter 1 are some designer’s representation of actual women and men. switches. but it’s truly far from being real life. but the fact that it is predicted to bring rain a week in advance is interesting. someone is going to give you some models and expect you to understand them to the point that you can use them in your digital design. Example 2: Role Models – These are generally people that are expected to be looked up to. Digital design uses modeling to aid in the understanding and/or the design of digital circuits. we’ll probably get rain. The prediction is based on models of previous weather patterns. we do not have the full description. And imagine for a second if your video game modeled nothing in real life? Can your brain actually imagine something that is has no concept of? 3. 5. 4. These are actually really bad models (literally) because they don’t represent anything other than an attempt to make people feel inadequate about the bodies so that they’ll consume more crap.

(b). if there is not an accompanying black box model with the written description. Figure 1. VHDL is a hardware description language. not a programming language. Sometimes black boxes are used with appropriate describing labels as a substitute for these symbols. The timing diagram: Timing diagrams graphically describe the operational characteristics of a digital circuit based on the status of inputs and outputs plotted as a function of time. you should be able to generate one based on the written description. There many special symbols that are used to model certain digital devices. We’ll start dealing with this more in later chapters. We’ll cover black box designs as they relate to digital design in the next section. 16 . Figure 1. Note that when the circuit element model is used. The digital circuit element model: These are actually nothing more than special black box models and should not be listed as a different type.3(a) shows a VHDL model of a circuit.2 shows an example of a timing diagram for some unspecified digital circuit. • • • • (a) (b) Figure 1. The black box model is simply box that graphically shows the inputs and outputs to the digital circuit.Digital McLogic Design Chapter 1 • The black box model: This is probably the most used and useful model in digital design. When these symbols are used. The VHDL model: VHDL provides a language of its own to describe the operation of digital circuits. We’ll deal with timing diagrams in a later chapter.1: An example of a black box model (a). The written description model: A model of a digital design or component is something nothing more than a written description. and a digital circuit element model with its corresponding black box model.1(b) shows an example of a digital circuit element model and its corresponding black box model.3(b) shows a written description of a digital circuit. Figure 1.1(a) shows an example of a black box model used in digital design (don’t worry about the details now). there is no need to label the corresponding black box model. Figure 1. In this case. Although VHDL has special syntax and constructs typically associated with computer programming languages. Figure 1. everyone knows what they mean.

end process. and thus.Digital McLogic Design Chapter 1 Figure 1.CLK) begin if (R = '0') then Q <= '0'. but those approaches would be more attractive if they used a few fun features of black box models. when S is asserted. Incidentally. we’ll show some of the basics of modeling as it relates to digital design. The R input takes precedence over the S input. nQ : out std_logic).2: An example of a timing diagram (don't worry about the details). Unlike modeling techniques such as VHDL. In the following discussion. When R is asserted (negative logic). 1. Q. Two inputs. The circuit has four inputs and two outputs.R : in std_logic. The last general comment regarding these model types is that you should be able to generate all of these types of models for any circuit that you design. CLK : in std_logic. you should not forget the overall purpose of using a model: models are quick ways to transfer information. nQ <= not D.3: An example of a VHDL model (a). and 2) fully document your design. Keep in mind that if you’re primarily modeling something other than digital circuits. your job as a digital designer is two fold: 1) design a digital circuit. (a) (b) Figure 1. architecture dff of dff is begin process(D. This being the case. entity dff is port (D. black box modeling has no syntax or rules that you must adhere to. particularly digital circuits. R and S. these two models described the same digital circuit. The outputs are always complements of each other. nQ <= '1'. end dff.6 The Black Box Model in Digital Design The black box model is extremely useful in designing anything. Models are your friends and they’re going to help you in every aspect of your digital design career. end dff. end if. the output is ‘1’. the Q output is ‘0’. the more quickly you can glean information from it. nQ <= '0'.S.S. There are approaches to designing digital circuits that typically don’t use black box models. The clearer the information being represented by the model. you may take a different approach to 17 . are asynchronous negative logic inputs. The Q output follows the D output on the active clock edge (rising-edge triggered). Generally speaking. elsif (S = '0') then Q <= '1'. the more model is more effective. elsif (rising_edge(CLK)) then Q <= D.R. and a written description of a digital circuit (b).

inputs are placed on the left side of the box while outputs are placed on the left side of the box.4 shows a few examples of a black box models. But here are a few strong guidelines you should attempt to adhere to: • • • • The “flow” of digital models generally goes from left to right. Because the box is dark.4 represent the first step in black box modeling. circles are used elsewhere in digital design. be creative and generate good models.4. Put arrowheads on you signals if it’s not completely obvious what is an input and what is an output (and it usually isn’t). In digital design. In other words. 20 19 18 . the word “black” in black box is meant figuratively and not literally. And. respectively. (a) (b) Figure 1. by all means. Note that in each of the models in Figure 1. Place labels on boxes if the reason for the box’s existence is not patently obvious (and it usually isn’t). Figure 1. Thus.4: A few examples of basic black box models. if you have a better idea for models. Use any shape except circles. there is no light shed on the interior of the box. use these ideas when you’re creating your models. Inputs and outputs represent digital signals going into and out of the circuit. Figure 1. the black box has a label. All signals should generally be labeled unless there is some compelling reason not to (and there usually isn’t). One of the hallmarks of any type of design is the ability to abstract the design across many levels. And in case you have not figured it out yet.4(a) shows the basic black box model with inputs and outputs listed on the left and right sides. a high-level model of something may not be that useful to use if we were hoping for a low-level model (and vice versa). Black box models are generally used to represent this hierarchy by essentially having a set of black box models for a given design. Keep in mind here that the goal is to transfer information: so strive to make your hierarchical models clear and concise21.Digital McLogic Design Chapter 1 creating models.4(c) is another equivalent model that uses “self-commenting” signal names to differentiate the circuit’s I/O. The models shown in Figure 1. I’m thinking about using the term “dark box modeling” instead of black box modeling.4(b) shows an equivalent model with the inputs and outputs (I/O) indicated with the use of arrowheads on the signal lines. Let’s take one more step and then you’re on your own. For our particular purpose. These different levels of a model make up a hierarchy of a particular design with each level offering a different type and/or amount of information from other levels. the box is considered black because we don’t really know what’s inside of it20. Figure 1. What I’m trying to say here is that I have no hard rules for you to follow when you make your black box diagrams. All the prizes go to the best models. respectively. The digital circuit itself is represented by a box19 and the inputs and outputs are represented by lines going into and out of the box. Figure 1. huh! 21 This notion will be much clearer in later chapters when you’re actually using more meaningful black box models. (c) This is tough to write about because there are really no hard rules for black box diagrams. therefore. we’re most concerned about the inputs to and the outputs from a digital circuit. Somewhat poetic.

19 .6. It just so happens that these two models are used in a larger model shown in Figure 1.6(b) is somewhat similar to the model shown in Figure 1.5 shows an example containing two black box models.5.6(a) since interior connections are not listed.6(b) seems to contain less information than the box in Figure 1. Without being too judgmental. • • • Figure 1. The model in Figure 1. You can use this fact to extrapolate which are the inputs and outputs for most of the signal in the higherlevel model.6(a).5: Two example black box models. The model in Figure 1.Digital McLogic Design Chapter 1 I encourage you to make up your own rules.5). The two models in Figure 1. • From Figure 1. it is not known precisely which signals are inputs and outputs by the way the model is drawn. A black box named Z_BOX appears on the lower level and was not previously defined. but they are worth looking at. (a) (b) Figure 1.6(a) shows a black box diagram that sports a two-level hierarchy. The interior black box diagram at the lower level is true to what is shown in Figure 1.6(a). The I/O characteristics of the Z_BOX remain a mystery. Figure 1. Figure 1. Figure 1. the lower level contains four previously defined models (these are the models shown in Figure 1. your models are judged by how well they transfer information between entities. the higher-level model does not contain arrowheads on the signal nor do the signals contain self-commenting names.6 may not be the best models ever devised. with a big difference as pointed out below. The upper-level is the MY_BIG_BOX model. Here are a few examples to both drive home the black box modeling approach as a general approach to understanding things. Have fun.6: Two examples of black box diagrams with similar features but varying levels of detail. what’s in this box is therefore a total mystery and we’ll hope it’s defined elsewhere (which it’s not). Specifically.6 are almost identical. This is actually the same example presented in three different flavors. Whatever you do.

You know the water heater heats water (duh!). But then again. especially considering you may know nothing about hot water heaters. look again at the problem description. Figure 1. Note that when this problem asks for subsystems. we can thus declare ourselves done with this problem. The problem is expecting you to simply do something. The first step in all design problems should be to draw a box and place a somewhat meaningful label on it. (a) (b) (c) Figure 1.7: A possible thought process for this example. The point here is that you started with nothing and you ended up with a reasonably helpful model. This is not necessarily a bad thing. Are we done? Because the problem statement did not provide us with much direction as to the level of detail desired for the solution. Example 1-2 Provide a black box diagram showing a natural gas-powered storage-type water heater and some of its important subsystems. The next step is to consider what little you know about the solution from the problem statement.7(b). Note the arrowheads are used to show direction for the inputs and outputs. therefore. your black box diagram should appear similar to Figure 1. you probably know. particularly if you know nothing about hot water heaters. 20 . You know that the heater is a natural gas heater. And you should definitely get used to the vagueness about how the problem was stated: that’s fairly typical in most engineering pursuits. but it is a great starting point. or more importantly you can figure out. The best approach to take here is not to panic. And check it out: the model in Figure 1. it is basically requesting that you do some type of hierarchical design. how a hot water heater works. you probably won’t be providing your solution to the Maytag company for immediate fabrication.7(c) is somewhat descriptive. And for the last step. This step ain’t much. for anything you ever do in any engineering problem. Once you include these in your model. so it must have an input for natural gas (so include that in your model). Without too much effort.7(a) shows the result of this complicated step. Solution: The first thing to notice about the problem is how vaguely it is stated. Figure 1.Digital McLogic Design Chapter 1 Example 1-1 Provide a black box diagram showing a natural gas-powered storage-type water heater. particularly if you have no idea of what you’re doing. And that’s about it. Solution: This is the same problem but now you’re expected to know something about hot water heaters. there must be a cold water input as well as a hot water output.7(c) show the model when this input is included. this should always be the first step.

The control unit is the brains of the heater and is going to turn on the burner 22 Generally. that is. it keeps the water at some desired temperature without letting it get too much above or below that temperature. I can’t think of anything else. there must be a fume exhaust (and I should have included this in the previous example had I thought of it then). The first step in the solution is to once again borrow from the final solution from the previous example.8(b) show a two-level hierarchical support with the top-level being the HWHEATER2 black box that the lower levels being the three subsystems. Once again. Once again. a thermostat regulates the water temperature. We could do more but… why bother since our solution has satisfied the original problem statement. we’ll declare this problem completed. this is not that big of a deal unless you’re a total nimrod23. Once again. we’re now expected to know something about how the subsystems interact with each other. we’ll add a small amount of detail and call the problem done.8(b) shows the final solution to this example. Figure 1. There must be a storage tank for the hot water. Note that our final solution in Figure 1. Figure 1. There must be gas burner in there too.Digital McLogic Design Chapter 1 Step one is a hallmark of all design: don’t reinvent the wheel: borrow you solution from the previous example since it was a rather cool hot water heater design. 23 But now is your chance to learn something about the art of gas-powered hot water heater design. make a list of all the subsystems that would probably be required for the hot water heater in this design. The next step is to add some connections between the internal black boxes.9(a) show the result of this step with a new label being attached to the top-level black box. And come to think of it.8(a) shows the result of this step (though the name of the black box has changed from the previous example). the problem did not state exactly how much detail you need to include. So in this case.8: A possible solution to this example. 21 . (a) (b) Figure 1. Example 1-3 Provide a black box diagram showing a natural gas-powered storage-type water heater and some of its important subsystems. Whereas in the previous example we were expected to know something about the heater’s subsystems. There must be a control unit22 to maintain a relatively constant water temperature by turning on the gas when the water cools and turn it off when it reaches the desired temperature. Figure 1. Include enough detail in your model to show the basic interaction of the various subsystems. Solution: This example represents a slight modification to the original problem. Step two.

The black box modeling technique allowed us to take random bits of information and reassemble them in a viable model that seemed to solve the given problem. keep the thought of digital design in mind. 24 And that’s good enough for most every administrator in academia. we started out with nothing as well as very little knowledge about hot water heaters.Digital McLogic Design Chapter 1 when the water gets too cold. rethink it. We did what the problem asked. Although this example had nothing much to do with digital design. This set of examples hopefully showed you the power of black box modeling. let’s add some more detail. if your design in not coming relatively easy. let’s connect the arrows from the higher level to the lower-level subsystems. As you read these. at least you’ll look like a pro24. we had an interesting little model of our hot water heater. That means the control unit must monitor the temperature of the tank (one connection goes to the tank) and tell the burner to turn on/off (another connection goes to the burner). Figure 1. start drawing black boxes and arrows. Mealy’s second law of digital design: if your design is running into obstacles that require kludgy solutions. these examples only roughly stated the level of detail we should use in the problem solution. Since we have a few subsystems listed. (a) (b) Figure 1. This notion is fairly intuitive. First. Mostly importantly. and we’re probably a little bit smarter. we did the best we could without worrying too much about the fact that the U.9: A possible solution to this example. and start again. In other words. 22 . If you have no idea what you’re doing. then moved on. start drawing black box models and 1) list what you do know (such as inputs/outputs and given signal name. Secondly.9(b) shows the final result. Patent office probably would not like our black box model. As a result. toss out the design and start over from square one. but while we’re at it. while we were working these examples. the hierarchical design approach used in these examples is the mainstay of viable digital design practice. At this point we could be done with the problem. This is the cool thing about black box modeling: it provides you with a method of creating a path to the problem’s solution when you’re feeling like you have no idea where to go.S. Mealy’s first law of digital design: if in doubt. But seriously. There are two major things to note about this problem. toss it out. and 2) label everything (such as the names of the blocks). never forget Mealy’s first and second laws of digital design. By the time we were done with these examples.

These ideas are somewhat worth expanding upon. Moreover. Probably the best way to view the digital circuits you’ll be designing is that your circuit establishes a structured relationship between the circuit’s inputs and outputs in such a way as to solve the given problem. The first step in solving a problem is to know something about the problem. There are many approaches to solving digital problems. In some later chapter. Please note that modeling a digital circuit is not necessarily digital design. then your digital design seemingly works properly. the problem description generally tells us the “inputs” and “outputs” the circuit will behave. we’re ready to grasp the main ideas behind modern digital design and relate them to the approach taken by this text. you’ll need to create a digital circuit and place it (figuratively speaking) in the black box of Figure 1. there are may approaches to designing digital circuits. In a nutshell. In other words. Figure 1. The two main approaches this text takes to modeling digital is black box models and VHDL. pronounced ver-baj. although we won’t initially know what goes in the box from a given problem description. digital design is a matter of “creating” the interior of the Digital Circuit box shown in Figure 1.10: “Digital Design” in a nutshell: a general model of a digital circuit. This text generally treats the design process different from the modeling process. The keys to this definition lie with “creating a digital circuit” and the “problem” that is “solved”.10:. The best is yet to come.7 Digital Design Overview Even though we’re only a few pages into the introductory verbage25 of digital design. Definition of verbage: part verbose. Solving a Problem: “Solving a problem” could mean many things but our approach is specific to digital circuits. using digital circuits to solve problems is the theme of this text. The VHDL model can later be used to implement the circuit on certain digital devices. In order to solve the given problem. The digital circuit you design can be modeled as a device that generates the correct outputs to the circuit given a set of inputs26.10:. Modeling is simply one of many ways to represent a digital circuit. it would be something such as: digital design: the creation of digital circuits to solve problems. Figure 1. If you were somehow required to embody digital design in one short sentence. 26 25 23 . we’ll modify this definition of a digital circuit as a device that generates the correct sequence of outputs to a specific sequence of inputs. The problem statements in digital design generally state the desired outputs for a given a specific set of inputs. part garbage. If your digital circuit manipulates the inputs in such as way as to provide the requested functionality on the outputs. Creating Digital Circuits: There are many ways to create a digital circuit and we’ll soon be exploring a few of these ways.10: shows the general model (there’s that word model again) of a problem that we’ll use as a starting point for all the problems presented in this text.Digital McLogic Design Chapter 1 1.

The flavors are generated by doping the silicone with special substances. The example shown in Figure 1. This is an extremely low-level view of digital electronics and is way out of the scope of this text. 24 . But generally speaking. however. Figure 1. it’s the movement of electrons that make operation of digital circuits possible. We’ve seen this notion before in Figure 1.Digital McLogic Design Chapter 1 1. Once again. Once again. digital design can be performed at many different levels. The level you choose to design your digital circuit at is based on many factors. this level of view of a digital circuit is still too lowlevel for this text. a notion that we’ll live and die with in digital design. Once again. The set of figures listed below describe a few different levels of abstraction associated with digital design. huh? Why do you think they call it dope? The symbols in this figure are the accepted circuit schematic symbols (they’re models. In digital design. This figure shows two different flavors of silicone that are sandwiched together to form a device known as a diode. Figure 1. you’ll be doing your design as the highest level of abstraction possible in order to increase your effectiveness as a digital designer. complexicated. the concept of levels of abstraction are more often referred to as the black box approach to digital design or sometimes as the object-level design approach. The good thing about digital design is that it contains a built-in mechanism that indirectly controls the complexity and thus facilitates the understanding of complex digital circuits. Later chapters in this text provide more details regarding these notions.12: The basis of digital electronics is what the electrons are doing in a piece of semi-conducting material (namely sillycone). you can also design a digital circuit at many different levels. Sounds fun. you won’t need to know much about these levels other than the fact that they exist. it’s the electrons moving around in a controlled manner that make useful things happen in electronic circuits. you’ll soon discover that digital circuits quickly become complex and complicated (or. it is a form of hierarchical design. No matter how it is referenced. The term “abstraction” is often used in the realm of computer science. Because you can view a digital circuit at many different levels.8 The Digital Design Paradigm As you study digital design. Technically speaking. of course) for the diode. as some idiots like to say).6 is an example of hierarchical design.6 with our discussion of modeling. Have no fear. there are many different ways to model a digital circuit and these ways can generally be divided into “levels of abstraction”.11: This is a cheap model of an electron. It’s interesting to note that many electronic engineering students will eventually need to deal with diodes in those pesky analog-type courses. Roughly speaking. This text only touches upon a narrow window the digital design hierarchy.

this device is still too low-level for this text.15. we’ve been abstracting to higher and higher levels relative to digital electronics. These two modes are where the term digital comes from and are typically referred to as OFF-ON. these transistors operate exclusively in only two modes. HIGH-LOW. Note that we no longer include the “p” and “n” level of modeling in this figure.14. etc. The notion of digital in our approach to digital design is derived from this device. each of the gates shown in this figure is actually an abstracted model of a transistor circuit. Figure 1. You’ll soon be learning how to design useful digital circuits using these gates. we still want to steer clear of having any direct dealings with transistors. In other words. Digital circuits modeled using these devices are referred to as gate-level circuits or gatelevel designs. Lucky for us that VHDL strongly supports object-level design. This text also deals directly with this level of digital circuit. Together they form what is known as a CMOS element (Complimentary Metal Oxide Semiconductor).16: Up to this point. You could just as easily model the circuit on a transistor level. I like to refer to digital circuits drawn using these devices as object-level circuits because of the nice analogy made to object-oriented software design. but using the gates are much easier to understand. are used to construct some useful and interesting circuits. The devices in this figure are models of standard digital circuits which are constructed of the gates shown in Figure 1. we’re purposely ignoring the terms voltage here. Figure 1.15. 25 . This transistor is able to operate in four different modes. combined with the gates of Figure 1. These gates perform specific and useful digital operations that you’ll learn about later. These and similar devices. The trend continues with this figure. This device is a Bipolar Junction Transistor (BJT). Figure 1. The interesting thing about this device is that it’s operating characteristics forms the basis of all digital electronics.14: This symbol is comprised of two transistors: a PMOS and an NMOS. But in the end. This text deals directly with gates such as the ones in this figure. In digital electronics. These two transistors are connected such that they form an element that performs a basic digital function (it performs inversion).15: This figure shows some of the gates used represent transistor circuits such as those in Figure 1. But since this text does not deal with basic analog electronic devices.Digital McLogic Design Chapter 1 Figure 1. Once again.13: This device is somewhat similar in construction to the diode but there’s more of it.

these devices are massively complex despite the fact they are comprised primarily of devices that are relatively simple to understand. You are rarely expected to design digital components from the ground up. Like the calculator example. Viewed from this level. Devices as complex as this one are beyond the scope of this text. If you are able to understand the operation of the core digital devices.17: And lastly. a simple algorithm can be used to do long division to arrive at the same result as a division operation on a calculator. the reality in digital design land is that there are only a relatively few number of core digital devices out there.16. The notion of object-level digital design is fully supported by the presence of large design libraries full of digital devices waiting to be used by a crafty digital designer. and you can design just about any digital circuit. you’ll also be able to understand any digital device. But. there is always an effort to group a bunch of small things of varying purpose into a special box (sounds like modeling to me). If you had to design everything starting from their basis low-level digital parts. you’d simply rather not do them and opt to use the calculator for its speed and accuracy. The same is true for most of the digital design problems.Digital McLogic Design Chapter 1 Figure 1. Though you have (or should have) the ability to do many of the tasks you relegate to your calculator. you would not be a productive digital designer. which are also discussed in later chapters. the series of figures in embodies a major theme behind digital design: abstracting to higher levels in order to increase your understand and effectiveness as a digital designer. regardless of its complexity. Add in the many digital modules contained in typical VHDL design libraries. the calculator does it faster and without error: the wisest decision is to use the calculator. you’ll have the ability to do the lower-level black box design but you avoid it because you’ve done it before. no one is going to pay you the big bucks to designing circuits and components that have already been designed. These special boxes perform specific functions though the details of how the special box performs those functions are not necessarily important at that specific box level. You should not consider the black box diagram approach or the hierarchical design approach to problem solving anything new. you understand it. embedded in those tools are devices that have already been designed and are ready for re-use in your designs. The modern digital designer needs to be a master of the tools. you can design an amazing number of different circuits. Even them most complex digital circuit can be decomposed into a set of these core digital devices. Said a bit differently. And to drive the point home even further. As you will soon find out. Keep in mind that devices like this are so complexicated that they necessarily were designed at very high level of abstraction. For this course. You’ll learn how to design certain standard devices and then abstract them to a black box in order to not worry about the lower-level details. You’ll forever more use only the black box without worrying about implementation details of what’s inside. As you’ll see later. We’ll deal with this more directly in later chapters. most every digital design tool that exists out there has an extensive list of black-box digital devices.15 and Figure 1. if you have the inclination to actually dig that deep into low-level details. Digital designers of yesteryear were masters of paper designs since that was about all they could do27. This decomposition is a reversing of the hierarchical design process. For example. The approach is also a standard building block in top-down and bottom-up design paradigms. 27 26 . when you’re out there in the real world. and you have better things to do. it’s actually similar to doing many simple everyday tasks such as using a calculator. Although this text only deals with embodies the abstraction levels shown in Figure 1. This is particularly true in an academic environment were the quarters and semesters pass too quickly to spend time actually implementing real digital circuits. From these relatively few modules. there are only a relatively few digital design modules that we’ll be learning about and working with. Besides. abstracting to really high levels are digital devices such as microprocessors. VHDL is a tool that allows you easy access to these device libraries. drawing a black box model is generally the first step in any digital design problem.

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Figure 1.18 shows a quick overview of digital design as it relates to the introductory digital design topics covered in this text. You don’t need to know any of this now, but what you’ll hopefully see from Figure 1.18 is that there aren’t that many standard digital devices (or modules) out there (and the ones that are out there, are generally very simple devices). We’ll visit Figure 1.18 many times later in this text. In summary, here’s all I know about digital design: 1) Digital design is based on a relatively small set of digital devices. 2) Digital design relies heavily on various modeling approaches. 3) Digital design modeling relies heavily on hierarchical modeling.

Figure 1.18: The quick digital design overview.

1.9

Computer Science vs. Electrical Engineering

Without doubt, the object oriented approach to software design is perfectly analogous to the modern Electrical Engineering approach to digital design. The similarities are wickedly similar. • In computer programming, you have the ability to create programs at many levels such as machine code, assembly language, or higher level languages such as C or Java. In digital design, you can design at the transistor level, the gate level, the object level, etc. In both cases, the lower the level you design at, generally speaking, the more time and effort you’ll need to put into it.28

There are of course instances in both fields where you would definitely want to choose to design on a lower level as opposed to a higher one.

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•

In computer science, reusing previously designed and tested code is a good way to increase your productivity. A significant portion of computer program design involves the incorporation of previously designed modules in the current program. As a result, there are many software packages out there that simply provide bunches of modules that do something meaningful. Not surprisingly, much of the productivity software out there is written a very high level29. In the modern electrical engineering approach to digital design, you have many similar options such as off-the-shelf digital devices and the ability to create and use various design libraries. This distinction between computer science and modern electrical engineering approach to digital design is further blurred with the introduction and promulgation of hardware design languages such as VHDL and Verilog and their associated device libraries.

The point here is that these two fields are really similar. They also have the interesting relationship that one would not exist without the other. Good engineers are fluent and productive in both electrical engineering and computer science (while bad engineers tend to exhibit hatred towards one of the other or both30). Start on the road of being a good engineer by not fearing or avoiding the field that is “not part of your major” or “outside your area of interest”. Always put effort into celebrating and working with the interconnectedness of these two fields. One major consideration that primarily computer science students should consider is the fact that a great deal of time and effort in the real world go into creating Electronic Design Automation (EDA) tools. Generally speaking, these are software tools that increase the productivity of hardware designers. This heavily implies that if your primary interest is software development, having a solid understanding of the needs and methods of the digital hardware design engineer is going to make you a better and/or more marketable software developer. In other words, if it was not for major advances in software tools, digital hardware designers would still be wiring boards to circuits and cutting out rubylith31.

1.10

One Final Comment

Throughout this text, you’ll be learning many tools and techniques associated with digital design and engineering in general. Once you’ve mastered these tools and techniques, there is a tendency to approach digital design problems by rote. Learning to do problems by rote is somewhat OK in early stages of learning digital design because of the newness of much of this material limits the complexity of problems. Doing problems by rote could arguably be a good approach if digital design was one of those engineering topics that carry little importance in the big scheme of things (we all know of such topics). But digital design material is important. The relation that digital design has to computers in general is equivalent to the relation that addition has to general mathematics: it’s tough to do math without understanding the basics of addition. The more completely you learn and understand the material presented in this text, the better off you’ll be when you eventually take on more complex digital designs or be required to apply basic digital design concepts in later engineering and/or computer coursework. If you memorize the material, you sooner or later forget it. If you truly understand the material, you’ll never forget it. The better you understand the material, the less work and struggle you’ll face when actual digital design rears its ugly head sometime in the future. This means you’ll have more time to actually have a life as opposed to spending time in a cave in front of a computer or textbook (that is, if having a life is something you aspire to).

Could you imagine what a nightmare it would be to write Windows application code at a low-level such as assembly language? 30 In the real world, these people are referred to as human resources; in academia, these people are referred to as administrators (or adminstators for short). 31 Go check this out on www.wikipedia.org…

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Chapter Summary • Digital Design (definition): the creation of digital circuits to solve problems. And a somewhat longer

version: The creation of a digital circuit that establishes a structured relationship between the circuit’s inputs and outputs in such a way as to solve the given problem.

**• Modern Digital Design: Modern digital design is truly design oriented as opposed to historical
**

approaches which were not designed oriented due to the unavailability of implementation tools. Modern digital design is driven by Hardware Description Languages such as VHDL and Verilog. The availability of HDLs and the relative low cost of PLD-based hardware allow digital designs to be implemented and tested significantly more quickly than historical design techniques.

• Analog vs. Digital: The term digital refers to items that are discrete in nature while the term analog

refers to items that are continuous in nature. While the world we live in is primarily analog, computers are primarily digital. One important function of digital design is to allow the successful interaction between computers the rest of the analog world.

**• Models in Digital Design: a model is a representation or a description of something using a certain
**

level of detail. The main purpose of the model in digital design is to transfer information to the entity using the model. There are four main types of models used in digital design: black box model, timing diagrams, written descriptions of digital circuits, and VHDL models.

• The Digital Design Paradigm: Digital designs can quickly become large and complex in order to meet

their required functionality. To control this complexity and to promote design efficiency, digital design is generally performed at different levels of abstraction. In this design paradigm, circuit behavior at the current level of abstraction becomes more relevant than the circuit implementation details of lower levels of abstraction. This digital design paradigm is usually referred to as hierarchical design.

• Mealy’s First Law of Digital Design: if in doubt, draw some black box diagrams. • Mealy’s Second Law of Digital Design: if your digital design is running into weird obstacles that

require kludgy solutions, toss out the design and start over from square one.

**• Digital Design Overview: Digital Design is based on a relatively small set of digital devices, relies
**

heavily on various modeling techniques, and particularly relies on hierarchical modeling.

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Chapter Exercises

1) The analog world we live in has many people who seem to thrive on the use of digital photography. Practically everyone it seems has a digital camera, or has the equivalent on their cell phone or computer. A conversion from analog to digital occurs somewhere in the camera. Where exactly does this analog-to-digital (ADC) occur? Explain as best you can. 2) One of the themes of this chapter is the hierarchical design approach. Would it be possible to have too many levels for a given design? Explain your answer without being too verbose. 3) The dimmers used for incandescent lights mentioned in this chapter can actually be considered digital in nature. Although the dimmer effectively provides what a continuous range of light frequencies between the ON and OFF limit, how can it possibly still be digital in nature? Explain as best you can. 4) If you were required to take a “hierarchical” approach to reading this chapter, briefly describe how you would do it. 5) Draw a block box model of the following devices (be sure to label your model as completely as possible): a) the family dog, b) the tree growing in the forest, c) a bottle of beer, d) your best friend, e) your wallet or purse, f) a typical compost pile. 6) Draw a block box model of the following devices (be sure to label your model as completely as possible): a) microwave oven, b) handheld calculator, c) television, d) portable MP3 player, e) refridgerator/freezer. 7) Draw a two block diagrams, each using a different level of description, for the following devices (be sure to label your model as completely as possible): a) an internal combustion engine car, b) a typical soda dispensing machine.

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Chapter 2

2

Chapter Two

2.1

Introduction

The previous chapter hopefully gave you a small taste for what exactly is meant by the term “digital” and the term “model”. In this chapter, we’ll combine these two words and actually do something intelligent and creative people refer to as “digital design”. Digital design is not just the pseudo-title of this book; it’s really where we want to be. The “art” of digital design has not as of yet been refined to the point of being able to present the subject in only one way using the same set of solid definitions and algorithms. From a beginner’s standpoint, the digital design process can be done by rote, which is not a good thing unless you intend to completely kill off your basic creative nature. Although this chapter presents a single approach to digital design, it is by no means the only approach nor is this approach written in stone. This chapter represents the first step in digital design. Your mission is to realize that digital design solutions can be generated and represented in many different ways. Do not use the knowledge presented in this chapter as a road map; instead, use it as a means to open the door to another world: digital design-land. In that world, you’ll find that you’re truly on your own. Have fun; it’s really not that big of a deal.

**Main Chapter Topics
**

NUMBER SYSTEM INTRODUCTION: Since number usage has become second nature in our everyday existence, we probably have forgotten some of the underlying characteristics that make numbers “work”. This chapter provides a friendly reminder of common definitions associated with number systems as well as a brief introduction to binary numbers. DIGITAL DESIGN OVERVIEW: This chapter uses a simple design example to introduce a structured digital design process. The chapter presents several different design representations as well as an introduction to the Boolean algebra, its basic axioms, and associated theorems. DEMORGAN’S THEOREMS: Probably the most widely used theorem in digital design, DeMorgan’s theorems are used to describe and generate product of sums and sum of products representations of functions. TIMING DIAGRAMS: The operation of digital circuits is often specified, explained, and/or modeled by the use of timing diagrams. This chapter provides an introduction to timings as they relate to the simple digital circuits introduced.

(Bryan Mealy 2011 ©)

2.2

Number System Basics

Without much doubt, humans have spent most of their existence doing quite well without the concept of numbers or a number system. Number systems eventually became an integral part of human life as humans

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evolved and progressed1. The concept of numbers, for better or worse, has corrected the basic limitation of the human brain in its lack of ability to handle large quantities of “things”. My eighth grade algebra teacher2 once told the class a story about some primitive culture. I’ve long since forgotten why exactly he told this story, but I never forgot it. This was the day I found out that I was not much better than a caveman. He told the class about some primitive culture somewhere in the world and about the number system they used. This number system was comprised of three “numbers”: one, two, and many. What has always impressed me about this story was the fact that it still nicely describes the way my brain “processes” certain type of situations where keeping track of a certain number of items is necessary. Although this number system seems extremely limited compared to the number systems we currently use, this caveman simple number system remains well matched to limitations of the human brain. Figure 2.1 demonstrates a basic limitation in the human brain. In Figure 2.1(a), it’s fairly obvious to the unencumbered human brain that there is one dot in the square. Your brain can hopefully both see and process this information almost instantaneously3. Your brain probably has no problem “counting” the number of dots in the square of Figure 2.1(b) either. But once you arrive at Figure 2.1(c), your brain cannot instantaneously gather this information: your brain is instantly overloaded by the sheer number of dots in the square (even though there are relatively few). In essence, your brain is not any more sophisticated than the brain of the person in the so-called primitive culture. But as you know, we modern humans are able to both conceive and process the dots in the square of Figure 2.1(c). The way we do this is to represent the quantity of dots in the square with a “number”. This number is defined by a previously and mutually agreed upon set of rules to ensure that everyone who is processing the quantity of dots in the square arrives at the same result. There is even a mutually agreed upon set of squiggles that are used to represent the numbers.

(a)

(b)

(c)

Figure 2.1: An example showing a basic limitation of the human brain.

2.3

Number Systems and Binary Numbers

Although you’ve been working with numbers and number systems most of your life up until now, a quick review of the some of the underlying structure and definitions is in order. We’ll go more into depth with our study of number systems in some later chapter; providing a brief introduction to the binary number system is the primary focus of this chapter. Keep in mind that the reason binary numbers are so important in the study of digital design is the fact that a binary number nicely models the high-voltage vs. low-voltage relationship in the underlying transistor implementation of digital circuits. First of all, here are a few quick definitions. The concepts presented in this section should be nothing new to you but many of you may have never seen or simply forgotten the actual definitions. It’s sort of sad… although you’re probably able to tweak around with multi-variable calculus but you also probably have forgotten what exactly a radix point is. Welcome to higher education.

1 2

Although the usage is an apparent first step in human de-evolution. It was Mr. Fangman; the year was 1975. 3 Although some individuals may take longer, particularly individuals who have job titles such as “administrators”.

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Number System: a language system consisting of an ordered set of symbols (called digits) with rules defined for various mathematical operations. Radix: the number of digits in the ordered set of symbols used in a number system. Number: a collection of digits; a number can contain both a fractional and integral part. Radix Point: a symbol used to delineate the fractional and integral portions of a number. As example, consider a decimal number (radix = ten). Since the number is a decimal number, we can use either one of ten different symbols to represent a decimal number. If we were only limited to ten numbers, the number system would be of little use to us. But, by placing digits side-by-side and tossing in some special rules, we can represent just about any possible number. When we place digits side-by-side, we are representing numbers in what is known as juxtapositional notation. Using juxtapositional notation allows numbers greater than the radix-1 to be represented. Juxtapositional notation can be used for number systems of any radix value. Each of the digit positions in juxtapositional notation can be any of the digits in the ordered set for the given radix. For decimal numbers, the numbered set is [0,1,2,3,4,5,6,7,8,9]. Figure 2.2 lists some other fun facts regarding numbers and juxtapositional notation. Figure 2.2 shows that numbers are divided into their integral and fractional. The radix point delineates the integral and fractional portions of the number (the radix point is that funny dot that you’re not supposed to call a decimal point unless the radix is ten). Each digit in both the fractional and integral portions of the number is a member of the set of numbers associated with the given radix.

**NUMBER = (N)R = (Integer Part) . (Fractional Part) ↑ Radix Point
**

Figure 2.2: The form of a typical number.

Figure 2.3 provides an alternative and more formal definition of a number. This definition also includes some of the typical lingo used to describe numbers. Note that there is nothing too amazing about this approach; it’s just the convention that most everyone happens to use.

NUMBER = (N)R = (An-1 An-2 … A1 A0 . A-1 A-2 … A–m) R where: R ≡ Radix A ≡ a digit in the number A n-1 ≡ the most significant digit (MSD) A -m ≡ the least significant digit (LSD)

Figure 2.3: Another form of a typical number.

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Example 2-1 Describe the integral and fractional portions of the following number: 989.45

Solution: The solution to this problem should be second nature to you. “989” is the integral portion of the number; “45” is the fractional portion of the number. Note that the radix point divides the integral and fractional portions of the number. Also note that since there is no listed radix value, the radix value of ten is implied and thus the number is a decimal number. The standard we’ll use in this text is that if a radix value is not listed, then a decimal number is implied. Numbers listed in other radii should explicitly list the radix or explicitly state somewhere that a non-decimal radix is being used. 2.3.1 Common Digital Radii

Numbers do not always include the radix number. As pointed out in the example, if numbers do not list the radix, the assumption you make is that the radix is 10 (a decimal number). It’s generally safe to make this assumption since we humans deal best with decimal since that is what we’ve been taught from day one. In the study of digital design and other such things, there are four common radixes that are used: base 10, 2, 8, and 16. For this introduction to numbers, we’ll only be looking at numbers with a radix of ten (decimal) and a radix of two (binary). Table 2.1 shows the symbol set for the decimal and binary numbers. The important thing to note here is that the set of symbols for a binary number comprises of only ‘0’ and ‘1’, with the highest valued number in each set being the number that equals the radix-1. Also good to point out here that the values in Table 2.1 read lowest values to highest values (left to right). RADIX 10 2 NAMES decimal binary SYMBOL SET 0,1,2,3,4,5,6,7,8,9 0,1

Table 2.1: The most commonly used bases in the study of digital things.

2.4

Juxtapositional Notation and Numbers

The use of juxtapositional notation allows quantities larger than the (radix-1) to be represented. You are already familiar with such notation since you have spent most of your lives dealing with decimal numbers. The theory behind this notation is no different in other bases but we’ll remind you of it here. Juxtapositional notation means that the symbols in a given number system are placed side-by-side in order to represent quantities larger than the numbers in the given set. Larger numbers are represented by assigning a weight to every digit position in the number. By convention, the numbers are monotonically increasing (scanning right to left) powers of the radix in question. The weighting of the digit to the immediate left of the radix point is the radix raised to the zero power (by convention). These attributes are widely accepted conventions but are by no means required. The following to examples demonstrates these ideas. These two examples use radii of ten and two, respectively. Be sure to compare and contrast the items that are the same and different.

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Example 2-2 Show the weightings associated with each digit in the following number: 987.45

Solution: Table 2.2 shows the solution to Example 2-2. The important thing to notice about this solution is that the radix exponential row uses the radix to monotonically increasing/decreasing powers to designate the weightings. This convention follows the juxtapositional number conventions listed in Figure 2.3. Decimal Value of Digit Weight Radix Exponential Positional Value

100

10

1

0.1

0.01

102 9 x 100 (900)

101 8 x 10 (80)

100 7x1 (7)

10-1 4 x 0.1 (0.4)

10-2 5 x 0.01 (0.05)

.

↑ Radix Point Table 2.2: The solution to Example 1-1.

Example 2-3 Show the weightings associated with each digit in the following number: 101.112

Solution: Table 2.3 shows the solution to Example 2-3.

Binary Value of Digit Weight Radix Exponential Positional Value

4

2

1

0.5

0.25

22 1x4 (4)

21 0x2 (0)

20 1x1 (1) .

2-1

2-2

1 x 0.5 1 x 0.25 (0.5) (0.25) ↑ Radix Point

Table 2.3: The solution to Example 2-3. Since decimal and binary are the two primary radii used in digital design (decimal for humans; binary for the actual hardware), you should definitely understand the previous examples and also memorize the numbers listed in Table 2.4. You’ll be using binary and decimal numbers throughout this text although some other useful radii are presented in a later chapter. You’ll eventually commit these numbers to your memory because you’ll be using them so often in digital design and computer-type applications. But, if you 35

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put the time into memorizing them now, you’ll save yourself a lot of time, effort, and struggle in the near future. (Hint: take notice of the pattern, as it changes from right to left) Note that the binary numbers listed in Table 2.4 are listed as four binary digits, or bits. As you’ll see later, a group of four bits has special significance in digital design land. Including the leading zeros in the binary numbers enables you to read the number quickly; omitting the leading zeros does not change the value of the number Decimal (base 10) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Binary (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Table 2.4: Numbers that every successful digital designer has memorized.

2.5

Digital Design

If you’re reading this sentence, it is probably because you have opted to pursue the path of becoming an engineer. Although I’ve officially been an engineer for way too long, I’m still not sure what an exactly an engineer is or does. As best that I can figure it out, an engineer is a person who solves problems4. More specifically, an engineer is a person who solves problems that have enough technical content to be considered engineering problems. Since an engineer is a problem solver, and since this text is all about digital design, and since you’re obviously reading this text, let’s take a look at a basic model for solving digital design problems. Being the average smart person that you are, you’ve probably solved a lot of problems during your life. But have you ever really analyzed your approach to solving problems? In case you haven’t, we’ll be talking about a possible approach in this section. As best that I can see it, the approach that I generally take to solving a problem is listed below. Note that this approach is generic enough to be applied to any problem, not just digital design problems. I suspect that everyone who considers themselves a problem solver take a similar approach. Here is my basic algorithm to solving problems5. 1) Define the problem: understand the starting point and requirements 2) Describe your solution to the problem: propose a path to the solution

As opposed to administrators: their main goals are to create problems for engineers and then do their best to prevent the engineers from solving them. Administrators are basically jealous that they don’t have the brains or ethics to become engineers. 5 Typical administrator are not aware of any such problem solving algorithms; but be sure to ask them about their many “justifying their existence” algorithms.

4

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3) Implement your solution to the problem: embodiment of the solution The following verbage represents an introduction to digital design presented in the context of an actual problem. There is a lot of information presented so try not to lose track of the basic approach. Keep in mind that we’re designing a digital circuit; you might want to take a different approach if you were designing a stick in the mud. 2.5.1 Defining the Problem

The basis of any design problem is a statement of the problem at hand. As previously stated, in digital design you are typically faced with designing a digital circuit that processes some set of inputs and generates the desired output. It is understood that for here and evermore in this course that both the inputs to the circuit and the outputs from the circuit are digital values. Figure 2.4 provides the problem statement for this painfully long design example.

Example 2-4 Problem Statement: Design a digital circuit where the output of the circuit indicates when the 3-bit binary number on the input is greater than four. Figure 2.4: The Problem Statement. The basic concept of all digital design is simple: you’re simply creating a circuit that provides the correct output(s) to a given set of input(s)6. Read that sentence again, it’s important. The problem is that there are many approaches to performing digital design; this section presents only one of them. What you’ll find is that you will eventually develop your own style and approach to digital design as you gain experience with the digital design process and problem solving in general. Keep in mind that the overall goal is to solve the problem; the approach you take to solving the problem is not always the most important or the most efficient thing, especially this early on in your digital design education. You’ll initially be on a mission to collect tools and experience with digital design: the more you learn, the more you’ll realize that you’ll never use a significant portion of what you learned. The first step in defining this problem is to translate what is being asked in the problem statement (words) to some other form. A good place to state with any digital design problem is to draw a diagram of the circuit that clearly shows both the inputs to and the outputs from the circuit. Drawing a diagram of the circuit should be the first step in solving any digital design problem. From the problem statement, you can see that the digital circuit that satisfies this problem has three inputs (the 3-bit binary number) and one output (states a quality of the input that we’re interested in). The starting point in any digital design is to draw a black box model that indicates the stated circuit inputs and outputs. We’ve seen this approach to modeling other things in the previous chapter. Recall that a model in this digital context is simply a description of a digital circuit. This is purposely a loose definition because there are once again about a bajillion-and-one ways to describe a digital circuit. The diagram in Figure 2.5(a) is just one of these ways. What is nice about the diagram of Figure 2.5(a) is that is clearly shows that our final circuit will have three inputs and one output (as indicated by the direction of the arrows). The circuit shown in Figure 2.5(b) is another model of our final circuit. The difference between these two models is the fact that the model in Figure 2.5(b) has given specific names for the inputs and outputs. Note that the circuit models of Figure 2.5(a) and Figure 2.5(b) show roughly the same thing but the Figure 2.5(b) provides a higher level of detail and is probably a better model in the context of this problem. Recall that the term “model” does not imply a specific level of detail. For the purposes of solving this problem, the

6

What you see later in this course is that the outputs can also be based on a sequence of inputs. For now, we’ll pretend that the circuit outputs are based solely on the circuit inputs at a given time.

37

6: The empty and completed truth table for Example 2-4. There one piece of important information missing from the model of Figure 2.5(b): since the three inputs represent a binary number.Digital McLogic Design Chapter 2 model of Figure 2.5(b) are nothing special: the “B” could mean binary. The next step in solving this problem is to establish a relationship between the circuit’s inputs and outputs. but a purpose of having a model is for anyone to look at it once and quickly understand what is going on.6(b) shows the truth table with every possible combination of the three binary inputs and the outputs that indicate when the input combination solves the stated problem. In general. Once again. but it’s always better to explicitly state your assumptions. Since we’re the digital designers here. your solution in the context of the model of Figure 2.6 shows the truth table for this problem: Figure 2. For this problem.6(a) shows the empty truth table while Figure 2. 38 . let’s consider the B2 input to be the most significant bit (MSB) and the B0 input to be the least significant bit (LSB). you must always state this extra information when you are performing digital design. the approach we’ll take is to state an input/output relationship such that the stated problem is solved. The table used to display this input/output relationship is referred to as a truth table. It may be tedious. and be correct. what are the binary weights of the inputs? You need to state this in your problem solution in order for the solution to have meaning. Figure 2. if you were not to state this extra piece if information. the “F” is a typical name given to the outputs of a digital circuit because the output is a function of the inputs (more on this later).5: Two different models of the proposed digital circuit. B2 B1 B0 F B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 (b) B0 0 1 0 1 0 1 0 1 F 0 0 0 0 0 1 1 1 (a) Figure 2. You could probably make an implicit assumption here. the numbers following the Bs are probably (we’ll comment on this soon) associated with the weighting factors of the binary numbers. The signal names applied to the model in Figure 2.5(b) would make no sense.5(b) can be considered better because we need to use the signal names in this approach to solving this problem. This approach to specifying the input/output relationship represents one of many valid techniques used to solve digital design problems. (a) (b) Figure 2. The way we’ll do this is to list every possible unique combination of the three inputs and assign an output value that indicates when the inputs satisfy the original problem.

Truth tables are typically divided into rows of four thus proving that life is good. the value of F is dependent upon the values of the B2. Using 1’s and 0’s at this point in the design allows us to abstract past the need to deal with voltages (which is a good thing for people who don’t know what voltage is). is greater than four as specified by the problem. we enter 1’s for the cases where the input combination is greater than four. Conversely. There is no real secret to this style of designing circuits. because in binary. For this example. This particular style of digital design is considered an exhaustive approach in that every possible input combination is listed. These attributes are listed below: • The tables have eight rows. The truth table shown in Figure 2. In case you’re thinking that this problem is sort of straight-forward (and boring) in the way that the outputs were specified. There is always a binary relationship between the number of inputs to the circuit and the number of rows in the truth table. which represents a binary number. The truth table is set up so that F is truly a function in every sense of the word. Would this approach be possible if the circuit had 24 inputs? No. For this example. In terms of the digital circuitry. the functional relationship would not exist and the world would be sad.6(b) has been filled in with 1’s and 0’s. and B0 inputs. The fact that 1’s and 0’s are used is for the most part traditional in digital design (it’s easier and faster to write than other options such as ONOFF). In other words. B1. you’re right. The first three columns of the truth table show every unique combination of the three input values. This is no different from the concept of functions in mathematics where there are independent variables and dependent variables.5.6(b). For this example. a 1 in the F column shows when the input combination. Onto the next step. If the output were to have two different values for one row in the truth table. since there are three inputs.6.Digital McLogic Design Chapter 2 There are some interesting and important things to note about the truth tables shown in Figure 2. In this case. the approach taken in this problem serves a good purpose7 and justifies the learning of other more efficient approaches in later chapters. the output F has only one value for each possible input combination. B2. • • • • This is the end of the first step: the problem is now 100% defined using the truth table in Figure 2. we entered 0’s for the cases where the inputs bits represent a number less than five. Also. the counting begins at 0. Therein lies one of the basic limitations of the iterative approach. Be sure to note that the decimal equivalents to the listed input values range from zero to seven (0-7). An extra grid line is added to the middle row of the truth table in order to increase the readability of the table. But not to worry. the 1’s and 0’s are used to model the voltages that are used to drive the underlying hardware of the circuit. there are 23 (eight) unique combinations of the three inputs. The column for the output shows what we want the circuit output to be if that particular combination appears on the inputs. 39 .6(a) is empty while the truth table shown in Figure 2. We’ll be modeling voltages using 1’s and 0’s for the remainder of this text. Keep in mind that each of the inputs to this circuit can only take on one of two values: 0 or 1. This approach is referred to as the iterative approach to digital design (or iterative design) but I like to refer to it as BFD (for brute force design). 2.2 Describing the Solution 7 And the purpose is learning the basics of digital design. B1 and B0 are the independent variables while F is the dependent variable.

5: Boolean algebra Axioms 5a 6a 7a 8a 9a x⋅0 = 0 x⋅0 = 0⋅ x = 0 x⋅ x = x 5b 6b 7b 9b x ⋅1 = x x+0 = 0+ x = x x+x = x x=x x⋅x = 0 Null element Identity Idempotent Double Complement Inverse x+ x =1 Table 2. this is definitely an area you’ll want to explore in other digital design textbooks.6: Single variable theorems.7 list the theorems that can be proven by using the set of axioms in Table 2. A theorem is a proposition that can be proved true from axioms.5. it is generally somewhat klunky to work with. In case you have forgotten what algebra is.1} which clearly shows the two-values (that binary thang again). are completely defined by the axioms shown in Table 2.Digital McLogic Design Chapter 2 Although the truth table has completely defined the solution to this problem. Table 2. is based on a set of operators defined over the set of elements in question. We’ll opt to move onto more useful things. the basic operators in Boolean algebra. What we need to do here is develop a “science” of sort to more efficiently and generally describe the solution to this problem. From this set of axioms. 10 Proving the theorems using the basic axioms is a typical exercise in most digital design texts. In case you actually want to prove these theorems. namely. especially as the number of circuit inputs increase. and the overbar ( ).5.5 lists the basic axioms of Boolean algebra. it’s a mathematical system used to generalize arithmetic operations by using letter or symbols to stand for numbers based on rules derived from a minimal set of basic assumptions. substitute the binary values in to the expressions in the theorems using the axioms. If we are able to develop this new science.6 and Table 2. similar to normal algebra. a guy named George Boole developed some methods to deal with a two-valued algebra9. Although his original intent was to model logical reasoning in a mathematical context. These basic assumptions are referred to as axioms. we’ll be able to continue on in digital design and solve more complex design problems. This is really the short version. I dare you10. theorems can be proved true or false. This two-valued algebra has since come to be known as Boolean algebra. Here’s the shortened version of the story8. About a bajillion years ago. the dot ( • ). Boolean algebra. the cross-looking symbol (+). Go for it. 9 8 40 . Table 2. From these axioms. 1a 2a 3a 4a 0⋅0 = 0 1 ⋅1 = 1 0 ⋅1 = 1 ⋅ 0 = 0 0 =1 1b 2b 3b 4b 1+1 = 1 0+0 = 0 1+ 0 = 0 +1 = 1 1= 0 Table 2. An axiom is a statement universally accepted as true. his work currently forms the basis for all digital design. Lucky for us that someone a real long time ago already developed the “science” we’re looking for. The possible elements in this set are {0.

Figure 2. AND (logical multiplication) OR (logical addition) NOT (inversion) x 0 0 1 1 y 0 1 0 1 F = x⋅ y 0 0 0 1 x 0 0 1 1 y 0 1 0 1 F = x+ y 0 1 1 1 x 0 1 F=x 1 0 Table 2.7 once again provides the truth table defining the solution to this problem. Recall that the goal of this section was to produce a scientific method of describing the function associated with the solution of the original problem. a truth table is usually used to define these operators. B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 F 0 0 0 0 0 1 1 1 Figure 2. Table 2.5 is the definition of the three operators. The three operators actually have names. The dot operator ( • ) is referred to as the AND operator and used to signify an AND operation (sometimes referred to as logical multiplication). The cross operator (+) is referred to as the OR operator and is used to define an OR operation (sometimes referred to as logical addition). Since that problem appeared about five pages ago. Although the axioms completely define these operators.7: The truth table for the original problem.7: Two and three-variable theorems. The overbar is referred to as the NOT operator and is used to define a NOT operation (usually referred to as inversion or complementation).8: Truth tables for the three basic logical operators. The most important result gathered from the basic axioms of Table 2.Digital McLogic Design Chapter 2 10a 11a 12a 13a 14a 15a x⋅ y = y⋅ x ( x ⋅ y) ⋅ z = x ⋅ ( y ⋅ z) x ⋅ ( y + z) = ( x ⋅ y) + ( x ⋅ z) x ⋅ ( x + y) = x ( x ⋅ y) + ( x ⋅ y) = x ( x ⋅ y) = x + y 10b 11b 12b 13b 14b 15b x+ y = y+x ( x + y) + z = y + ( x + z) x + ( y ⋅ z) = ( x + y) ⋅ ( x + z) x + ( x ⋅ y) = x Commutative Associative Distributive Absorption Combining DeMorgan’s ( x + y) ⋅ ( x + y) = x ( x + y) = x ⋅ y Table 2. 41 .8 shows the truth tables associated with these three definitions.

use parenthesis.8 shows the long and drawn out text of this verbal solution. So. But since we went to all the trouble to describe Boolean algebra.8: One approach to describing the solution to Example 2-4. what we mean in this context is that we need some way to implement this function in actual hardware12.9. This equation is referred to as a Boolean equation or sometimes as a Boolean expression. In other words. Just as there are AND. how would you do it? There just so happens to be entities out there referred to as “logic gates” that implement the individual logic functions for you. and NOT functions. All you currently know are the basic functions associated with Boolean algebra: AND. Notice the extensive use of the words “and” and “or” in the solution of Figure 2. A typical digital design synonym for implementing a function in hardware is to “realize” the function or “function realization”. OR. Figure 2. If actually had to implement this circuit in hardware. The output of the circuit is a ‘1’ when: (B2=1 and B1=0 and B0=1) or (B2=1 and B1=1 and B0=0) or (B2=1 and B1=1 and B0=1) Figure 2. The reality is that the word implement has many connotations. Figure 2. OR. you’ve defined (step 1) and described (step 2) your solution which means you’re now ready to implement your solution.9: A better approach to describing the solution to Example 2-4. and NOT operators. Sometimes Boolean expressions such as these are written using parenthesis around the individual terms that are being ANDed together11.8.Digital McLogic Design Chapter 2 We now have several different ways of describing the function that provides a solution to the problem at hand. The first representation is the truth table which we declared as being klunky. There are several important things to note about the in Figure 2. Also worthy of note here is that the expression implies some form of precedence of the AND. The NOT operator (represented by the bars above the independent variables) has highest precedence followed by the AND. Figure 2. a logic gate is a physical device that implements a logic function. A second solution is sort of a verbal and non-scientific solution. and NOT.8 and Figure 2. • An equation is listed (note the presence of the equals sign). There are many types of gates out there in digital design-land. and then the OR function. • 2.3 Implementing the Solution Up to this point. and NOT gates) that implement these functions. 42 . Once again. This expression is written in functional form in that the complete set of independent variables is listed directly on the left side of the equals sign while the dependent value is listed on the right of equals sign.9. but for now we’ll only deal with these basic three gates. F(B2.9 shows a better (more efficient and scientific) way to describe the function using Boolean algebra.10 shows these three basic gates. there also happen to be physical circuits (AND. OR. Note the similarities in the solutions provided in Figure 2. if in doubt. OR. B1. 11 12 Use of parenthesis reduces the need to memorize operator precedence. B0) = B2 ⋅ B1⋅ B0 + B2 ⋅ B1⋅ B0 + B2 ⋅ B1⋅ B0 Figure 2.5.

11: A more generic and intuitive definition for AND and OR functions. we now have the ability to implement the solution in actual hardware. Figure 2. the functions remain consistent.10: The basic gate symbols used to model AND.9 that describes the circuit from the circuit model shown in Figure 2. From this example. Given one of these models. we’re not going to actually implement the circuit. 43 . You can hopefully see from this definition that AND and OR gates can have as many inputs as they need while still exhibiting the basic AND and OR functionality. and 4) circuit model. In general. In the cases of more than two inputs. As you’ll soon find out. you should be able to go back and fourth between the various representations of a Boolean function. and 2) be able to actually implement the circuit. Make sure you understand the relationship between the circuit model shown Figure 2.10 are nothing more than models. Inverters. OR. Figure 2. As you can probably see by now.Digital McLogic Design Chapter 2 the symbols shown in Figure 2. there are many more ways to represent a Boolean function. In other words. Each one of these representations could be considered a model of a digital circuit13. can only have one input and one output. you should 1) be able to generate any of the other models. Instead.12: The circuit model that solves Example 2-4.12. But for this problem.12 and the Boolean equation shown in Figure 2. we learned of and worked with four different representations of a Boolean function: 1) truth table. this form of abstracting is typical in digital design. however. Also good to note here are some issues associated with AND and OR gates. To test your understanding of this relationship. we’re going to provide yet another model for the circuit. and NOT functions.12 shows a model of the final circuit implementation.11. AND gates: the output is only a ‘1’ when all the inputs are a ‘1’ OR gates: the output is only ‘0’ when all the inputs are ‘0’ Figure 2. you should be able to generate the associated Boolean equation shown in Figure 2. AND gate OR gate Inverter Figure 2.9. These gates must have at least two inputs but are not limited to a maximum number of inputs. With these gates. the gates represent the associated logic functions but without providing details as to how the functions are implemented. 2) written description. 13 Although not all of these models are dark box models. A more generic definition of AND and OR gates is listed in Figure 2. 3) Boolean equation.

students are required to become intimately familiar with these theorems by proving them using the axioms. you’ll also quickly realize that some forms of function representations are more appropriate than others in modeling digital circuits.6 Representing Functions A Boolean function. let’s back up to the design example we were previously using. DeMorgan’s theorem happens to be one of those theorems. B1. it is not the only form. or just SOP form. to model digital circuits. Note that this name makes sense in that there are three terms in the equation that are logically multiplied together (these product terms have been wrapped in parenthesis). First. or simply “function” as is typically used in digital design land. these three representations are functionally equivalent.14). The reality is that the function can be represented by describing the inverted output (the right-most column shown in Figure 2. Familiarity with DeMorgan’s theorem is going to allow us to represent functions in many different ways.13: The solution to the previous example listed again here.1 DeMorgan’s Theorems The list of theorems shown in Table 2. Note that in the SOP form. In other words.6. The truth is that modern digital design rarely has a direct use for most of these theorems. B0) = (B2 ⋅ B1⋅ B0) + (B2 ⋅ B1⋅ B0) + (B2 ⋅ B1⋅ B0) Figure 2. Generating an equivalent POS form for the truth table shown in Figure 2. you wrote the Boolean equation based on the rows of the truth table that contained a ‘1’. The other important thing to notice here is that there are many ways to modeling this input/output relationship of a digital circuit. Up until now. The remainder of this chapter deals with describing some of the other more popular approaches to representing functions and thus modeling digital circuits. The only 44 . As you have already found out. The sum of products form. is an equation that describes an input/output relationship of a module in terms of digital logic. function forms. you have seen three main approaches: the truth table. 2. The form of this equation is referred to as the sum of products (SOP) form. you found which rows contained a ‘1’ in the output and you included the product term for that row in the final Boolean equation. the theorems that are actually useful are used all the time. Although there are probably about a gajillion approaches to modeling a digital circuit. Another widely used Boolean equation form is referred to as the product of sums (POS) form. In other words. is probably the most widely used equation form in digital design land. These product terms are then logically added together to complete the equation. As you become more familiar with digital logic you’ll be able to go back and forth between these forms very quickly.14 is the same as the F column except the associated values are complimented. But for better or worse.7 is relatively long. The new representation of a digital circuit is derived from an application of DeMorgan’s theorem after gathering information from a truth table. solutions to digital problems. or more specifically.14 have a complementary relationship to each other. these three forms say the same thing but say it in three different ways. Figure 2. The POS form is obtained from the truth table in a way that is similar to the SOP forms. This section deals directly with using DeMorgan’s theorems to generate new representations. there are only a few standard approaches. the two right-most columns of Figure 2. there are many different ways of modeling this input/output relationship. In standard versions of digital logic courses. a Boolean function.6 and Table 2. But then again.13 shows once again the Boolean equation that describes a solution to that design problem. In other words. and thus. and a circuit model.Digital McLogic Design Chapter 2 2. There are two important things to notice here. F(B2.14 is similar to the approach for generating the SOP form. For this explanation. The good news is that you’ve seen three of the more standard approaches already. Secondly. Note the right-most column in Figure 2.

So now let’s generate an equation for F in POS form. X + Y = X ⋅Y X 1 + X 2 + K + Xn = X 1 ⋅ X 2 ⋅ K⋅ Xn X ⋅Y = X + Y X 1 ⋅ X 2 ⋅ K ⋅ Xn = X 1 + X 2 + K + Xn ☯+ +K + = ☯⋅ ⋅K⋅ ☯⋅ ⋅K ⋅ =☯+ +K+ Table 2. Table 2. The final form listed in Table 2. but also to emphasize the fact the “variables” shown in the previous equations are not necessarily Boolean variables as is implied by the equations.10 appears in the items listed below. 14 Be sure to note that looking for 1’s in the inverted output column is exactly the same as looking for 0’s in the noninverted output column. The approach to take is to list the product terms that have a ‘1’ on the output of the complimented output14.9: DeMorgan's theorem in two-variable and generalized forms.14: The truth table for the original problem with a complemented output added. and bowling. In either case. DeMorgan’s theorem is also useful in other fields such as discrete mathematics.9 is provided not only for its pure shock value. The explanation of each row in Table 2. In other words. you were interested in the rows of the truth table that had a ‘1’ for the output.Digital McLogic Design Chapter 2 difference is that we’ll need to apply DeMorgan’s theorems multiple times to get to the POS form we’re looking for. Let’s start this process by taking a look at DeMorgan’s theorem. This first step is similar to generating SOP form but you’re actually generating an equation in SOP form for the compliment of the output15. The symbols shown in the first two equations can be either simple Boolean variables or more complex Boolean expressions.9 shows DeMorgan’s theorems listed in both two variable and generalized forms.10 shows the set of equations generated by seeking a POS expression for the given function. the overbar applies to the entire expression that it covers. For the POS form. computer programming. DeMorgan’s theorem is one of the more commonly applied logic theorems in digital design-land. the complement of the output does not represent a solution for the given problem. 45 . B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 F 0 0 0 0 0 1 1 1 F 1 1 1 1 1 0 0 0 Figure 2. 15 Keep in mind that a complement of the output is not the desired output relative to the original problem. you’re not interested in the rows that have a ‘1’ on the output. Table 2. The key here is to notice that for the SOP form. This is especially true in the context of circuit forms because the theorem allows for the transformation of a circuit from one form to another.

(b) Both sides of the equation in (a) are complemented. The expression on the right side of the equals sign shows the results after the first application of DeMorgan’s theorem.Digital McLogic Design Chapter 2 (a) (b) (c) (d) (e) F = (B2 ⋅ B1⋅ B0) + (B2 ⋅ B1⋅ B0) + (B2 ⋅ B1⋅ B0) + (B2 ⋅ B2 ⋅ B1) + (B2 ⋅ B1⋅ B0) F = F = (B2 ⋅ B1⋅ B0) + (B2 ⋅ B1⋅ B0) + (B2 ⋅ B1⋅ B0) + (B2 ⋅ B2 ⋅ B1) + (B2 ⋅ B1⋅ B0) F = (B2 ⋅ B1⋅ B0) ⋅ (B2 ⋅ B1⋅ B0) ⋅ (B2 ⋅ B1⋅ B0) ⋅ (B2 ⋅ B1⋅ B0) ⋅ (B2 ⋅ B1⋅ B0) F = (B2 + B1 + B0) ⋅ (B2 + B1 + B0) ⋅ (B2 + B1 + B0) ⋅ (B2 + B1 + B0) ⋅ (B2 + B1 + B0) F = (B2 + B1 + B0) ⋅ (B2 + B1 + B0) ⋅ (B2 + B1 + B0) ⋅ (B2 + B1 + B0) ⋅ (B2 + B1 + B0) Table 2. This is an important distinction. In other words. they describe the same input/output relationship but they do so in different ways. (c) Since the double complement of a variable equals that variable. that is. 46 . Note that there are five product terms.7 Timing Diagrams 16 This may seem a little “follow the rules” oriented but it will make more sense later as we delve deeper into other digital design topics. which by some Boolean axiom or theorem. The SOP and POS forms are functionally equivalent. you now have an approach for generating both an SOP and POS form of equations describing a digital relationship. In particular. (e) The double complements are removed from the variables by an application of a basic Boolean algebra axiom. These are massively common forms so make sure you know and understand them. Complimenting both sides of an equation is an extremely common operation when dealing with Boolean algebra. Although this is a valid SOP form for the complemented output. The final result of this step provides the desired POS form. the giant overbar is now distributed to the individual product terms and the OR operators were changed to AND operators. Once again.10: Generating a POS form from multiple applications of DeMorgan's theorem. we’re looking for a POS form for the uncomplemented output. (a) This equation is SOP form generated by listing the product terms for the 0’s of the F column or the 1’s of the complemented F column. our ultimate goal is to have an equation for F in POS form so we still need to massage this equation in order to get it into POS form. 2. In summary. (d) DeMorgan’s theorem is applied to each of the product terms individually. preserves the equality. Note that the product terms are now all complemented and are ANDed together. The result is that we now have an expression for F. the doublecomplimented F on left side of the equals sign becomes uncomplemented. understand where these forms came from: the SOP form is generally associated with the 1’s of the circuit while the POS form is generally associated with the 0’s of the circuit16. Once again. the overbar is distributed to the individual components of the product terms and the logic operators are switched from AND to OR.

Once you understand the basics of timing diagrams. you’ll be dealing more with the second item. A digital circuit’s outputs react dynamically to the circuits inputs. but we’ve left it out in order to keep this discussion general. In this context. these signal changes are referred to as toggles in digital lingo. we can talk about time in general. 17 It takes time for the electrons to move around in the underlying sillycone. Keep in mind that nothing is instantaneous in actual digital circuits although we typically can model signal changes in circuits as being so. the circuit’s outputs must respond such that they continue to match the specifications for a given set of inputs. A digital circuit must operate over a given time span in order to “adapt” to the circuit inputs. Figure 2. For now. these flavors differ primarily in the voltage levels used to drive the hardware. (3) This timing diagram is similar to the timing diagram of (b) but the H and L have been replaced with 1 and 0.15: Example timing diagrams. the circuit’s inputs are generally expected to change. Figure 2. Although these representations are considered 100% accurate descriptions of the circuits. respectively. We opt to ignore voltage concerns by abstracting our digital designs to a higher level such that we don’t need to deal with voltage levels. the two values are referred to as H and L. Generally speaking. Keep in mind that the horizontal axis is considered the time axis in each of these timing diagrams. In other words. “important” could have many meanings. Because of this. only the important parts of the circuit are specified. we only use the term “time” but we have attached no metric such as “seconds” or “milliseconds” to the time. a description and comments regarding each of these timing diagrams is listed below. These dotted lines are sometimes omitted but are often included in more “busy” timing diagrams in order to increase the readability and understandability of the timing diagram. You’ll find out that although there are many ways to represent timing diagrams. This “timelessness” forms somewhat of an artificial representation of a circuit in that digital circuits actually operate over given periods of time17. voltage levels are an issue we can often not worry about. The line represents the value of digital signal in question. We’ll be going over a few of the more important ones in this section. these meanings start to surface. This is one of the many reasons digital circuits are so exciting. As we travel deeper into digital design land. In this case. When you’re actually designing and implementing circuits. There are many flavors of digital hardware out there. in a written text such as this one. we’ll only be dealing with the first item. Note that the signal has two values. which represent the high and low values of the signals.Digital McLogic Design Chapter 2 We currently have developed several methods to model digital circuits. you’ll be able to quickly adjust to any timing diagram symbology that you’ve not seen or used before. (1) This timing diagram shows line that seems to go randomly up and down. 47 . they are somewhat timeless in nature. timing diagrams are massively important in digital design-land for two main reasons: 1) timing diagrams are used to specify and/or model digital circuit operation18. Timing diagrams show a digital circuit’s operation over an arbitrary period of time. In other words.15 shows five example timing diagrams. which is what you would expect from a digital signal. and 2) timing diagrams are used to verify that digital circuits are operating as specified either by using some type of simulator or examining the waveform output from the actual circuit. 18 More often. the concepts of timing diagrams and their relation to digital circuits is not a complicated concept. There is some special terminology and symbology typically used in timing diagrams. This emphasizes the point that the two values of the digital signals are actually models representing some actual digital hardware. (2) This timing diagram explicitly shows the two values of the signals. we’re describing the digital operation of a circuit. when this change occurs. The signal shows various transitions from high-to-low and lowto-high. the signal is given a name. At this point in your digital design careers. For this example. more specific time metrics are introduced in other chapters. Also included in this timing diagram are the horizontal dotted lines which are used to show the high and low values of the signals.

the style of this timing diagram uses slanted lines. the signal toggles.15: Example timing diagrams. But once again.Digital McLogic Design Chapter 2 (4) This is another common style of modeling digital signals. While the previous timing diagrams used vertical lines to represent high-to-low and low-to-high transitions. At (c). The upper signal in the timing diagram is labeled ‘x’. One of the uses of timing diagrams is to represent the operation of digital circuits and devices. the intent of this timing diagram is to show the changes in the output (F) as a function of the input (x)20. At (b). At (e). for any one given instance of time. Note that the lines are always slanted in the direction of advancing time. the timing diagram shows how the x signal acts as a function of time. 20 19 48 . the timing diagram ends with the signal in a low state. (1) (2) (3) (4) (5) Figure 2. respectively.16 does indeed show the complimentary relationship between the input and output as you’d expect from an inverter. let’s demonstrate their operation with timing diagrams. Around the time indicated by (d).16 show an inverter and an associated timing diagram. At (a) in the timing diagram shows that the given signal is initially in a low state at the beginning of the timing diagram. or more simply stated. In reality. The signal names x and F are used to represent the input and output to the inverter. The signal activity shown in ‘x’ line is arbitrary. the signals cannot change state instantaneously as they seem to do in the other listed timing diagrams. Since we are currently familiar with three digital devices. toggles19. Toggling refers to switching states and includes both low-to-high and high-to-low transitions. the signal toggles two times (similar to (b) and (c)). the output is necessarily high or low (but never both). or once again. (5) The final timing diagram is nothing new. Figure 2. What we want to do is use this timing diagram to toss some typical timing diagram lingo at you. In other words. Keep in mind that once again shows the true functional relationship between the input (the independent variable) and the output (the dependent variable). the signal switches from a high state to a low state. it is generally more common in digital design land to model the signal transitions are occurring instantaneously. Figure 2. the signal switches from a low state to a high state.

Digital McLogic Design Chapter 2 Figure 2. Likewise.19 are once again arbitrary. the output is only high when both of the ‘x’ and ‘y’ inputs are high.17(b) shows that for an OR gate. (a) (b) Figure 2. are dependent upon the inputs. the value of the input variables over time is arbitrary.19 shows an example timing diagram associated with the truth table.19 represent particular moments in time.17(a).17: Example timing diagrams for an AND gate (a) and an OR gate (b). At each of these moments in time. Figure 2. there is nothing special about the input timing.19 uses some special notation to indicate that the timing diagram does indeed reflect the characteristics of the associated truth table. B1=’0’.17 shows example timing diagrams for AND and OR gates. For example. Note that the timing diagram includes the three inputs and one output listed in the truth table. the output is a ‘0’. Under these particular signal conditions. Note that in Figure 2.18 shows the truth table associated with this example while Figure 2. Keep in mind that for both timing diagrams of Figure 2. The input signal characteristics in Figure 2. the (1) label is used to indicate a match between the second row in the truth table where B2=’0’.17 once again match our previous description of AND and OR gate operation. 49 . let’s generate a timing diagram for the main example problem we used in this chapter. and B0=’1’. of course. the index into the truth table is provided to aid in your perusal of the timing diagram. Figure 2. The vertical dotted lines in Figure 2.17. The outputs. And for our final example. Figure 2. Figure 2.16: Example timing diagram for inverter. the output is only low when both of the ‘x’ and ‘y’ inputs are low. The two timing diagrams of Figure 2.

They will save your butt someday when your circuit is not working for some unknown reason. Timing diagrams are your friends: use them to help you understand what you’re doing and/or what you’re expected to do in digital design-land. 1. Here are a few more comments regarding timing diagrams. the “vertical” transitions in the signals indicate a discontinuity21 in the signal. The truth here is that you’re not being told the entire story regarding timing diagram. Technically speaking. Don’t fear them: there’s simply not that much to them. Figure 2.19 were chosen to such that they did not overlap any transitions on the input signals.19: Timing diagram for main problem specified in this chapter. 2. 50 . Please refer to your bulky book. 21 It’s one of those calculus terms. The truth is revealed in later chapters after you prove you worthiness to the digital gods and have sacrificed enough bits and time.18: The truth table for the original problem (Example 2-4). The vertical dotted lines in Figure 2.Digital McLogic Design Chapter 2 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 F 0 0 0 0 0 1 1 1 Figure 2.

This problem is a case of going from a circuit model implemented in SOP to a circuit implementation in POS form. The resulting equation is: F ( A. Looking back at Table 2. 22 To “DeMorganize” means to apply DeMorgan’s theorem. 6) use the derived POS equation to re-implement the circuit. 4) solve for the complemented output. This term was coined by the infamous Professor Freeman Freitag sometime in the mid-1980s. and timing diagrams. The entire procedure is listed below for both product terms. for any given relationship. and finally. there are functionally equivalent ways to represent the relationship. you can see that you’ll have two product terms (two AND gates) that are logically added together (one OR gate). 51 . from the circuit. Here we go. The problem right now is that both of the product terms are missing an independent variable which we’ll need to add. This being the case. you’ve seen several equation forms (SOP & POS). As you’ve seen already. we need to make this look like a more familiar SOP form in order to transfer the equation to a truth table. there are many ways to represent a functional relationship in digital-land. The circuit is in SOP form. we’ll solve this problem in sort of a strange way. The we’ll take is as follows: 1) write out the equation implemented by the circuit. you’ll find that 9b is the theorem we’re looking for: x + x = 1 . There are actually many ways to do this but since you know so little (at the present stage in your digital career). 3) use the equation to fill in a truth table.Digital McLogic Design Chapter 2 Examples Example 2-5: Change the following circuit implementation from a SOP to a POS form. We’ll add it by multiplying the first product term by (C + C ) = 1 (according to 9b in Table 2. you should be able to go from any one form to any other form. Note the first product term is missing the C variable. The way we’ll do this is to logically multiply the equation by ‘1’.6) which officially does not alter the value of the product term. a comment. 2) expand the equation to something that looks like a more familiar SOP form. B. C ) = A ⋅ B + A ⋅ C 2) Although this equation is officially in SOP form. Solution: First. 5) complement the equation and DeMorganize22 the result until you have the equation in POS form. That is. truth tables.6. 1) Write out the equation implemented by the circuit.

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 1 ( A ⋅ B ⋅ C) 0 1 ( A ⋅ B ⋅ C) 1 ( A ⋅ B ⋅ C) 1 ( A ⋅ B ⋅ C) 0 0 4) The next step is to solve for the complemented output. B. this result appears below the following table. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 1 0 1 1 1 0 0 F 1 0 1 0 0 0 1 1 F ( A. Note that a ‘1’ is placed in the F column for the corresponding product terms in the equation derived in the previous step of this solution. The steps in this process are shown below. C ) = A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C 3) Now that the terms look familiar. they can be entered into a truth table. We want an expression for F so we must complement both sides of the equation and DeMorganize the result a bunch of times. This is done the long way by adding a complemented F column to the previous truth table. From the table below we can write an SOP equation for the complemented output. B. A ⋅ C = A + C ⋅ ( B + B) A⋅C = A⋅C ⋅ B + A⋅C ⋅ B A⋅C = A⋅ B ⋅C + A⋅ B ⋅C F ( A.Digital McLogic Design Chapter 2 A ⋅ B = A ⋅ B ⋅ (C + C ) A⋅ B = A⋅ B ⋅C + A⋅ B ⋅C The final equation is listed below. 52 . C ) = A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C 5) The final equation is an expression for F-bar (another way of saying a complemented F).

C ) = A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C F ( A. This is not. C ) = A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C F = ( A ⋅ B ⋅ C) ⋅ ( A ⋅ B ⋅ C) ⋅ ( A ⋅ B ⋅ C) ⋅ ( A ⋅ B ⋅ C) F = ( A + B + C) ⋅ ( A + B + C) ⋅ ( A + B + C) ⋅ ( A + B + C) F = ( A + B + C) ⋅ ( A + B + C) ⋅ ( A + B + C) ⋅ ( A + B + C) 6) And finally. B. representative of digital design. 53 . This problem is more of a drill problem to help you understand and apply some of the principles that were discussed in this chapter. This turned out to be a long problem. however.Digital McLogic Design Chapter 2 F ( A. the last step is to draw a circuit model for the final equation of the previous step. B.

from the circuit. Solution: The solution to this problem is similar to the previous problem. 1) Write out the equation implemented by the circuit.Digital McLogic Design Chapter 2 Example 2-6: Change the following circuit implementation from a POS to a SOP form. C ) = ( A + B) ⋅ ( A + C ) 2) We need to put the above equation into SOP form so we can easily enter its information into the truth table. the steps are the same but you need to apply them in reverse order. we’ll get an expression for F-bar in SOP form. you can see that you’ll have two sum terms (two OR gates) that are logically multiplied together (one AND gate). F = A⋅ B + A⋅C F = A ⋅ B ⋅ (C + C ) + A ⋅ C ⋅ ( B + B) F = A⋅ B ⋅C + A⋅ B ⋅C + A⋅ B ⋅C + A⋅ B ⋅C 54 . We’ll use the same approach as before. B. F = ( A + B) ⋅ ( A + C ) F = ( A + B) ⋅ ( A + C ) F = ( A + B) + ( A + C ) F = A⋅ B + A⋅C 3) From here we need to expand each of the product terms to include each of the independent variables. The resulting equation is: F ( A. If we complement both sides of the equation and then DeMorganize it. The circuit is in POS form.

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4) The equation above tells us where the 0’s live in the truth table. If we know where the 0’s live, we also know where the 1’s live and that is what we’re looking for in order to give us an equation for this function in SOP form. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 0 1 1 1 0 1 0

F

1 1 0 0 0 1 0 1

5) Now we can write an equation for F.

F = A⋅ B ⋅C + A⋅ B ⋅C + A⋅ B ⋅C + A⋅ B ⋅C

6) And the final step is to draw a model for the final circuit implementation.

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Design Examples

Example 2-7: Half Adder Design a circuit that adds two bits. The output of this circuit should indicate the sum of the added bits and whether the addition operation has generated a carry-out or not. This circuit is one of the most basic circuits in digital design and is known as a Half Adder, or HA. Solution: Although at this point you may not feel as if you know too much about digital design, you truly know enough to design a significant and relatively important digital circuit. With a quick example, we can drive home the design point and have a crapload of fun in the process. You may require some background in order to do this problem. While performing a mathematical operation using decimal numbers is no big deal for you, performing a similar operation using binary numbers requires a special, slightly altered state of consciousness23. What you’ll soon discover, if you have not discovered it already, is that performing mathematical operations in decimal and binary follows the same rules. The only difference is that the binary number system only contains two symbols: ‘0’ and ‘1’. If you were to add two, single-digit, decimal numbers, your result would either be a single digital (less than ten) or two digits (greater than ten). Looking at that in another way, operation results greater than or equal to the radix are represented by two digits while results less then the radix are represented with a single digit. In the case of the two digit result, one digit represents the result of the addition while the other digit represents the value that “carried-out” from the single-bit addition. The same is true for binary addition. There are only four different possible results for binary addition of single bit: Table 2.11 shows these four possibilities as well as the SUM and Carry-out results. The only item of relative interest in Table 2.11 is the fact that adding ‘1’ to ‘1’ results in a sum of ‘0’ with a carry-out of ‘1’. If you consider the Carry-out to be the MSB and the sum to be the LSB, the total result is “10” which is the binary equivalent of 2 (two) in decimal24. So much for the background, now let’s tackle the actual design process. Operation 0+0 0+1 1+0 1+1 SUM 0 1 1 0 Carry-out (CO) 0 0 0 1

Table 2.11: All possible single-bit addition operations with sum and carry results.

Step 1) Define the Problem: The problem statement for this problem represents a good start at defining this problem. As with all problems, draw a high-level diagram of the final circuit. From the problem statement, you can see that this circuit contains two inputs and two outputs. Figure 2.20 shows the two

23 24

Not really. OK, I saw a student with the following words written on his t-shirt “There are 10 types of people in the world, those who understand binary and those who do not”. Even my TA has the shirt. If this saying is copywritten, then feel free to sue the life out of me. Thanks.

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inputs (arbitrarily named OP_A and OB_B)25 and two outputs SUM and CO. Table 2.12 and Table 2.13 show the empty truth table (only the independent values are listed) the completed truth table for this design. In the design process, you generally start out with an empty table and then proceed to fill in the independent and dependent values (the inputs and outputs, respectively) in that order. If you don’t do it in this order, no special penalties are applied.

Figure 2.20: The black-box diagram for the example problem.

OP_A 0 0 1 1

OP_B 0 1 0 1

SUM

CO

OP_A 0 0 1 1

OP_B 0 1 0 1

SUM 0 1 1 0

CO 0 0 0 1

Table 2.12

Table 2.13

Step 2) Describe the Solution: Note that for this problem, you’ll need to generate two Boolean expressions: one for the SUM and the other for the CO. For this problem, we’ll use SOP form since the problem statement did not specify a preference. The final equations are written by logically summing the product terms associated with rows in which 1’s appear.

SUM = OP _ A ⋅ OP _ B + OP _ A ⋅ OP _ B

CO = OP _ A ⋅ OP _ B

Equation 2-1: The final equations for Example 2-7.

Step 3) Implement the Solution: The final step involves translating the Boolean expressions listed in Equation 2-1 into circuit form. Figure 2.21 shows the final gate-level implementation.

25

Although you could choose just about any signal names for the inputs and outputs, you should assign names that are self-commenting. In other words, OP_A (operand A) is arguably a better label than FINGER_NAIL although both labels are equally valid.

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Figure 2.21: The circuit representation of the final solution for Example 2-7.

In case you don’t see it yet, you’ve officially designed one of the basic circuits in digital design-land: the half-adder (HA). In other words, the circuit shown in Figure 2.21 adds two bits and generates a result. The two inputs are digital values as are the two outputs. If you were to purchase the appropriate digital circuitry, you could actually set up this circuit and make it work.

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Chapter Summary • Number Structure: Numbers represent quantities that are too big for our brain to understand and

process. Numbers are formed by using a basic set of symbols associated with the particular radix in question. Numbers use juxtapositional notation to represent quantities larger than the numbers represented by the associated symbol set. Weightings are assigned to digit positions and each position in a number has a different weighting. Numbers are comprised of both integral and fractional portions which are delineated by a radix point.

**• Binary Numbers and Digital Design: Binary numbers are used in study of digital design because of
**

the fact that a binary number nicely models the high-voltage vs. low-voltage relationship in the underlying transistor implementation of digital circuits.

**• Digital Design: The design of a digital circuit is driven by the need to solve a problem. The basic
**

process of digital design can be described in three steps: 1) define the problem, 2) describe the solution, and 3) implement the solution. Solutions to digital design problems are often described with Boolean equations which have their basis in Boolean algebra. There are many possible ways to represent solutions to digital design problems. These many solutions are considered functionally equivalent in that they all describe the same thing but do so in different ways.

**• SOP and POS Representations: Two of the most common ways to represent Boolean functions are
**

using sum-of-products (SOP) and product-of-sum (POS) forms. DeMorgan’s theorems are probably the most important theorems in digital design and are used to generate functionally equivalent forms.

**• Timing Diagrams: One common and useful approach to modeling digital circuits is a timing
**

diagram. Timing diagrams show the state of signals over a given span of time. Timing diagrams explicitly show the functional relationship of digital circuits in that for every unique set of inputs, there is only one unique set of outputs. Timing diagrams use a signal’s value (most often either ‘1’ or ‘0’) as the independent variable (the vertical axis) and time as the dependent variable (the horizontal axis). Complete timing diagrams can be used to completely specify a digital circuit’s correct operation.

•

Important Standard Digital Modules Presented in this chapter: • Half Adder (HA)

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Chapter Exercises

1) Generate a Boolean equation that is equivalent to each of the following truth tables in both SOP and POS forms.

B2 0 0 0 0 1 1 1 1

B1 0 0 1 1 0 0 1 1 (a)

B0 0 1 0 1 0 1 0 1

F 0 1 1 0 1 0 0 0

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1 (b)

F 1 0 1 1 0 1 0 0

X 0 0 0 0 1 1 1 1

Y 0 0 1 1 0 0 1 1 (c)

Z 0 1 0 1 0 1 0 1

F 0 0 0 1 1 1 0 0

t 0 0 0 0 1 1 1 1

u 0 0 1 1 0 0 1 1

v 0 1 0 1 0 1 0 1 (d)

F1 1 1 0 0 0 1 0 0

F2 0 0 1 1 0 0 1 1

2) Convert the following functions to POS form and truth table form. a) b) c)

F ( A, B, C ) = A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C F ( A, B, C ) = A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C F ( X ,Y , Z ) = X ⋅Y ⋅ Z + X ⋅Y ⋅ Z + X ⋅Y ⋅ Z + X ⋅Y ⋅ Z

3) Convert the following functions to SOP form and truth table form. a) F ( R, S , T ) = ( R + S + T ) ⋅ ( R + S + T ) ⋅ ( R + S + T ) ⋅ ( R + S + T ) ⋅ ( R + S + T )

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b) c)

F ( A, B, C ) = ( A + B + C ) ⋅ ( A + B + C ) ⋅ ( A + B + C ) ⋅ ( A + B + C ) F ( X ,Y , Z ) = ( X + Y + Z ) ⋅ ( X + Y + Z ) ⋅ ( X + Y + Z ) ⋅ ( X + Y + Z )

4) Draw a circuit representation for the following Boolean equations: a)

F ( X ,Y , Z ) = X ⋅Y ⋅ Z + X ⋅Y ⋅ Z + X ⋅Y ⋅ Z + X ⋅Y ⋅ Z

b) F ( R, S , T ) = ( R + S + T ) ⋅ ( R + S + T ) ⋅ ( R + S + T ) ⋅ ( R + S + T ) ⋅ ( R + S + T )

5) Did you notice anything strange or unique about the solution for the previous problem? 6) Use the following equation to complete the listed timing diagram.

F ( A, B, C ) = A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C

7) Use the following equation to complete the listed timing diagram.

F ( R, S , T ) = ( R + S + T ) ⋅ ( R + S + T ) ⋅ ( R + S + T ) ⋅ ( R + S + T ) ⋅ ( R + S + T )

8) Fill in the output for the following timing diagram based on a HA.

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9) Represent a half-adder (HA) with in POS form. Show both the equations and circuit form of this solution.

10) For the following two circuits, change the form from either POS to SOP.

(a)

(b)

11) For the following circuit, change the circuit to a have an output for F in SOP form.

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Design Problems

1) Design a circuit that has three inputs and two outputs. One of the outputs indicates when the 3-bit input value is less than three; the other output indicates then the input is greater than five. Provide the equations that describe your circuit in SOP form. Implement the final circuit using AND gates, OR gates, and inverters. 2) Design a circuit that has three inputs and two outputs. One output indicates when the three inputs (considered a binary number) are even; the other output indicates when the three input bits are odd. Implement the final circuit using AND gates, OR gates, and inverters. 3) Design a circuit whose 3-bit output is two greater than the 3-bit input. The binary count should wrap when the output value is greater than 1112. Complete the following timing diagram based on your design.

4) Design a digital circuit that controls a switch box according to the following specifications: If either one (and only one) or two (and only two) of the three input switches are on, the output is on. For this problem, assume that “on” is represented by a ‘1’. Use SOP form for your output equation. Implement your final circuit using AND gates, OR gates, and inverters. 5) Redo the previous problem but use POS form in both your equation and final implementation. Compare the two different approaches to these circuits: explicitly list the device count for each implementation (a device is either a AND, OR, or inverter).

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3

Chapter Three

3.1

Introduction

Our approach to this point in digital logic design was to present digital logic basics and the basics of digital circuit modeling. Unfortunately, this introduction was somewhat on the quick side and many of the finer points of both topics were not covered in order to allow you to actually design and model some digital logic circuits from start to finish. This chapter adds some more knowledge and techniques that help you design and/or represent digital circuit. This chapter also adds another flavor of design which is inherently more powerful (in some situations) than the BFD approach discussed in the previous chapter.

**Main Chapter Topics
**

STANDARD LOGIC GATES: This chapter introduces the exclusive OR (XOR) and exclusive NOR (XNOR) gates. STANDARD FUNCTION REPRESENTATIONS: This chapter introduces several standard methods used to represent functions and the terminology associated with these representations. FUNCTION REDUCTION USING KARNAUGH MAPS: This chapter introduces the concept of function reduction, and in particular, function reduction using Karnaugh maps. ITERATIVE MODULAR DESIGN (IMD): This chapter introduces the notion of iterative modular design in the context of a standard digital circuit.

(Bryan Mealy 2011 ©)

3.2

More Standard Logic Gates

Although AND and OR gates implement the most basic digital logic functions, AND and OR gates are not the most widely used gates. In reality, AND and OR gates have some limitations that are not shared in the two most common digital logic gate-types: NAND and NOR gates. In addition to these gates, the XOR and XNOR gates are also widely used in digital design-land. The NAND gate and NOR gate are formed by complementing the output of AND and OR gates, respectively. The names NAND and NOR are a shortened version of NOT-AND (for NAND) and NOTOR (for NOR). Figure 3.1 shows that the NAND and NOR gates can be modeled by adding an inverter on the output of the AND and OR gates. Inverting the AND and OR gate outputs can be considered as creating a new functional relationship and is thus rewarded by a unique gates symbols for these two new functions. The two new gate symbols for the NAND and NOR gates are shown in Figure 3.2. Most appropriately, Figure 3.3 shows the truth tables associated with the NAND and NOR functions. Note that in Figure 3.3, the truth tables show that the outputs of the NAND and NOR gates are in fact complimented versions of AND and OR gates, respectively.

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(a)

(b)

Figure 3.1: Functional equivalent models for the NAND (a) and NOR (b) logic gates.

(a)

(b)

Figure 3.2: The NAND (a) and NOR (b) logic gates.

A 0 0 1 1

B 0 1 0 1 (a)

F = A⋅ B

A 0 0 1 1

B 0 1 0 1

F = A+ B

1 1 1 0

1 0 0 0 (b)

Figure 3.3: Truth tables for the NAND (a) and NOR (b) logic functions.

There are actually several reasons why NAND and NOR gates are used more often than AND and OR gates. One thing to keep in mind is that all logic gates are implemented by placing transistors into a circuit such that they create the desired logic functions. From a standpoint of the underlying transistor implementation, there is no direct advantage to using a AND gate instead of a NAND gate. One of the advantages that NAND and NOR gates do have over AND and OR gates is that they are considered to be functionally complete. This means that a NAND gate (or a series of NAND gates) can be used to implement any Boolean function1. In other words, a single NAND gate can be used to generate an AND function, an OR function, or a complement function (INVERTER). While some of the details of this statement are beyond what you need to know now at this point, you can see from the truth table for the NAND gate in Figure 3.3(a) that there are two possible ways to create an inverter from a NAND gates. Using a NAND gate to generate an AND function is obtained by adding an inverter to the output of the NAND gates. Using a NAND gate to generate an OR function is a topic covered in a later chapter. Rows 1 and 4 of the NAND gate’s truth table (shown in Figure 3.3(a)) indicate that if the two inputs to the NAND gate are equivalent, the output is an inversion of the input. This is implemented in actual hardware by connecting a single signal to both inputs of the NAND gate; this result is shown in Figure 3.4(a). Rows 3 and 4 of the NAND gate’s truth table indicate that if one of the inputs to the NAND gate is fixed to a logic ‘1’, the output of the NAND gate exhibits an inversion function based on the other input. This is

1

The same is true of a NOR gate; the details are not provided here.

65

7. These equations differ slightly from the definitions of the previous gates we’ve dealt with.6 provide the official definitions for the XOR and XNOR functions. you’ll use these equations often in digital design.4: Making an inverter from a NAND gate. Note that in these equations that the XOR function has its own special operator symbol: the circled cross.5 shows the schematic symbol for these two gates.4(b) shows this relationship. The truth tables shown in Figure 3.Digital McLogic Design Chapter 3 implemented in hardware by connecting one of the NAND gate inputs to the high voltage in the system you’re working with. Figure 3. One final thing to note here is that the XNOR gate is often referred to as an equivalence gate because the gate output is a logical ‘1’ when the two gate inputs are equivalent. You can see this relationship from the XNOR definition of Figure 3.7 shows the official Boolean equations describing the XOR and XNOR functions. The leads to the fact that the XOR and XNOR are often described in terms of the equations listed in Figure 3. Note that the XOR and XNOR functions are complements of each other as is true with the OR and NOR gates. The final type of logic gates that we’ll introduce in this chapter are the exclusive OR or XOR gate and exclusive NOR gate or XNOR gate. Note the similarity between these gates and the OR and NOR gate symbols. (a) (b) Figure 3. There is also a special operator for XNOR gates which is not shown2 in Figure 3. Figure 3.7 are both important and useful. Whereas the AND/NAND and OR/NOR gates are defined by the basic axioms of Boolean algebra. 66 . sometimes the simple OR gate is referred to as an inclusive OR gate as opposed to the exclusive OR gate we’re dealing with now.6(b).5: The exclusive OR (XOR) and exclusive NOR (XNOR) gates. You may want to stare at them for awhile.7(b): the circled dot. the XOR/XNOR gates are not. 2 The equation editor I used when writing this does not contain the required symbol. The equations in Figure 3. Figure 3. (a) (b) Figure 3. Moreover.

We eventually went on to describe Equation 3-1 as sum-of-products form (SOP) but that is not the whole story.Digital McLogic Design Chapter 3 A 0 0 1 1 B 0 1 0 1 (a) F = A⊕ B 0 1 1 0 A 0 0 1 1 B 0 1 0 1 F = A⊕ B 1 0 0 1 (b) Figure 3. for your convenience. this equation is actually listed in what is known as standard SOP form. Figure 3. We’ll be picking up other ways as we progress through this text. The functions are defined such that they describe an input/output relationship of a digital circuit. keep in mind that you should be able to translate any one function representation to any other function representation. There are a lot of ways to represent functions in digital-land. F = A ⊕ B = AB + A B (a) F = A ⊕ B = A B + AB (b) Figure 3.1 Minterm & Maxterm Representations Without you knowing it. From the truth table of Figure 3. but once it is derived (from whatever method you used to derive it) you need to somehow represent it.8. The design part of digital design has to do with deriving the function. You know that the equation is in SOP form because you can see the product terms being summed together. As it turns out. let’s return to the design overview example used in the previous set of notes. you generated the Boolean function shown in Equation 3-1 to describe the information shown in the truth table. So what makes it a standard SOP form? 67 .7: The official equations describing the XOR and XNOR functions. this section presents a few of the more popular ways. For this section.8 shows the equation for this function.3. Once again. 3. you’ve already been exposed to minterm representations and maxterm representations of functions.3 Representing Functions A significant part of designing digital circuits is often centered about implementing functions. 3.6: Truth tables for the exclusive OR (XOR) and exclusive NOR (XNOR) functions.

there is also going to be a standard product of sums (POS) form which contains standard sum terms that are logically multiplied together. this form is sometimes referred to as a maxterm expansion. As you see from Table 3.1. and B0 to A. Or equivalently. F = B2 ⋅ B1⋅ B0 + B2 ⋅ B1⋅ B0 + B2 ⋅ B1⋅ B0 Equation 3-1 Equation 3-1 is considered a standard SOP form because each of the product terms contains only one instance of each of the function’s independent variables. In this case.C) function. Equation 3-3 shows the standard POS form of the function. Another term that gets kicked around sometimes is that fact that an equation listed in standard SOP form is often referred to as a minterm expansion of the function. The main difference between minterms and maxterms is that maxterms describe the locations of the 0’s in the function’s output.8: The generic function used in a previous chapter. and C to make things easier for the lazy author). Note that the independent variables in the product terms can appear in either complemented or uncomplimented form. F = A ⋅ B⋅ C + A ⋅ B⋅ C + A ⋅ B⋅ C Equation 3-2 As you have probably guessed. 68 .B.Digital McLogic Design Chapter 3 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 F 0 0 0 0 0 1 1 1 Figure 3. B.1 shows the product terms for three-variable (A. the product terms have also been labeled as minterms which is simply another name for a standard product term. a standard sum term is referred to as a maxterm. maxterms describe the 1’s in the output of the complemented function. Equation 3-2 shows the standard SOP form of the function from the previous example (note that we’ve switched from B2. B1. The product terms in Equation 3-1 are considered something special in that they are standard product terms3. F = (A + B + C) ⋅ (A + B + C) ⋅ (A + B + C ) ⋅ (A + B + C) ⋅ (A + B + C) Equation 3-3 3 Later in this set of notes you’ll see that listing all the terms as standard product terms not generally done. Each row in the truth table has a unique product term associated with it. When we’re describing a function using product terms. Table 3. we simply list the product term associated with the row in the truth table that contains an output of ‘1’.

1: A listing minterms and maxterms for the each combination of circuit inputs. you first complement it and then tweak it using DeMorgan’s theorem. C ) = F (1.9.10: Examples showing the complimentary relationship between minterms and maxterms. B. and as the names implies.10(a).0. The compact minterm and 69 . In Figure 3.0.0) = A + B + C F ( A.0) = A ⋅ B ⋅ C F ( A. 3. F ( A. For a given row in the truth table. C ) = F (1.10 shows an example of this relationship for the fourth row in Table 3.0) = A ⋅ B ⋅ C F = A+ B+C F = A+ B+C (a) F ( A. representing functions in standard SOP or POS forms is somewhat klunky. the compact minterm form or the compact maxterm form is usually used instead. To remedy this. B. As a final note here.0.1.2 Compact Minterm & Maxterm Function Forms As you can clearly see.3. it’s a lot less work than the standard forms. C ) = F (1. there is a special relationship between the minterms and maxterms. the equation for the given minterm is complimented and then DeMorganized to provide the associated maxterm.0) = A + B + C F = A⋅ B ⋅C F = A⋅ B ⋅C (b) Figure 3. B.9: The secret relationship between minterms and maxterms. Figure 3. Minterm = Maxterm Maxterm = Minterm Figure 3. C ) = F (1. This fairly easy to do. To generate a minterm from a maxterm (or vice versa). B.0. the minterms and maxterms are compliments of each other as is shown by the equations in Figure 3.Digital McLogic Design Chapter 3 A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 minterm maxterm F 0 0 0 0 0 1 1 1 index 0 1 2 3 4 5 6 7 A⋅ B ⋅C A⋅ B ⋅C A⋅ B ⋅C A⋅ B ⋅C A⋅ B ⋅C A⋅ B ⋅C A⋅ B ⋅C A⋅ B ⋅C A+ B +C A+ B +C A+ B +C A+ B +C A+ B +C A+ B +C A+ B +C A+ B +C Table 3.

Figure 3. and 3) make your circuit consume less power.12 shows the two main equation forms for the previous example. while switching from one form of a function to another is excruciatingly exciting. these two forms look significantly different but are actually functionally equivalent.1. standard POS. As you know. One final comment on the different function forms. all of these different forms are functionally equivalent. these are the standard SOP and standard POS forms. You’ve already have been exposed to functionally equivalent circuit of different sizes with the example we’ve been using over the course of this and the previous chapters. In other words.7) (a) F ( A. Greek symbols have been used for this process with the summation symbol used for listing minterms (since it is a “summing” of product terms) and the capital Pi symbol used for listing maxterms4.3 Reduced Form Representation: Karnaugh-Maps There are three main recurring themes present in modern digital design: 1) make your circuit smaller. B. The final result is that if you can make the circuit “smaller” life is good. the word “smaller” has many connotations. faster. 70 .1) associated with where the 1’s and 0’s of the circuit reside in a given truth table. you would not be able to properly list a standard sum or standard product term. compact minterm. you would choose the standard SOP form because there would be less work to do. Implicit in this definition is that the two circuits in question are functionally equivalent. 6 There is a famous quote out there in digital land: “smaller. standard SOP. Figure 3. One important thing to note here is that these compact forms always need to be listed as a function of the independent variables. As you’ll see later in your engineering careers. For the purpose of this chapter. but it’s actually more complexicated than that.12 is that if you had to implement this circuit using discrete gates and wires and all that ugly stuff. C ) = ∏ (0. as most digital design textbooks typically lead you to believe. compact maxterm. it certainly does not represent true digital design. But honestly. We’ll work more with this later. As you may guess. 5 And also timing diagrams. You’ve now have learned the following ways to represent functions: truth tables.3. your circuit operates faster and consumes less power. we’ll define one circuit to be smaller than another circuit if it uses less gates and/or if the gates in the circuit contain less inputs. F ( A. if your circuit is smaller. There is one main problem with the previous statement: we have not defined the word “smaller”. you’ve never be able to achieve all of these things with the current digital technology6. and circuit forms5. sort of. 2) make your circuit faster.Digital McLogic Design Chapter 3 maxterm forms are simply a case of listing the decimal index (shown in the right-most column of Table 3. less power… choose any two”. particularly in digital design-land. Some of the function forms are easier to represent when the circuit is in reduced form (no one wants to draw a large circuit on a piece of paper if there is a smaller equivalent circuit. B.4) (b) Figure 3. Generally speaking. I’m not sure who said this. 3.2. 4 If you consult the right source.11: Compact minterm and maxterm forms for the current example. These forms are closely related in that they essentially provide multiple ways of representing the same thing.11 shows the compact minterm and compact maxterm forms for the example we’re working with. Traditionally. you’ll find that the Pi symbol is associated with multiplication. C ) = ∑ (5. This is not the right source. This being the case. you should be able to change from any one of the forms to any other one of the forms. Making the circuit “smaller”. Beginning digital design students are primarily concerned with the first issue: making your circuit smaller.6. What should be obvious from looking at Figure 3. If you did not include all of the independent variables. regardless of the number of gates or gate inputs.3.

Your time is valuable and you do make mistakes. B0) = (B2 ⋅ B1⋅ B0) + (B2 ⋅ B1⋅ B0) + (B2 ⋅ B1⋅ B0) F(B2. B1.8. Karnaugh maps are essentially a tool to visually apply the Combining theorem (which was listed in the previous chapter and once again here for you convenience). 14a ( x ⋅ y) + ( x ⋅ y) = x 14b ( x + y) ⋅ ( x + y) = x Combining Table 3. If you felt so inspired to write your own program. a significant component in most introductory digital design courses is to make students reduce functions using the list of theorems presented in the previous chapter.2: The Adjacency theorem in living color. The computer is limitless in the number of independent variables it can handle and does not make mistakes.13: 71 . There are a few important things to note about the K-map of Figure 3. there are also many algorithms out there that you could code up and have them reduce functions for you. use Karnaugh Maps. But this is simply not the case for several reasons. if you really had to reduce a function and needed to know that you did the right thing. Figure 3.13 shows an empty three-variable K-map and a threevariable K-map including the output data from Figure 3. First. Use a computer to reduce functions when you can. B1. If this was the only way to reduce a function. Secondly.8 into a special diagram referred to as a Karnaugh map. there are better ways to reduce functions by hand (and we’ll be learning those ways in this section). B0) = (B2 + B1 + B0) ⋅ (B2 + B1 + B0) ⋅ (B2 + B1 + B0) ⋅ (B2 + B1 + B0) ⋅ (B2 + B1 + B0) Figure 3. There are actually many programs out there that reduce functions for you. Reducing functions.12: Two functionally equivalent forms of the example circuit. (a) (b) Figure 3.13: An empty Karnaugh map and a K-map that contains a functional relationship.Digital McLogic Design Chapter 3 or reducing it. everyone would need to learn to reduce functions with the various digital theorems. or function reduction refers to the practice of making the function representation smaller without changing the overall input/output relationship of the function. is the main these of this section of verbage. if you can’t use a computer. Jumping right into it… what we want to do is enter the information shown in Figure 3. you would use a computer. F(B2. Unfortunately. The Combining theorem is usually referred to as the Adjacency theorem which is going to be a better definition for our purposes.

the B variable is not included in the product term. This is going to seem somewhat funny at first but… you’ll quickly get the hang of it. There are three distinct parts to performing K-map reduction: 1) entering the function data into the K-map. or cell. vertical does not mean much in this example.14: The K-map with groupings (a) and the reduced equation (b). A similar argument can be made for the C variable but we’ll not bore you with the details. we’ll deal with why and how we made these grouping next. Figure 3. The approach from here is to start making groupings of 1’s in the K-map in Figure 3. For the grouping made with the solid line in Figure 3. 2) making the groupings in the K-map. F = AB + AC (a) (b) Figure 3.13(b). Writing down the equations from a K-map is a simple matter of listing (in product term form) where the grouping resides in the K-map in terms of the independent variables. We’ve covered the first topic for 3-variable K-map. Figure 3. the top row of the K-map is associated with the complement of input A while the bottom row of the K-map is associated with the uncomplimented A. Figure 3. There is necessarily one K-map cell for each row in the truth table.1.14(a). the data associated with the output variable is placed into the corresponding cell in the K-map. you should be able to see that it lives in the A row and the two C columns. What this does mean is that cell 4 is adjacent to cell 6 despite the fact that they don’t appear to be connected.Digital McLogic Design Chapter 3 • Each square. • There are major portions of the K-map that are associated with a given state of each input variable. they are functionally equivalent. Once again. each cell in the K-map is adjacent to cells in the horizontal and vertical directions.12. In other words. The result is the product term AC. and now we’ll cover how to write equations for the groupings you made in step 2). Note that the equation in Figure 3. and 3) generating the equation to represent the groupings. the right-most four cells of the K-map are associated with the uncomplimented B variable wile the left-most four cells of the K-map are associated with the complimented B. For example. This jog becomes more pronounced for the 4-variable K-map which we’ll deal with soon. in the K-map contains a number which is an index into the original truth table of Table 3. What you need to know now is that the numbering system used in the K-map has a funny jog in it.14(a) shows the groupings we’ll make. aside from the fact that these equations appear different.14(b) shows the final grouping associated the two groupings made in Figure 3. Note that the complimented C variable appears on left-most and right-most rows of the K-map. A similar argument can be made for the grouping made with the dotted line: this grouping lives cleanly in the A row and the two B columns and thus generates a product term of AB.14(a). Similarly.14(b) shows the two product terms associated with the grouping shown in Figure 3. Of course. Since this grouping resides in both the B and complemented B columns. Since a unit-distance code has been used.14(b) is much “smaller” or more “reduced” than the equations shown in Figure 3. • The K-map includes a funny numbering system which is referred to as a unit-distance code (discussed in a later chapter). 72 .14(a).

Karnaugh maps inherently generate reduced SOP forms.14(a) follow the rules in Figure 3. Once you have grouped the 0’s. you must apply DeMorgan’s theorem. For the POS form. What you’ll find in many digital design textbooks is that there are a set of rules that list exactly how to make the groupings. 1) Groupings must contain either 1. 8. however. These rules. F = A + BC F = A + BC F = ( A) ⋅ ( BC ) F = A ⋅ (B + C) F = A ⋅ (B + C) (a) (b) Figure 3. you need complement the generated equation and apply DeMorgan’s theorem to generate the final POS expression.Digital McLogic Design Chapter 3 The next step is learning the basic rules of making the groupings. Keep in mind that it is massively important to be able to generate either a reduced SOP or POS form using K-maps. Kmaps can also be used to generate reduced POS forms. In case you didn’t notice. you’ll be a K-map superstar. you’re able to generate a SOP equation for the complimented output function. or 16 cells 2) Groupings must have four corners (such as squares or rectangles) 3) Make the groupings as large as possible (cover as many cells as possible with one grouping while following the previous two guidelines) 4) Make as few groupings as possible to cover the “cells of interest” Figure 3. you’re grouping 0’s which creates an SOP expression for the complemented function. There are a few tricks8 associated with using K-maps. From there. 4. Despite this fact. Figure 3. These rules are generally hard to follow because they generally span about a full page of the text. These are not really tricks. you must start the process by grouping the 0’s in the K-map7. once you see and use these tricks a few times. can be condensed into the three rules listed in Figure 3.15. Notice in the groupings made in Figure 3. as with the truth table approach to generating a POS form from a SOP for of the complemented output. 73 . From there.16: The K-map with groupings (a) and the reduced equation (b). The grouping of terms to generate POS forms follows the same rules as the SOP forms but with one exception: for POS forms.15. 2.15: The three rules of generating K-map groupings. they’re actually only groups that are not patently obvious from the stated K-map rules. The following set of figures shows all the interesting K-map tricks that you need to 7 8 Recall that grouping the 0’s for a function is equivalent to grouping the 1’s for the complimented function.16 shows an example of this process. The K-map techniques are similar: for the SOP form you first need to group the 1’s in the K-map and then write down the product terms associated with the groupings. It’s sort of a drag to follow rules such as these but you’ll quickly get the hang of things.

4.3) F = AB + AC + BC F = ( A + B)( A + C )( B + C ) (b) Figure 3. F ( A.19: K-map grouping for SOP (a) and POS (b) forms. The examples in the following figures are listed in conjunction with the compact minterm and maxterm forms. B.17: K-map grouping for SOP (a) and POS (b) forms.18: K-map grouping for SOP (a) and POS (b) forms.4. F ( A. C ) = ∑ (0. B.6) F = AB + AC + BC (a) F ( A.5.5.5.3. B. C ) = ∏ (1.2. B. C ) = ∏ (1.Digital McLogic Design Chapter 3 be aware of in order to successfully use K-maps to reduce functions.6.4.3) F = A⋅C ⇒ F = A + C (b) Figure 3. 74 . F ( A.7) F = AB + C (a) F ( A. C ) = ∏ (0. B. C ) = ∑ (1.6) F = AC + BC ⇒ F = ( A + C )( B + C ) (b) Figure 3. C ) = ∑ (0. B.2.7) F = A+C (a) F ( A.

20: The K-map with groupings (a) and the reduced equation (b).3.5. please don’t forget the jog.14) F = ABC + ABD + ABC +BC D F = ( A + B + C )( A + B + D)( A + B + C )( B + C + D) F = B + AC D + AC D (a) (b) Figure 3. C ) = ∏ (4.712.21: K-map grouping for SOP (a) and POS (b) forms. In addition to the jog in the count that appears in the third and fourth columns in the 3-variable K-map. D ) = ∑ (0.Digital McLogic Design Chapter 3 The four variable K-maps are only slightly different than the three variable K-maps. The most common error in when using 4-variable K-maps is to forget to make the row jog when entering values into the K-map.20 shows a blank 4-variable K-map with the funny count listed.13. F ( A. B. they become second nature and there won’t be anything you need to commit to memory (except for the row jog).8.6. Figure 3.15].1. B. C . a similar jog appears between the third and fourth rows in the 4-variable K-maps. but after you do a few of these.20 are all the known tricks for dealing with 4-variable K-maps.10.11. Listed in the figures following Figure 3.2.9. The number appearing in the cells are indexes into a truth table that contains 24 or 16 entries [0. There are not that many and they are not that complicated as they do follow all four of the K-map grouping rules.14) F ( A. These may seem strange at first. Figure 3. 75 .7.

15) F ( A. there many instances where there are rows in a truth table (and thus cells in a K-map) that do not have a specified output. or more reduced The process of reducing functions that are incompletely specified. D) = ∑ (0.Digital McLogic Design Chapter 3 F ( A.5. F ( A.12. functions that contain don’t care entries.22: K-map grouping for SOP (a) and POS (b) forms. you don’t care what the circuit outputs are.5.12.13.9.14) F = C D + BD +BC D F = (C + D)( B + D)( B + C + D) (b) F = B D + C D +BCD (a) Figure 3. The assignment of 1’s or 0’s to the don’t 76 . D) = ∑ (0.3. C .8.3. B. it generally helps in the function reduction process. D) = ∏ (2.9.2.4. What is good about this is that if the output in that row does not matter.3. B. 3.11. D) = ∏ (1. Functions such as these are considered incompletely specified functions.1.10) F = AC + AD + ABC D (a) F ( A. The lines in the truth table that have no specific output can be thought of as follows: if the input conditions associated with an incompletely specified row appear on the circuit inputs. Although this may sound somewhat problematic. B. B. you can assign it either a ‘1’ or a ‘0’ which has the potential effect of making your final equation “smaller”.15) F = AC + AD + AB + AC D F = ( A + C )( A + D)( A + B )( A + C + D) (b) Figure 3.10.8.13. C . C .23: K-map grouping for SOP (a) and POS (b) forms. is easier than it sounds.6.6.4.4 Karnaugh-Maps and Incompletely Specified Functions As you’ll find out later in your digital design career.7. or as them are more commonly known. C .11.7.

14) F = C D +BC Figure 3. so consider committing to memory.24 and Figure 3.24 and Figure 3. In this case.7. You are not obligated to group the don’t care entries.15) + ∑ md (4. In this way. you can either choose to include the don’t cares in your groupings or leave it out. the smaller the associated product term will be. This is why they call it reduction.6.25 is the nomenclature used to specify the don’t cares for the compact minterm and maxterm forms. C . B. while you are obligated to group all the 1’s in the K-map. Figure 3. 77 . you’ve implicitly assigned a ‘0’ to that cell. Including the don’t cares can help you make bigger groupings and thus increased reduction of the function. in this case. you never actually make the assignments directly.24: The K-map groups for a reduced SOP form. you are should only group the don’t cares if it makes your grouping larger which has the effect of making you product terms contain a fewer number of independent variables.10. For example. if you have a function with don’t cares in it and you are aiming to generate a reduced SOP equation.12. D) = ∑ (0. you’re implicitly assigning the cell with the don’t care to a ‘1’.Digital McLogic Design Chapter 3 care cells in the K-map is done implicitly. F ( A.5. you group all the 1’s in the map and use the don’t cares to make your groupings larger9.25 show examples of function reduction with an incompletely specified function. if you’re grouping the 1’s and you opt not to include a don’t care in a group. Keep in mind that if you include a don’t care in a grouping of 1’s. You’ll sometimes see this nomenclature. The approach is to use a “-“ in the associated K-map cells that are don’t cares.8. A similar argument can be made for the case of generating a reduced POS form. 9 Keep in mind that the larger the grouping. Also worthy of note in Figure 3. you’re grouping 0’s and using the don’t cares to help make the 0-groupings larger.

C . they also can be used to help you obtain XOR and XNOR functions out of an equation reduced by normal K-map methods.26(b).27 shows to large striped groupings while Figure 3. and. If you see these conditions in your K-map. F = AB + A B = A ⊕ B (a) F = BC + BC = B ⊕ C (b) Figure 3. you’ll know that the equation generated from applying standard K-map techniques can be further reduced as is shown in Figure 3. Figure 3.5 Karnaugh-Maps and XOR/XNOR Functions And as a final note on K-maps.26: 3-Variable K-maps with diagonal (a) and stripes (b).3.25: The K-map groups for a reduced POS form. The approach here is to 1) use the K-map to alert you to the fact that a XOR-type function is present. you be able to further reduce the Kmap-generated equations as shown in Figure 3. Figure 3.28 shows two large diagonal groupings. Once noted.26(a).9. 3. look closely at your final equation and factor out the XOR-type functions. 78 . these rules are once again long and somewhat complex. Figure 3.10.3.11.13) ⋅ ∏ Md (4. Although there are explicit rules on how to take XOR-type functions directly from a K-map.2. B. The key to noticing whether a K-map contains a XOR-type function is to see that your groupings have formed some stripes or diagonals.5. The preferred approach uses characteristics of the K-map groupings to ascertain whether the K-map has a XOR-type function in it.14) F = C D + BC F = (C + D)( B + C ) Figure 3.26(b) shows an example of striped groupings.26(a) shows an example of diagonal groupings. 2) use Boolean algebra to factor the XOR-type function out of the resulting equations. A few examples should drive home this point.Digital McLogic Design Chapter 3 F ( A. D) = ∏ (1. Once you note this.6.

29 is that it will hopefully. In reality. The two truths that you need to realize are that 1) you rarely see some of these representations. But to aid you in your learning and understanding of the representations.4 Function Form Transfer Matrix We’re to the point now where we’ve learned about many different ways to represent a function. F = BC + BC + A BD F = ( B ⊕ C ) + ABD Figure 3. you loose sight of the fact that your main goal is to develop a basic understanding of digital principles. The standard digital design problem at this phase of digital design is to do what you need to do to transfer between the various function representations. Figure 3.27: 4-Variable K-map with stripes. The justification for providing Figure 3. and 2) it will get you past this early phase of a digital design course where we’re not really doing much digital design. Enough of this blather… here are a few things to notice about Figure 3. but it’s fairly straight forward to learn.29 is provided.29 represents a bunch of “rules”. it’s boring. Figure 3.28: 4-Variable K-map with diagonals. Yes. 79 . 1) remind you off all the ways to represent functions10 and how they are related. there are still a bunch more ways to represent functions that we have to wade through.29. 3. Rules in digital design are not good because if you get too caught up in following and/or memorizing rules. 10 Keep in mind. and 2) you don’t generally spend a lot of time going from one representation to another as it not typically done in any modern forms of digital design.Digital McLogic Design Chapter 3 F = C D + CD + ABC F = (C ⊕ D) + ABC Figure 3.

By easy. Note that if you have a VHDL model. except one. you could conceivably go from any one representation to any other representation if you thought enough about it or were interested in breaking a sweat. We’ll get to those later when we do more VHDL.29 represents the “easy” paths between the various function representations. At this point. • • • • Figure 3. I mean.29 are bi-directional arrows. but life is simply too short for that.29: Function representation transform matrix (be sure to read the explanation for this). such apply Boolean algebra theorems. it is not necessarily straight-forward to go from a VHDL model to a reduced form. 80 . There truly is an easy way to go back and fourth between compact minterm/maxterm representation and VHDL. The best way to do this is to transfer the information back to the K-map. the only way to generate a reduced form is by using a K-map. There is no easy way to get between reduced SOP and POS forms.Digital McLogic Design Chapter 3 • The matrix in Figure 3. All of the lines drawn in Figure 3. There are actually other ways.

Figure 3.30 shows the black box diagram for the full adder. As always. The bottom line is that while the HA was a two-bit adder. let’s start this design out with a black box diagram. In other words.31: The truth tables associated with the FA design specifications. you’ll find that the variable representing the sum can’t be reduced (knowing what you currently know about K-maps). Figure 3. The outputs of the circuit are identical to the half adder: SUM and Carry-out. The next step in the design is to specify the input/output relationship of the design. In other words. too). Solution: The first thing to notice about this design is its similarity to the half adder (HA).31 are then entered into a K-map for reduction. the outputs of the HA and FA are identical.30: Black box diagram of the full adder. The variable representing the carry-out is reduceable. The difference between the HA and the full adder (FA) in this problem is that the FA contains an extra input.31 shows the result of this step. 81 . a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 ci 0 1 0 1 0 1 0 1 (a) s co a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 ci 0 1 0 1 0 1 0 1 (b) s 0 1 1 0 1 0 0 1 co 0 0 0 1 0 1 1 1 Figure 3. the carry-in bit. The two output columns of the truth table shown in Figure 3. This is left as an exercise for you (you really need to do this. Once you drop the output variable information into a K-map. we must specify what the outputs we want (based on the problem specification) for a given set of inputs. The outputs are then assigned based on the problem’s original specification of adding the three input bits. The truth table is one approach for defining this relationship since it lists every possible combination of the input variables (the independent variables). the FA is a three-bit adder. Figure 3. this circuit completes the following operation: (a + b + ci) where a and b are the standard additive operands and ci represents the carry-in bit.Digital McLogic Design Chapter 3 Design Examples Example 3-1: Full Adder (FA) Design a circuit that adds three bits: two bits are associated with a standard addition operation while the third bit is considered a carry-in bit.

if any two (and only two) switches are one.Digital McLogic Design Chapter 3 Equation 3-4 shows the final equations for the two output variables. it would be a great idea to give both the inputs and outputs intelligent looking names. you could easily draw the final circuit model.32 shows the black box diagram for this circuit. 82 . Figure 3. The best approach in this relatively not-too-complex circuit is to start with a truth table. From these output equations. s = a ⋅ b ⋅ ci + a ⋅ b ⋅ ci + a ⋅ b ⋅ ci + a ⋅ b ⋅ ci co = b ⋅ ci + a ⋅ ci + a ⋅ b Equation 3-4: Boolean equations describing sum and carry-out outputs of the FA. The circuit should have the following characteristics (this is a verbal model of the circuit): o o o o If the enable switch is off. The next step will be to create a relationship between the circuit’s outputs and the circuit’s inputs. the single output will be low (off) Otherwise. In this step. then the output is high (on) Three switches will never be on simultaneously The circuit output is low under all other conditions Solution: The first step in these types of problems is to draw a block diagram of the circuit. Figure 3. Drawing the final circuit model for the FA is left as an exercise for the reader. Example 3-2: Special Switch Network A circuit is required in order to control a network of switched. Keep in mind that this is a functional relationship in that each combination of digital inputs has only one unique value on the digital output.32: Black box diagram of circuit. The circuit has four inputs: three of the switches are normal on/off switches while the fourth switch is an enable switch for the entire circuit. Figure 3.33 shows the completed truth table for this example. The circuit has four inputs and one output.

Figure 3. This problem has a fairly common digital input: the enable input. Note that in the truth table shown in Figure 3. This is an important feature in digital design: always keep it in mind. 83 .33 can be used to populate a K-map and the resulting expression for the output is found in Equation 3-5. F_OUT = (EN ⋅ SW3 ⋅ SW2) + (EN ⋅ SW2 ⋅ SW1) + (EN ⋅ SW3 ⋅ SW1) Equation 3-5: The expression for the problem solution. because it was stated that the condition will never happen.35 shows an alternate solution for this problem. the rows with the 1’s in the output have EN asserted in each case. take a quick look at it and make sure that it actually makes sense. Note that the enable controls the final output by having ultimate control over the AND gate on the output. Figure 3. Also note that the final row is listed as a don’t care.34 shows the circuit model the implements a solution to the problem. it is possible to somewhat simplify the design by handling the enable input separately from the main problem. If you stare at this equation. This will hopefully allow for a smaller final equation. you should stare at your final solution for a few minutes to verify that it’s not totally wanky.Digital McLogic Design Chapter 3 EN 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SW3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SW2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SW1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F_OUT 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 - Figure 3. Equation 3-5 does actually make a lot of sense. This means nothing is going to happen unless the enable input is asserted which is what the original problem stated. We take advantage of the fact that this condition never happens by assigning a don’t care to the output associated with those input conditions. As with all of these problems.33. In many of these cases. The truth table shown in Figure 3. you can see that it is somewhat intuitive based on the original problem description. Now that you’ve completed the truth table.33: Truth table for problem solution.

First. Secondly it involves a second type of design approach that is necessarily different from the standard truth table approach we’ve been using so far. The circuit output should contain both four-bit answer as well as a carry-out generated by the addition operation.34: The brute-force logic solution to the problem. A single bit is used to represent the carry-out value. In Figure 3. Example 3-3: Ripple Carry Adder (RCA) Design a circuit that will add two four-bit values.35: A more intuitive logic solution to the problem. So let’s do it. Figure 3. 84 . the two 4-bit input operands are represented using bus notation as is the 4-bit sum output. Solution: The importance of this problem can’t be overstated.Digital McLogic Design Chapter 3 Figure 3. it involves the design of a ripple carry adder which is one of standard circuits in digital design land.36 shows a black box diagram that conforms to this problem’s specifications.36. The first step is once again to draw a black box diagram of the final circuit. Figure 3.

37 shows the final solution for this problem. as shown in Figure 3.36: Black box diagram for the ripple carry adder. this approach represents a standard digital design approach that you’ll be using quite often in the future. This problem requires that we design a 4-bit adder. In general. the correct values on each sum bits must wait until the carry-out has been generated from the lower-order 1-bit adder. This approach presents a dilemma because. 85 • . is that the carry must “ripple” from the lower-order adders to the higher-order adders (or right-to-left in Figure 3. In other words.37: Black box diagram for a 4-bit Ripple Carry Adder. A bunch of important comments are sure to follow. Why not assemble the 1-bit adders in such a way as to create a 4-bit adder? Well. we would be faced with creating a truth table and stuffing the output variables with values that solved the given problem. There is a better approach we can take. The reason this circuit is referred to as a ripple carry adder or RCA. Representing every possible combination of these eight inputs in a truth table would require a truth table of 256 rows. generating the correct second-from-right sum bit is dependent upon the carry-out from the HA. that is the approach we’ll use for this problem. each bit 1-bit adder must add the “correct” values. From this. While this would be wholly possible. the higher the weighting. While the a and b inputs are understood to be immediately available. Once again. this problem contains eight inputs. Figure 3. The weightings of each bit location are implied by the numbering used for the inputs and sums in Figure 3.36. doing so would represent the ultimate grunt work. if we were to use out standard design approach. this adder is assumed to be binary in nature and uses the standard weighting associated with binary numbers. but we’ve already designed two different types of 1-bit adders.Digital McLogic Design Chapter 3 Figure 3. To ensure the correct answer on the circuits outputs. Here are those promised important points: • How does this circuit work? There are four 1-bit adders connected in a special manner. But it gets worse: reducing the results in an eight variable K-map would requires many years of mediation at some temple high in the Himalayas. The s3 output bit is referred to as the most significant bit (MSB) while the s0 is referred to as the least significant bit (LSB). the carry-outs are dependent upon the carry-ins from the previous bit location moving from right to left (except for the HA).37). This approach leverages the fact that we’ve already design some bit-type adders (name the HA and the FA).37. The higher the number “index”. Figure 3. Beyond that.

We’ll talk more about this later. if we suddenly wanted an 8-bit adder. we also completed this design without using any K-maps or Boolean equations. the design is iterative in that we placed a number of the previous design modules such that our original design specifications were satisfied. we simply add four more FAs to the 4-bit RCA design. Related to the previous point. The IMD approach is extremely powerful because you are generally freed from the many constraints of the truth table and BFD in general. • 86 . We essentially completed this design on a higher level than we completed previous design. This being the case. In other words. This is valid digital design approach that is referred to as iterative modular design (IMD). The design is modular in that we used previously designed modules.Digital McLogic Design Chapter 3 • We completed this design without using a truth table. we completed this design exclusively using previously designed modules (namely the HA and FA).

• Important Standard Digital Modules presented in this chapter: • • Full Adder (FA) Ripple Carry Adder (RCA) 87 . regardless of the number of gates or gate inputs. • There are three main recurring themes present in modern digital design: 1) make your circuit smaller. These outputs can be assigned such that the final function representation is more reduced. We declare one circuit to be smaller than another circuit if it uses less gates and/or if the gates in the circuit contain less inputs. • Reducing functions. Implicit in this definition is that the two circuits are functionally equivalent. and 3) make your circuit consume less power. • Functions can be represented using many different forms. The K-map inherently generates a SOP form but can be also generate POS form by multiple applications of DeMorgan’s Theorem. and reduced forms. but a better approach is to simply use your brain to see possible XOR functions in K-maps and Boolean factorization to flush out the terms. Rumor has it that you can only choose two of these options. There are large sets of rules that can be applied to this process. 2) make your circuit faster. respectively. • Three and four-variable Karnaugh maps are used to reduce Boolean equation representations of functions. • Exclusive OR (XOR) and exclusive NOR (XNOR) are two more standard gates used in digital logic. • Incompletely specified functions. or don’t cares as they are commonly known. • Iterative Modular Design was introduced as a powerful design method that bypassed the constraints presented by the truth table and the entire BFD approach. • Karnaugh maps that contain “stripes” and/or “diagonals” indicated that XOR (or XNOR) functions are present. or function reduction refers to the practice of making the function representation smaller without changing the overall input/output relationship of the function.Digital McLogic Design Chapter 3 Chapter Summary • NAND and NOR are formed from complimenting the outputs of the AND and OR gates. The forms presented in this chapter include standard SOP and POS forms. NAND and NOR gates are generally used more often that AND and OR gates in digital design. The final equation describing the circuit can be further reduced if the XOR-type functions are factored out. are sometimes found in digital design. These functions are somewhat useful for some basic digital circuits such as the Full Adder (FA). compact minterm and maxterm forms.

4.10. C) = ∏ (2. Y. B.9. C. C.13.8.8.4. C.13.13. C.15) 2) Write an expression for F in compact minterm form: F2(A.6. B.5.2.8.5.10) 4) Write an expression for F in compact maxterm form: F(A. E) = (A + B + C+ D + E)(A + B + C + D + E) 11) Write a reduced expression for F in POS form: 88 .6.12) 5) Write an expression for F in standard SOP form: F(U. B.6.9. C) = ∑ (3. D) = ∏ (2.7.7.6.13. B. B. B.15) F = (X.6. D) = ∑ (0.1. C.13) F7(A.33.11. D) = ∑ (0.6.3.6.5) 9) Implement F using a minimum of logic devices: 10) Convert the following standard POS equation to compact maxterm form: F(A.11.12. B.12. B. Y. D) = ∏ (2.10. V. Y.13.6. C. D) = ∏ (4.2.4.2.11. C.59) 6) Write an expression for F in standard POS form: 7) F(U. B. B. F1(A. W. D) = ∑ (0.23.14.5. B.4.15) F(A.5. Z) = ∑ (2. C.7) F6(A.5.2. X. C) = ∑ (1.4.10.9. C.7) F4(A.15) 3) Write an expression for F in compact maxterm form: F = (A. W.Digital McLogic Design Chapter 3 Chapter Exercises 1) Write a reduced Boolean equation in SOP form for each of the following functions. D. Z) = ∏ (12.51) 8) Implement F using a minimum of logic devices: F = (A.3. D) = ∏ (4. C) = ∑ (0. B.15) F8(A.11.6) F3(A. D) = ∑ (2. B.6) F5(A. X.10.1 2.8.4. V. Z) = ∑ (0.4.

C.7. F(A. 89 .8.15) ⋅ ∏ Md(1.8.10. C. B.11. D) = ∏ (2.7.14.14) 13) Write the reduced SOP expression for the following function: F(A.12.15) +∑ md(0.11.9.5.12.5) 14) For the following equation: F(A. B. B. D) = ∑ (4. D) = ABD + BCD + ABD 12) Write the reduced SOP expression for F given the following function: F(A.15) a) write the reduced SOP equation for F b) write the reduced POS equation for F 18) Convert the following expression to compact maxterm form in terms of F.13.14) a) write the reduced SOP equation for F b) write the reduced POS equation for F 15) Write an expression for F in compact minterm form that describes the following circuit: 16) Write an expression for F and F in reduced SOP form that describes the following circuit: 17) From the following compact minterm form: F(A.15) 19) Write an expression for F in standard sum of products form (SOP). B. B.6. C. D) = ∑ (0.11.5.Digital McLogic Design Chapter 3 F(A.6. D) = ∑ (2.3.6. B.10.7.11. C.3.10. D) = ∑ (5.2.11. C.6. C.

4.13.5.9.15) 90 . D) = ∑ (2.6.14.11.7.Digital McLogic Design Chapter 3 F(A. C.10.12.8.3. B.

B.7.12.13) +∑ md(0.5. D) = ∑ (2. (a) (b) (c) (d) 91 .8. C.Digital McLogic Design Chapter 3 20) Write an expression for F in compact maxterm form that describes the following circuit: 21) Write the reduced SOP expression for F given the following function: F(A.1.10) 22) The equation describing the circuit below was not reduced before the circuit was implemented. Analyze the circuit and re-implement (draw the circuit) in reduced form using AND & OR gates and Inverters.9.

(a) (b) 92 .Digital McLogic Design Chapter 3 23) Re-implement the following functions in reduced POS form.

Two of the inputs are considered the fractional portion of a binary number while the other two inputs are considered the integral portion of the binary number. Implement the associated output functions in reduced SOP form.5. The outputs of this circuit should represent a 2-bit binary number associated with the 4-bit input but with rounding up and down. In other words. the output of the RCA is inverted from what it would normally be. the problem becomes a matter of what should be done with the output in order to solve the problems specifications. Round the output either up or down when necessary. Implement the associate output functions in reduced POS form. if the input is greater or equal to 0. 93 . 4) Design a special 4-bit RCA with the following specifications. At this point. the output should represent the input rounded up. 3) A given circuit has four inputs. when this input is in the ‘1’ state. t output should represent the input rounded down to the nearest integer.Digital McLogic Design Chapter 3 Design Problems 1) Design a circuit whose outputs represent the square of the two circuit inputs. HINT: Since you know all about RCAs. Otherwise. your solution to this example should include a dark box labeled RCA (no need to reinvent the wheel on this problem). This circuit has an input named INV_OUT. 2) Design a circuit whose outputs represent the square root of the circuit’s 4-bit inputs.

(Bryan Mealy 2011 ©) 4.Digital McLogic Design Chapter 3 4 Chapter Four 4. the term functionally equivalent refers to the fact that the input/output relationship of the circuit is preserved but the implementation details are different. We saw an example of two different circuit forms for a given circuit in previous chapters (keeping in mind that the various forms are were functionally equivalent. This chapter presents the theory behind generating several new forms and outlines when such forms are most useful. This term generally refers to the fact that any given digital logic function can be implemented using physically different circuits. For these circuit forms. There are various reasons why you would want to use one form over another. the equivalent circuits are generated from equations that look distinctively different from each other. The new circuit forms presented in this chapter are definitely some of the most widely used representations of circuits. Main Chapter Topics CIRCUIT FORMS: Previous chapters have presented various functionally equivalent representations of circuit. the final circuit appears distinctively different also. In other words. This chapter outlines minimum concepts as they apply do function representations.2 Circuit Forms The term “circuit forms” is a somewhat common term in digital logic design vernacular.1 Introduction While future chapters delve more into actual design topics. This chapter presents a historical overview of PLDs and outlines some of the basic operating features. The circuit form portion of this chapter is really important but the other topics are sort of just interesting but not as universally useful as were the topics covered in previous chapters. In the context of a digital system. There is another flavor of circuit forms that we need to examine in this section. MINIMUM COST CONCEPTS: Being that there are many different approaches to representing functions. There was a time when this material was a much more important part of an introductory digital design course1. this is really interesting stuff but you may never see it again despite the fact that you may be well on your way to becoming the world’s greatest digital designer. 94 . PROGRAMMABLE LOGIC DEVICES (PLDS): PLDs can be considered a key element in modern digital design. the question arises when one representation should be used over another. and generally speaking. The more desired form is usually decided in the context of efficiency in 1 Back in the days when paper designs ruled the world and teachers had nothing better to test students on. this chapter represents a picking up the digital pieces not covered in the previous chapters. The chapter’s topics do present a nice foundation of digital knowledge and history that you’ll find useful now and then. but that was a long time ago. one form is often desired over another.

These two expressions are generated from grouping the 1’s of the circuit (left column) or the 0’s of the circuit (right column). The forms that are discussed in this section can be generated with successive applications of DeMorgan’s theorem. so if you know how to use this theorem. there are only about four common circuit forms. These two forms can be reduced using K-mapping techniques to the expressions shown in 1(b) and 2(b). 95 . The nice thing about the standard forms is that they are all generated from successive applications of DeMorgan’s theorem. If you examine a standard digital design textbook. This approach is somewhat standard and generates the most common forms of a circuit. these forms are so common that we’ll refer to them as standard circuit forms. In reality. the good news is that you’ve already been working with several of these forms. Equations 1(a) and 2(a) of Table 4.2 a written description of this procedure. we’ll opt to stick to the standard eight types in this chapter. Table 4. The resultant equations serve as the starting point to generate other forms.1 show the compact minterm and compact maxterm forms of an arbitrary function. you won’t have to waste your time memorizing how the various forms are derived. The following steps described how to generate the set of eight standard forms from the two compact forms. respectively. In truth. you’ll find that some textbooks actually list bunches of strange and wonderful circuit forms. there are about as many circuit forms as you could spend the time generating. 4.Digital McLogic Design Chapter 4 that one form may require fewer gates and/or inputs than another form.1 The Standard Circuit Forms There are eight common and easily generated/derived circuit forms.2.

9.4.7.10.2.6.13.Digital McLogic Design Chapter 4 1(a) F = ∑ (1.3.8.11.12 ) AND/OR Form 1(b) OR/AND Form 2(b) 2(c) 2(d) 2(e) F = AC + C D + A B C F = AC + AC D + A B D ( ) F = ( AC ) ⋅ ( AC D ) ⋅ ( A B D ) F = ( A + C ) ⋅( A + C + D) ⋅( A + B + D) F = AC + AC D + A B D NAND/NAND Form 1(c) NOR/NOR Form 2(f) F = AC + C D + A B C F = (AC ) ⋅ C D ⋅ A B C F = A + C ⋅ A + C + D ⋅( A + B + D) F = A+C + A+C + D + (A+ B + D ( )( ) 1(d) ( )( ) 2(g) ( ) ( ) OR/NAND Form 1(e) AND/NOR Form F = A +C ⋅ C + D ⋅ A + B + C NOR/OR Form ( )( )( ) ) 2(h) F = AC + AC D + A B D ( ) ( ) ( )( ) NAND/AND Form 2(i) 1(f) F = A + C + C +D + A + B + C ( ) ( ) ( F = AC ⋅ AC D ⋅ A B D ( )( ) Table 4.15) 2(a) F = ∏ (0.14. 96 .5.1: The generation of standard circuit forms by using DeMorgan's theorem.

NOR/OR Form The NOR/OR form shown in 1(f) is obtained by DeMorganizing the entire OR/NAND form shown in 1(e). The equation in 2(e) shows the final OR/AND form which is also referred to as the Product of Sums (POS) form. The overbar over the entire term is not altered. The right side of the equality is obtained by an application of DeMorgan’s theorem. one of the compliments is used to DeMorganize the expression. On the right side of equation 1(c). The final function represents a summing of the associated product terms. This is referred to as NOR/NOR form because each of the individual sum terms are complimented (a NOR function). the compliment of the function ( F ) is obtained. the overbar on the right side of the equals sign is distributed to the individual terms in the equation. The NOR/NOR form of the expression is shown in 2(g). the overbar on the right side of the equals sign is distributed to the individual terms in the equation. The double compliment on the left side of the equation 2(f) drops out. On the right side of equation 2(f). which preserves the equality and produces the equation shown in 2(c). The NAND/NAND form of the expression is shown in 1(d). In this way. OR/AND Form The form in 2(b) is obtained by applying K-map reduction techniques to the 0’s of the circuits output. The overbar over the entire term is not altered.1. This is done by complementing the expressions on both sides of the equals sign. This is referred to as NAND/NAND form because each of the individual product terms are complimented product terms (a NAND function). NAND/NAND Form The form in 1(c) is obtained from the AND/OR form by double complimenting both sides of the equation in 1(b). AND/NOR Form The AND/NOR form shown in 2(h) is obtained by DeMorganizing the individual terms from in 2(g) to change them from sum terms to product terms. since the K-mapping was based on the 0’s of the circuit.2: Written description of the circuit forms and derivations shown in Table 4. These individual terms are ORed together and complimented which changes it from an OR function to an NOR function. The individual groupings in the K-map form what are referred to as the product terms. one of the compliments is used to DeMorganize the expression. NAND/AND Form The NAND/AND form shown in 2(i) is obtained by DeMorganizing the AND/NOR form shown in 2(h). OR/NAND Form The OR/NAND form shown in 1(e) is obtained by DeMorganizing the individual terms from 1(d) to change them from product terms to sum terms. In this way. Double complimenting each side of the equation preserves the equality of the expression. Table 4. In this case. 97 . The equation in 2(d) is obtained by dropping the double compliment on the left side of equality.Digital McLogic Design Chapter 4 AND/OR Form The form in 1(b) is the AND/OR form and is referred to as the Sum of Products (SOP) form. The expression is in AND/OR form but we’ll massage it into a different form by writing an expression for F rather than F as is listed in 2(b). The double compliment on the left side of the equation 1(c) drops out. NOR/NOR Form The form in 2(f) is obtained from the OR/AND form by double complimenting both sides of the equation in 2(e). This form is obtained from a K-map by grouping the 1’s of the circuit’s output and performing Kmap reduction techniques. These individual terms are ANDed together and complimented which effectively changes it from an AND function to an NAND function.

the best choice is to draw the circuit of Figure 4. Once again.Digital McLogic Design Chapter 4 Yep. Since the right-most NAND gate of Figure 4. We’ll explain the details of this later. The form shown in Figure 4.1 and Figure 4. Let’s look at the AND/OR form and it’s relation to the NAND/NAND form. For now.1 matches the equation shown in equation 1(b).3. someone who is not familiar with the circuit may have doubts. the NAND/NAND form is the most widely used form. The circuit implementation of the OR/AND form provided in Equation 2(b) is shown in Figure 4. you’ll be more able to handle some of the fine points. you should use some type of OR-looking gate. the solution is to remove the right-most AND form of a NAND gate and replace it with an OR form2 of a NAND gate as is shown in Figure 4. just go with it and do your best to “match bubbles”. Generally speaking. Note that in this implementation the inverters have been replaced by overbars on the inputs signals in order to save time. A similar type of argument can be made for the OR/AND and NOR/NOR circuit forms. The “bubbles” are polarity indicators. This is a deep and often confusing subject (mixed logic) that is addressed in a later chapter.2(a) is that the bubbles “don’t match”3. there sure are a lot of forms out there. And to state it once again. when you are asked to provide the circuit diagram for a function in NAND/NAND form. Another thing that is disconcerting about the circuit of Figure 4.2(b). it is somewhat misleading because it no longer resembles the AND/OR form that it originated from.2(a) is actually implementing an OR function. OR/AND. This is an indicator that something may be wrong. In the real world. I like calling this the no-brainer approach to circuit forms.2(b). so please just take it without explanation for now. Although in the case shown in Figure 4. In summary. The subsequent NAND/NAND circuit implementation as it appears in Equation 1(d) is shown in Figure 4. these are two of the most popular circuit forms.2(a). and NOR/NOR forms are definitely the most common forms. Figure 4. Since this is an NAND/NAND form.2(b).2(b) indicates. 98 .1 and add the bubbles in the appropriate location to make the circuit appear like that of Figure 4. The relationship between these forms is nicer than you may be initially thinking after plodding through the math provided in Table 4. The good news is that the AND/OR.1. While the circuit implementation is correct in that only NAND gates are used in the implementation.2: The confusing (a) and totally clear (b) approach to NAND/NAND representations. NAND/NAND. you should not the similarities between the circuit of Figure 4. By the time you get it explained to you. Although this is somewhat out of the blue. The common AND/OR form circuit implementation is shown in Figure 4.1: The beloved AND/OR form.1.2(a) the implementation is truly correct. (a) (b) Figure 4. the 2 3 Don’t worry about this wording for now. there are two forms of NAND gates as Figure 4.

3: The good’ole OR/AND form.4(a). there are about a bajillion definitions of the word “minimum” in terms of implementing a circuit. The final word on 4 5 Once again. 99 . or the number of inputs to the gates in the circuit. While the circuit shown in Figure 4. especially those digital designers who understand basic mixed logic principles.4(b). the rightmost NOR gate is implemented using the AND4 version of the NOR gate. you would end up with the circuit shown in Figure 4. In this implementation. it would be cheaper to use them for your circuit because you can probably get them for a good price6. etc. There are many ICs out there that contain different flavors of standard gates such as AND. out there in the real world. OR.4: The confusing (a) and totally clear (b) approach to NOR/NOR representations. 4. In reality.4(b) is the preferred approach. Figure 4. The definition of minimum can also mean the number of integrated circuits (ICs) used to implement a circuit5. A better NOR/NOR implementation appears in Figure 4.Digital McLogic Design Chapter 4 inverters have been omitted and are replaced with complemented input signals (don’t try this at home). if you’re required to implement a function in NOR/NOR form. Once again. the circuit shown in Figure 4. The comforting thing here is that the NOR/NOR form implementation of Figure 4. etc. don’t worry about this wording for now. For beginning digital design courses.4(b) is strikingly similar to that of Figure 4. 6 It’s something only a business major would understand. NAND gates.4(a) is technically correct. If we were to implement this circuit in the NOR/NOR form as listed in 2(f). this definition usually refers to the number of gates used to implement a circuit. it is misleading and is avoided by digital designers. This turns out to be somewhat of an open-ended concept due to the fact that this approach requires that the word “minimum” be properly defined before knowing what the minimum cost is. (a) (b) Figure 4. It’s all strange and somewhat obscure stuff. The definition of minimum cost is further obscured by the fact that your company may already have a bajillion ICs that are expensive but since you have nothing else planned for them.3.3 Minimum Cost Concepts The desired approach to implementing circuits is to implement them at a minimum final cost.

These ICs were generally referred to as SSI and MSI (small scale integration and medium scale integration where the difference between small. This is especially true as general purpose computers become involved in the game with various forms of design automation tools. 8 White boards with many holes in which to stick in wires and components. the world is happy. 9 Components had long posts that were used to connect to other components via thin wire. for given designs. unless given other specific directions. In the end. medium. such as improved productivity. These designs were generally done on protoboards8 or wire-wrap boards9 because fabricating your own printed circuit board (PCB) was too expensive. The final word is this: minimum cost concepts is mostly a relic from the past in terms of an introductory digital design textbook. This section of notes is an attempt to remind you of both how you’ve gotten to the digital place you find yourself today and to give you a greater appreciation of some of the tools and hardware you currently use on a daily basis. Table 4.4.1 Digital Design: Twenty Years Back Twenty years ago. the form that uses the least amount of gates is generally the minimum cost solution. it’s amazing how far digital integrated electronics have come is such a short time. The SSI and MSI chips did not have too much functionality so even a simple digital design ended up requiring a lot of ICs if the design was actually implemented. The discussion that follows is centered around the path that got us to where we are today in the context of hardware design and programmable logic devices (PLDs). 4. What is even more amazing is that as things become more developed. you have the ability to use equivalent gates which can sometimes reduce the overall device count (particularly the number of inverters used in a circuit). The forms primarily used are the reduced SOP and POS. Generally speaking. An example of MSI would be an IC that contained a counter or a multiplexor (digital devices you’ll learn about later). All the designs in the digital courses were primarily paper designs and there was little point in implementing them in actual hardware. and large scale integration is determined by the number of transistors in an IC)7. if the circuit works. Up to this point. the approach taken by digital logic design these days is to abstract things to an impressively high level. In most applications. the speed at which changes happen seems to increase. digital circuits were centered around discrete logic that was contained on integrated circuits (ICs). There were a few circuits that were actually implemented and students learned quickly that actually implementing circuits was a time consuming task. or too impossible. make sure they provide you with an adequate definition of “minimum”. This was not the case all those years ago when computers were expensive and useful software was essentially nonexistent.3 lists some of the good points and bad points of this level of design.4 Programmable Logic Devices In case you have not noticed yet. 7 100 . it’s easier and cheaper to model a circuit using VHDL and not worry about the fine details of how it’s constructed at a lower level. 4. While there are a lot of good things to be said about this approach.Digital McLogic Design Chapter 4 minimum cost is this: if someone tells you to apply minimum cost concepts to your design. too messy. The truth is that most everything is relatively cheap in the world of digital design. In particular. If you stop and think about it for a moment. When the concept of minimum cost arises. One thing that is not cheap is your salary. An example of SSI would be an IC with a few NAND gates on-board. there is one really bad thing that you should be aware of: so many of the low level details are hidden from you that you’re at risk of losing your basic foundation of digital logic. you generally take a look at both POS and SOP forms. you’ve learned to implemented functions with many different forms.

5 shows three interesting connections. and not easily modified. and no connection (c). These were relatively simple devices such as the PALs (programmable array logic) and PLAs (programmable logic arrays) that were discussed in introductory digital logic courses. Multiple ICs required lots of board space and consumed a lot of power. Have you ever seen a fuse box attached to an IC? 101 .5(a) shows a connection between two signals that was made at the factory. this connection was made at the “mask-level” it cannot ever be changed. The terminology that is typically used is that if a connection was connected with a “fuse”. then the connection was not made. Figure 4. they had been around for awhile but they were now becoming affordable to real humans and student-types. It’s suffice to say here that the programmable portion of the PLD acronym is based on blowing or not blowing these fuses11. Figure 4. 2.2 Digital Design: The Early 1990’s Back around this time. hard to debug. 4.Digital McLogic Design Chapter 4 Good Points: 1. Bad Points: Circuits were tedious to assemble (proto-board. Table 4. and implement designs at a relatively low cost. (a) (b) (c) Figure 4. These early devices were not large or complex and were very understandable when presented in digital logic courses.5(b) shows a connection made with a fuse (the X is the symbology used to indicate that a connection is made between the two signals).4. In reality.3: Some of the good and bad points of early digital design. Modern PLDs are large and complex but a brief but solid introduction to such devices is well worth the effort. If the connection did not have a fuse. The programmability of these devices is centered around the presence of connections (or lack there of) made in the circuitry. The model of a fuse is that it can be broken. The early PLDs could essentially be modeled as an array of AND logic connected to an array of OR logic. You could go to the local electronics store. Figure 4. 2. the actual silicon does not contain a “fuse”. Actual semiconductors use various forms of technology to obtain the functionality of a fuse. PC board). 1. You could get most of the designs working using a minimal amount of test equipment (about the only thing I could afford in those days was a multimeter). and thus the connection between the two signals will no longer exist. a fuse-based connection (b). 10 11 Actually.5: A factory made connection (a). Generally speaking. the connection was made. programmable logic devices (PLDs) started appearing10. buy the required ICs.

A model of such a circuit is shown in Figure 4. some modern PLDs contain AND and OR planes. we can use AND/OR circuit forms to implement function (recall the AND/OR function forms). I suggest you do some product searches on the internet. the shortcut symbology of Figure 4. Even the simplest of AND/OR-based PLDs contain more logic than is listed in these diagrams.7(b). For each of the gate inputs. the number of gate inputs can be excessive. Yeah. What these PLDs provide is a single device that can implement many different functions simultaneously. To combat this ugliness. This can most accurately be considered a model of a programmable logic array because both the AND plane and OR planes are programmable. the models shown in Figure 4. 12 In this context. The important thing to note here is that these devices have AND planes and OR planes.6: is used. As you already know.6: The shortcut notation generally used in describing PLDs. is shown in Figure 4. Another similar device.Digital McLogic Design Chapter 4 Some other standard terminology is used in PLD-land is shown in Figure 4. If this raises your curiosity. architecture refers to the internal structure of the device.6:. Several types of PLDs can be modeled as an AND plane that connects to an OR plane. This device is noticeably similar to the PLA but the connections in the OR place are programmed in the factory and thus cannot be reprogrammed by you the user. In other words.7: are very simple models. programming the device is a matter of removing the unwanted fuses. Moreover. As you’ll see in some of the upcoming diagrams. 102 . the diagrams can ugly real fast due to the shear number of logic devices contain on the devices. the programmable array logic. but many have other styles of internal architecture12.7(a). or PAL. The reality is that these simple models for PLDs are not overly accurate any more. Figure 4. there will need to be an input signal line. What this symbology does is to allow all of the gate inputs to be modeled as one input.

Digital McLogic Design Chapter 4 (a) (b) Figure 4. In an effort to make the devices more functional.8 or Figure 4.8 indicate connections and form the literal inputs to the individual AND gates.9: are the output options that are typically included with PLDs.8 implements are listed in Figure 4. The X’s in the AND plane of Figure 4.8 shows an example PLD. The four functions that the PLD in Figure 4. Let’s take a look at one example PLD and analyze the functions it’s implementing. they certainly do not represent intelligent logic design. Don’t get overly excited about these equations. the outputs are generally available to be fed back to serve as inputs to other functions. Figure 4.7: A PLD with all the fuses in place (all connections made). The column of AND gates implements a bunch of product terms. these are fuses that have not been removed by the programming practice. Not listed in Figure 4. The row of OR gates implement SOP functions as they collect the product terms from the AND array. This somewhat more complex type of circuitry allows the devices to implement a greater number of functions as well as more complex functions. Although the functions it’s implementing have no real meaning.9. The dots in the OR plane represent connections to the OR gates below. 103 . we can still analyze it to verify we have the PLD analysis technique down. Once again.

The general diagram of a CPLD is shown in Figure 4. There are two major types of PLDs that we’ll be working with in this course: the complex programmable logic device. The I/O blocks shown in Figure 4. or FPGA. or CPLD. there is not too much worth saying about them now. 104 . The CPLD does contain structures that can be categorized as AND/OR arrays while the FPGA generally does not. The PLD-like part (AND/OR array) is referred to as a logic block and are connected to one another through programmable interconnects.10 can be considered a single PLD. The idea behind the CPLD is to put a bunch of PLDs on a chip and give them the ability to talk with one another.10. These two types of devices are complete different architectures (internal workings). Each of the logic blocks shown in Figure 4.Digital McLogic Design Chapter 4 Figure 4. You’ll study these devices in further detail in other courses.8. F1 = AC + C + BC D F 2 = AC + B F3 = C + BD F 4 = AC + A Figure 4. It is the programmable interconnects that give the CPLD flexibility and efficiency.8: Typical model of a PAL.9: The Boolean functions implemented by the PAL of Figure 4. and the field programmable logic device.10 are also configurable (as opposed to programmable) to include pull-up resistors and other fun-type things that are generally associated with digital outputs and serve to extend the flexibility of the device.

Often time the capacity of a CPLD is measured in terms of macrocells. Macrocells are an important part of CPLDs they have significant functionality and are fully programmable which makes modern CPLDs massively powerful. Some of the good points and bad points of PLDs such as these are listed in Table 4.12. In the end. the major design focus bought about by PLDs shifted to producing a description of the circuit that matched the design requirements rather than making sure all the ICs on your board were talking to each other. a logic block is comprised of an AND/OR array which is connected to a macrocell. There are actually many other types out there that are not listed in Figure 4. Figure 4. This figure shows that all of the different programmable devices discussed in this chapter are forms of PLDs.Digital McLogic Design Chapter 4 Figure 4. Figure 4. In case you’re overloaded with acronyms.4.12 as this is a modern digital logic textbook and not a history of technology textbook.11: Logic Block and its relation to PIs and I/O. check out Figure 4.10: General diagram of CPLD. 105 .11 shows an expanded view of the logic blocks. The macrocells provide polarity control and output level adjustment among other things. As you can see.

Table 4. 2. 3. Required learning a “programming language” (namely a hardware description language. Not easily tested due to the fact that so much circuitry was onboard the PLD. Electronic Design Automation (EDA) tools appear and prosper. more board space. 2.4: The good and bad points of early PLD design. faster circuits). 106 . 3. Reduced the number of ICs required in a design (lower power. Figure 4. or HDL). 1. More flexible: circuits could be changed quickly without major revamping (the devices were programmable). Bad Points: Required special hardware and software to program the PLDs.12: A Venn diagram showing the relationship between various PLDs.Digital McLogic Design Chapter 4 Good Points: 1.

Although there are an effectively infinite number of ways to represent a function. Programmable logic devices are a relatively new area in digital design. Software tools. Although early PLDs were simple devices.Digital McLogic Design Chapter 4 Chapter Summary • Circuit forms are used to implement logic functions using an overall implementation scheme. modern PLDs are massively functional to the point of being the defining device of digital design. allow modern digital designers to bypass the low-level details of PLDs and implement circuits on a higher level. PLDs are world of their own and are massively complex at the gate level. If you are required to implement a minimum cost solution for a given function. NOR/NOR). Minimum cost concept pertains to the many functionally equivalent forms of circuits. The most popular forms are SOP-type forms (AND/OR. When many circuit forms are possible. there are only a few standard ways. however. the circuit with the minimum cost is often implemented. the term “minimum cost” must be explicitly defined. Many factors can be used to determine the minimum cost of a given function. • • 107 . NAND/NAND) and POS-type forms (OR/AND. These standard ways are referred to as circuit forms and can be derived from repeated applications of DeMorgan’s theorem.

C.11.9.11.6. B. and C (A is the most significant bit and C is the least significant bit) and the output is F. F (A. C.15) 4) Implement F using a minimum of logic devices (AND. OR. D) = ∑ (0. D) = ∑ (0. OR. and inverters): F = (A. Assume propagation delays are negligible.2.14. The control variables are A. B.15) 7) The following timing diagram completely defines a function F(A. 8) List the Boolean expression implemented by the PLD on the left.Digital McLogic Design Chapter 4 Chapter Exercises 1) Write the following expression in OR/AND form: F(A.12. F = (A + C + D) + (A + C + D) + (A + C + D) 3) Implement F using a minimum of logic devices (AND. D) = (A + C) + (B + D) + (A + C + D ) 2) Write a Boolean expression in NOR/NOR form that is equivalent to the following expression. Implement the following Boolean expression for the PLD on the right: 108 .4.B.C) that has been implemented on an 8:1 MUX. C. Y. Write an expression for this function in reduced NAND/NAND form. C.5) 5) Implement F using a minimum of logic devices (AND.10.8.10.4. and inverters): F = (X.15) 6) Implement the following circuit (draw the circuit) in reduced form using only NAND gates. B. Z) = ∑ (0.5.1. B.13.4. D) = ∑ (1. B. OR.7.11.14.8) + ∑ md(10.13. and inverters): F = (A.

B.3.Digital McLogic Design Chapter 4 F5 = AB C + A BC + ABC F6 = AB + BC + A C .7) F8(A. B.5. C.3.10. D) = ∑ (2. Implement the following Boolean expression for the PLD on the right: F5 = BD + ACD + A BCD + BD + ACD F6 = ACD + BD + ACD + AC + AC F7 = AC + A BCD + BD + ACD + BC F8 = BD + ACD + ABCD + BC 109 . F7(A.6.11) 9) List the Boolean expression implemented by the PLD on the left. C) = ∑ (2.4.5.

110 . Implement the following Boolean expression for the PLD on the right: F5 = A BC D + BC F6 = BC +AC F7 = AC +ABCD F8 = A + D .Digital McLogic Design Chapter 4 10) List the Boolean expression implemented by the PLD on the left.

Digital McLogic Design Chapter 4 111 .

The first ten numbers are the same as decimal numbers. BINARY ARITHMETIC: The basics of binary arithmetic using signed and unsigned binary numbers are presented. but the last six are sort of new. The less than good news is that you need to become fluent with binary since it is the only number system that digital hardware is able to understand. Since there are not 112 . The bad news about binary is that it is sometimes a pain in the ass to work with.2. you’ll only need to directly know two of them in order to master digital design: decimal and binary. Main Chapter Topics NUMBER SYSTEMS: This chapter review previously presented number systems and describes the hexadecimal and octal numbers. (Bryan Mealy 2011 ©) 5.2 Number Systems A previous chapter presented a general overview of number systems. Although there are definitely a lot of number systems out there. The foundation of digital knowledge that you’ve built up to now is sufficient to introduce the topic of binary number representations and conversions between representations in the context of arithmetic-type circuit design. The good news is that you probably already know decimal. It’s not all that bad. the skills you develop working with these number systems is something you constantly use in digital design.1 Chapter Overview One of the major uses for digital logic design is creating circuits that perform mathematical-type operations. The concepts presented in this chapter allow you to design some reasonably interesting circuits and useful circuits. The emphasis is on fixed number lengths and detection of result validity after mathematical operations. But the good news about working with binary is that there is some help available. computer science. It’s actually sort of fun. computer engineering. and bowling. radix complement.Digital McLogic Design Chapter 5 5 Chapter Five 5. CONVERSIONS BETWEEN MIXED RADII: Basic algorithms to convert between presented number systems are described. 5. The bad news is that you have to learn the hexadecimal (radix=16) and octal (radix=8) number systems in order to aid you in your work with binary numbers. BINARY NUMBER REPRESENTATIONS: Common representations of signed binary number are presented. and diminished radix complement.1 Hexadecimal Number System The hexadecimal number system contains sixteen numbers in its associated ordered set of symbols. But more importantly. These representations include sign magnitude.

we draw on that familiar juxtapositional notation where we start placing the numbers side by side. The importance of memorizing the first three columns of Table 5. it customary to switch to alpha characters. Table 5.1 cannot be overemphasized. you won’t regret it. The thing of interest here is that once we run out of symbols in the octal number system (as we do for numbers greater than seven).Digital McLogic Design Chapter 5 more familiar decimal numbers to act as the final six numbers in the hexadecimal number system.1: Numbers that every digital designer better memorize really soon. base 10 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 base 2 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 base 16 Hexadecimal 0 1 2 3 4 5 6 7 8 9 A B C D E F base 8 Octal 0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 Table 5. 5. we use the letters A F to represent the hex numbers 10-15. Table 5. In other words.1 shows this characteristic for several important digital radii. the better off you’ll be in your digital design or computer science (or bowling) career in general.2. The faster you have this stuff memorized. I would suggest you make some flash cards and use them for a few minutes per day.1 shows the hexadecimal numbers along with the associated decimal and binary numbers (in 4-bit format). Convince yourself that this carry over notation is similar to the decimal number system but the carry over occurs at eight rather than at ten. It’ll be time well spent.2 Octal Number System The octal number system contains eight numbers in its ordered set of symbols. there is no need to use alpha characters as we did for hexadecimal numbers. Since there are less than the ten standard numbers in the decimal system. 113 .

There were few examples in an earlier set of notes for decimal and binary.4 + 0. Table 5.015625 (0. As a reminder to you.4) 8-2 1 x 0. Example 5-1 Convert 372.3 Number System Conversions The reality is that we humans think in decimal but computers and other digital devices operate in strictly binary.3 provides the solution to Example 5-2. the digit positions in any number using juxtapositional notation have weights associated with them. ↑ Radix Point Final answer: 192 + 56 + 2 + 0. While hex is used often in digital design.1 (0. is an example of hexadecimal to decimal conversion.015625 = 250. Example 5-2 Convert 1CE.Digital McLogic Design Chapter 5 5. octal numbers are not used as often.125 0.2 shows the solution to Example 5-1.1 Any Radix to Decimal Conversions This topic was covered in a previous chapter.415625 Table 5. Example 5-2. 114 .318 (octal) to decimal Example 5-1 is an example of octal to decimal conversion. respectively. below are two examples for octal and hex numbers. The use of hexadecimal is purely an aid for humans to handle long strings of 1’s and 0’s. VHDL readily understands hexadecimal which is yet another added bonus.3. 5. Table 5.A416 (hexadecimal) to decimal. What you see in this section is that hex and octal numbers are used to simplify the representation of binary number. The next example.015625) . This means we’ll need to be able to translate between the various number systems typically associated with digital design. Decimal Value of Digit Weight Radix Exponential Positional Value 64 8 1 0. The weights are multiplied by the associated number in order to generate the final number.2: The solution to Example 5-1.015625 82 3 x 64 (192) 81 7x8 (56) 80 2x1 (2) 8-1 3 x 0.

The first value that was generated by using this algorithm was the least significant digit (LSD) which was the remainder after the first division. it proves that the algorithm is valid and it will work when transferring from decimal to a number of any radix value. we’ll only be interested in decimal to binary conversions. it actually proves a point). Example 5-3 provides an overview of this division process.003906 = 462.3: The solution to Example 5-2. Example 5-3 Convert 487 to decimal. the conversion process becomes much more tedious than the already tedious decimal to binary conversion.625) ↑ Radix Point 0.2 Decimal to Any Radix Conversion Converting numbers from decimal to a number system of any radix can employ the use of many different algorithms. Wow! Although this example was sort of funny because it did no actual conversion. it truly does work for any radix.066409 Table 5.0625 16-1 10 x 0.003906 16-2 4 x 003906 (0. 115 . we’ll only be looking at decimal to binary in this section. Although this approach will work for converting decimal to any base. Not surprisingly. Example 5-4 shows an example of a decimal-to-binary conversion while an even more meaningful example appears in Example 5-5. 5. We’ll take a look at the most straight-forward for a human algorithm in this section. And since this method involves repeated division. The decimal to binary conversion is going to be the conversion you use most often. The final value that is generated using this algorithm is the most significant digit (MSD). From Example 5-3 example you can see that the repeated division by the radix value decomposes the original value into its individual weighted components. it becomes very painful to make these conversions for anything except decimal to binary conversions. Although you could you this technique to convert to any base. If you were to reassemble the number with the MSD on the left and the LSD on the right. let’s first convert a decimal number to a decimal number (don’t worry. For those brave enough to try.Digital McLogic Design Chapter 5 Binary Value of Digit Weight Radix Exponential Positional Value 256 162 1 x 256 (256) 16 161 12 x 16 (192) 1 160 14 x 1 (14) . you would get the original number back. The approach we’ll take is to divide the number multiple times by the radix value. The best bet if you need to do these conversions is to use a calculator. 0. These are common digital design terms and stand for Most Significant Bit (MSB) and Least Significant Bit (LSB). As motivation for converting the integral portion of decimal number to binary. 0625 (0.3. For our digital applications. There are actually two parts to this approach. one for the integral and fractional portions of numbers.0625 + 0. Note that in both of these examples that we’re using the terms LSB and MSB. the technique is referred to as repeated radix division (RRD).015625) Final answer: 256 + 192 + 14 + 0. The gory details are listed below.

decomposing a yet larger integral decimal number into a yet larger binary number. This algorithm is referred to as repeated radix multiplication (RRM). 147 ÷ 2 = 73 73 ÷ 2 = 36 36 ÷ 2 = 18 18 ÷ 2 = 9 9÷2=4 4÷2=2 2÷2=1 1÷2=0 Remainder: 1 Remainder: 1 Remainder: 0 Remainder: 0 Remainder: 1 Remainder: 0 Remainder: 0 Remainder: 1 LSB = 1 Final Answer: 14710 =100100112 MSB = 1 Table 5. Example 5-6 provides an overview of this algorithm. There two somewhat worthy examples shown in Example 5-7 and Example 5-8. Yes. Note from the result shown in Example 5-6 that the first integral result is the MSD of the original number. we’ll peel off the newly created integral portion of the number and put it aside. The approach we’ll take is to multiply the number repeatedly by the radix value and see what the result is.6: The solution to Example 5-5. Example 5-5 Convert 147 to binary.4: Decomposing an integral decimal number into a decimal number. The final value we obtain is the LSD of the original number. 12 ÷ 2 = 6 6÷2=3 3÷2=1 1÷2=0 Remainder: 0 Remainder: 0 Remainder: 1 Remainder: 1 LSB = 0 Final Answer: 1210 =11002 MSB = 1 Table 5.5: The solution to Example 5-4: Decomposing a decimal number into a binary number. As a motivational example for converting the fractional portion of a number to some other base. Example 5-4 Convert 12 to binary. let’s first convert a fractional decimal number to decimal number. 116 . this too has a point.Digital McLogic Design Chapter 5 487 ÷ 10 = 48 48 ÷ 10 = 4 4 ÷ 10 = 0 Remainder: 7 Remainder: 8 Remainder: 4 LSD = 7 MSD = 4 Table 5. In each step.

Example 5-8 Convert 0. 0.75 × 2 = 1. The other key point about this example is that the answer we obtained is no longer a proper equation. 0. Stopping the algorithm after four iterations is arbitrary.Digital McLogic Design Chapter 5 There are two key points about the example shown in Example 5-8. First.0112 LSB = 1 Table 5.758 0.879 × 2 = 1. 117 . we decided to end it after four iterations of the algorithm.8: Solution to Example 5-7: Decomposing a fractional decimal number into a binary number. Without this subscription.879 ≈ 0.0 remove the 2 remove the 4 remove the 3 MSD = 2 LSD = 3 Table 5. since our conversion never ended as nicely as the example of Example 5-7. as opposed to the example shown in Example 5-7. 0.032 0. doing four iterations was boring enough.43 0. Example 5-7 Convert 0.758 × 2 = 1.032 × 2 = 0.75 0.243 to decimal.375 to binary. In reality. we must use the approximation symbol.0 remove the 0 remove the 1 remove the 1 MSB = 0 0.243 × 10 = 2. Example 5-6 Convert 0.7: Solution to Example 5-6: Decomposing a fractional decimal number into a decimal number.5 × 2 = 1.11102 LSB = 0 (?) Table 5. we would have to interpret this number as decimal thus pissing off the digital goddesses.43 × 10 = 4. For the sake of sanity in this example.064 remove the 1 remove the 1 remove the 1 remove the 0 MSB = 1 0. the example in Example 5-8 does not appear to end.3× 10 = 3.375 × 2 = 0.375 = 0. Also note that in all of these examples a subscripted two was used to indicate that the converted number was in binary.50 0.879 to binary.9: Solution to Example 5-8. decomposing a fractional decimal number into a binary number.516 × 2 = 1.516 0.2 0.

Be careful to not make this error. This works because both binary and hex numbers are powers of two which allows for the individual weightings of the numbers to be powers of two also.A816 Figure 5. to get around this. Well. The conversions shown in Example 5-9 and Example 5-10 highlight the relationship between the group of fours in the context of a binary to hexadecimal conversion and a hexadecimal to binary conversion. the conversion process is also quite friendly.Digital McLogic Design Chapter 5 5. This is not the case. it becomes a real drag to look at the seemingly endless strings of 1’s and 0’s that form the binary numbers. 118 .3. • • In Figure 5. This makes the numbers much more readable. 1100110. you can ignore them (but don’t forget they’re not there). The problem is that our minds don’t easily recognize a large string of bits too well. A common mistake is to see that final ‘1’ in the fractional portion of the number think that is equivalent to a binary ‘1’. In other words. As an example of this consider the fact that nine bits looks a lot like eight bits at a quick glance.101012 = 66.3 Binary ↔ Hex Conversions Although binary is the language used by digital circuits. Since zero has no value. The key to converting between binary and hex numbers is to note that groups of four binary numbers can be substituted for a single hex number (and vice versa). Note that in these examples the numbers have the radii clearly indicated thus indicating mastery of the subject. we use hexadecimal and octal representations for binary numbers wherever possible. There are a few special items to note in these examples.1: The solution to Example 5-9. the final bit is associated with a hexadecimal ‘8’ and not ‘1’. • Example 5-9 Convert 1100110. Zeros are added to the end of the fractional portion of the number (commonly referred to as bit-stuffing).101012 to hexadecimal.1 the leading zeros in the number were omitted. actually the number has the weight associated with the MSB of a 4-bit binary number. respectively.

The key here is to bit-stuff the fractional portion of the binary number being converted so that you don’t make a mistake in the weighting. this method works because we’re transferring back and forth between radii related by powers of two. D37.110112 to octal.2: The solution to Example 5-10. Example 5-12 Convert 241.AC16 to binary. 1101101. Once again. 119 .668 Figure 5.4 Binary ↔ Octal Conversions Converting between binary and octal numbers is similar to the binary-hex conversion. the binary-octal conversions use the “group of threes” approach. Example 5-11 Convert 1101101. While the binaryhex conversions used the “group of fours” approach.Digital McLogic Design Chapter 5 Example 5-10 Convert D37.3: The solution to Example 5-11.101011002 Figure 5.AC16 = 110100110111.4: Using the group of fours technique to convert a binary number to hexadecimal.3.328 to binary Figure 5.110112 = 155. The group of threes approach is inherent the same as the group of fours approach so not much comment is provided there. 5.

328 = 10100001. On the other hand. For example. this is only true for unsigned binary numbers.1 Binary Coded Decimal Numbers (BCD) You’re about to learn several different common ways of representing numbers using binary codes. after that we run out of decimal digits and then have to take our shoes off. we’ll need many more representations to be fluent in digital land.Digital McLogic Design Chapter 5 241.5: The solution to Example 5-12.10 shows the four bit code words and the decimal digits they represent. there’s nothing to stop you from generating your own binary code just for the heck of it. Note that these are the same as the group of fours concept for the first ten rows. there is nothing stopping us from using more than four bits to represent the digits but that would end up have lots of unassigned codes. the word code refers to how a set of bits is interpreted. These are the binary coded decimal and unit distance codes. Moreover. we only have eight different unique bit patterns which is not be sufficient to represent the ten symbols in the decimal number system. In this context. you would naturally think about juxtapositional notation and the weights of the numbers which happen to be powers of two (the radix for binary). 120 . As it is. if you were to see a bunch of bits.011012 Figure 5. 5. Generally speaking.4 Other Useful Codes Using binary patterns to represent numbers is a major field of study in modern engineering. we’re going to need at least four bits to uniquely represent each of the digits. Table 5. 5. Binary coded decimal (BCD) numbers are somewhat similar to the group of fours so we’ll talk about it in this section. there are literally and endless number of binary codes in use. Since there are ten different numbers in the decimal system.4. As you’ll soon find out. Despite the fact that there are such a great number of binary codes in use today. In that we currently live in the information age. the weights associated with each bit position are increasing powers of two. binary codes are generated in order to efficiently represent some given information. We could not represent the set of decimal numbers with three bits because with three bits. there are a few highly useful codes that are worth taking a look at. Up until this point. there are sixteen different bit combinations possible with four bits which results in six bit combinations not being used when representing the set of decimal digits1. The goal is to have a unique set of bits to represent each of the digits in the decimal system. going from the radix point and moving to the left. Decimal 0 1 2 3 1 BCD Code 0000 0001 0010 0011 Although these six combinations are often used to represent “numbers” 10-15 hexadecimal.

This is generally not done and is only done here to help you read these numbers late at night. For now. this is similar to stuff you’ve already done. these two figures have slight spaces between the bits to somewhat group them into groups of four bits.Digital McLogic Design Chapter 5 4 5 6 7 8 9 - 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 5. As you’ll see. let’s do a couple of examples. The primary role of BCD numbers is to represent decimal number on certain types of displays in devices that are able to display decimal numbers. Two examples of these conversions are shown in Example 5-13 and Example 5-14.10: The decimal digits and their associated BCD codes.6: The solution to Example 5-13. Also. 121 . Example 5-14 Convert 396 to BCD. One thing to note from these examples is that the leading zeros in the BCD numbers are usually shown in the representation. 011001111000BCD = 678 Figure 5. Example 5-13 Convert 011001111000 (BCD) to decimal.

As you can see from Table 5. In this context. A unit distance code (UDC) is a set of code words where the maximum distance between any two code words is one. Often times when people mention Gray and Unit Distance codes.11. it’s usually in the context of “the distance between two codes”. UDCs are quite important in several areas of digital land.12 lists a few examples of UDCs.15] which could be a represented with a 4-bit binary code. Table 5.Digital McLogic Design Chapter 5 396 = 001110010110BCD Figure 5. You’ve already been exposed to UDCs but don’t worry about going to the health center or anything like that. Take a look at the examples shown in Table 5. they’re actually referring the unit distance property and not the special characteristics associated with Gray codes. In other words.7: The solution to Example 5-14. Generally speaking. we can talk about the distance between two code words in the set. 122 . each of the code words is different from all of the other code words in the set. An example of a code set would be the binary numbers associated with the decimal range [0. Since this set of code words now has order. and a specified constant bit-length. We essential changed the cell numbering in a K-maps in order to obtain unit distance ordering on both the rows and columns which allowed the Adjacency theorem to be applied in a visual manner. Just know where you hear the words “unit distance” that it’s describing a relationship between two binary number used to represent something of importance. Table 5. when you see the word distance. you only need to toggle one bit. the distance between two code words is defined as the number of bits that must be toggled (inverted) to form one code word out of a contiguous code word in the set. 5.11: A few examples of “distances” between code words. uniqueness.2 Unit Distance Codes (UDC) The concept of “distance” in digital-land has a special and relatively simple meaning. to get from one code word to the next code word in the sequence.4.11 shows an example of a 5-bit binary code. the set of codes also has a specified sequence.11. Code Word A 00000 01110 00111 Code Word B 11111 00110 11100 Distance 5 1 4 Comment 5 bits must be toggled Toggle second bit from right Toggle outer two bits Table 5. What this implies is that you have a given set of binary code words of equal length. Also good to note here is that a special form of UDCs are Gray Codes. There is actually a science to creating UDCs but we’ll not go into that here.

and radix complement (RC). The key to this method is to agree upon a standard location for this bit. The reality is that computers don’t have an easy and efficient way to place a “-“ sign front of numbers that are to be interpreted as negative. let’s exploit the similarities between these three representations. such as a ‘1’.Digital McLogic Design Chapter 5 2-bit UDC 00 01 11 10 4-bit UDC 0001 0011 0111 1111 1110 1100 1000 0000 8-bit UDC 10000001 11000001 11000011 11100011 11100111 01100111 01100110 00100110 00100100 00000100 00000000 10000000 Table 5. This section presents an overview of representing signed numbers using only the set of symbols associated with the binary number system (namely 1’s and 0’s). But there are a few standard ways used to represent signed binary numbers which we’ll discuss in this section. 5. In particular.5. The reality is that the most widely used is RC notation but we’ll be working with all three and classify the work we do with the less used notations as a wicked academic exercise. 5. computers generally don’t rely on tradition in order to do what they do. Before we start.1 Representing Signed Numbers in Binary Notation There are actually an infinite number of ways to represent signed numbers in binary. But alas.12: Examples of 2. Keep in mind that we only have the option of using ones or zeros to represent negative numbers. You can make up any number of ways and they would be just as valid as any other way2. to indicate that a particular number is negative. computers only have the ability to represent numbers with ones and zeros. there are three representations of interest: sign magnitude (SM). The other accepted numerical tradition is that when the number is positive. and 8-bit UDC codes. There is of course no problem when you’re simply writing numbers on a piece of paper because all you need to do is drop a “-“ in front of the number and everyone has come to the agreement that such a number is a “negative” number.5 Signed Binary Number Representations As you probably know by now. Sadly enough. each of these representations has their good and bad points which will be mentioned later. a “+” sign usually does not appear in front of the number. Once we introduce these representations. 2 Chief Financial Officers (CFOs) of large companies do this all the time. there is hope. 123 . The easiest and most efficient approach to represent sign numbers is to use a single bit. we’ll concern ourselves with the issues regarding the number ranges of these signed representation and standard mathematical operations with the most common of these representations. diminished radix complement (DRC). This is all fine and good for positive numbers but is seemingly inadequate for negative numbers. 3. There are three standard methods used to represent signed numbers in binary notation.

5. OK. a) 111000012 b) 0100112 124 . Example 5-15 Change the sign of the following binary numbers represented in SM: a) 011000012 b) 1100112 Solution: Changing the sign involves toggling the sign bit and doing nothing to the magnitude bits.8 provides a visual representation of the bit positions of the sign and magnitude bits. Figure 5.13 listed everything you may want to know about tweaking SM numbers.13: Standard operations on binary numbers represented in SM. then the number is interpreted as negative with the magnitude being represented by the magnitude bits. If the sign bit is a ‘1’. If the sign bit is a ‘0’. the sign-bit standard is now carved in stone. Once again. In SM notation. This position is commonly referred to as the MSB position which not surprisingly stands for “most significant bit”. Note that this problem can be done without knowing the decimal equivalents of these binary numbers. Operation Multiply number by -1 Convert positive SM to decimal equivalent Convert negative SM to decimal equivalent Procedure toggle (change state) the sign bit apply binary-to-decimal conversion on magnitude bits 1) note that the number is negative 2) do binary to decimal conversion on magnitude bits 3) add in minus sign (from step 1) Table 5.5.Digital McLogic Design Chapter 5 The accepted position of this bit is in the most significant bit position (highest weighting) of the number that is being represented. the sign bit indicates the sign of the number and the other bits represent the magnitude of the number. Table 5. Figure 5. This effectively separates the number into a bit that represents the sign and some bits that represent the magnitude. the most significant bit position is considered to be the left-most bit position. The MSB in any signed number representation we’re discussing is the sign bit.8: Some generic nine-bit number that is interpreted as being signed.2 Sign Magnitude Notation (SM): Sign Magnitude is the most straight-forward of the three notations because SM notation closely resembles the original model of signed numbers presented in the previous paragraph. the number is a positive number with a magnitude represented by the magnitude bits.

Conversion to decimal is done directly since the sign bit is zero and adds nothing to the final decimal number. Example 5-17 Change the sign of the following binary numbers represented in DRC: a) 011100012 b) 10011012 Solution: Changing the sign involves toggling all the bits. Table 5. Adding the negative sign complete the solution: -19.5. Conversion to decimal is done by noting that the number is negative and doing a binary to decimal conversion on the magnitude bit. Operation Multiply number by -1 Convert positive DRC to decimal equivalent Convert negative DRC to decimal equivalent Procedure toggle all the bits (1’s complement) do binary to decimal conversion on magnitude bits 1) note that the number is negative 2) toggle all the bits (1’s complement) 3) do binary to decimal conversion on magnitude bits 4) add in minus sign (from step 1) Table 5. In DRC notation. b) This number is a negative 6-bit binary number.14 lists everything you may want to know about tweaking DRC numbers. a) 100011102 b) 01100102 125 . The answer is 97. this is a straight-forward matter: toggle all the bits in the binary number (referred to as a 1’s complement). This problem can be done without knowing the decimal equivalents of these binary numbers. 5. The magnitude bits are 100112 which represent 19 in decimal.Digital McLogic Design Chapter 5 Example 5-16 Convert the following binary numbers represented in SM to their decimal equivalents: a) 011000012 b) 1100112 Solution: a) This number is an 8-bit positive number.3 Diminished Radix Complement (DRC) DRC representation is best explained by the operations required to change the sign of the number.14: Standard operations on binary numbers represented in DRC. Once again. the sign bit indicates the sign of the number and the other bits represent the magnitude of the number (but the magnitude is represented differently for positive and negative numbers).

toggle every bit after the first ‘1’ bit that is found (but don’t toggle the first ‘1’ bit). This operation is somewhat straight-forward yet not as simple as the SM and DRC representations. There is hope though.9. b) This number is a negative 6-bit binary number. and 4) adding the negative sign. its negative 1100112 0011002 0011002 represents 12 in decimal Adding the negative sign completes the solution: -12 5. 126 .Digital McLogic Design Chapter 5 Example 5-18 Convert the following binary numbers represented in DRC to their decimal equivalents: a) 011100012 b) 1100112 Solution: a) This number is an 8-bit positive number. 3 This is actually not a trick. When you encounter a ‘1’. Figure 5.5. it can sometimes lead to errors since you’ll possibly need to deal with a carry bit across the span of the number. 2) toggling all the bits. For positive numbers. examine each bit from right to left. The two’s complement is defined as “one greater than the 1’s complement”.15 lists everything you may want to know about tweaking RC numbers. the magnitude bits are considered to be in a two’s complement representation. Conversion to decimal is done by 1) noting that the number is negative. NC stands for “no change” while TOG stands for “toggle”. In Figure 5. In RC notation. A few examples of this will drive the point home. This means that to find the 2’s complement of a binary number. If the number is negative. The magnitude bits are once again interpreted differently for positive and negative numbers. you toggle all the bits (the 1’s complement) and then add 1 to the result. Finding the two’s complement of a number can be done by hand in two different ways. Table 5. it is more of an algorithm. The easiest way to find the 2’s complement of a number is to apply the following trick3: starting from the right-most bit in the binary number. the magnitude bits are interpreted directly as a simple binary number. 1) 2) 3) 4) Yep.4 Radix Complement (RC): RC representation is once again best explained by the operations required to toggle the sign of the number. the sign bit indicates the sign of the number and the other bits represent the magnitude of the number. Conversion to decimal can be done directly using standard binary to decimal conversion techniques since the sign bit is zero and will add nothing to the final decimal number.9 shows just about every case you’ll ever hope to run across. The answer is 113. Though this works fine. and 3) doing a decimal to binary conversion on the resulting number.

This problem can be done without knowing the decimal equivalents of these binary numbers. Operation Multiply number by -1 Convert positive RC to decimal equivalent Convert negative RC to decimal equivalent Procedure take the two’s complement of the number do binary to decimal conversion on magnitude bits 1) note that the number is negative 2) take the two’s complement of the number 3) do binary to decimal conversion on magnitude bits 4) add in minus sign (from step 1) Table 5.Digital McLogic Design Chapter 5 (a) (b) (c) (d) Figure 5. Solution: Changing the sign involves taking the two’s complement of the numbers. b) 10011012.15: Standard operations on binary numbers represented in RC. a) 110010112 b) 01100112 127 .9: Four examples showing the 2's complement conversion algorithm. Example 5-19 Change the sign of the following binary numbers represented in RC: a) 001101012.

Figure 5. Don’t be one of these people. all 2n possible values can be represented.10 is the fact that with SM and DRC representations.Digital McLogic Design Chapter 5 Example 5-20 Convert the following binary numbers represented in RC to their decimal equivalents: a) 001101012 b) 10011012 Solution: a) This number is an 8-bit positive number. Keep in mind that just about everyone is weak when it comes to the notion of 2’s complement math: they get by because they rely on some other entity to mask their lack of understanding of the concepts. The really important thing to notice about Figure 5. But with RC. 1) 2) 3) 4) Yep. and 4) tacking on a negative sign to the result. The ideas are not that complicated once you get used to them. and 3) doing a decimal to binary conversion on the resulting number. only 2n-1 out of the 2n possible values for a given value of n are representable in those notations. computer science. It almost seems that this means one less bit can be used to represent the magnitude of the number and only one half as many numbers can be represented by the same amount of bits4. b) This number is a negative 7-bit binary number. But… if you’re able to grasp the ideas presented in this section. The section that follows is slightly painful. think about it for a minute. This is one of the reasons why RC representation is most commonly used for signed binary number representations in computers. computer engineering. The smaller numbers in parenthesis in Figure 5. DRC. generally speaking. The resulting range is not larger and it no longer starts at zero (as it does for an unsigned binary number). 4 If this does not make sense.10 shows visually what the last few sentences is trying to say. The range of a signed binary number is now centered about zero. And getting use to them will assuredly give you direct benefits down the line. doesn’t that mean that there is one less bit to have a “weighting” in the number? 128 . Conversion to decimal is done by 1) noting that the number is negative. This is not exactly the case. its negative 10011012 01100112 01100112 represents 51 in decimal Adding the negative sign completes the solution: -51 5.10 is that the letter n represents the number of bits in the binary value. you’ll be much better off in digital design.5 Number Ranges in SM. The key to reading Figure 5. and croquet. and RC Notations The reality of representing sign numbers in binary is that an extra bit (the sign bit) is used to represent the sign. If there is one bit dedicated to the sign bit. by golly. The answer is 53. the range of numbers that can be represented with a binary number is shifted downwards when a sign bit is used.10 shows the number ranges when n=8 which is a common bit width in computerland. The reality is that. Conversion to decimal can be done directly using standard binary to decimal conversion techniques since the sign bit is zero and will add nothing to the final decimal number.5. 2) taking the two’s complement.

Without doubt. Make sure you really understand this statement. Data inside of a computer is transferred around via these registers. the computer is comprised of a fixed set of hardware.Digital McLogic Design Chapter 5 Unsigned Binary Number Range Signed Binary Number Ranges SM and DRC RC Figure 5.10 are based on a fixed register size (and hence. if you exceed the limits of the data you’re using. What this means to us is that there are fixed sizes of registers5 that can be used to perform the arithmetic operations. 129 . you’ll run into some of these topics later in your computer education but they’re beyond the scope of this discussion. or 2) go under the stated range of data you’re using6. your fixed result will be valid. The crux of this discussion is that you’ll want to know when you’ve exceeded these limits so you can know whether your answer is valid or not. These topics are not overly complicated but they can seem somewhat strange when you first see them. if you can design a computer to perform efficient mathematical operations. respectively. you’ll have a good computer (based on your definition of good). 5. The ramifications of a fixed register size such as eight bits is that your mathematical operations must stay within these limits if want the result of your particular operation to be valid. In other words. This discussion is nicely framed in the context of how a computer would actually perform addition and subtraction. The reality is that if you stay within these limits. The bit-width of these registers is fixed in a particular computer’s hardware. you’re answer will be invalid. Namely. word length) of eight bits. 6 Going over or under the stated range means the number is off the left or right side of the number line shown in Figure 5. The problem is that there are a bunch of trade-offs along the way. the precision of the arithmetic performed by the computers is limited to some pre-determined value. The topic of binary arithmetic and computers is a deep subject that many people spend their entire lives studying.10: Number ranges for signed and unsigned binary numbers.10. There are two main ways to exceed these limits: 1) go over the stated number range for the size of the data you’re using. This discussion is limited to the issues involved with addition and subtraction of signed and unsigned binary numbers. For example. the number ranges shown in Figure 5. Keep in mind that we’ll need to continue this 5 A register is a piece of hardware that stores a given number of bits.6 Binary Addition and Subtraction There are a few recurring topics regarding the addition and subtraction of binary numbers. Generally speaking.

Overflow would result when the addition of two numbers exceeds the top-end of the given range. all you need to do to subtract one binary number from another is to take the two’s complement of that number and add it to the other number. 5. The good thing here is that we limit our discussion to RC representations only. This knowledge could be actually valuable if you were to find yourself on Jeopardy but it is not something I’m aware of outside of this paragraph. The number represented by the variable A is referred to as the augend.6. the results of your mathematical operation can either underflow or overflow the given number range. Also. Some useful definitions involving the addition and subtraction of two numbers are appropriate here.16 and Table 5.1 Binary Subtraction One of the many recurring themes in digital design land is the fact that you always want to design your circuit to do what they need to do but to do it using as little hardware as possible. the only new thing here is that we’ll be applying this concept in the context of binary subtraction. the better off the world will be.17 list everything you need to know about the overflow and underflow of binary numbers. Although it would be no big deal to design a circuit that did addition and another circuit that did subtraction. After this addition operation. and C is referred to as the difference. This is not a big deal in computerland. Changing the sign of a number is no big deal when dealing with RC numbers: all you need to do is take the two’s complement. Table 5. 5. or digital circuitry. takes up space and consumes power.Digital McLogic Design Chapter 5 discussion for both unsigned and signed binary data. This concept is something you’ve used extensively in standard mathematics. N1 . and C is referred to as the sum.N2 = N1 + (-N2) Equation 5-1: Indirect subtraction by addition. you need to look at a few items that will tell you if your result is valid or not because your result may have exceeded the number range you’re working with. the cool approach is to have one circuit do both operations. Consider adding two numbers A and B with a result C. These two examples arbitrarily use four-bit numbers. In other words.6. B is referred to as the subtrahend. Consider subtracting one number B from another number A with a result C.2 Operations on Unsigned Binary Numbers When dealing with unsigned binary numbers. the extra bit to the left of the four-bit result is the carry bit from the given operation. B is referred to as the addend. In case. The equation for this operation would look like: A + B = C. A is referred to as the minuend. These factors play out directly in this discussion in the context of binary subtraction. Underflow would be the result of subtracting a given binary number from a smaller binary number (the result would be negative which would violate the unsignedness of the number). Generally speaking. Equation 5-1: shows the basic formula for this approach. the less circuitry your design contains. The method used to do this is referred to as indirect subtraction by addition. Mathematical operations in computers do not come for free: they are done by hardware that you’ll soon be learning about and designing. 130 . Hardware.

The approach to dealing with operations on signed binary number is much more intuitive than dealing with unsigned binary numbers. There was no underflow and the difference (the four-bit result) is a valid. 1001 + 0011 = ? + 0 Example 5-22 1011 + 0111 = ? + 1 1011 0111 0010 1001 0011 1100 The carry from the MSB is 0 which indicates there was no carry. The carry out of the MSB is ‘0’ which indicates there was no carry.0011 = ? add the negation of 0011 (two’s complement) 1001 1101 0110 0111 0100 1011 The carry from the MSB is ‘1’ which indicates there was a carry. Therefore the sum (the four-bit result) is not valid. There are only two concepts that you need to keep in mind7 which are listed below for your convenience.6. the results of your mathematical operations can once again both underflow and overflow the given number range. Underflow in Unsigned Binary Subtraction Description Indicator Example 5-23 The difference between two binary numbers is below the number range associated with the operation. Table 5. 7 Remember that we are now dealing with signed binary numbers which means that the MSB in the numbers is designated as a sign bit.3 Operations on Signed Binary Numbers When dealing with signed binary numbers. Therefore the sum (the four-bit result) is a valid. The carry out of the MSB is 1 which indicates there was a carry.17: The low-down on unsigned underflow. The carry-out from the MSB addition is ‘0’.Digital McLogic Design Chapter 5 Overflow in Unsigned Binary Addition Description Indicator Example 5-21 The sum of two binary numbers exceeds the number range associated with the operation The carry-out from the MSB addition is ‘1’. 131 . An underflow has occurred and the difference (the four-bit result) is not valid.16: The low-down on unsigned overflow. 5. 1001 . There is a science behind all of this but understanding the basic principles will allow you to work with this type of problem without memorizing this stuff. + 1 Example 5-24 0111 .1100 = ? + 0 Table 5.

In other words. The following examples in Table 5. the result from the operation A . Overflow: Adding a positive number to a positive number. Also due to indirect subtraction by addition. if the two numbers have different sign bits when the final addition is done. this can included adding a negative number to a negative number. Underflow: Subtracting a positive number from a negative number. In either case. The reality is that overflow and underflow can only happen in the following two scenarios: a. The 132 .Digital McLogic Design Chapter 5 1) Overflow can never occur if you’re adding a positive and negative number. this can include subtracting a negative number from a positive number. There is actually an easy way to check for this but we’ll save the particulars of this operation until we start talking more about VHDL. you’re adding a negative number to a positive number.B will always be valid if both A and B are positive numbers or if A and B are both negative numbers. It’s that easy. the answer is guaranteed to be valid. b. In even other words. 2) Overflow and underflow only occurs when you add to numbers that have the same value for sign bits but the result has a sign bit of a different value. This concept affects both addition and subtraction keeping in mind that subtraction is done by negating the subtrahend and adding it.19 spell out every possible scenario for both overflow and underflow in both addition and subtraction operations. But due to the indirect subtraction by addition.18 and Table 5.

The sign of addend and augend are positive (based on the indirect subtraction by addition) and the sign of result is positive. The sign of addend and augend are different (based on the indirect subtraction by addition) so there can be no overflow or underflow. The result is not valid: an overflow has occurred. No overflow has occurred in this operation and the result is valid.1110 = ? add the negation of 1110 0100 0010 0110 + 0 0100 .18: The low-down on overflow in signed binary numbers.Digital McLogic Design Chapter 5 Overflow in Signed Binary Addition and Subtraction Description The result of an operation between two binary numbers is beyond the number range associated with the operation. The result is valid (the carry is discarded).1100 = ? add the negation of 1100 0100 0100 1000 + 0 Table 5. 133 . The result is not valid: an overflow has occurred. The sign of the addend and augend are the same (both indicate positive numbers) but are different than the sign of the result. The result is valid (the carry is discarded). The sign of addend and augend are different so there can be no overflow or underflow.0011 = ? Example 5-29 add the negation of 0011 0100 1101 0001 + 1 Example 5-30 0100 . Indicator Example 5-25 Example 5-26 Example 5-28 0100 . 0011 + 0010 = ? + 0 0100 + 1110 = ? + 1 Example 5-27 0110 + 0101 = ? + 0 0110 0101 1011 0100 1110 0010 0011 0010 0101 The sign of addend and augend are positive and the sign of result is positive. No overflow has occurred in this operation and the result is valid. Two numbers of the same sign are added and the result is a number of a different sign (this is the direct addition of two numbers or the addition associated with the indirect subtraction by addition method). The sign of the addend and augend are the same (based on the indirect subtraction by addition) but are different than the sign of the result.

0110 = ? Example 5-36 add the negation of 1101 1001 1010 0011 + 1 Table 5. The sign of the addend and augend are the same (both indicate negative numbers) and match the sign of the result. The sign of the addend and augend are the same (both indicate negative numbers) but are different than the sign of the result. Indicator Example 5-31 Example 5-32 1110 + 1111 = ? + 1 1110 1111 1101 Example 5-33 1100 + 1001 = ? + 1 1110 . 134 . Two numbers of the same sign are added and the result is a number of a different sign (this is the direct addition of two numbers or the addition associated with the indirect subtraction by addition method).1111 = ? 1100 1001 0101 Example 5-34 add the negation of 1111 1110 0001 1111 + 0 1100 .Digital McLogic Design Chapter 5 Underflow in Signed Binary Addition and Subtraction Description The result of an operation between two binary numbers is below the number range associated with the operation. The result is valid (the carry is discarded). The result is valid (and the carry is discarded). The sign of the addend and augend are the same (based on indirect subtraction by addition) and match the sign of the result. The result is valid (and the carry is discarded). The sign of addend and augend are different (based on indirect subtraction by addition) so there can be no overflow or underflow. The result is not valid.19: The low-down on underflow in signed binary numbers. The result is not valid. 1111 + 0010 = ? + 1 1111 0010 0001 The sign of addend and augend different so there can be no overflow or underflow. The sign of the addend and augend are the same (based on indirect subtraction by addition) but are different than the sign of the result.0011 = ? Example 5-35 add the negation of 0011 1100 1101 1001 + 1 1001 . The result is valid.

In case you have not gotten the point yet. but for what it’s worth. you’re to the point where you can start doing some mildly interesting designs. The three approaches are listed below as well as some boring explanation.7 The Big Digital Design Overview Now that you’ve learned about both binary arithmetic and digital arithmetic circuits (a previous chapter). 1) Brute Force Design (BFD): Also known as iterative design. here it is: modern digital design consists primarily of Modular Design. This design approach allowed us to bypass the truth table approach of BFD and enabled us to create mildly complex circuits such as the ripple carry adder (RCA). Thus. So here they are: dark box modeling rules: 8 9 But let me know if you think of another approach.Digital McLogic Design Chapter 5 5. 135 .20. There are only a few rules you need to follow when doing modular design. Recall that we’ve been claiming all along that hierarchical design is massively powerful. We also drew boxes within boxes within boxes which we labeled as hierarchical design9. 3) Modular Design (MD): This approach is similar to what we did in the first chapter.20: Matrix explaining why Modular Design can save the world. IMD would be included as a subset of modular design. now we’ll state that modular design of any type is massively powerful. It’s really not that big of a deal but it is certainly worth some type of formal discussion. There are three approaches to digital design. You do modular design by plopping down dark boxes and connecting them up in intelligent ways. this section sums up what digital design is to me. but we’re opting to call it a design approach all its own. So tucked in the back of a chapter on binary mathematics is the big overview of digital design. hierarchical design is a form of modular design. but most importantly. any possible digital design you do necessarily fits into one of these approaches8. In this approach. Remember the dark box design approach? This was actually a good example of Modular Design. 2) Iterative Modular Design (IMD): This was the second approach to design we worked with. I encourage everyone to figure out their one pseudo-formal approach to digital design. The dark box models convey various levels of information regarding the digital circuit. I’m sure digital design means different things to different people. An even more pointless piece of drivel is represented by Table 5. someone can take you model and actually convert it to a working circuit. Design Approach Brute Force Design Iterative Modular Design Modular Design Pros Really straight forward Straight forward Massively powerful Cons Limited by truth table size Not applicable to all designs Requires a working brain Table 5. I’ll for sure add it to this list. This was the first design approach we worked with and was based on assigning outputs to every possible input combination via a truth table. we were most interested in drawing bunches of dark boxes to model our designs. The dark box diagrams are of course a form of modeling. Most appropriately.

RCAs. it’s a mystery how any of the outputs are assigned. we’re left scratching our heads. we’ve seen relatively few of these boxes: HAs.21. You could make this model valid by providing a definition for the ADDER somewhere in your design. This is also a true digital box. Being non-standard. This has all the correct inputs for an RCA. This is a true digital box. we know exactly how it works and how it is built. This is an invalid model. If you replace the HA in a RCA with a FA. At this point.21: Some good and bad example of standard digital dark boxes. Model This is labeled RCA but since we know RCAs to have multiple inputs (bundles) for the addend and augend. we can’t assume we know exactly what this box is doing. There are a lot of standard digital “boxes” out there. Please read through the examples shown in Table 5. Having this input is very handy and is used quite often in digital design. people will not know what you’re trying to model. This is a valid model and there is no need to define it anywhere else in your model. This is a valid model. This is an invalid model. Strongly consider using a ruler if you’re modeling by hand. Since we know what an RCA is. but since it has the ADDER label. and the various gates we’ve talked about. Table 5. 136 . and the inputs and outputs of the box labeled RCA match what we know about RCAs. You could assume it’s a RCA but you could be wrong. you’ll have the extra carry-in input as is listed in this model. To make it valid would required that it be defined somewhere so we all know what it is. everyone will know what you’re talking about and there is no need to define it at a lower level. The catch here is that you must use these boxes in the exact way there were defined. Every box you use in your model should either be clearly defined somewhere (such as at another level) or be a standard digital “box”. Comment This sort of looks like a 3-input OR gate. but having two outputs makes it non-standard. if you don’t. FAs. If you call out one of these boxes in your models. This is a bad model. Provide a definition for all dark boxes: Modern digital design is facilitated with dark box modeling. Label everything: Make sure the reader of your model does not need to make any assumptions about anything.Digital McLogic Design Chapter 5 • • • Be clear and concise: A messy dark box model or circuit diagram is a tragedy that hinders the efficient transfer of information.

What we need to do is use the other approach to changing the sign which was to take the 1’s complement and add ‘1’. you could use VHDL to model a circuit using this algorithm. Figure 5. Take a look at it then read and understand the comments that follow: there are a lot of important digital practices taking place in this problem that you need to know. Minimize your use of hardware in your final model Solution: This is a really important and instructive circuit out in digital design-land. At this point in your design career you may be wondering what to do.11.12. Taking the 1’s complement of the input only requires an inverter for each input to the circuit. This circuit has an output signal VALID that is ‘1’ when the addition operation is valid. Without too much hoopla. Actually. Adding ‘1’ can be done in several ways (though we’ll only use one way for this problem). Keep in mind that the first step is always to draw a dark box diagram of your solution. Figure 5.11: Dark box diagram for RC Sign Changer. 10 137 .12: Dark box diagram for RC Sign Changer. it does not work for digital hardware10. The resulting circuit would be valid but it would be less optimal than using a more intelligent approach. The standard method we learned was the visual algorithm method of starting at the left-most number and look for the first ‘1’ etc.Digital McLogic Design Chapter 5 Design Examples Example 5-37: RC Sign Changer Design a circuit that changes the sign of an 8-bit signed binary number in radix complement form. Although this worked great on paper. Your solution should be provided in the form of a dark box model. The next step is to gather in what you know about changing the sign of binary numbers in RC notation. Note the nicely labeled model shown in Figure 5. the final solution for this example is shown in Figure 5.

The solution starts with drawing a dark box diagram of your solution. The way the circuit is connected in this problem is that B is always zero. generally speaking. Figure 5. Although you always need to connect your inputs to something. To do this. This means that the total equation for the RCA is: SUM = A + B + Cin. the outputs don’t need to be connected if you’re not using them. Lastly. The final implemented equation is therefore: SUM = (not A) + 1. sometimes you also see a Vcc or a Vdd which indicates the signal is connected to the higher voltage rail in the circuit. You also see this notation often in digital design so get used to it. always look back to the original problem for clues. It appears that a single inverter was used on an 8-bit bundle. The first clue is that you’ll be adding a number to another 138 . Minimize your use of hardware in your final model. The funny thing indicates that the Cin input to the RCA is connected to ‘1’. This is actually an accepted shorthand notation for indicating that every signal in the bundle is inverted.13: Dark box model for solution. The next step is to start speculating about what’s goes on the inside of the box.11: the inputs and outputs match in both bundle size and name.12 is consistent with the box in Figure 5. • • • • Example 5-38: Special RC Addition Circuit Design a circuit that adds ‘2’ to an 8-bit signed binary number in radix complement form. Solution: This is another really important and instructive circuit in that it’s does not seem trivial at first.13. and Cin is always ‘1’. This is no big deal. This funny thing indicates that the B input of the RCA is connected to “ground” or ‘0’. We could have drawn eight inverters but it would have messed up our diagram. This circuit has an output signal VALID that is ‘1’ when the addition operation is valid. but does in fact have a relatively simple solution. The Cout signal of the RCA is not connected to anything.Digital McLogic Design Chapter 5 • • The box in Figure 5. The Cin signal has a funny thing connected to it. Note the nicely labeled model shown in Figure 5. This equation therefore is the 1’s complement plus one that we’re looking for and the circuit implements it rather nicely. you may be wondering why this circuit works. You see this notation often. The B signal has a funny thing connected to it. The RCA as drawn in this problem uses a FA for the LSB. Your solution should be provided in the form of a dark box model. A is always inverted. Note that you could have drawn this diagram even if you knew nothing else about how to proceed with the solution.

check out Figure 5. The big question is how iare we going know if the addition operation is valid or not? The answer lies in the fact that since we’re adding two signed binary numbers in RC form. The next thing we’ll need is some type of circuitry indication when the solution is valid or not. we can connect IN_VAL to one of the RCA operands and “hardwire” a binary “2” to the other operand.Digital McLogic Design Chapter 5 number which means that we’re going to need an adder. but it’s a valid way since there are only three inputs. the answer will only be valid if the sign of the result is the same as the sign of the two input operands. Although the inputs to the CTRL box are still unknown. Therefore.16. table entries were A=1 have are listed as don’t cares.14. OK… let’s put it down. The CTRL circuit is going to indicate if the operation was valid or not.14 that will help you move toward the solution. we know the output is going to be the VALID signal. Figure 5. The output of this circuit is going to be the result of the sum so we can connect the output of the RCA to the OUT_VAL signal. 139 . 11 It may not be the best way. Here are some interesting to note about Figure 5. The only adder we know about is a RCA so that’s that well use. The resulting truth table is shown in Figure 5. We will not need the Cout signal of the RCA so we can leave it unconnected since it’s an output. The result of listing all of these interesting things is shown in Figure 5. • • • • The next step in the solution is to design the interior of the CTRL box. This is often referred to as “control” circuitry. Note that because the sign-bit of the A input will always be ‘0’.15. Therefore. The key to filling out this table is to note that the result of the binary addition is only going to invalid when the sign bits of the operands are the same and the sign bit of the result is different. • The RCA is going to add two things: the IN_VAL and the number “00000010” (which is 2 in binary). the CTRL box will need three inputs: the sign bits of the two RCA operands and the sign-bit of the SUM operand.14: The next step in the solution. The best way to do with is with a truth table11.

But this approach is more structured and thus. the fact that the sign bit of the A input to the RCA does not affect the problem makes sense. we instead just started working towards a solution starting with what little we knew about the problem.Digital McLogic Design Chapter 5 Figure 5.18. Figure 5.18 represents the lower-level of the solution A few comments… yes. Note that we did not need the A sign-bit input after all.17 represents the higher-level portion of the solution while Figure 5. The final solution is shown in Figure 5. we eventually ended up at the solution.15: The next step in the solution. more clearer. It did not have to be in that we could have placed the OR gate of Figure 5. Note that there are two parts to the solution. The equation that describes the truth table of Figure 5. 140 . In the end.17 and Figure 5.17. each of these parts represents a different level of the design. Using this approach. this is a true hierarchical design. Also note that we never really had an idea of the final solution when we started the problem.18 into the dark box diagram of Figure 5.16: The truth table modeling the CTRL box. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 S 0 1 0 1 0 1 0 1 VALID 1 0 1 1 - Figure 5.16 is: F = B + S .

17: The final solution to this problem.18: The other part of the final solution.Digital McLogic Design Chapter 5 Figure 5. 141 . Figure 5.

Signed binary numbers commonly use one of three representations: sign magnitude (SM). One of the key concerns when performing binary arithmetic operations is whether the result is valid or not. binary-to-octal. Binary addition and subtraction has special meaning in the context of signed binary number representations. Signed binary numbers typically use a sign-bit to indicate the sign (negative or positive) of a given number. particularly since hierarchical design is a form of MD. or Radix Complement (RC). The important most common conversions are decimal-to-binary. By far. Each of these conversions used special algorithms. 2) Iterative Modular Design (IMD). • • • • • 142 . and 3) Modular Design (MD). Conversion between numbers used in digital design is often required. Binary coded decimal (BCD) and unit distance codes (UDCs) are two of the commonly used binary codes in digital logic. Diminished Radix Complement (DRC). hexadecimal-to-binary. Binary subtraction is typically done by using addition. This technique is referred to as the indirect subtraction by addition method. and binary to hexadecimal. Modular Design is the most powerful. octal-to-binary.Digital McLogic Design Chapter 5 Chapter Summary • • Hexadecimal (base 16) and octal (base 8) are two of the primary number systems commonly used and associated with digital design. binary-to-decimal. There are three basic approaches to digital design 1) brute force design (BFD).

a) b) c) d) e) 001100 . Indicate which results are valid based on the given number range. Indicate which results are valid based on the given number range. a) b) c) d) e) 01001010 + 00010000 11110000 + 00010001 11100100 + 00100101 01000000 + 01110000 01001000 + 01111111 143 .011011 010010 . Indicate which results are valid based on the given number range.000110 4) Complete the following mathematical operations on the unsigned binary numbers. a) b) c) d) e) 001100 + 000011 001110 + 000111 100101 + 101010 001000 + 111100 000100 + 101111 3) Complete the following mathematical operations on the unsigned binary numbers.Digital McLogic Design Chapter 5 Chapter Exercises 1) Complete the following table: # bits 4 6 8 10 11 12 14 15 16 unsigned binary range signed binary range (RC) 2) Complete the following mathematical operations on the unsigned binary numbers.001000 111010 .111100 010001 .000111 100101 .

10111 j) 11101 .01110 10100 .01001 i) 10111 .11001 7) Complete the following mathematical operations on the signed binary numbers (RC representation).11111100 6) Complete the following mathematical operations on the signed binary numbers (RC representation).11000010 11010011 .E716 to octal.00011 h) 01001 .11000 01010 .112 by 8.01110 11111 .11110 8) 9) 10) Convert 2AF6.01001110 00100101 .10100 00111 .11010 k) 11000 .10001110 10000001 .328 to hex.11110 01110 . Convert 721. Indicate which results are valid based on the given number range. Indicate which results are valid based on the given number range.00111100 11000000 . a) b) c) d) e) 01000001 . Indicate which results are valid based on the given number range. a) b) c) d) e) 00011 + 00111 01110 + 00011 01001 + 00100 01010 + 00111 01011 + 01001 f) 00011 .01010 11101 . 144 .00111 g) 01110 . a) 10111 + 01000 b) 11001 + 01111 c) 11101 + 00100 d) e) f) g) h) 11010 .00100 11010 . Multiply 101011011.00100 i) j) k) l) m) 00110 .11100 01010 .Digital McLogic Design Chapter 5 5) Complete the following mathematical operations on the unsigned binary numbers.

What is the maximum distance between any two of the following numbers? 0011. 1110 1110 0001 0011 Which of the following three SB numbers has the largest magnitude? a) = 1110 0001 (SM) b) = 1001 1101 (DRC) c) = 1001 1100 (RC) The three numbers below are listed in hex but they represent 8-bit signed binary numbers in the given formats. 1100. Which of the two following positive numbers has a larger magnitude? 4A. Divide 1AF.E16 or 499. 0111. 23. 000. 1110. 1111.7510 Which of the following two signed binary (SB) number are greater? Assume the numbers are given in radix complement (RC) form. Write the decimal equivalents of the number 1011 11002 if the number is in SM.3D16 by 8.2348 by 64. 0001. Can the follow set of number be made to form a gray code?: 0011.801 What is the minimum radix value of the following number?: BA.B16 Which of these two positive numbers is greater? 1F3. 011. 0001. Multiply 345. Which of the three numbers is the most negative? a) = B4 (SM) b) = CC (DRC) c) = D1 (RC) Assemble these numbers into a gray code sequence: 111. 1100.558 or 15B. DRC and RC forms. 001.Digital McLogic Design Chapter 5 11) 12) 13) 14) 15) 16) 17) 18) Divide 4573. 1110 1110 0000 0010 Which of the following two signed binary (SB) number has a larger magnitude? Assume the numbers are given in radix complement (RC) form. 0111.728 by 4.916 112. 0110. 110. 0110.123 Which of these two positive numbers is greater? 533. 100. What is the minimum radix value of the following number?: 145. 1110. 1111.648 19) 20) 21) 22) 23) 24) 25) 26) 145 .

cross out one code word from each column to make the code shown in the column into a unit distance code. Circle the codes that are unit distance codes. 0000 0010 0110 1110 1111 1100 1101 1001 0001 00000 10000 10001 11001 11011 10111 10011 10010 00010 28) Create a 6-bit unit distance code that contains at least eight unique code words. The first code word should be a unit distance from the last code word (circular). These two columns represent two separate unit distance codes – your answer will not necessarily be the same code word for each code. 29) 0000 0100 0110 0010 0011 1111 1110 1100 1000 30) 0000 0001 0011 0111 0110 1100 1000 The table below shows five separate binary codes. Add the required code words only in the rows indicated with arrows. add one code word to each column to make the code shown in the column into a unit distance code. These two columns represent two separate unit distance codes. In the table below. 01000 01001 01011 01111 11111 01111 01110 01100 00100 00000 00000 00100 01100 01110 11111 11110 11100 11000 10000 000 001 011 111 110 100 0000 1000 0100 0010 0001 0000 0001 0011 0010 0110 0100 1100 1000 146 .Digital McLogic Design Chapter 5 27) In the table below.

5) Design a circuit that subtracts ‘3’ from an 8-bit signed binary number. Minimize your use of hardware in your final model. 4) Design a circuit that provides the absolute value for an 8-bit signed binary number. 8) Design a circuit that translates an 8-bit number in signed magnitude form to an 8-bit number in diminished radix complement form. Your solution should be provided in the form of a dark box model. This circuit has an output signal VALID that is ‘1’ when the operation is valid. 6) Design a circuit that multiplies an 8-bit signed binary number by two. 7) Design a circuit that multiplies an 8-bit signed binary number by three. Your solution should be provided in the form of a dark box model. Minimize your use of hardware in your final model. 2) Design a circuit the changes the sign of an 8-bit binary number in diminished radix complement form. Minimize your use of hardware in your final model. Minimize your use of hardware in your final model. Your solution should be provided in the form of a dark box model. Assume the number is in diminished radix complement form. Minimize your use of hardware in your final model. Assume the number is in radix complement form. Your solution should be provided in the form of a dark box model. For this problem. 10) Design a circuit that translates an 8-bit binary number in radix complement form to an 8-bit number in diminished radix complement form. assume the RC number will always be less than zero. This circuit has an output signal VALID that is ‘1’ when the operation is valid. Your solution should be provided in the form of a dark box model. Assume the number is in radix complement form. 9) Design a circuit that translates an 8-bit number in diminished radix complement form to an 8-bit number in signed magnitude form. 3) Design a circuit that provides the absolute value for an 8-bit signed binary number. Assume the number is in radix complement form. This circuit has an output signal VALID that is ‘1’ when the subtraction operation is valid. 147 . Your solution should be provided in the form of a dark box model. Minimize your use of hardware in your final model.Digital McLogic Design Chapter 5 Chapter Design Problems 1) Design a circuit the changes the sign of an 8-bit binary number in sign magnitude form. Assume the number is in sign magnitude form.

the basic VHDL design units are introduced. Another common problem with several digital design texts is that they attempt to simultaneously integrate the 148 . AND INTRODUCTION: This chapter describes the motivation and justifications used by this text to introduce VHDL. and later tried to integrate the HDL concepts into existing material. Material presented in this manner has a tendency to be confusing and easily forgotten if misunderstood or never applied. VHDL MODELING INTRODUCTION: VHDL modeling is introduced by presenting various examples.2 VDHL in Modern Digital Design Although there are many online books and tutorials available dealing with VHDL. but also give them the skills and confidence to continue on with VHDL-based digital design and the development of skills required to solve more advanced digital design problems. The skills presented with this and subsequent chapters allow digital design students to not only navigate modern digital design in the early courses. Material with these characteristics is written from the standpoint of someone who is painfully intelligent or has forgotten that their audience may be seeing the material for the first time. (Bryan Mealy 2011 ©) 6. The approach taken by this chapter is to provide students with only what they need to know to quickly get them up and running in VHDL. Although these texts make for worthy reference material. it is much easier to build on what you know as opposed to continually adding information that is not directly applicable to the subjects at hand. these sources are often troublesome for several reasons. much of the information regarding VHDL is either needlessly confusing or poorly written. Secondly. however.6 Chapter Six 6. Most of this material would best be presented later in the presentation.1 Chapter Overview The purpose of this VHDL presentation is to provide a guide to help develop the skills necessary to be able to use VHDL in the context of modern introductory and intermediate level digital design courses. Main Chapter Topics VHDL INTENT. The primary uses of VHDL are also briefly described. they do not. As with all learning. PURPOSE. the common approach for most VHDL manuals is to introduce too much extraneous information and too many topics too early. VHDL DESIGN UNITS: The entity and architecture. once you obtained and applied some useful information. First. It is blatantly obvious that in these texts. make for a good learning experience. Most modern introductory digital design texts suffer from similar drawbacks. One common problem with digital design texts is that VHDL is not smoothly integrated into the learning experience. the authors had previously written the non-HDL portion of the text.

VHDL is a powerful tool. Using an HDL is much like using a computer language. Once you learn the basic concepts of programming. This approach to VHDL in no way presents a complete description of the VHDL language. digital design students should be able to quickly and efficiently create useful VHDL models and enhance their understanding of digital systems and the modern digital design paradigm. the basic programming concepts do not change and are directly applicable most any programming language. There are many online VHDL references and tutorials as well as many relatively inexpensive VHDL texts available from online booksellers3. The VHDL modeling paradigm is also an interesting companion to algorithmic programming. simulation. The intent of this introduction to VHDL is to present topics in the context of the average student who has some knowledge of digital logic and has some skills with algorithmic programming languages such as Java or C. I can tell you first hand that this guy knew close to nothing about VHDL and was not interested in learning anything useful. you only need to learn the syntax of the new language. The information presented in this text is focused on a base knowledge of the approach and function of VHDL. Sort of strange. This text opts to use VHDL for modeling digital circuits. There are only a few. The two major HDLs are VHDL and Verilog. and they’re not that complicated. This attribute leads to the now famous TMI syndrome (too much information) and serves no useful purpose.com. With a proper introduction to the basics of VHDL combined with a logical and intelligent introduction of basic VHDL concepts.Digital McLogic Design Chapter 6 introduction of several HDLs (include VHDL. The ideas presented herein represent what generally the core ideas you’ll need to get up and running with VHDL. some of the fine details of VHDL have been omitted from this approach. It is well worth noting that VHDL and other similar hardware design languages are used to create most of the digital integrated circuits found in the various electronic gizmos that currently overwhelm our modern lives. Keep in mind that HDLs do have special “concepts” that you must know that are different from the basic concepts of a programming language. but welcome to the Cal Poly EE Department. In an effort to expedite the learning process. One final comment: the VHDL introduction presented in this text quickly brings you down the path to understanding VHDL and writing solid VHDL code. In this way. The same is true when learning an HDL. In computer programming. Verilog. There are several HDLs out there that you could be learning. 3 Check Ebay or www. the more it will enhance your learning experience independently of your particular area of interest. Cal Poly students were stuck with that book for years and only one person in the EE Department actually did something about it (no one else really cared about the low quality of instruction that the book provided). The worst digital design textbooks ever written are structured using this format2. be sure to take a look at some of these references. The author worked at Cal Poly. Anyone who has the time and inclination should feel free to further explore the true depth of the VHDL language. 1 149 . 2 There was such a book used at Cal Poly for years. however. you can quickly learn a different programming language because you’ll only need to learn the syntax of the new language. Being able to write solid VHDL code facilitates the design and understanding of digital circuits.addall. If you find yourself becoming curious about what you’re not being told about VHDL in this text. This is a blatant attempt to increase the sales of the text without giving thought to the trials and tribulations of the digital design students who’ll be using the text. The concept of using software to design hardware that is controlled by software will surely cause you endless hours of contemplation. If you understand the basic concepts of the HDL modeling paradigm. The more you understand in the time you put into studying and working with VHDL. Lastly. and test tool rather than another batch of throw-away technical knowledge encountered in some forgotten class or laboratory. Lastly worthy of comment is the fact that some texts include the HDL information only at the end of the text. and ABEL)1. students will be able to view VHDL as a valuable design.

But different from higher-level computer languages such as C and Java. Modern digital design is more about appropriately5 modeling digital circuits and maintaining a quality description of the circuit as opposed to learning a bunch of throw-away knowledge that only serves to allow the instructor to write and grade exams more easily. VHDL represents a modern digital design paradigm. The main function of VHDL is describing digital circuits4. VHDL is not. 1) Modeling Digital Circuits and Systems: A digital circuit/system is any circuit that processes or stores digital information.Digital McLogic Design Chapter 6 6. Although the word model is one of those overly used words in engineering. we’ll only give it a brief mention here. the “V” in VHDL is short of yet another acronym: VHSIC or Very High-Speed Integrated Circuit. you understand the VHDL design paradigm and you use it to your advantage rather than fight it. The tendency for most people familiar with a higher-level computer language such as C or Java is to view VHDL as just another computer language. 4 150 . In other words. Once again. however. But since knowing this history is probably not going to help you write better VHDL models. One of primary great features of modeling digital circuits with VHDL is that the rich syntax rules associated with VHDL forces you to describe the Probably a better way to view VHDL is as a tool to “model” digital circuit. Obviously. These inherent differences should encourage and inspire you to rethink how you write VHDL models. The common mistake made by this approach is to attempt to “program” in VHDL as you would “program” a higher-level computer language. The HDL stands for Hardware Description Language. It is. This leads to a more appropriate vernacular to describe a pile of VHDL source code: you generate VHDL models as opposed to writing VHDL source code. in this context is simply refers to a description of something that presents a certain level of detail. 5 The word appropriately here means that you stay within the designated boundaries of the modeling system. This problem is compounded once the size and complexity of your digital circuits becomes greater.3.3 VHDL Introduction VHDL has a rich and interesting history. the state of technical affairs these days has obviated the need for nested acronyms. there are four primary purposes for learning and using hardware description languages such as VHDL. Consulting the proper text or search engine yields this information for those who may actually have an interest. The latter terminology is more of a computer science-type lingo so we’ll definitely try to steer clear of using it. Attempts to write VHDL code with a higher-level language style generally results in VHDL code that no one understands. These four main purposes of VHDL align perfectly with what VHDL should be used for in introductory and intermediate digital design courses.1 Primary Uses of VHDL Although HDLs have many uses. it will most likely be inefficient due to the fact that the resulting hardware is needlessly large and overly complex. Another way to look at this is that higher-level computer languages are used to describe algorithms (inherently sequential execution) and VHDL is used to describe hardware (inherently parallel execution). And if the circuit does actually work. is the primary use for VHDL. The “HDL” acronym is vastly important. Understanding the basics of VHDL allows you to avoid these problems. Higher-level computer languages are sequential in nature. This is not altogether a bad approach in that such a view facilitates a quick understanding of the language syntax and structure. 6. the tools used to synthesize the circuits described by this type of code have a tendency to generate circuits that generally don’t work correctly and have bugs that are nearly impossible to trace. or hardware modeling. Moreover. In this case. the emphasis in modern digital design is to develop skills that are immediately applicable and can be easily built upon. VHDL is a true computer language with the accompanying set of syntax and usage rules. The accepted definition of model is somewhat open in that it does not specify what that certain level of detail is. “describing hardware”. Actually. worthy to state what the VHDL acronym stand for.

see the next item). modeling a circuit using VHDL guarantees a specific circuit operation (this assumes that the model is synthesized correctly. the only possible way to understand complex digital circuits is to model them on different levels of abstraction. work with the limitations of the VHDL toolset in order to generate solid VHDL models. you’ll be able to translate your VHDL models into actual functioning circuits. here are a couple of items that you should never forget when working with VHDL. Historically speaking. Keep in mind that the software tools are written by humans and inherently have limitations. Modern engineering companies no longer pay engineers to construct circuits. if you’re using a synthesizer that was provided for free. these skills are only 6 7 It’s not really magic. VHDL fulfills these promises. In other words. The tendency here is to prefer graphical-type simulator because they are initially easy to use because they provide a graphical method to model circuits and thus have an inherently more comfortable learning curve. 2) Digital Circuit Synthesis: With readily available software tools. 4) Hierarchical Design Support: As was previously stated.2 The Golden Rules of VHDL Before we go further. This allows you to implement relatively complex circuits in a relatively short period of time and allows you to spend more time designing your circuits and less time actually constructing your circuits7. • VHDL is a Hardware Design Language: Although most people have probably had previously exposure to some type of higher-level computer language. As you will see later. VHDL provides everything that is necessary in order to describe the operation any digital circuit.Digital McLogic Design Chapter 6 circuit in an unambiguous manner. • VHLD has imitations: Although VHDL is flexible enough to allow the modeling of a given circuit in a virtual infinite number of ways. So why should you have to do it? 151 .3. There are other digital circuit simulators available to model your digital designs. There is actually a well-defined science behind it. The awards go to those who can best model their complex circuits in simple ways rather than relying on the synthesizer to do the dirty work. The problem with this approach is that as your digital circuits become more complex. 3) Digital Circuit Simulation: Once you’ve generated a VHDL model. These simulators typically contain some type of graphical method to model circuits. it is far less likely that this synthesizer will actually do what you’re hoping it will do (you’ll have to pay real money for the secret sauce). In other words. VHDL models are magically6 interpreted by software tools in such a way as to create actual digital circuits in a process known as synthesis. VHDL was used for circuit simulation before software tools were created to use the VHDL models for circuit synthesis. Just because your circuit synthesizes does not mean you have created a robust model. 6. do not push the limits of this flexibility. this is similar to the standard software design paradigm. Moreover. you’ll find yourself explicitly connecting a bunch of lines on the computer screen which quickly becomes tedious. software tools can use this model in order to simulate how an actual implementation of the circuit would operate. The more intelligent approach to digital circuit design is to start with a system that is to be able to describe exactly how your digital circuit works without having to worry about the details of connecting massive quantities of signal lines. VHDL contains the functionality necessary to support multiple levels of abstraction.

the information in this section remains constant. you VHDL models. A VHDL model with a neat appearance is a better model in that it transfers more information to the human reader in a faster. Items such as case sensitivity and white space are meaningless to the software responsible for interpreting the models. • Have a general concept of what your hardware should look like. thus angering the VHDL gods. but are of utmost importance for the humans who may be tasked with understanding the models. . will be better. 152 . and thus your circuit will be inefficient digital circuits (if they actually work in the first place). In other words. Although your approach to VHDL modeling in general will change as you acquire more advanced modeling skills. it is vitally important that you don’t abuse the language.4 VHDL Invariants This section contains information regarding the “non-technical” use of VHDL. We present this information at this point because it provides valuable direction that is usable anytime time you use VHDL. Although VHDL is vastly powerful. you are “modeling hardware”. If you are not able to roughly envision the digital circuit you’re trying to model in terms of basic digital building blocks. You have two choices in VHDL land: write beautiful VHDL code or write crap. Making these ideas second nature should help eliminate some of the drudgery involved in learning the syntax of a new computer language while laying the foundation for creating more robust VHDL models. If you use this control properly. more efficient manner. but it is not as magic as it initially appears to be. you’re not “programming”. The primary purpose of the invariants listed in this section is to give the digital designer creating the VHDL models an extensive amount of control over the final model. you should memorize the basic information presented in this section. Although it’s rarely a good idea for people to memorize anything. if you don’t understand the basic digital constructs8. There is a strong analogy between higher level programming languages and digital design in that even the most complex digital circuits are describable in terms of basic digital constructs10. 6. it’s probably bad VHDL code. Don’t forget about this section: come back and reread it once you generated a few VHDL models as it will make more sense then. there are several structures in VHDL that appear similar to constructs in higher-level languages. When you’re working with VHDL. simply stated. If your VHDL code appears too similar to code of a higher-level computer language. 6. Your VHDL code should reflect this fact. VHDL does not use these structures in the same way as the higher-level language. Digital design is similar to higher-level language programming in that even the most complicated programming at any level are decomposable into some simple programming constructs9.Digital McLogic Design Chapter 6 indirectly applicable to VHDL. As you will soon discover. there is no inbetween.4. This point relates closely to the item in the previous bullet. VHDL is cool. Regardless of this fact. you won’t be able to generate solid VHDL models. you’ll probably misuse VHDL.1 Case Sensitivity 8 9 And there’s really only a few of them… It’s the structured programming thing all over again… 10 Basic digital constructs include one of the relatively few “standard” lower-level digital devices.

The general rule is to comment any line or section of code that may not be clear to a reader of your code besides yourself. although your code looks great in your editor. The moral of this story: know thy editor. Dout <= A and B.1 have the exact same meaning (don’t worry about the syntax of the statement or what the statement actually means though).2 once again shows that VHDL is not case sensitive.4.2 White Space VHDL is not sensitive to white space (spaces and tabs) in the source document. The result is crappy looking VHDL code and loss of friends in your social network. nQ <= in_a OR in_b. Figure 6. Not all of these editors handle whitespace in the same manner. it could possibly look like crap (improper indentation) in an editor that someone else who needs to work with your code is using12. it is inevitable that many different text editors will be used. Figure 6. Appropriate use of comments increases both the readability and the understandability of VHDL code.1 shows an example of VHDL case sensitivity and not good VHDL coding practices. It’s hard to image code that has too few comments: don’t be shy. when you generate hard-copies of your code.3 shows two types of commenting styles.This next section of code is used to blah-blah 11 Deep down in the bowels of VHDL. Figure 6. there are no block-style comments (comments that span multiple lines but don’t require comment marks on every line) in available in VHDL13. there are some instances of case sensitivity but you’ll more likely than not run into these instances for a long time. each printer contains an evil demon that interprets you tab characters in such a way as to mess up your code. 6.4. The only inappropriate use of a comment is to state something that is patently obvious. Note that Figure 6. -. 6.2 have the exact same meaning. First.Digital McLogic Design Chapter 6 VHDL is not case sensitive11.3 Comments Comments in VHDL begin with “--“ (two consecutive dashes). The VHDL synthesizer ignores anything after the two dashes and up to the end of the line in which the dashes appear. Keep in mind that Figure 6. use lots of comments.1 An example of VHDL case insensitivity. Also worthy of noting on this topic is the use of tabs in your VHDL models. however.2 is not an example of good VHDL coding style in that neither of the statements is as readable as they could be. This means that the two statements shown in Figure 6. There are two reasons not to use tabs in your VHDL models. 13 Many editors. Second. 12 When you’re working on a large project with many people. 153 . Unfortunately. The two statements in Figure 6. doUt <= a AnD b. Research has shown that using lots of appropriate comments is actually a sign of high intelligence.2: An example showing VHDL's indifference to white space. Once again. nQ <= In_a or In_b. Figure 6. are able to comment and uncomment large sections of code automatically.

there are precedence rules associated with the various operators in the VHDL language.6 Control Constructs: if.4 Parenthesis VHDL is relatively lax on its requirement for using parenthesis. 154 . the VHDL synthesizer interprets the two statements shown in Figure 6.4. The VHDL synthesizer is not as forgiving as other languages when superfluous semicolons are place in the source code. if x = ‘0’ and y = ‘0’ or z = ‘1’ then blah. the VHDL language contains if.Assign next_state value to present_state Figure 6. This fact helps when attempting to remove compile errors from VHDL code since semicolons are often inadvertently omitted during initial coding. Like other computer languages. the synthesizer rarely flags that line as an error. Make a special note of this section as one you may want to reread once you’ve had a formal introduction to these particular statements.4. then Figure 6. if ( ((x = ‘0’) and (y = ‘0’)) or (z = ‘1’) ) blah. Always remember the rules stated below when writing or debugging your VHDL code and you’ll save yourself a lot of time.some useful statement end if. -. 6. In other words. if you forget to include a semicolon on a particular line. Though it is possible to learn all these rules and write clever VHDL source code that will ensure the readers of your code will be scratching their heads.some useful statement end if. a better idea is to practice the liberal use of parenthesis to ensure the human reader of your source code understands the intent of the code. -.3: Two typical uses of comments.4.4: An example of parenthesis use that produces clarity and happiness. PS_reg <= NS_reg. Don’t worry about the syntax presented in Figure 6. 6.fake for block-style commenting.some useful statement blah. -.blah-blah blah-blah. and loop statements.Digital McLogic Design Chapter 6 -. and loop Statements As you soon will find out. Note that in Figure 6. -. the extra white space in addition to the parenthesis to makes the lower statement more clear. -. This type of comment is the best -. VHDL statements are terminated with a semicolon.4 as being equivalent. case. 6. A common source of frustration that occurs when learning VHDL is the classic dumb mistakes involving these statements.5 VHDL Statement Termination Similar to other algorithmic computer languages. The main challenge them becomes to know what constitutes a VHDL statement in order to know when to include semicolons. As an example.some useful statement blah. we’ll touch on that later. case.4.4.

Remember. Listed below are the hard and soft rules (i.1. respectively) regarding VHDL identifiers. and the underscore character (‘_’). you must follow them or you should follow them. digits (0-9).e. Shorter names make for more readable code. signal names. family. A few examples of both good and bad choices for identifier names appear in Table 6. and friends.7 Identifiers An identifier refers to the name given to discern various items in VHDL. • Identifiers must start with an alphabetic character. In other words. • Identifiers should be self-commenting. but longer names present more information. It’s up to the designer to choose a reasonable identifier length. the VHDL version is “elsif” • Each case statement is terminated with an “end case” • Each loop statement has a corresponding “end loop“ statement 6. • Identifiers must not end with an underscore and must never have two consecutive underscores. understandable. Examples of identifiers in VHDL include variable names. • Identifiers can only contain some combination of letters (A-Z and a-z). Examples of identifiers in higher-level languages include variable names and function names. intelligent choices for identifiers make your VHDL code more readable. 155 . • Identifiers can be any length (contain many characters).4. People should quietly mumble to themselves “this is impressive looking code… it must be good”. and port names (all of which will be discussed soon). the text you apply to identifiers should provide information as to the use and purpose of the item the identifier represents. superiors.. and more impressive to coworkers.Digital McLogic Design Chapter 6 • Every if statement has a corresponding then component • Each if statement is terminated with an “end if” • If you need to use an “else if” construct.

Unfortunately.8 Reserved Words As with other computer languages.2 are standard operator names such as AND. Obviously. indifference to white space. particularly coding text.1: Examples of desirable and undesirable identifiers. 6. (the basic gates used in digital logic). the level of readability of any document. Notably missing from Table 6. and lax rules on parenthesis creates a virtual coding anarchy. A partial list of reserved words that you may be more inclined to use appears Table 6. is 156 .4. the VHDL language assigns special meaning to many words.9 VHDL General Coding Style Coding style refers to the appearance (as opposed to the function) of the VHDL source code. These special words. Generating readable code is therefore the main emphasis in VHDL coding style.2. the freedom provided by case insensitivity. XOR.Digital McLogic Design Chapter 6 Valid Identifiers data_bus_val WE div_flag port_A in_bus clk descriptive name classic “write enable” acronym a real winner provides some info input bus (a good guess) classic system clock name 3Bus_val DDD mid_$num Invalid Identifiers begins with numeric character not self-commenting contains illegal character contains consecutive underscores ends with underscore uses VHDL reserved word total garbage true but try to avoid valid way too ugly possibly lacks meaning illegal character (dash) no comment… last__value start_val_ in @#$%%$ this_sucks Big_vAlUe pa sim-val RSS_SUX Table 6. A complete list of reserved words appears in Appendix. usually referred to as reserved words. 6. etc.4. OR.2: A short list of VHDL reserved words. can therefore not be used as identifiers. access after alias all attribute block body buffer bus constant exit file for function generic group in is label loop mod new next null of on open out range rem return signal shared then to type until use variable wait while with Table 6.

Digital McLogic Design Chapter 6 subjective. Any VHDL code you may encounter at this point is most likely written by someone with more VHDL experience than a beginner such as yourself. Nice looking code will slant such subjectivity in your favor. Once this is done. Using a consistent coding style enables you to find errors both before compilation and/or after the compiler has found an error. • Adopting a good coding style helps you write code without mistakes. Second. Increased readability is primarily accomplished through the use of indenting certain portions of the program. Style-files are massively useful and should be provided by anyone who is evaluating the appearance of your VHDL code. Examining a circuit diagram containing appropriately named black boxes is much more understandable than staring at a circuit containing a countless number of logic gates. 157 . Instead of stating a bunch of rules for you to follow as to how your document should look. In the black box approach. • Look for and/or request that you be provided with a VHDL style-file that explicitly shows how your code should appear. • Chances are that if your VHDL source code is readable to you. using self-commenting identifiers. 6. Emulate the good parts of their style while on the path to creating an even more readable style of your own. or someone who signs your paycheck at the end of the day. As with other compilers you have experience with. These are the people you want to please. units of action which share a similar purpose are grouped together and abstracted to a higher level. the module is referred to by its inherently more simple black box representation rather than thinking about the details of the circuitry that actually performs that functionality. First. it simplifies the design from a systems standpoint. you’ll find that the VHDL compiler does a great job at knowing a document has error but a marginal job (at best) at telling you the exact location of the error or what the error is. This is particularly true in the case of indenting your code. Other great reasons for using black box diagrams were discussed in Chapter 1. someone who is assigning a grade to your code. you should instead strive to simply make your source code readable. • A properly formatted document explicitly presents information about your design that would not otherwise be readily apparent. These people are most likely massively busy and more than willing to make a subjective glance at your code.5 Basic VHDL Design Units The “black box” approach to any type of design implies a hierarchical approach where varying amounts of detail are available at each of the different levels of the hierarchy. • If in doubt. the black box approach allows for the reuse of previously written and working code. you should model your VHDL source code after some other VHDL document that you find organized and readable. Writing VHDL code is similar to writing code in other computer languages such as C and Java in that you have the ability to make the document more readable without changing the function of the document. it will be readable to others who may need to peruse your document. This approach has two main advantages. These other people may include someone who is helping you get the code working properly. Listed below are a few thoughts on the notion of a readable document. and provided proper comments when and where necessary.

We’ll present information regarding the various VHDL data types in a later chapter. the VHDL entity and architecture are closely related. 16 VHDL is a strongly-typed language. The port_clause specifies the actual interface of the entity.5. The data_type refers to the type16 of data associated with that port. In VHDL terms.Digital McLogic Design Chapter 6 Not surprisingly. The port_name is an identifier used to differentiate the various signals. The port_clause is nothing more than a list of the signals from the underlying circuit that are available to the outside world which is why the entity declaration is often referred to as an interface specification. respectively. data_type. Figure 6. there are many typing rules that you must follow. The entity essentially provides a simple “wrapper” for the lower-level circuitry. The mode specifies the direction of the signal relative to the entity where signals can either enter (inputs) or exit (outputs) the black box15. an entity declaration officially describes the black box. Figure 6. The VHDL entity construct provides a method to abstract the functionality of a circuit description to a higher level. Our approach here is to present an introduction to writing VHDL code by describing the entity and the moving onto the details of writing the architecture. 6. In VHDL. creating the entity is relatively simple while the major portion of VHDL modeling is dedicated to properly describing the architecture. The bold font is used to describe VHDL keywords while italics are used to show names that are supplied by the writer of the VHDL code.5 shows the syntax14 of the entity declaration.1 The Entity The entity is VHDL’s version of the black box. There are many data types available in VHDL but we’ll deal primarily with the std_logic type. The entity_name provides a method to reference the entity. and 2) the stuff that goes in the black box (which of course can be other black boxes). Familiarity with the entity will hopefully aid in your learning of the techniques to describing the architecture. the entity simply lists the various input and outputs of the underlying circuitry. Figure 6. Since VHDL is describing a digital circuit. the black box is specified (or referred to) by the entity and the stuff that goes inside the black box is specified (or referred to) as the architecture. A “port” is essentially a conduit that interfaces a signal inside the box with a signal on the outside world. For this reason. 1) the black box. VHDL bases its descriptions of circuits on the black box approach. This signal can be either an input to the underlying circuit from the outside world or an output from the underlying circuit to the outside world. 15 There are actually other mode specifiers but we’ll discuss them at a later time. As you probably can imagine.5: Generic form of an entity declaration.6 shows the syntax of the port_clause. data_type Figure 6. port ( port_name : mode port_name : mode port_name : mode ). entity entity_name is [port_clause] end entity_name. The concept of boldness is for readability only. 14 158 . data_type. This wrapper effectively describes how the black box interfaces with the outside world. The two main parts of any hierarchical design are.6: Syntax of the port_clause. These input and output signals are associated with the keywords in and out. your VHDL synthesizer won’t have a use for it.

7 shows an example of a black box and the VHDL code used to describe it. There is no one great way to “line things up” so try to at least make it readable and for sure make it consistent.It does a lot of killer things.8 provides another example of a black box diagram and its associated entity declaration. • The VHDL code includes comments which simulate the telling of almost intelligent things. Once again.7. • This example provides a black box diagram of the model. Figure 6. The port names are delineated by commas. Most of the important things to note regard the readability and understandability of the VHDL code. • Each port name is unique and has an associated mode and data type. kill_a : out std_logic. crtl_a. ---------------------------------------------------------------entity killer_ckt is port ( life_in1 : in std_logic.Digital McLogic Design Chapter 6 Figure 6.7: Example black box and associated VHDL entity declaration.7 are equally applicable in Figure 6. drawing some type of diagram helps with any VHDL code and digital design in general. Figure 6. end killer_ckt. draw a picture. Remember… don’t be a wuss. • The VHDL compiler allows several port names to be included on a single line. 159 . ----------------------------------------------------------------. All of the ideas noted in Figure 6. kill_c : out std_logic). ctrl_b : in std_logic. most editors do not allow you to use bold text.Here’s my interface description of the killer circuit -. This is not a requirement. Recall that white space is ignored by the compiler. This again is not a requirement but you should always be striving for readability. The bolding of the VHDL keywords reminds you what the VHDL keywords are. This is a requirement.8. • The port names are somewhat lined up in a feeble attempt to increase readability. you should therefore strive for readability. Listed below are a few things to note about the code in Figure 6. kill_b : out std_logic. life_in2 : in std_logic.

In other words. out std_logic_vector(15 downto 0). the word bus in computer lingo also refers to established data transfer protocols.Digital McLogic Design Chapter 6 --------------------------------------------------------------. As you would imagine.8: An example of an input/output diagram of a circuit and its associated VHDL entity. a_st_1. each separate signal in the bus name contains the bus name plus a number to separate it from other signals in the bus. they’re so straightforward.out_sel is used to select one inputs based on the -. analyzing. in std_logic_vector(7 downto 0). To disambiguate the word bus. The std_logic data type now includes the word vector to indicate each signal name contains more than one signal. in std_logic_vector(16 downto 1). busses are used often in digital circuits. Bundles are easily described in the VHDL entity. magic_in_bus big_magic_in_bus tragic_in_bus data_bus_in_32 mux_out_bus_16 addr_out_bus_16 : : : : : : in std_logic_vector(0 to 3). These sets of signals are commonly referred to as bus signals in computer lingo. The signals in the bundle can be listed in one of two orders which is specified by the to or downto keyword.9 shows a few examples of the new data type and associated syntax. Most the more meaningful circuits that you’ll be designing. Unfortunately.9. There are ways to reference individual members of each bus but we’ll mention those now. in std_logic_vector(0 to 31). sv0. As you can see by examining Figure 6. we’ll be using the word bundle to refer to a set of similar signals and bus to refer to a protocol. big_sig_b : in std_logic. a_st_2 : out std_logic). st_1.9: A few examples of bundled signals of varying content. Bus lines are made of more than one signal that differ in name by only a numeric character. Hopefully. The argument lists shows these two methods in the parenthesis that follow the data type declaration. Figure 6. Be sure not to forget the orientation of signals when you are using this notation in your VHDL 160 . and testing using VHDL have many similar and closely related sets of inputs and outputs. Producing VHDL code with greater clarity should decide which of these orientations to use. In fact. In these examples note that the mode remains the same but the type has changed. VHDL uses a new data type for bundles and a special notation to indicate when a signal is a bundle or not. out std_logic_vector(0 to 15). end out_sel. st_2 : out std_logic. fax_add : in std_logic.conditions of sv0 and sv1 blah blah blah -------------------------------------------------------------entity out_sel is port (big_sig_a. Figure 6. there are two possible methods to describe the signals in the bundle. Figure 6. we’ll throw in one last twist before we leave the realm of VHDL entities. you’re not finding these entity specifications too challenging. sv1 : in std_logic. Individual bus signals are generally referred to as elements of the bus.

this is actually an interface -. The slash across the signal line indicates the signal is a bundle and the associated number specifies the number of signals in the bundle.10 is that the input lines sel1 and sel0 could have been made into a single bundle containing two signals.5.Unlike the other examples. As you can probably imagine.10 shows a black box followed by its entity declaration. The most challenging part about learning VHDL is becoming familiar with the myriad of possible ways that VHDL can describe a circuit. we’ll hide a bulk of the details from you in an effort to make you more comfortable with the basic syntax. 17 I have no idea what this means. Note that the black box uses a slash/number notation to indicate that the signal is a bundle. Figure 6. A more appropriate introduction to bundles would be to see this notation used to describe an actual black box. I put it in here because it sounded incredibly stupid. we’ll introduce more details regarding VHDL. describing the external interface to a circuit is generally much easier than describing the operation of the circuit. Figure 6.for a MUX that selects one of four bus line for the output.10: A black box example containing bundles and its associated entity declaration. ---------------------------------------------------------------------entity mux4_8 is port ( a_data : in std_logic_vector(0 to 7). A good practice is to adopt either the “to” or “downto” style and stick with it in all your VHDL models. Don’t feel bad that you really don’t know what you’re doing because you won’t realize that you don’t really know what you’re doing until much later17. At this point in your digital design career. the VHDL architecture describes the internal implementation of the associated entity. c_data : in std_logic_vector(0 to 7). ----------------------------------------------------------------------. b_data : in std_logic_vector(0 to 7). The architecture is describes what the circuit actually does.sel0 : in std_logic. 6. data_out : out std_logic_vector(0 to 7)).Digital McLogic Design Chapter 6 model. d_data : in std_logic_vector(0 to 7). 161 . end mux4_8. The approach we’ll take is to present some simple examples that utilize simple VHDL operators.2 The Architecture The VHDL entity declaration describes the interface or the external representation of the circuit. Worthy of mention regarding the black box of Figure 6. In other words. Once we introduce more details regarding digital logic and digital design. sel1.

• The declarative region contains items that are used by the architecture but don’t directly describe the operation of the circuit.5. Because the input/output relationship for a given digital circuit can be complex. Figure 6. later bullets cover these items. The examples used in this section are complete but they are simple enough such that they the declarative region of the architecture is left blank. the VHDL designer can include a myriad of information in the architecture body. There are a few key features in the architecture body commenting on.11: The architecture body beautiful in all its generic glory. try to make your identifier names give a hint as to the function of the architecture. The key to VHDL modeling is that every VHDL model has an entity/architecture pair. architecture arch_identifier of entity_name is {declarative region} begin {statement region} end arch_identifier.Digital McLogic Design Chapter 6 6. • The entity_name is the name associated with the entity that a given architecture is describing. designing simple architecture bodies becomes second nature once you do it once or twice. we’ll cover some of the more useful items in a later chapter. Figure 6.3 The Architecture Body The term “architecture body” is the name given to the thing that defines the input/output relationship to the ports listed in the VHDL entity. We’ll do a few simple example follow this boring description. we’ll only present the basics and leave the more challenging stuff until later. • The bold-face typing lists the VHDL keywords. For now.4. • Each architecture body contains one begin statement that terminates the declarative region and an associated end statement that terminates the architecture body. For the following examples. The italicized text represented items that the VHDL designer needs to provide. You’re actually able to put many different items in this area which emphasizes the versatility of VHDL in describing circuit operation.7 outlined the rules governing identifiers.11 shows the generic form of the architecture body. Section 6. • The statement region contains VHDL statements that directly describe the operation of the circuit. Don’t allow the sheer number of items in the list below intimidate you. Be sure to apply self-comment when choosing names for your entities. The VHDL designer also provides the stuff in the braced delineated items. • The arch_identifier is a label that you must supply. 6.6 Simple VHDL Models: entity and architecture You now have enough information in order to model digital circuits using VHDL. we’ll use the architectures to directly model Boolean expression as 162 .

Logic Function AND OR Compliment Logic Symbol Logic Example VHDL Operator AND OR NOT VHDL Example A AND B A OR B (NOT A) A⋅ B + A⋅ B A+ B A Table 6.12 shows the black box diagram while Figure 6. The statement region is filled with basic expressions that model the logic that implements the required circuit functionality. the only operators we’ll need to get started are the operators associated with these three logic functions. we’ll talk about those later. Example 6-1 Provide the VHDL code that models the following Boolean equation: F(B2. Up to this point.12: The black box diagram for Example 6-1.Digital McLogic Design Chapter 6 were presented in the previous chapter18. Figure 6. Inverters are not actually considered to be “gates”. various operators are used to implement required operations. The black box diagram is particularly helpful in VHDL modeling because does a great job of modeling the entity. you have only been introduced to three different logic gates: AND. As you know from higher-level computer languages. B0) = B2 ⋅ B1⋅ B0 + B2 ⋅ B1⋅ B0 + B2 ⋅ B1⋅ B0 Solution: The place to start with any digital design problem is with a black box diagram. Table 6.3: A few of the logic operators used in VHDL.3 shows an overview of these three operators. B1. Fortunately. OR.13 provides the entire solution to Example 6-1. 18 19 The implication here is that there are always other ways to generate your models. and INVERTERs19. 163 . VHDL likewise contains many useful operators. Figure 6.

14 shows the black box diagram for this example. F : out std_logic). • The solution includes a trivial comment in order to remind you of the importance of commenting your code. • The statement region of the architecture contains one statement. Figure 6. Figure 6. • The individual product terms in the solution are placed on three separate lines and lined up nicely in order to increase the readability of the solution. Although the solution in Figure 6. the value of the signal is determined by performing the logic operations on the right side of the signal assignment operator. This one statement uses the signal assignment operator (“<=”) to assign the result of the logic operations to the output.15 provides the full solution. architecture ex1_a of ex1 is begin -. consider this a good use of white space. • The declarative region of the architecture is left blank.B1.13 is relatively short.Digital McLogic Design Chapter 6 entity ex1 is port (B2. he signal on the right side of the signal assignment operator is assigned the result.implement F <= (B2 AND (B2 AND (B2 AND end ex1_a.B0 : in std_logic.13: The full solution (VHDL model) for Example 6-1. 164 . Boolean expression (not B1) AND B0) OR B1 AND (not B0) OR B1 AND B0). end ex1. In other words. Figure 6. Example 6-2 Provide a VHDL model that is equivalent to the following circuit model: Solution: Be sure to note the similarities between this example and Example 6-1. there are some important points to note: • The entity name (ex1) is used to associate the architecture with a specific entity.

Digital McLogic Design Chapter 6 Figure 6.C : in std_logic. entity ex2 is port (A.14: The black box diagram for Example 6-2. F : out std_logic). end ex2_a.B. 165 . end ex2.implement Boolean expression associated with ckt model F <= (A AND (not B)) OR ((not A) AND (not C)). Figure 6.15: The VHDL model for Example 6-2. architecture ex2_a of ex2 is begin -.

The mode specifier can be either an in or an out while the type is either a std_logic or std_logic_vector. • The word bundle is preferred over the word bus when dealing with multiple signals that share a similar purpose. 3) generating actual hardware from VHDL models. • The entity declaration describes the inputs and outputs to a circuit. • The main uses of VHDL include: 1) modeling digital circuits in an unambiguous manner. • Signals described in the entity declaration include a mode specifier and a type. • Basic VHDL operators include logic operators (AND. 166 . This set of signals is often referred to as the interface to the circuit since these signals are what the circuitry external to the entity uses to interact with the given circuit. The word bus has other connotations that are not consistent with the bundle definition. and 4) hierarchical design support. Bundled signals such as these are always easier to work with in VHDL as compared to scalar types such as std_logic. Any introductory digital design text that does not integrate VHDL and basic logic concepts will make a good Kleenex substitute in a pinch. 2) simulating digital circuits. and NOT) and signal assignment operators (“<=”). • Multiple signals that share a similar purpose should be declared as a bundle using a std_logic_vector type.Digital McLogic Design Chapter 6 Chapter Summary • VHDL is an integral part of modern digital design. • VHDL models generally comprise of an entity and architecture. OR.

Digital McLogic Design Chapter 6 Chapter Exercises What is referred to by the word bundle? Why is the word bundle more appropriate to use than the word bus? What is a common method of representing bundles in black box diagrams? Why is it considered a good approach to always draw a black box diagram when using VHDL to model digital circuits? Write VHDL entity declarations that describe the following black box diagrams: 1) 2) 3) 4) 5) (a) (b) (c) (d) (e) (f) (g) (h) 167 (i) .

CTRLB OUTA. (a) (b) 168 .bun_b_bun_c : in std_logic_vector(7 downto 0). entity ckt_a is port ( in_a : in_b : in_c : out_f : end ckt_a.Digital McLogic Design Chapter 6 6) Provide black box diagrams that are defined by the following VHDL entity declarations: in std_logic.ldb. lazy SMD end ckt_f. entity ckt_a1 port ( J. (e) entity ckt_f is port ( rss_bytes. (c) entity ckt_d is port ( big_bunny : in std_logic_vector(31 downto 0). way_bad. rss_dogface worthless.RAM_WE. byte_out : out std_logic_vector(3 downto 0). reg_a. reg_c : out std_logic_vector(7 downto 0).OUTB end ckt_b. What are they? is : in std_logic. in std_logic. mx : in std_logic_vector(1 downto 0). mux_ctrl : in std_logic_vector(3 downto 0). (a) (b) entity ckt_c is port ( bun_a. entity ckt_b is port ( LDA. reg_b. in std_logic.) entity ckt_d is port ( mr_fluffy : in std_logic_vector(15 downto 0).RAM_OE SEL_OP1. : : : : in std_logic. rss_sux.ldc : in std_logic. SEL_OP2 RAM_DATA_IN RAM_ADDR_IN RAM_DATA_OUT end ckt_e. out std_logic).LDB ENA. (d) entity ckt_e is port ( RAM_CS.ENB CTRLA. in std_logic_vector(23 downto 0). in std_locic_vector(9 downto 0). lda. : : : : in std_logic. end ckt_c. : in std_logic : out std_logic. : : : : : in std_logic. insecure. in std_logic_vector(7 downto 0). out std_logic_vector(7 downto 0)). in std_logic. end ckt_d. out std_logic_vector(7 downto 0)). in std_logic out std_logic). byte_out : out std_logic_vector(7 downto 0)). (f) 7) The following two entity declarations contain two of the most common syntax errors made in VHDL. in std_logic_vector(3 downto 0). out std_logic_vector(32 downto 0). go_away big_joke.K CLK Q end ckt_a1. end ckt_d.

Z ) = X ⋅ Y ⋅ Z + X ⋅ Y ⋅ Z + X ⋅ Y ⋅ Z + X ⋅ Y ⋅ Z c) F ( A. B. B. C ) = ( A + B + C ) ⋅ ( A + B + C ) ⋅ ( A + B + C ) ⋅ ( A + B + C ) d) F ( X . Y .Digital McLogic Design Chapter 6 8) Provide VHDL models that implement the following Boolean expressions. 169 . Z ) = ( X + Y + Z ) ⋅ ( X + Y + Z ) ⋅ ( X + Y + Z ) ⋅ ( X + Y + Z ) 9) Provide VHDL models that implement the following circuit models. a) F ( A. (a) (b) (c) (d) 10) Provide a VHDL model that implements a half adder (HA). C ) = A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C + A ⋅ B ⋅ C b) F ( X . Y . Use only one architecture for your solution.

Modular digital design is done at a higher-level than truth table-based iterative designs2. once you learn the few basic digital circuit types out there and become fluent with their use. (Bryan Mealy 2011 ©) 7.1 Chapter Overview One of the underlying themes in digital design is the use of modularity. this solution works fine for smaller digital circuits (circuits with a limited amount of inputs). While the main components in truth table-based designs were the independent variables. even the most complex digital circuit can be subdivided into a set of the relatively few standard digital circuits. The modular design approach is so powerful because it generally models circuits using pre-designed (and tested) modules connected by a combination of signals and 1 2 Please recall the iterative design is extremely limited while iterative modular design is much more powerful. In other words. Hence. Up until this point. iterative modular design1. What you’ll find as you work through this text is that there are simply not that many different types of basic digital circuits out there. The examples presented in this chapter are basic but form a complete foundation of VHDL structural model. Recall the cases of the half and full adders vs. 170 . You’ve already seen the power of the modular approach to digital design in iterative design vs. Main Chapter Topics VHDL STRUCTURAL MODELING OVERVIEW: This chapter presents an overview and the motivation behind VHDL structural models. you’ll be well on your way to be coming a great digital designer. The modularity theme is also one of the major themes of computer program design. The HA and FA were designed with a purely iterative approach while the RCA was design with an iterative modular approach. VHDL STRUCTURAL MODELING MECHANICS: This chapter shows some of the syntax and mechanics involved in using structural modeling. connecting a bunch of standard circuits can best be done with a modular design approach. the main components of modular digital design are pre-designed circuits (the modules).2 Modular Digital Design The general approach to becoming an efficient digital designer is to incorporate modular digital design techniques where ever possible. But if you take that previous statement and look at it in the opposite way. the ripple carry adder. you can create complex digital circuit designs by connecting a set of standard digital circuits in an intelligent way. To put this statement in other terms. the truth table has been our primary tool for generating solutions to digital design problems. In other words. the HA and FA used truth tables as a starting point of the design while the RCA used a modular approach. Modular digital design is another design approach that bypasses some of the basic limitations of truth table-based design. If there actually is a better way. I don’t know what it is. While.Digital McLogic Design Chapter 6 7 Chapter Seven 7. it is not feasible to generate a truth table and subsequent Karnaugh map for circuit larger than four inputs.

VHDL modules can be placed in appropriately named files and libraries in the same way as higher-level languages. This chapter is essentially showing you how to design at a higher-level by showing you how to recall previously design modules and use them in your current design. 7. Although the examples in this chapter seem rather simple. These modules can be easily reused in other designs thus saving the designer time by removing the need to reinvent and retest the wheel. after all the commentary regarding complex designs. there are often design libraries out there that contain useful modules that can only be accessed using a structural modeling approach5. we present a few simple examples. however ready to understand the VHDL-based support mechanism of modular digital design. there are too many people like that already (and most of them end up being adminstrators).3 VHDL Structural Modeling The design of complex digital circuits using VHDL should closely resemble the structure of complex computer programs. Although we’re not at the point of designing meaningful circuits at the modular digital design level. VHDL structural modeling supports modular digital design by directly supporting the hierarchical design partitioning. And finally. they represent the basis of implementing and understanding even the most complex digital circuits. It is not a stretch to state that any complex digital model that does not employ structural modeling techniques would be considered a substandard use of VHDL. Many of the techniques and practices used to construct large and well structured computer programs written in higher-level languages should also be applied when using VHDL to describe digital designs4. One of the many great attributes about VHDL is its support of modular design and module reuse. we are. the examples presented in this section are rather simplistic in nature. VHDL is designed to support this form of coding efficiency. Having access to these libraries and being fluent in their use will serve to increase your digital design efficiency and allows you to design more useful digital circuits while expending a lot less effort. Many computer programs can be modeled as a set of modules that are made to interact with each other with the additions of some extra code referred to as glue code. 171 . The modular design approach increases your efficiency as a digital design by allowing you to assemble previously designed modules into a new and different circuit. You should never find yourself reinventing the wheel in your digital designs. 3 This term is analogous to the term glue code used in computer science. But don’t be fooled. glue logic is some extra logic that is required to assure the correct interaction of pre-design hardware modules. Moreover. This common structure we are referring to is the ever so popular modular approach to coding. Modular designs promote understandability by packing low-level functionality into modules. The benefits of modular design to VHDL are similar to the benefits that modular design or object oriented design provides for higher-level computer languages. We are still relatively early into the world of digital design so you’ll probably be thinking that structural modeling is unnecessary. These examples show the essential details of VHDL structural modeling. 5 This means that you can use the module but you can’t see the model the VHDL model that generated the module.Digital McLogic Design Chapter 7 possibly something that is generally referred to as glue logic3. The hierarchical approach extends beyond code written on the file level. The term structural modeling is the terminology that VHDL uses for the modular design. The VHDL mechanism used to support modular digital design is referred to as structural modeling. Though the structural approach is most appropriately used in complex digital designs. It is up to the designer to conjure up digital designs where a structural modeling approach would be more appropriate. 4 Simply stated. Try not to be substandard. you’ll soon be to the point where the only way you can intelligently model your circuits using VHDL is to use structural modeling. Similarly in digital design. The VHDL modular design approach directly supports hierarchical design which is essential when attempting to understand complex digital designs.

The general approach used in C is to: 1. A VHDL model can be viewed in a similar manner. 172 . etc). Although there is some new syntax to become familiar with. this one module then in turn uses one other module. Besides that. 3. When a computer program is viewed at this level. The general approach used in VHDL is similar: Table 7. 7. once you complete a few structural designs.Digital McLogic Design Chapter 7 Keep in mind that your first exposure to structural modeling may be somewhat rough. Name the module you plan to describe (the entity) Describe what the module will do (the architecture) Let the program know the module exists and can be used (component declaration) Use the module in your code (component instantiation.3. A properly constructed complex VHDL model generally can be viewed as modules using modules (using modules. flat designs are considered poor practice6 in that they typically obfuscate the purpose of the program or design. 4. the use of the methods. each of the levels is based on the depth of the associated function calls. 3.1: Similarities between modules in "C" and VHDL. As with computer programming. But with both computer programming and VHDL modeling. they 6 This is almost too general of a statement. In this context. 4. “C” programming language Describe function interface Describe what the function does (coding) Provide a function prototype to main program Call the function from main program the entity VHDL the architecture component declaration component instantiation (mapping) Table 7. 2. there is nothing forcing you to use the modular approach. or mapping). respectively. Between these two statements is a lot of gray area so the overriding factor in using VHDL to describe circuits is to make your models as clear and concise as possible.1 lists the similarities between these two approaches. this new syntax becomes ingrained in your brain and it becomes second nature to apply. Name the function interface you plan on writing (the function declaration) Code what the function will do (the function definition or function body) Let the program know it exists and is available to be called (the proto-type) Call the function from the main portion of the code. Simple designs should definitely use flat models while complex designs should always use hierarchical models. 2. procedures. For example. The different levels associated with a VHDL models are associated with the depth of structural modeling used in the design. In other less useful computer languages.1 VHDL and Programming Languages: Exploiting the Similarities The main tool for modularity in higher-level languages such as C is the function. 1. a three-level VHDL model contains a base module that contains at least one module. and subroutines accomplish a similar modularity. it can be modeled as having different levels. A typical computer program is structured as functions calling functions (calling functions. etc).

They are actually simple gates but the interfacing requirements of the VHDL structural approach are the same regardless of whether the circuit elements are simple gates or complex digital subsystems. Solution: As you probably have realized. Example 7-1 Implement the following circuit using a two-level VHDL structural model. but it is by no means considered to be digital design. once again. it simply allows you to implement your dark box models.1 shows the original circuit model redrawn with some extra information added. signals that cross this boundary must appear in the entity declaration for this implementation. This example in reality is not an example of good VHDL modeling in that the circuit can be implemented using other more straight-forward approaches. Using one VHDL statement to model this circuit would be an example of a flat design (only one level).4 Structural Modeling Design Overview VHDL structural modeling is best explained using a simple example. 7. In this case. Assigning names to the internal signals is a requirement for VHDL structural implementations as these signals are subsequently assigned to the various sub-modules on the interior of the design (somewhere in the architecture). 173 . The first step in this solution is to redraw the circuit shown in the problem statement. The use of structural modeling supports digital design. internal signals are defined to be signals that do not cross the dashed entity boundary..Digital McLogic Design Chapter 7 really piss me off because although they are technically correct. Figure 7. First. Second. Since the problem states that the solution must use two levels. The extra information provided in Figure 7. each of the internal signals of Figure 7. the dashed line represents the boundary of the top-level VHDL entity i.e. they take too long to understand and they take even long to fix when there is an error present. The following example introduces structural modeling by implementing a simple circuit model. this circuit can be modeled in VHDL using a single statement (based on a single Boolean equation).1 is given a label (or name). As you will see.1 relates to the VHDL structural implementation. VHDL structural modeling concepts are 100% syntactical in nature: VHDL structural models do nothing other than allow you to implement dark box designs (which are thus hierarchical in nature). The approach of this solution is to model each of the discrete gates as individual modules or “systems”. we must use structural modeling to implement our solution. The examples that follow primarily instruct you on using and understanding the special VHDL syntax associated with structural modeling.

Descriptions of XNOR function -----------------------------------------------------------entity big_xnor is Port ( A. The new information is contained in how the circuit elements listed in Figure 7. We only need to provide one definition of the XNOR gate despite the fact that Figure 7. end ckt1.2 is used as modules in a larger circuit. The implementations shown in Figure 7.Digital McLogic Design Chapter 7 Figure 7.Description of 3-input AND function -----------------------------------------------------------entity big_and3 is Port ( A. end ckt1. 174 . The modular VHDL approach allows us to reuse circuit definitions and we freely take advantage of this feature in this solution. ------------------------------------------------------------.1 shows three XNOR gates. We need to provided as least one definition for both the XNOR gate and the 3-input AND gates. F : out std_logic). F : out std_logic). The first VHDL-based portion of the solution is to provide entity and architecture implementations for the individual gates shown in Figure 7.C : in std_logic. architecture ckt1 of big_and3 is begin F <= ( A and B and C ).B.1. Figure 7.2: Entity and Architecture definitions for discrete gates.B : in std_logic. end big_xnor. ------------------------------------------------------------. architecture ckt1 of big_xnor is begin F <= not ( (A and (not B)) or ( (not A) and B) ).2 shows the VHDL models for the XNOR and AND gates.1: A redrawn version of the original circuit model.2 presents us with no new VHDL details. Figure 7. end big_and3.

1.4: Entity declaration for Example 7-1. transforms your circuit into a hierarchical design. by definition. Note that in Figure 7. B_IN : in std_logic_vector(2 downto 0). you’ll not need to refer back to these rules (you’ll find that there’s really not that much to it). Step One: The first step in a structural implementation is identical to the standard approach we’ve used for the implementing other VHDL circuits: the entity. The best way to do this is by cutting. For our design. Keep in mind that the following a bunch of rules is not the best approach to “knowing” something. declaration refers to the act of making particular design units available for use in a particular design.4. 3.Interface description of circuit ----------------------------------------------------entity my_ckt is Port ( A_IN : in std_logic_vector(2 downto 0). Figure 7. the parenthetical operators associated with the input signal names imply that bundle notation is used. These design units are essentially modules that are used and/or defined in the lower levels of the design.4 shows that subsequent entity declaration uses bundle notation.1. Figure 7.Digital McLogic Design Chapter 7 Now that we’ve defined the lower-level modules. but it is a good approach to learning something. we’re ready to implement the higher-level module. EQ_OUT : out std_logic). 2) where to place it. -----------------------------------------------------. the XNOR and 3-input AND gate are considered the interior modules) and can be located by the VHDL synthesizer. The difference between an entity declaration and a component declaration is that the word entity is replaced with the word component. 4. Note that the act of declaring a design unit. A component declaration can be viewed as a modification of the original entity declaration for the individual modules. we need to declare two separate design units: an XOR gate and a 3-input AND gate. The declaration of a design unit makes the unit available for later placement in the overall design hierarchy. Figure 7. Step Two: The next step is to declare the design units that are used by the top-level circuit.3: The basic steps required in a VHDL structural model. and modifying the 175 .3 lists the basic procedures used for implementing a structural VHDL design. In other words. In VHDL lingo. There are two factors involved in declaring a design unit: 1) how to do it. the word component must also follow the end keyword to terminate the declaration. signals that intersect the dashed lines are signals that the entity uses to interface with the outside world and therefore must be included in the entity declaration. The entity declaration is derived directly from dashed box in Figure 7. and.1 and is shown in Figure 7. After you do a few VHDL structural models. end my_ckt. Generate the top-level entity declaration Declare the lower-level design units used in design Declare required internal signals used to connect the design units Instantiate and Map design units Figure 7. 2. pasting. which were previously defined. These steps assume that the entity declarations for the interior modules already exist (for this example.

F : out std_logic). F : out std_logic). In some texts. 7 Sometimes the original entity declaration is not available. you’ll be using a component from a design library and the component declaration is provided either directly or by “including” the particular design library.1 These three signals are analogous to local variables used in higher-level programming languages in that they must be declared before they are used in the design. each signal associate with a component must either map to other component or to a signal in the entity associated with the next higher level in the design. Note Figure 7. end component. end big_and3. Step Four: The final step is to create instances of the required modules and map these instances of the various components in the architecture body. end big_xnor. the process of instantiation includes what we’ve referred to as component declaration but we’ve opted to keep these ideas separate. F : out std_logic). component big_and3 Port ( A. end component. while instantiation refers to the creation of individual instances of the component in the statement region of the architecture body. The approach presented here is to have declaration refer to the component declarations in the declarative region of the architecture body. component big_xnor Port ( A. Figure 7. The only difference is that the intermediate signal declaration does not contain the mode specifier.6 that the declaration of intermediate signals is similar to the signal declaration contained in the entity body. Figure 7. For this design.6.6 shows all of information appearing in the final solution. This mapping step associates external connections from each of the components to signals in the next step upwards in the design hierarchy.C : in std_logic.B. Figure 7. as the word “instance” implies. In these cases. three signals are required and used as the outputs of the XOR gates and inputs to the AND gate. In other words.B. The mapping process provides the interface requirements for the individual components in the design. entity big_xnor is Port ( A.B : in std_logic. The signal declarations are included as part of the final solution shown in Figure 7. These signals effectively provide an interface between the various design units that are present in the final. The component mapping process is therefore included in our definition of component instantiation.5: A comparision of entity and component declarations. Each of the individual mappings includes a unique name for the particular instance as well as the name associated with the original entity. F : out std_logic). 176 . The actual mapping information follows the VHDL keywords of: port map. Each of the signals associated with individual components “maps” to either an internal or external signal in the higher-level design.B : in std_logic. As you quickly find out. Figure 7. the use of intermediate signal in this manner is an extensively used feature in VHDL. Step Three: The next step is to declare internal signals used by your model. The required internal signals for this design are the signals that are not intersected by the dashed line shown in Figure 7. the appearance of instances of design units is the main part of the component instantiation process.C : in std_logic. Internal signal declarations such as these appear with the component declarations in the declarative region of the architecture.5 shows the two entity declarations and their associated component.Digital McLogic Design Chapter 7 original entity declaration7. Technically speaking. The resulting component declaration is placed in the declarative region of the architecture declaration (after the architecture line and before the first begin line). entity big_and3 is Port ( A.6 shows the component declarations as they appear in working VHDL code.

F => p3_out). In this manner. architecture ckt1 of my_ckt is -. orderly. begin x1: big_xnor port map (A => A_IN(2).C : in std_logic. F : out std_logic). x2: big_xnor port map (A => A_IN(1). It is worthy to note that the solution shown in Figure 7. F : out std_logic). B_IN : in std_logic_vector(2 downto 0). end component. B => B_IN(1). each of the signals in the interface of the design units are listed and are directly associated with the signals they connect to in the higher-level design by use of the direct mapping operator “=>”” operator. => => => => p1_out.6: VHDL code for the top of the design hierarchy for the 3-bit comparator.p2_out. end component.XNOR gate -------------------component big_xnor is Port ( A.3-input AND gate ------------component big_and3 is Port ( A.B.intermediate signal declaration signal p1_out. In this approach. a1: big_and3 port map (A B C F end ckt1. and allows the signals to be listed in any order. p3_out.6 is not the only approach to use for the mapping process. end my_ckt. The approach shown in Figure 7. -.6 uses what is referred to a direct mapping of components. the proper choice of labels increases the self-commenting nature of your design and is considered good a VHDL programming approach.Digital McLogic Design Chapter 7 One key thing to note in the instantiation process is the inclusion of labels for all the instantiated design units. F => p1_out).p3_out : std_logic. EQ_OUT : out std_logic).B : in std_logic. Figure 7. connections between external signals from the design units are associated with signals in the design unit by order of their appearance in the mapping statement. In other words. x3: big_xnor port map (A => A_IN(0). Labels should always be used as part of design unit instantiation because the use of appropriate labels increases the understandability of your VHDL model. F => p2_out). p2_out. EQ_OUT). entity my_ckt is Port ( A_IN : in std_logic_vector(2 downto 0). -. The only possible downside of this approach is that it uses up a lot of space in your VHDL source code. complete. a practice that rarely presents problems. This approach has several potential advantages: it is explicit. B => B_IN(0). The other approach to mapping is to use implied mapping. This differs from direct mapping because only signals from the 177 . B => B_IN(2).

p3_out).B. The question arises as to whether the synthesizer is able to differentiate between the signal names across the hierarchy. architecture ckt2 of my_ckt is component big_xnor is Port ( A.B_IN(0).B : in std_logic.7 shows an alternate but equivalent architecture for Example 7-1 using implied mapping. Figure 7. F : out std_logic). port port port port map map map map (A_IN(2).7: Alternative architecture for Example 7-1 using implied mapping. it was able to bypass one of the interesting issues that arise when using structural modeling. different levels of the design will often contain the same signal name. like compilers for higher-level languages.C : in std_logic. Note that the labels used in Example 7-1 did not provide much information due to the relative simplicity of the problem. Name collision does not occur because the signal name on the left side of the direct mapping operator (“=>”) is understood to be internal to the component while the signal on the right side is understood to reside in the next level up in the hierarchy. In this case.EQ_OUT).8: An example of the same signal name crossing hierarchical boundaries. Probably the most common occurrence of this is with clock signals. These labels should be used to present information to the human reader of the VHDL model. x5: some_component port map (CLK => CLK. (p1_out. VHDL synthesizers. CS => CS). 178 .p2_out. Figure 7.p2_out). The association between signals in the design units and the higher-level design are governed by the ordering of the signals as they appear in the component declaration. Also worthy of comment here is the label included with each component instantiation. Often when dealing with structural designs. component big_and3 is Port ( A. a component instantiation such as the one shown in Figure 7. This label precedes the name of the component being instantiated.Digital McLogic Design Chapter 7 higher-level design appear in the mapping statement as opposed to direct mapping where signal names from the both levels are explicitly mapped. end component. F : out std_logic).p2_out. Please avoid the temptation to rename one of these signals to make the model clearer (it will only make the model more oogly). (A_IN(1). Signals with identical names at different levels are mapped according to what appears in the component instantiation statement.p1_out). are able to handle such instances. (A_IN(0). begin x1: big_xnor x2: big_xnor x3: big_xnor a1: big_and3 end ckt2.p3_out. signal p1_out.B_IN(1).p3_out : std_logic. end component.B_IN(2).8 is both valid and commonly seen in designs containing a system clock. Figure 7. This approach uses less space in the source code but requires that signals be placed using a particular ordering. Due to the fact that this design was relatively simple.

Digital McLogic Design Chapter 7 Example 7-2 Implement the following circuit using both a flat VHDL model and a two-level VHDL structural model. There are two points we want to make with this solution beyond which were not present in the previous solution.10: The architecture for the flat version of Example 7-2. In real life.9: The entity declaration for Example 7-2. Figure 7.9 shows the entity declaration that is used for both the flat and hierarchical version of the solution. or top-level. of the solution. Figure 7. Note that the flat version model is short and to the point and represents the approach you should take when you’re required to model relatively simple circuits such as this one. one version may be faster but larger and more power consuming than another version. F : out std_logic). Figure 7.B. Figure 7. 179 .11(a) provides the remainder of the solution.11(b) provides the lower-level of the solution while Figure 7. the development tools would interpret these circuits as being functionally equivalent and generate the exact same hardware. Figure 7. In other words.C : in std_logic. For example. Listed below are a few interesting points regarding the solution. Figure 7. But since this chapter introduces VHDL structural models. Solution: The solution to this example is similar to the solution to the previous example. entity ckt_ex is Port ( A. Figure 7.11(b) provides the higher-level. • Both architectures share the same entity declaration. end. we’ll continue modeling circuits in a less optimal manner8. architecture ckt1 of ckt_ex is begin F <= (A AND B) OR ((not A) AND (not C)).11 shows the solution for the hierarchical version of Example 7-2.10 shows the flat version of the solution.11(b) shows the VHDL models of the 2-input AND and OR gates while Figure 7. 8 In all likelihood. end ckt_ex. there are often occasions where the same circuit is modeled differently. This fact emphasizes that writing clear and concise VHDL models is much more important than attempting to “optimize” (whatever that means) the length of your VHDL code.

11(a). F : out std_logic). inv2_s : std_logic. inv2_s <= not C. end or_2. architecture or_2 of or_2 is begin F <= A OR B. end component. instantiation => inv1_s.AND gate and2: and_2 port map (A B F instantiation => A. B => a2_s. (a) (b) Figure 7. end component. -. end ckt2. F => F). -.model for two-level solution architecture ckt2 of ckt_ex is -.B : in std_logic. This helps the human reader of this solution instantly realize the difference between intermediate signals and signal appearing on the entity declarations. Adding such a postfix is considered good coding practice so you should strongly consider adopting this coding style. The “_s” postfix notation was added to the labels associated with the intermediate signals. architecture and_2 of and_2 is begin F <= A AND B.Digital McLogic Design Chapter 7 • This design used intermediate signals in several areas. => a2_s.OR gate instantiation or1: or_2 port map (A => a1_s.AND gate and1: and_2 port map (A B F -.intermediate signal declaration signal a1_s. Although you could have modeled an inverter on a lower-level (as was done with the AND and OR gates).model for 2-input OR gate entity or_2 is Port ( A. F : out std_logic). • -. a2_s : std_logic. 180 . => B. => a1_s).2-input AND gate declaration ------component and_2 is Port ( A. it is clearer to use the two statements as shown in Figure 7. -.B : in std_logic.11: The two-level solution for Example 7-2. -. end and_2. -. begin -. => inv2_s.inverters for A and C inputs inv1_s <= not A.model for 2-input AND gate entity and_2 is Port ( A. end or_2. -. F : out std_logic). Two separate statements are used to model the two inverters in the design. end and_2.B : in std_logic.B : in std_logic. signal inv1_s. F : out std_logic).2-input OR gate declaration -------component or_2 is Port ( A.

This solution shows that the inverters can be modeled by placing the NOT operator into port mapping section of the instantiation.12: Yet another solution for Example 7-2. Figure 7.You’ll soon be more concerned with ensuring your digital design actually do what they’re supposed to be doing. => a2_s.AND gate and1: and_2 port map (A B F -.2-input OR gate declaration -------component or_2 is Port ( A. => a1_s). there are a few things to note in order to get you going. F => F).another model for two-level solution architecture ckt3 of ckt_ex is -.OR gate instantiation or1: or_2 port map (A => a1_s. a2_s : std_logic. It does initially seem like there is a lot of syntactical stuff to remember.5 Practical Considerations for Structural Modeling While reading about structural modeling is all good and fine. Structural modeling is not something you’ll ever worry about once you get into it as it quickly becomes a no-brainer. 7. => B. -. Attempting to place Boolean expressions in the port mapping clauses is not permissible and angers the VHDL goddesses. Similar to higher-level language programming. => (not B). instantiation => (not A).B : in std_logic.12 shows yet another solution for Example 7-2.intermediate signal declaration signal a1_s. Figure 7.Digital McLogic Design Chapter 7 And finally. you don’t really learn it until you actually implement a few models. B => a2_s. F : out std_logic). -. F : out std_logic).B : in std_logic. Once you get deeply into VHDL.AND gate and2: and_2 port map (A B F instantiation => A. -. begin -. This approach is acceptable but does not work for any other operator other than the NOT operator. end component. end ckt3. but once you really start doing it and do it a few times.2-input AND gate declaration ------component and_2 is Port ( A. -. you’ll be using structural modeling almost everywhere. there is a world full of previously written VHDL models that you can quickly and easily 181 . it becomes second nature. But as a beginner. end component.

• Figure 7. Figure 7. it is up to you and/or you development environment to make sure the higherlevel entity finds the lower level entities/components. There is a library clause before each entity. Once again. The software analogy is of course that the environment creates its own makefile. if you’re using modules from device libraries. what it does is allow you to state which library you’re using for each object. Strangely enough. the VHDL synthesizer needs to be able to find all this stuff.13 are listed below. • • The font is really small… this is because I was trying to fit it all on one page. A couple things to note about Figure 7. This style follows a C programming style in that the objects you use are defined before you use them. While this seems troublesome.13 shows an example of the approach where everything your structural model requires is placed in the same file. What you need to remember here is to cut and paste these lines and drop them in before each entity declaration. there may be an environment out there where it is required. The lower-level components are placed in the file before the higher level-components. Sorry about that. When it comes to entity objects. The comments were chopped out for the same reason.14 shows the multiple file approach to structural modeling. your designs will be relatively simple and you won’t be accessing these libraries as of yet. 182 . The VHDL models in Figure 7.Digital McLogic Design Chapter 7 incorporate into your design using structural modeling. As far as VHDL development environments go. but it makes the code more readable to the human viewer. you have two choices when it comes to first using structural modeling. the software generally does all the magic stuff for you. You can either place all of the entities in the same physical VHDL file or you can use the VHDL development environment you’re using to make your particular design aware of entity objects that your design uses as components. this is a requirement of VHDL. But since you’re probably learning VHDL now. This is not a requirement9. • 9 Actually. Here are a few worthwhile things to note: • • The font is small and the meaningful comments are missing… Each of the cells in the table is considered to be in different physical VHDL files. this makes them similar to functions (the function prototype or definition needs to be known to the compiler before the function is called in the program). In the end.14 are 100% equivalent.13 and Figure 7.

ALL.vhd ----------------------------------------------------------------------------------------------------------------library IEEE.B : in std_logic. signal inv1_s. end and_2. a2_s : std_logic.Filename: all_in_one_file. component or_2 is Port ( A.STD_LOGIC_1164. architecture ckt2 of ckt_ex is component and_2 is Port ( A.C : in std_logic. F => a1_s). or1: or_2 port map (A => a1_s. Figure 7. F : out std_logic). use IEEE. signal a1_s. 183 . ----------------------------------------------------------library IEEE. B => a2_s.B : in std_logic. inv1_s <= not A. end or_2. F : out std_logic). end ckt2. begin and1: and_2 port map (A => A.STD_LOGIC_1164. inv2_s <= not C.ALL. F => a2_s. B => inv2_s. B => B. entity and_2 is Port ( A. inv2_s : std_logic.B : in std_logic. end or_2.B. use IEEE. entity or_2 is Port ( A.STD_LOGIC_1164.ALL. F : out std_logic). end component. entity ckt_ex is Port ( A. end component.B : in std_logic.Digital McLogic Design Chapter 7 ---------------------------------------------------------------------------------------------. F => F). end and_2. architecture and_2 of and_2 is begin F <= A AND B. end ckt_ex. F : out std_logic). F : out std_logic). use IEEE. and2: and_2 port map (A => inv1_s. ------------------------------------------------------------library IEEE.13: One approach to an actual structural model. architecture or_2 of or_2 is begin F <= A OR B.

F : out std_logic).STD_LOGIC_1164. F : out std_logic). entity or_2 is Port ( A. entity ckt_ex is Port ( A. end or_2.STD_LOGIC_1164. Figure 7. end and_2.ALL. ---------------------------------------------------.STD_LOGIC_1164. ----------------------------------------------.ALL. architecture ckt2 of ckt_ex is component and_2 is Port ( A.B : in std_logic. entity and_2 is Port ( A.here is the first file ---------------------------------------------library IEEE. end ckt2. or1: or_2 port map (A => a1_s. use IEEE. use IEEE.ALL. a2_s : std_logic. inv2_s <= not C.B : in std_logic. end component. F => a2_s.here is the first file -----------------------------------------------library IEEE. F => F). end and_2. F : out std_logic). architecture and_2 of and_2 is begin F <= A AND B. end component. F : out std_logic). signal a1_s. 184 .Digital McLogic Design Chapter 7 ------------------------------------------------.B. B => B.B : in std_logic.here is the third file --------------------------------------------------library IEEE. inv2_s : std_logic.C : in std_logic. begin and1: and_2 port map (A => A. F : out std_logic). component or_2 is Port ( A.B : in std_logic. end ckt_ex. and2: and_2 port map (A => inv1_s. architecture or_2 of or_2 is begin F <= A OR B. use IEEE. inv1_s <= not A. B => inv2_s.14: The multiple file approach to structural modeling. F => a1_s). B => a2_s. signal inv1_s. end or_2.

The ability to abstract digital circuits to higher levels is the key to understanding and designing complex digital circuits. • VHDL structural model supports the reuse of design units. • VHDL structural modeling is can be divided into the four distinct steps: 1) generate the higher-level entity declaration. It is. 2) declare the lower-level design units. A flat design is a VHDL model that does not use a structural model and is only used by total wankers such as one professor/author/wanker in the Cal Poly EE Department10. This includes units you have previously designed as well as the ability to use pre-defined module libraries. 3) declare the intermediate signals. 185 . and 4) instantiated the required design units. VHDL structural modeling is similar to higher-level programming in its abstraction and modularization capabilities. The bad news is that the damage this person did to students will require some finite amount of time to repair. • VHDL structural modeling establishes a design hierarchy which is considered a multi-level design. however.Digital McLogic Design Chapter 7 Chapter Summary • Structural modeling in VHDL supports hierarchical design concepts which are hallmark of all digital design. Either direct mapping or implied mapping can be applied. problematic to use implied mapping and always much better to use direct mapping. • Design unit instantiation includes the design unit mapping. 10 The good news is that this person finally retired.

N : in std_logic. architecture my_ckt of ckt is T => t_in. component bb2 port ( L. begin b1: bb1 port map ( D E F G H b2: bb2 port map ( L M N P end my_ckt. end component. end ckt. x2. CLK => CLK. P : out std_logic). Each of the associated VHDL models should contain at least two levels. t2_s : std_logic. end component. x3). => => => => x1.E : in std_logic. end ckt.M. entity ckt is Port ( EN1. Be sure to completely label the final diagram.G. signal x1. x2. C : out std_logic). x1.x2. CLK => CLK. Q => t2_s ). Q : out std_logic). Z : out std_logic). C). Z <= t2_s OR t1_s. signal t_in. => => => => => A. Q => t1_s ).B : in std_logic. CLK : in std_logic. t1_s. EN2 : in std_logic. x3.x3 : std_logic.CLK : in std_logic.H : out std_logic). end component.Digital McLogic Design Chapter 1 Chapter Exercises 1) Draw a block diagram of the circuit represented by the VHDL code listed below. architecture ckt of ckt is component T_FF port ( T. t2 : T_FF port map ( T => t1_s. B. t_in <= EN1 AND EN2. (a) (b) 186 . end quiz1_ckt. (a) (b) 2) Provide VHDL structural models for the circuits listed below. begin t1 : T_FF port map ( component bb1 port ( D. F. entity ckt is port ( A.

Digital McLogic Design Chapter 1 (c) (d) 3) Provide a VHDL structural model for a 4-bit ripple carry adder. 187 . Assume the lowest order bit is implemented with a full adder instead of a half adder.

Digital McLogic Design Chapter 1 188 .

selective signal assignment.1 Chapter Overview Up until this point. digital design performed at a higher level of abstraction is generally more efficient in most contexts. VHDL CONCURRENT STATEMENT TYPES: VHDL contains four major types of signal assignment statements: concurrent signal assignment. These statements are referred to as concurrent statements in that they are interpreted as acting in parallel (concurrently) to all other concurrent statements. VHDL MODEL TYPES: VHDL contains three major model types: 1) dataflow. VHDL is much more structured and more powerful than we’ve been leading on. As you’ll see in this chapter. And as you would guess. Various VHDL modeling constructs supports the inherent parallelism in digital circuit. The slight problem regarding the material presented in this chapter is the fact that we base it around the simple logic functions we’ve been dealing with up to this point. The approach we’ve been taking is to get our feet wet with VHDL in order to develop a basic understanding of the methodology used to generate basic circuits. digital design does not have that much to do with the implementation of functions. conditional signal assignment. Model-types are determined by the type of concurrent statement used. But since your knowledge of digital logic and design has increased.Digital McLogic Design Chapter 8 8 Chapter Eight 8. Main Chapter Topics VHDL MODELING: The entity/architecture pair form the interface and functional description of digital circuit behavior. and process statements. VHDL BEHAVIORAL MODELING: The process statement is primarily used to describe circuit in terms of behavior as opposed to low level logic functions. Process statement use sequential statements to describe circuit behavior. you need to increase your level knowledge regarding using VHDL to model digital logic circuits. 2) behavioral. We’re at the point now where we’re ready to perform our designs at a higher level. Implementing functions with can be considered somewhat of a low-level approach to digital design. you have not really been told the entire story regarding VHDL. (Bryan Mealy 2011 ©) 189 . You’re ready to understand both this structure and the VHDL modeling paradigm. As you’ll surely discover in the upcoming chapters. and 3) structural models.

Lastly. really… Something you should become aware of in this chapter is that you’ve been dealing with “tables” a lot. The standard decoder has a relatively special relationship between the inputs and outputs. let’s step back and remember what it is we’re trying to do with VHDL. this chapter introduces some of those mechanisms. Yes. For all intents and purposes. from here on out in this text. which is essentially a fancy name for a LUT. function implementation in digital design is generally done by using a decoder. we’ll be considering all Boolean functions to represent a device that we’ll refer to as a generic decoder. The following chapter is broken into two parts. in a later chapter we’ll define a standard decoder which is nothing more than a subset of a generic decoder. since by our definition. 3 Recall that the entity declaration is used to describe the interface of a circuit to the outside world. they’re the same thing.Digital McLogic Design Chapter 8 8. the Karnaugh Map is generally a relic of the past glory days of digital design. In other words. Implementing a truth table via a function in digital-land is essentially the same thing as utilizing a LUT in computer science-land. So for now. just decoder. The definition what we’ll use for a generic decoder is this: any non-sequential digital device that establishes a functional relationship between the device input(s) and output(s). The tendency for students with computer Digital design is not about “implementing functions”. There is a special type of a table in computer science-and that you should be aware as it is perfectly analogous to the truth tables you’ve been working with so far. The only reason you’re taught to work with Kmaps is in case some old dude asks you to reduce a function during a job interview2. this chapter is based on nothing more than implementing functions. we’ll be mixing the notation between “function” and “decoder”. We’ll discuss this more later. you can assume the VHDL synthesizer will do the reduction for you and do it without making all the mistakes you probably make when you’re reducing functions by hand. 2 This is not exactly true. The second part is how you should implement functions using VHDL in case someone gave you a truth table form of a function. It is sort of fun anyways. We spent most of the time describing the architecture simply because there is so much less involved when compared to the entity3. or. Before we get into the newer details of architecture specification. We are. Working with K-maps also represents an instructive practice when first learning the nuts and bolts of digital design. for one reason or another. In computer science.2 The VHDL Programming Paradigm Our previous work with VHDL was limited to the idea of the basic VHDL design units: the entity and the architecture. The first part is just plain implementing functions assuming someone gave you some function to implement. or LUTs are very useful and you find them quite often in viable computer programming code. Generating functions that do something useful is the more impressive task. you should always be on the lookout for placed where you can use a decoder rather than trying to generate some fancy logic functionality. there is no need to bother reducing your functions. look-up tables. In other words. 1 190 . The first part is long and drawn out while the second part is really short. The underlying theme of this chapter is to describe some of the structured modeling techniques used by the architecture bodies to describe digital circuits. Realizing this simple fact is massively important. The architecture is used to describe how the circuit is intended to function. 8. For better or worse. Even a chimpanzee can implement digital functions. it allows you to get your feet wet with VHDL before doing meaningful design/modeling. but as with computer programming. VHDL has the ability to describe complex digital circuits. The truth here is that when you use VHDL. While this is kind of stupid1. describing a digital circuit.2 More Introduction-Type Verbage Painful as it sounds. Lastly.

When viewed correctly. it moves onto the next action specified somewhere in the associated source code. you need to keep these differences in mind as you learn more about VHDL and start using VHDL to model digital circuits of increasing complexity. Realizing this fact will help you to truly understand the VHDL programming paradigm and language. In computer programming languages.Digital McLogic Design Chapter 8 programming backgrounds is to view VHDL as just another programming language they need to learn to pass another class. you’re already both familiar and comfortable with the concept of concurrency. but that’s not what we’re referring to here. This notion of parallelism is considered an advanced concept and you’ll hopefully learn about it later. there is no option for parallelism5. or things happening concurrently. this idea of concurrent operation of all the elements in the circuit is the same in all digital circuits no matter how large or complex the circuits become. The key here is that the changes in the input to these gates can happen in at the same time. This problem most likely arises because VHDL has many similarities to other programming languages. But. This makes sense and is comfortable to us as humans because just like the processor.1 shows a simple example of a circuit that can be considered as operating in parallel. Once again. 191 . Although the circuit in Figure 8. Figure 8. Once again. The main similarity is that they both use a syntactical and rule-based language to describe something relatively abstract. the key to remember here is that we use VHDL to describe digital hardware. As you know. In this case. Once the processor finishes one action. As you’ve already had the basic introduction digital logic and its associated hardware. the gates are generally stupid in that the gate outputs are a direct function of the gate inputs. Whereas in computer programming where a processor steps one-by-one through a set of statements.1 only shows a few gates. VHDL can “execute4” a virtually unlimited number of statements at the same time (in other words. VHDL modeling is typically used to model digital hardware such as computers. in parallel).1 Concurrent Statements The heart of most programming languages is the statements that form a majority of the associated source code. When the rules are meaningful and well structured. to churn out more meaningful VHDL code. the processor can do amazing things. Although many students have used this approach to pass the basic digital design courses. changes to gate inputs can occur in parallel.1 or in any digital circuit in general. These statements represent finite quantities of “actions” to be taken. the difference is that they are describing two different things. VHDL modeling is significantly different than computer programming. A statement in an algorithmic programming language such as C or Java represents an action or actions to be taken by the processor. in the context of hardware is a much more straight-forward concept in hardware-land than it is in the world of software. In contrast. This is true of all the gates in Figure 8. In other words. the inputs are re-evaluated and the gate outputs may change accordingly.2. Anytime that any gate input changes. The computer program is generally a fixed set of instructions intended for execution on a pre-designed chunk of hardware. this is a bad approach. there is a possibility that the change may subsequently cause a change in the gate output. Once changes to the gate inputs occur. Parallelism. VHDL represents a completely paradigm than standard programming languages. we generally are only capable of doing one thing at a time and once we finish that one thing. and illuminate a nice contrast between a language that describes hardware and the language used to execute software on that hardware. 8. this activity generally happens simultaneously to all gates in a particular design. the differences between VHDL and computer programming language are both significant and distinct. we move onto the next thing. Once again. the instructions that form programs are usually targeted for execution on a single processor. This description lays the foundation for an algorithmic programming in that the processor does great job at following a set of rules which are comprised of instructions in the source code. 4 5 But it’s not really executing statements… The processor itself most likely exploits some form of parallelism.

The “<=” construct is referred to as a signal assignment operator.2 since it somewhat reflects somewhat of a natural organization of statements. Once again. by definition.2 lists the code that implements the circuit shown in Figure 8. 192 .1.3 are equivalent to the code shown in Figure 8. there is generally only one processing element to do all the work. The heart of VHDL programming is the concurrent statement. Figure 8. actions that occur concurrently. try to snap out of it quickly. So how then are we going to use text to describe some circuit that is inherently parallel using lines of text? We didn’t have this problem when discussing something inherently sequential such as standard algorithmic programming by a higher level language. or better stated. When writing code using an algorithmic programming language. VHDL statements are interpreted as being concurrent. This code shows four concurrent signal assignment statements. In other words.Digital McLogic Design Chapter 8 Figure 8. not to mention entering some lines of text into a computer. the concept of concurrency is a key concept in VHDL. A more complete discussion of concurrent signal assignment appears in the following section. AND D. we’re only capable of reading one line of text at a time and in a sequential manner. G H I J <= <= <= <= A C E G AND B. Here’s the trick. If you feel that algorithmic style of thought creeping into your soul. Since most of us are human. Figure 8. As a consequence of the concurrent nature of VHDL statements.1: Some common circuit that is well known to "execute" parallel operations.1. which your currently familiar with from previous chapters. This same limitation follows us around when we try to write some text. AND F. Keep this notion in mind anytime you are dealing with VHDL code. the three chunks of code appearing in Figure 8. These are statements that look a lot like the statements in algorithmic languages but they are significantly different because the VHDL statements.2: VHDL code that describes the circuit of Figure 8. Generally speaking. OR H OR I. The processing element generally does only one thing at a time in a sequential manner that is determined by the order of appearance of instructions in the associated source code. express concurrency. The reality is that we can’t write these four statements at the same time but we can interpret these statements as actions that are happening at the same time. the order that these statements appear in your VHDL source code make no difference. it would be a better idea to describe the circuit as shown in Figure 8. The VHDL programming paradigm built around the concept of expressing parallelism and concurrency with textual descriptions of circuits. Once again.2. since the statements are interpreted as occurring concurrently.

OR H OR I. they would have a completely different meaning: the order of statement appearance is massively important for higher-level computer languages. H + I. Keep in mind that if you were to rearrange the statements shown in Figure 8. AND D. the assignment operator signifies a transfer of data from the right side of the operator to the left side. AND F. you should be able to understand the code of Figure 8. AND F. G I J H <= <= <= <= A E G C AND B.2. In programming languages. AND F. “G = A + B. 8.2 The Signal Assignment Operator: “<=” Algorithmic programming languages always have some type of assignment operator. the statements shown in Figure 8.1. In this case. Figure 8.Digital McLogic Design Chapter 8 G J H I <= <= <= <= A G C E AND B. The signal assignment operator specifies a relationship between signals. this is the well-known “=” sign. In “C”.4: Higher-level language code similar to the VHDL code in Figure 8. This combination was chosen because it is different from the assignment operators in most other common algorithmic programming languages. AND B. F. the value of the signal on the right side of the signal assignment operator is assigned to the value on the left side of the operator. In yet other words. The operator is officially known as a signal assignment operator to highlight its true purpose. In an algorithmic programming language. G H I J = = = = A C E G + + + + B. The distinction between these two types of statements in VHDL and higher level languages should be becoming clearer.2. In other words. Figure 8. The similar statement in written in an algorithmic programming language.4 are designed to be executed by some type of processing element. the signal on the left side of the signal assignment operator is dependent upon the signals on the right side of the operator. Once again. they have completely different meanings. The statements in this code fragment are executed sequentially as opposed to concurrently as is the case for the VHDL code of Figure 8.2. In other words. AND D.” indicates that the value represented by variable A is added to the value represented by variable B and the result is then represented by variable G. There are four types of concurrent statements that are important in VHDL. AND D. The statement “G <= A AND B. the values of G. A and B are generally representative of memory locations somewhere in the associated hardware.4.” indicates that the value of the signal named “G” represents an ANDing of the signals A and B. D.2 and its relationship to Figure 8. although the two snippets of code appear somewhat similar. VHDL uses two consecutive characters to represent the assignment operator: “<=”. J G H I <= <= <= <= G A C E OR H OR I. This processing element executes one statement and then moves onto the next statement. We’ve already briefly discussed the concurrent signal assignment statement and we’ll soon examine it further and put it in 193 . the logic functions were replaced with addition operators and the signal assignment operators were replaced by the assignment operator. With these new insights into VHDL.2.1. OR H OR I. Figure 8.4 shows some “C” code that looks similar to the code listed in Figure 8.3: Three equivalent sets of statements describing the circuit shown in Figure 8.

conditional signal assignments. You should always strive for clarity when using VHDL to model digital circuits. The general form of a concurrent signal assignment statement is shown in Figure 8. Figure 8. though we could draw a diagram showing the familiar symbol for the NAND gate. Stated differently. Any VHDL code used to solve a particular problem is more than likely one of many possible solutions to that problem.6 shows the dark box diagram for this example and while Figure 8. Unfortunately. It’s good that your circuit works. This section presents a formal introduction to concurrent signal assignment despite the fact that most of the information presented is not new. As you know from your experience in other programming languages. In this case. In essence.5: Syntax for the concurrent signal assignment statement. more examples of expressions used in the examples that follow. You’ll soon be discovering and applying the versatility of these statements. The target is generally considered to be an output while the expression is generally considered to be the input or inputs. it’s always good practice to draw a diagram of the circuit you’re modeling. and C for the three input signal names. 8. Keep this in mind when you look at any of the examples provided in this text. the four types of statements represent tools which you can use to implement digital circuits. and selected signal assignments.Digital McLogic Design Chapter 8 context of an actual circuit.5.7 shows the associated VHDL model. Use A. or a set of operators that operate on other signals and evaluate to some value. B. target is a signal that receives the values of the expression. Remember. but that does not necessarily mean they “should” be done that way. this versatility effectively adds a fair amount of steepness to the learning curve. target <= expression. Some of the VHDL models presented in this text are presented to show that something “can” be done a certain way. a signal. the dark box is a nice aid when it comes to writing the entity declaration. Example 8-1 Write the VHDL code that models a three input NAND gate. An expression is defined by a constant. 194 . use F for the output signal name. but it’s even better if your circuit both works and was based on a great looking piece of VHDL code. Solution: Even though this is a simple example. The three other types of concurrent statements that are of immediate interest to us are process statements. we’ll choose to keep the diagram general and take the dark box approach instead.3 Concurrent Signal Assignment Statements The examples presented in earlier VHDL problem used concurrent signal assignment statements. several seemingly different pieces of code can actually produce the same result. there are always multiple ways to do the same things.2. Most of the concurrent signal assignment statements you’ve used thus far were examples of expressions. Furthermore. The same is true for VHDL code: several considerably different pieces of VHDL code an actually generate the exact same or functionally equivalent digital circuit. Figure 8.

the output is re-evaluated anytime a signal in the input expression changes. • This example highlights the use of several logic operators. the change occurs immediately. OR. The idea behind any concurrent statement in VHDL is that the output may change anytime one of the input signals changes. these logic operators are considered binary operators in that they operate on the two values appearing on the left and right side of the operator. Some of the logic operators available in VHDL are AND. But since there is only one CSA statement. architecture exb_nand3 of my_nand3 is begin F <= A NAND B NAND C. Example 8-1 demonstrates the use of the concurrent signal assignment (CSA) statement in an actual VHDL model.Digital McLogic Design Chapter 8 Figure 8. Figure 8. This is a key concept in developing a true understanding of VHDL (so you may want to read that sentence a few more times). The NOT operator is technically speaking not a logic but is available also. • The “stuff” between the begin and end statements is indented. architecture exa_nand3 of my_nand3 is begin F <= NOT (A AND B AND C). The NOT operator is a unary operator in that it only operates on the value appearing to the right of the operator. The idea of concurrency is more clearly demonstrated in the following examples. Note that both architectures reference the same entity declaration. end my_nand3. • Two architectures have been provided in this solution. they are both associated with the same entity. end exb_nand3. 195 . NOR. end exa_nand3. If this re-evaluation causes the output value to change. Proper indentation is good and quickly transfers information to the reader. and XNOR. the concept of concurrency is not readily apparent. In other words.B. NAND. F : out std_logic).6: Black box diagram for Example 8-1.7: Solution to Example 8-1 This example contains a few new ideas that are worth further mention. Moreover.C : in std_logic. XOR. entity my_nand3 is port ( A.

We’ll present the preferred approach later in this chapter. Keep in mind that the approach we’ll take to solving this problem is not optimal and is more for academic purposes. Don’t try this at home. 6 Tools such as K-maps are limited in the number of independent variables.9 is that is does not reflect the concept of concurrency since the architecture only contains one concurrent signal assignment statement.8: Black box diagram for Example 8-2.9 shows the associated VHDL model. Figure 8.8 shows the black box diagram for this example while Figure 8. it’s really not. You must strive to make all of your VHDL code as neat and organized as possible. you’re either going to make a mistake in the reduction process. What makes it so nice to look at is the fact that we’ve constructively used the fact that VHDL ignores white space and lined up stuff to make the code visually pleasing for the human element. One important thing to note from this VHDL model is that it is visually appealing. L 0 0 0 0 1 1 1 1 M 0 0 1 1 0 0 1 1 N 0 1 0 1 0 1 0 1 F3 0 1 0 0 0 0 1 1 Solution: While you might consider the first step in this solution is to reduce the given function. Figure 8. the best approach is to allow the VHDL synthesizer to do the optimization work for you. anytime you try to do the reduction yourself. The reality is that you never should reduce a function that will be modeled with VHDL: doing so simply defeats the purpose of using VHDL.Digital McLogic Design Chapter 8 Example 8-2 Write VHDL code to implement the function expressed in the following truth table. 196 . Moreover. One last comment regarding the solution shown in Figure 8. The problem is that reducing a function by hand has severe limitations6.

architecture f3_1 of my_ckt_f3 is begin F3 <= ( (not L) AND (not M) AND N) OR (L AND M AND (not N)) OR (L AND M AND N). Although the function itself is somewhat useless.N : in std_logic.non-reduced implementation of F3 entity my_ckt_f3 is port ( L. Figure 8. Figure 8. intermediate signal declaration appears in the declarative region of the architecture body. end f3_1.M. unfortunately. F3 = L MN + LM Equation 8-1 architecture f3_2 of my_ckt_f3 is begin F3 <= ((NOT L) AND (NOT M) AND N) OR (L AND M). In other words.11 that the declaration of the intermediate signals is similar to the port declarations appearing in the entity declaration except the mode specification is missing.9: The non-reduced solution to Example 8-2. Figure 8.10: Alternate solution to Example 8-2. The cool thing about the solution shown in Figure 8. end my_ckt_f3. This approach is analogous to declaring extra variables in an algorithmic programming language to be used for specifically for storing intermediate results.Digital McLogic Design Chapter 8 -.11 shows one final alternative solution to Example 8-2. The intermediate signals must be declared within the body of the architecture because they have no linkage to the outside world and thus do not appear in the entity declaration. they are interpreted by the VHDL synthesizer as being concurrent. F3 : out std_logic). To drive this point home. Figure 8. Since the statements are interpreted as being concurrent. These special statements are used to provide what is often referred to as intermediate results. Figure 8. Specifically. let’s deal with a reduced version of the function. The need for intermediate results in VHDL is provided by the declaration of extra signal values which are often referred to intermediate signals. This final solution once again shows an important feature in VHDL modeling. The solution shown in Figure 8. Note in Figure 8. end f3_2. the outside world does not need to know about these signals so they only need appear in the architecture.11 is the fact there are three distinct concurrent signal assignment statements. the order of their appearance in the architecture statement region has not effect on the overall function of the VHDL model.11 uses some special statements in order to implement the circuit. Equation 8-1 shows the reduced version of the function given in this example. Despite the fact that these three statements are listed sequentially. there is some worthwhile information associated with other approaches to modeling this function.10 shows an alternate solution to Example 8-2.12 shows yet another 197 . this solution once again does not demonstrate the concept of concurrency. For the other models to this example.

F3 <= a1_s OR a2_s. The main theme of VHDL is that you should use the VHDL tools at your disposal in order to model your circuits in the simplest possible way. The important idea here is that the use of intermediate signals allows you to more easily model digital circuits but do not make the generated hardware more complicated.Digital McLogic Design Chapter 8 functionally equivalent solution to Example 8-2. The use of intermediate signals was option in this example due to the fact that the example was modeling a relatively simple circuit. Secondly. As circuits become more complex. architecture f3_4 of my_ckt_f3 is signal a1_s. an equation entry approach. Luckily.intermediate signals begin a1_s <= ((NOT L) AND (NOT M) AND N). the use of intermediate signals is the norm for most VHDL models.11: Alternative but functionally equivalent architecture for Example 8-2. a1_s <= ((NOT L) AND (NOT M) AND N).12: Yet another functionally equivalent architecture for Example 8-2. there are a few other types of concurrent constructs that mitigate this tedium. Simple circuits have a higher probability of being understood and actually working. The tendency in using VHDL is to think that since there is more text written on your page.11 and Figure 8. becomes pointless. the ease at which the function in Example 8-2 could be implemented made the example trivial due to the fact that the problem was not overly complicated. end f3_3. a2_s <= L AND M. the overall complexity of a given VHDL model is not directly related to the length of the VHDL code used to describe it7. Generally speaking. a2_s <= L AND M. But as functions become more complicated (more inputs and outputs). architecture f3_3 of my_ckt_f3 is signal a1_s. The solutions shown in Figure 8. -. 7 But it is a well-known universal constant that only highly intelligent digital designers can consistently generate highly understandable VHDL models. This is simply not true. their use brings up some good points.a2_s : std_logic.a2_s : std_logic. Although the approach of using intermediate signal is not mandatory for this example. VHDL structural modeling is an excellent example of where intermediate signals are required. The thought here is that you’re trying to describe a digital circuit using a textual description language: you’ll often need to use intermediate signals in order to accomplish your goal of modeling the circuit.intermediate signals begin F3 <= a1_s OR a2_s.12 only differ by the ordering of the concurrent signal assignments. Figure 8. end f3_4. The point is that concurrent signal assignment statements are useful statements. -. using intermediate signals is technique that you’ll often need to use in your VHDL models. it’s the VHDL tools that have the final say in the size of your final design. the solutions are functionally equivalent. Figure 8. that the circuit you’re describing and/or the resulting hardware is larger or more complex. And finally. 198 . there are many occasions where intermediate signals must be used. particularly an equation that has been reduced by you the digital circuit designer. But since this ordering makes no difference. But most importantly. First.

Example 8-3 Write VHDL code to implement the generic decoder expressed by the accompanying truth table.Digital McLogic Design Chapter 8 8. The conditional signal assignment statement is probably easiest to understand in the context of a circuit. the associated expression is evaluated and assigned to the target. Figure 8. For our first example.14 lists one possible solution to this example. In a conditional signal assignment statement. Use only conditional signal assignment statements in your VHDL code. L 0 0 0 0 1 1 1 1 M 0 0 1 1 0 0 1 1 N 0 1 0 1 0 1 0 1 F3 0 1 0 0 0 0 1 1 Solution: The entity declaration does not change from Example 8-2 so the solution only needs a new architecture description. Note that there is only one signal assignment operator associated with the conditional signal assignment statement. Each of the multiple expressions is associated with a certain condition.13. let’s simply redo the Example 8-2 using conditional signal assignment instead of concurrent signal assignment. The condition is based upon the state of some other signal or signals in the given model. In this case. target <= expression when condition else expression when condition else expression. The target in this case is the name of a signal. 199 . The individual conditions are evaluated sequentially in the conditional signal assignment statement until the first condition evaluates as TRUE.2. The term conditional signal assignment describes statements that have only one target but can have more than one associated expression that can be assigned to the target. The syntax of the conditional signal assignment is shown in Figure 8.4 Conditional Signal Assignment Concurrent signal assignment statements discussed in the previous section have only one target and only one expression. only one assignment is applied per conditional signal assignment statement.13: The syntax for the conditional signal assignment statement. Figure 8. We re-listed the entity declaration here for your enjoyment.

• The solution uses relational operators. The associated expressions are the single digits surrounded by single quotes. There are actually six different relational operators available in VHDL. the associated conditions follow the when keyword. If none of the conditions listed above the final expression evaluate as TRUE. But despite this order of appearance characteristic. To drive home this point.m1 (L = ‘1’ AND M = ‘1’ AND N = ‘0’) else -. the better VHDL models you’ll be writing. In fact.14. • The conditions in the conditional signal assignment statement are evaluated sequentially. the order of appearance of conditions in the conditional signal assignment statement is important. There are a couple of interesting points to note about this solution shown in Figure 8. • If you look carefully at this code and notice that there is in fact one target and a bunch of expressions and conditions. the conditional signal assignment statement is a true concurrent statement8.Digital McLogic Design Chapter 8 -. • The last expression in the signal assignment statement is the catch all condition. make sure you include an else in your conditional signal assignment statements. 200 . In other words. Two of the more common relational operators (as opposed to assignment operators) are the “=” and “/=” operators which are the “is equal to” and “is not equal to” operators. the associated expression is assigned to the target and none of the other expression/condition pairs are evaluated. • The choice of listing the minterms associated with the function used in the solution was arbitrary. end f3_5. the last expression is assigned to the target.15 requires more code than the solution of Figure 8. architecture f3_5 begin F3 <= ‘1’ when ‘1’ when ‘1’ when ‘0’. The important thing to note is that the function was not reduced before it was modeled by the VHDL code.15 shows an alternative but functionally equivalent solution to this example.m6 (L = ‘1’ AND M = ‘1’ AND N = ‘1’) else -. Once one statement is evaluates are true. The solution could have just as easily worked with maxterms.14: Solution to Example 8-2. of my_ckt_f3 is (L = ‘0’ AND M = ‘0’ AND N = ‘1’) else -. respectively. F3 : out std_logic). 8 No joke: this is a complicated notion and is without doubt the most complicated aspect of VHDL.the same entity declaration as used previously entity my_ckt_f3 is port ( L. it looks a bit less efficient in terms of the amount of code. the “else” clause assures that some value is assigned to F3 when the conditional signal assignment statement is executed. This is a massively important point that we’ll come back to in later chapters. In this case. end my_ckt_f3. Unless you have some great reason not to.N : in std_logic. • It’s not much of an improvement over the VHDL code written using only concurrent signal assignment statements. In other words. Note that the solution shown in Figure 8. there is only one signal assignment operator used for each conditional signal assignment statement. The sooner you can wrap some dendrites around this.14.M.m7 Figure 8. Figure 8.

selective signal assignment statements only utilize one signal assignment operator.2.15: Alternate solution to Example 8-3.16: Syntax for the selected signal assignment statement. 201 .Digital McLogic Design Chapter 8 -. with choose_expression select target <= {expression when choices. Example 8-4 Write VHDL code to implement the generic decoder expressed by the accompanying truth table. Figure 8.16 shows the syntax for the selected signal assignment statement. Figure 8. As with conditional signal assignment statements. Use only selective signal assignment statements in your VHDL code. } expression when choices. Some highly interesting comments regarding the solution are soon to follow. Figure 8.the maxterm approach to this problem architecture f3_6 of my_ckt_f3 is begin F3 <= ‘0’ when (L = ‘0’ AND M = ‘0’ AND ‘0’ when (L = ‘0’ AND M = ‘1’ AND ‘0’ when (L = ‘0’ AND M = ‘1’ AND ‘0’ when (L = ‘1’ AND M = ‘0’ AND ‘0’ when (L = ‘1’ AND M = ‘0’ AND ‘1’. Selective signal assignment statements differ from conditional assignment statements in that the assignments are based upon the evaluation of a single expression as opposed to many different expressions. L 0 0 0 0 1 1 1 1 M 0 0 1 1 0 0 1 1 N 0 1 0 1 0 1 0 1 F3 0 1 0 0 0 0 1 1 Solution: This is yet another version of the my_ckt_f3 example originally appearing in Example 8-2. 8. end f3_6.5 Selected Signal Assignment Selective signal assignment statements are the third form of concurrent statements that we’ll examine. N N N N N = = = = = ‘0’) ‘0’) ‘1’) ‘0’) ‘1’) else else else else else ------ M0 M2 M3 M4 M5 Figure 8.17 shows the full solution to Example 8-4.

We’ll provide a full explanation in a later chapter. there are a few interesting things to note regarding this solution. This sort of makes intuitive sense in that only one assignment is being made.N : in std_logic.m1 -.17 shows a solution that is somewhat special because it represents really poor VHDL modeling practice. the middle clause (“‘0’ when ‘0’”) could be removed from the solution without changing the meaning of the statement. Generally speaking. some of the easier ways are out of reach of the 9 Don’t worry too much about this now. Figure 8. Although this example models the decoder using selective signal assignment. the “when others” clause in selective signal assignment statements act as a “catch-all” statements. The selective signal assignment statement uses a “when others” clause as the final entry in the statement. In actuality. In general. We’ll show a much more intelligent use of selective signal assignment later in this chapter. Similar to the final else clause in the conditional signal assignment statement. architecture f3_7 begin with ((L = ‘0’ (L = ‘1’ (L = ‘1’ select of my_ckt_f3 is and M = ‘0’ and N = ‘1’) or and M = ‘1’ and N = ‘0’) or and M = ‘1’ and N = ‘1’)) or -. end my_ckt_f3. In other words. the choosing expression for selective signal assignment statements is relatively simple and often times consist of just a single signal name. In other words. • There is only one signal assignment operator associated with the selective signal assignment statement.M. In general. this is an example of a bad choice of signal assignment statements. • • One general rule of programming languages or hardware description languages is that if you find yourself going to a lot of trouble modeling your circuit. But. there’s always an easier way to model some troubling circuits using VHDL.17: Solution to Example 8-4 Figure 8. The ramifications of a catch-all statement are of considerable importance in VHDL9. end f3_7. it is considered good VHDL programming practice to include all the expected cases in the selective signal assignment statement followed by the “when others” clause.the same entity declaration as used previously entity my_ckt_f3 is port ( L.Digital McLogic Design Chapter 8 -. It has to do with the unintended consequence of generating latches (which is not necessarily good). the body of the selective signal assignment statement can be thought of as deciding the appropriate assignment based on the given choosing expression. Unfortunately. ‘0’ when others. 202 . F3 : out std_logic). ‘0’ when ‘0’.m6 -.m7 F3 <= ‘1’ when ‘1’. there probably some trick embedded in the language that you’re not aware of. it is bad practice (and sometime impossible) to include all the possible cases in the selective signal assignment statement. the solution is not clear. The multiple sub-expressions in the main choosing expression are the confusing part of this problem.

But in some cases. 8.18 shows the general syntax for the process statement.18 implies. label: process(sensitivity_list) begin {sequential_statements} end process label. A couple of the more interesting points regarding the process statement syntax are discussed below.18: Syntax for the process statement. Some tricks10 regarding the implementation of generic decoders are presented later in this chapter. Example 8-5 Implement an XOR function using both concurrent signal assignment and a process statement. Once you grasp these similarities. There are three main types of sequential statements which we’ll describe soon.20 shows both a concurrent signal assignment and a process statement architecture for the entity of Figure 8. all the statements that appear between the begin and end keywords are evaluated in a sequential manner. Solution: Although we should draw a diagram for this circuit. The reality is that the process statement is a concurrent statement that necessarily contains sequential statements.6 The Process Statement The process statement is the fourth and final concurrent statement we’ll look at. No one will know. they’re really considered tools that you should have in your VHDL tool chest. Figure 8. we’ll start discussing the differences between the statements and of course work a few examples. 203 .2. But once again. Knowing of these techniques will increase your VHDL modeling efficiency and versatility. • As the definition in Figure 8. The main thing to notice about this syntax is that the body of the process statement comprises of sequential statements. we’ll first examine the similarities between it and the concurrent signal assignment statement. This is in stark contrast to concurrent statements in general which are evaluated concurrently. Figure 8.Digital McLogic Design Chapter 8 beginning VHDL designer. • The label listed in Figure 8.19. Figure 8. Figure 8. let’s stick to the similarities before we dive into the differences.19 shows an entity declaration for a XOR function. 10 They’re not really tricks. To understand the process statement. The main difference between concurrent signal assignment statements and process statements lies with these sequential statements. they’re not. let’s skip it just this one time. The main difference between the two architecture descriptions is the presence of the process statement in the listed code.18 is optional but should always be included to promote the selfcommenting of your VHDL code.

A similar mechanism exists for the process statement but you actually are given more control compared to the concurrent signal assignment statements.19: Entity declaration for circuit performing XOR function. but good enough for now. It’s definitely hard to see why more control would be an advantage with a circuit this simple. Figure 8. -.B) begin F <= A XOR B. end my_xor_process. The statement appearing in the concurrent signal assignment architecture is evaluated anytime there is a change in signal A or signal B. 11 12 This is not exactly true. all of the sequential statements in the process are revaluated11. -. These two approaches are effectively the same except the syntax is significantly different. any time there is a change in any signal in process sensitivity list. Evaluation of the process statement is controlled by the signals that are placed in the process sensitivity list. anytime there is a change in any of the signals listed on the right side of the signal assignment operator. end my_xor. execution of the statement in the behavioral style architecture is controlled by what signals appear in the process sensitivity list. entity my_xor is port ( A.20: Concurrent signal assignment and process statement descriptions of exclusive OR function. Even though both of the architectures listed in Figure 8.Digital McLogic Design Chapter 8 • Recall that the concurrent signal assignment statement operates as follows. • So here’s where it gets strange. This will make more sense as you start modeling more complex circuits.20 have the exact same signal assignment statement (F <= A XOR B. end my_xor_con_sig. F : out std_logic). 204 . Since it is a concurrent statement.B : in std_logic. end process xor_proc. This difference is considerable in that the process sensitivity list allows you more degrees of control in modeling the final circuit12.process statement architecture my_xor_process of my_xor is begin xor_proc: process(A.concurrent signal assignment architecture my_xor_con_sig of my_xor is begin F <= A XOR B. Figure 8. For the process statement.). the signal on the left side of the operator is re-evaluated.

this statement becomes less true as your VHDL models become more complex. Generally speaking. Keep this in mind when you read the descriptions that follow. Execution of the sequential statements (the statements appearing in the process body) is initiated when a change in any signal contained in the process sensitivity list occurs. Keep in mind that you’re modeling (or describing) a digital circuit. it is a concurrent signal assignment statement. The functional differences were discussed in Section 8. Process statements are massively versatile. And since the ins and outs of this interpretation are not always readily apparent.6. We’ll not say too much about the first type though because we’ve already been dealing with it’s identical to a concurrent signal assignment statement. 8. You must take advantage of concurrency in order to simplify your circuit descriptions. the signal assignment statement in the dataflow style architecture of Figure 8. VHDL is nothing more than a modeling tool.1. The other two types of statements are the if statement and the case statement. ugly. The structure and function of the VHDL if and case statements is strikingly similar.2. To drive the point home. There is a tendency with new VHDL designers is to use the process statement as a repository for a bunch of loosely related sequential statements. Also keep in mind that you’re not programming a computer. In order to avoid this dilemma. process statements are concurrent statements: they all execute concurrently.2. Divide up your intended functionality into several different process statements that communicate with each other rather than attempting to stuff all of your code into one giant. Another way to look at it is that if a signal assignment statement appears inside of a process than it is a sequential statement. the code is not understandable in the context of digital circuit generation. otherwise. complicated. It may take a while for you to gain a grasp of this concept due to the fact it seems like such a strange contradiction. Although syntactically correct. you should strive to keep your process statements simple and to the point.1 Sequential Statements The term “sequential statement” is derived from the fact that the statements within the body of a process are executed sequentially. 13 205 . execution of statements within the process body continues until the end of the process body is reached13. disgusting process statement.2 Signal Assignment Statements The sequential style of a signal assignment statement is syntactically equivalent to the concurrent signal assignment statement.6. This is actually a tough concept to grasp. you’re describing digital hardware. Remember. There are three types of sequential statements that we’ll be discussing. The temporary solution to not fully comprehending this distinction is between sequential statements and concurrent statements are to keep your process statements as simple as possible. The key to understanding sequential evaluation of statements occurring in a concurrent statement is to accept the fact that the VHDL synthesizer is going to examine your VHDL model and generate a valid digital circuit from it.6.2. bizarre. The nice part about both the if statement and the case statement is that you’ve worked with similar statements before in algorithmic programming languages.20 is a concurrent signal assignment statement while the same statement in the behavioral style architecture is a sequential signal assignment statement. some implementation details must be taken for granted until the time comes when you really need to fully understand the process statement. The strangeness evokes a philosophical dilemma: The process statement is a concurrent statement yet it is comprised of sequential statements.Digital McLogic Design Chapter 8 8.

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8.2.6.3 IF Statements The if statement is used to create a branch in the execution flow of the sequential statements. Depending on the conditions listed in the body of the if statement, either the instructions associated with one or none of the branches is executed when the if statement is processed. Figure 8.21 shows the general form of the if statement.

if (condition) then { sequence of statements } elsif (condition) then { sequence of statements } else { sequence of statements } end if;

Figure 8.21: Syntax for the if statement.

The concept of the if statement should be familiar to you in two regards. First, its form and function are similar to the if-genre of statements found in most algorithmic programming languages. The syntax, however, is a bit different. Secondly, the VHDL if statement is the sequential equivalent to the VHDL conditional signal assignment statement. These two statement essentially do the same thing but the if statement is a sequential statement found in a process body while the conditional signal assignment statement is one form of concurrent signal assignment. In other words, the if statement is a sequential statement version of a conditional signal assignment statement. Understanding the similarities of these two statements will help you understand and intelligently apply conditional signal assignment statements. Yet again, there are a couple of interesting things to note about the listed syntax for the if statement shown in Figure 8.21. • The parenthesis placed around the condition expressions are optional. They should be included in most cases to increase the readability of the VHDL source code. • Each if-type statement contains an associated then keyword. The final else clause has no then keyword associated with it. • As written in Figure 8.21, the else clause is a catch-all statement. If none of the previous conditions evaluate as true, then the sequence of statements associated with the final else clause are evaluated. In other words, if an else clauses is used in an if statement, every possible situation is covered and either the if clause or the else clause will be evaluated. • The final else clause is optional. Not including the final else clause presents the possibility that none of the sequence of statements associated with the if statement will be evaluated. This has deep ramifications that we’ll discuss later14.

14

Once again, it’s the unintended creation of a latch.

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Example 8-6 Write some VHDL code that implements the following function using an if statement.

F_OUT(A, B, C) = A BC + BC

Solution: Although it is not directly stated in the problem description, the VHDL code for this solution utilizes a process statement. This is because an if statement can only appear in VHDL source code as part of a process statement. Once again, this problem is implementing a simple function. We mentioned earlier that functions such as these are not often encountered when designing anything but simple digital circuits. Better examples of process statements are provided in later chapters (so try not to get too discouraged now). The VHDL code for the solution is shown in Figure 8.22. We’ve opted again to leave out the black box diagram in this case since the problem is relatively simple and thus does not demonstrate the power of behavioral modeling.

entity my_ex is port ( A,B,C : in std_logic; F_OUT : out std_logic); end my_ex; architecture fun_example of my_ex is begin proc1: process(A,B,C) begin if (A = ‘1’ and B = ‘0’ and C = ‘0’) then F_OUT <= ‘1’; elsif (B = ‘1’ and C = ‘1’) then F_OUT <= ‘1’; else F_OUT <= ‘0’; end if; end process proc1; end fun_example;

Figure 8.22: Solution to Example 8-6. There is not too much new information presented in Example 8-6. One good thing worth knowing is that the conditions portions of the if clauses evaluate to a Boolean value (either true or false). Once the first if clause evaluates as true, the assignment associated with that if clause is performed. The catch-all else statement assures an assignment is made each time one of the signals in the process sensitivity list changes. Once again, using an if statement is probably not the optimal approach to implementing Boolean functions. These examples do, however, show an if statement in action. Just to drive the point further into the ground, an alternate architecture for the solution of Example 8-6 is shown in Figure 8.23. While the solution shown in Figure 8.23 is technically correct, it obviously more cluttered and more confusing than the solution shown in Figure 8.22. Cluttered is bad unless you’re an academic administrator trying to justify your continued existence.

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architecture bad_example of my_ex is begin proc1: process(A,B,C) begin if ((A = ‘0’ and B = ‘0’ and C = ‘0’) or (B = ‘1’ and C = ‘1’)) then F_OUT <= ‘1’; else F_OUT <= ‘0’; end if; end process proc1; end bad_example;

Figure 8.23: An alternate solution for Example 8-6.

8.2.6.4 Case Statements The case statement is somewhat similar to the if statement in that a sequence of statements are executed if an associated expression evaluates as true. The case statement differs from the if statement in that the resulting choice is made depending upon the value of the single control expression. Only one of the set of sequential statements are executed for each execution of the case statement and is sole dependent upon the first when branch to evaluate as true. Figure 8.24 shows the syntax for the case statement.

case (expression) is when choices => {sequential statements} when choices => {sequential statements} when others => {sequential statements} end case;

Figure 8.24: Syntax for the case statement.

The when others line is not required but should be used for general good VHDL programming. Once again, the concept of the case statement should be familiar to you in several regards.

• • •

The case statement is a different and more compact form of the if statement. It is not as functional, however, because all the choices are based on the same expression. The case statement is similar in both form and function to case or switch-type statements in algorithmic programming languages. The case statement is the sequential equivalent to the VHDL selective signal assignment statement. The case statement and selective signal assignment statements essentially have the same capabilities but the case statement is a sequential statement found in a process body while the selected signal assignment statement is one form of concurrent signal assignment.

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Example 8-7 Write some VHDL code that implements the following function using an case statement.

F_OUT(A, B, C) = A BC + BC

Solution: This solution once again falls into the category of not being the best way to implement a circuit using VHDL. It does, however, illustrate another useful feature in the VHDL. The first part of this solution requires that we list the function as a sum of minterm. This is down by multiplying the non-minterm product term given in the example by 1. In this case, 1 is equivalent to (A + A) . This factoring operation is shown in Figure 8.25.

**F _ OUT ( A, B, C ) = ABC + BC F _ OUT ( A, B, C ) = ABC + BC ( A + A) F _ OUT ( A, B, C ) = ABC + ABC + ABC
**

Figure 8.25: Expanding the equation for Example 8-7.

Once you’ve listed the equation in standard minterm form, generating the VHDL model is based on the individual indexes associated with the minterms. Figure 8.26 shows the complete solution for Example 8-7. An interesting feature in this solution was the grouping of the three input signals which allowed for the use of a case statement in the solution. This approach required the declaration of an intermediate signal which was appropriately labeled “ABC”. Once again, this was probably not the most efficient method to implement a function but it does highlight the need to be resourceful and creative when describing the behavior of digital circuits.

entity my_example is port ( A,B,C : in std_logic; F_OUT : out std_logic); end my_example; architecture my_soln_exam of my_example is signal ABC: std_logic_vector(2 downto 0); begin ABC <= A & B & C; -- group signals for case statement my_proc: process (ABC) begin case ABC is when “100” => F_OUT <= ‘1’; when “011” => F_OUT <= ‘1’; when “111” => F_OUT <= ‘1’; when others => F_OUT <= ‘0’; end case; end process my_proc; end my_soln_exam;

Figure 8.26: Solution to Example 8-7.

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Another similar approach to Example 8-7 is to use the “don’t care” feature built into VHDL. This allows the logic function to be implemented without having to massage the inputs. As with everything, if you have to modify the problem before you arrive at the solution, you stand a finite chance of creating an error that would not have otherwise been created had you taken a more clever approach. Figure 8.27 shows an alternative solution (architecture only) for the Example 8-7. One definite drawback of using don’t cares in your VHDL code is that some synthesizers and some simulators do not handle them well. Most VHDL-type textbooks recommend not to use don’t care symbols in your VHDL models, so beware. All and all, it’s not a good idea to use don’t cares in VHDL. The VHDL model of Figure 8.26 is a better approach despite the fact that you had to massage the equation before you were able to model it in VHDL.

-- a solution that uses a don’t care architecture my_soln_exam2 of my_example is signal ABC: std_logic_vector(2 downto 0); begin ABC <= A & B & C; -- group signals for case statement my_proc: process (ABC) begin case (ABC) is when “100” => F_OUT <= ‘1’; when “-11” => F_OUT <= ‘1’; when others => F_OUT <= ‘0’; end case; end process my_proc; end my_soln_exam2;

Figure 8.27: An alternate solution for Example 8-7.

8.2.6.5 Caveats Regarding Sequential Statements As you begin to work with sequential statements, you tend to start getting the feeling that you’re doing algorithmic programming using a higher-level language. This is due to the fact that sequential statements have a similar look and feel to some of the similar programming constructs in higher-level languages. The bad part of this tendency is when your VHDL coding approach becomes similar to that of the higher-level language. Using VHDL sequential statements as higher-level language programming constructs is a common error made by those new to VHDL. This being the case, it is appropriate to remind you once again that VHDL is not computer programming: VHDL is a tool to describe hardware designs. You are, generally speaking, not implementing algorithms in VHDL, you are describing hardware. It’s a massively different paradigm and requires a different mindset. If you attempt to implement a relatively large circuit using one process statement, you’re going to fail. Although your code appears like it should work in terms of the provided statements, this is an illusion based on the fact that your mind is interpreting the statements in terms of a higher-level language. What’s even worse is when your code simulates as you expect it would but the synthesized hardware does not work properly. In this case, you have no choice but to change your original VHDL model. The reality is that circuit design methodology using VHDL is somewhat mysterious in that you are trusting that the VHDL synthesizer to magically know what you’re trying to describe. If you don’t understand the ins and outs of VHDL at a low level, you’re circuit is not going to synthesize properly a good portion of the time. Small and simple VHDL models are easy to understand and generally straightforward to make work. The general VHDL programming approach is to break large and/or modules into small and simple sub-modules. You should strive to keep your VHDL models simple, particularly your process statements. The best approach is to keep your process statements centered about a single function and have lots of process 210

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statements that communicate with each other. The bad approach is to have one massive process statement that does everything for you. The magic of VHDL is that if you provide simple code to the synthesizer, it’s more than likely going to provide you with a circuit that works and an implementation that is simple and eloquent. If you provide with synthesizer with complicated VHDL code, the circuit, may work and the circuit may be efficient in both time and space considerations, but probably not. As opposed to higher-level languages where small amounts of code often translate directly to code of relatively high efficiency, efficiency in VHDL code is obtained by compact and simple partitioning of the VHDL code based on the underlying hardware constructs15. In other words, simple VHDL models are better but the simplicity is generally obtained by proper partitioning and description of the model. So try to fight off the urge to impress your friends with the world’s shortest VHDL model; your hardware friends will know better.

8.3

Standard Models in VHDL Architectures

As you may remember, the VHDL architecture describes the functionality associated with some VHDL entity declaration. The architecture is comprised of two parts: the declarative region and followed by a collection of concurrent statements. We’ve studied four types of concurrent statements thus far: concurrent signal assignment, conditional signal assignment, selected signal assignment, and process statements. Concurrent statements pass information to other concurrent statements though the use of signals. In the context of actual VHDL models, we’ve been using the term intermediate signals to refer to the signals that control the inter-concurrent statement communication. There are four main accepted approaches to writing VHDL architectures. These approaches are known as dataflow style, behavioral style, and structural style architectures. The standard approach to learning VHDL is to introduce each of these architectural styles individually and design a few circuits using that style. Although this approach is good from the standpoint of keeping things simple while immersed in the learning process, it’s also somewhat misleading because more complicated VHDL circuits generally use a mixture of these three styles. Because the digital circuits we’ve modeled up to this point are relatively simple, our VHDL models could easily be described by one of these styles. As our circuits become more complex, most VHDL models employ some type of structural modeling. In other words, structural modeling supports the interconnection of black boxes but does not have the ability to describe the logic functions used to model the circuit operation. For this reason, structural modeling is less of a modeling style and more of an approach for interfacing previously designed modules. The concept of using either a dataflow, behavioral, or structural approach to VHDL modeling is somewhat of a pointless matter. The reality is that you’ll find yourself “doing what needs to be done” in order to model a circuit. As you gain experience modeling digital circuits with VHDL, you simply don’t put much thought into the style of architecture you’re using. The most important factor in VHDL is to make your models as simple as possible. Simple models are more robust and require less testing. Moreover, the simple interfacing of models facilitates the generation of larger VHDL models. But then again, the terms presented here are somewhat standard in the world of VHDL so you really need to be aware of them. 8.3.1 VHDL Dataflow Style Architecture

A dataflow style architecture specifies a circuit as a concurrent representation of the flow of data through the circuit. In the dataflow approach, circuits are described by showing the input and output relationships between the various built-in components of the VHDL language. The built-in components

15

And, having a good synthesizer helps. Companies that provide free synthesis tools will not generally give you their latest and/or greatest: you have to pay for that.

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of VHDL include operators such as AND, OR, XOR, etc. The three forms of concurrent statements we’ve talked about up until now (concurrent signal assignment, conditional signal assignment, and selective signal assignment) are all statements that are found in dataflow style architectures. In other words, if you exclusively use concurrent, conditional, and selective signal assignment statements in your VHDL models, you have used a dataflow model. If you were to re-examine some of the examples we’ve done so far, you can in fact sort of see how the data flows through the circuit. To put this in other terms, if you have a working knowledge of digital logic, it’s fairly straight-forward to imagine the underlying circuitry in terms of standard logic gates. These signal assignment statements effectively describes how the data flows from the signals on the right side of the assignment operator (<=) to the signal on the left side of the operator. The dataflow style of architecture has its strong points and weak points. It is good that you can see the flow of data in the circuit by examining the VHDL code. The dataflow models also allow you to make an intelligent guess as to how the actual logic will appear should you decide to synthesize the circuit. Dataflow modeling works fine for small and relatively simple circuits. But as circuits become more complicated, it is usually advantageous to switch to behavioral models. 8.3.2 VHDL Behavior Style Architecture

In comparison to the dataflow style architecture, the behavioral style architecture provides no details as to how the design is implemented or synthesized in actual hardware. VHDL code written in a behavioral style does not necessarily reflect how the circuit is implemented when it is synthesized. Instead, the behavioral style models how the circuit outputs will react to (or behave) the circuit inputs or the sequence of circuit inputs. Whereas in dataflow modeling you somewhat needed to have a feel for the underlying logic in the circuit, behavioral models provide you with various tools to describe how the circuit will behave and leaves the implementation details up to the synthesis tool. In other words, dataflow modeling describes how the circuit should look in terms of gates whereas behavioral modeling describes how the circuit should act. For these reasons, behavioral modeling is considered higher-up on the circuit abstraction level as compared to dataflow models. It is the VHDL synthesizer tool that decides the actual circuit implementation. In one sense, behavioral style modeling is the ultimate “black box” approach to designing circuits. The heart of the behavioral style architecture is the process statement. This was the fourth type of concurrent statement that we discussed. As you saw, the process statement is significantly different from the other three concurrent statements in several ways. The major difference lies in the process statement’s approach to concurrency, which is the major sticking point in learning to deal with process statements. 8.3.3 Behavioral vs. Dataflow

Often times when using VHDL, you’ll find yourself faced with a small dilemma: should you use a dataflow or behavioral model? The answer to this question is not overly simple. The bottom line is that as you gain experience, you’ll be able to answer this question without too much thought. In reality, when making this decision, you need to think about the ultimate goal of your VHDL model. In all likelihood, you’re modeling a circuit using VHDL because that circuit will eventually be implemented in one form or another. The truth is that the VHDL synthesizer is the middle-man between your VHDL model and the final form of your circuit. This being the case, you need to defer to the characteristics of the synthesizer you’re using.

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Listed below are a few simple guidelines governing the issues of behavioral modeling vs. dataflow modeling. These items were gathered from personal experience and reading many books on VHDL. As you gather your own experience with VHDL, you’ll be able to generate your own set of guidelines.

•

The constructs of behavioral modeling allow you to describe circuits at a relatively high level of abstraction. Modeling circuits at this level allows you to describe the operation of circuits without becoming bogged down in the low level implementation details. So if you need to model a complex circuit, your optimal choice is using a behavioral model. But keep in mind that modeling at this high of level forces you to put a lot of faith into the VHDL synthesizer. This is sometimes less that a good decision. No matter what you do, make sure you at least have some remote vision of what hardware should be used in your circuit implementation. There are not that many basic types of digital modules out there and even your most complex circuitry will be comprised of these modules. Although you don’t know it yet, none of the circuits we’ve been designing have the ability to “memorize” things16. We’ll get to this in later chapters, but for now, keep in mind that behavioral modeling is usually more useful when your circuits have memory elements. If you need to design a relatively simple circuit, you’re often faced with the choice of behavioral vs. dataflow. The word on the street is that if you can model your circuits using a dataflow model, it sometimes has advantages when the circuit is eventually synthesized. The “sometimes” in the previous sentence is based on the synthesizer characteristics and qualities. The “advantages” refers to the fact that sometimes using a dataflow model magically directs the synthesizer to generate a physically smaller circuit while exhibiting the desired functionality. In other words, if the synthesizer needs to thinks less, it often times thinks better. In the end, you should always use a dataflow model if you can do so without too much trouble. Don’t go way out of your way to force a design to be a dataflow model, however: the benefits generally are not there.

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•

•

8.4

Truth-table-based Decoder Implementations

As mentioned earlier, if you really had to implement a generic decoder in VHDL that was defined by a truth table17, you would not attempt to reduce it first. Instead, you whip out one of the following shortcut forms and implement it that way. I personally don’t memorize the forms that follow; anytime I actually need to use one, I need to pull out my cheat notes to remind myself of the proper syntax for these. 8.4.1 Selective Signal Assignment for Generic Decoders

This is the worn-out example we used for much of the verbage in this chapter. Here it is again for your pleasure.

This is a loose reference to the concept of memory and the hallmark of sequential circuits. We’ll introduce these concepts in an upcoming chapter. 17 This would also be true of compact minterm and/or maxterm forms. For that matter, it would also be true of standard SOP and POS forms, but you rarely see those used actual digital designs.

16

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Example 8-8 Write VHDL code to implement the decoder modeled by the accompanying truth table. Use selective signal assignment in your solution. L 0 0 0 0 1 1 1 1 M 0 0 1 1 0 0 1 1 N 0 1 0 1 0 1 0 1 F3 0 1 0 0 0 0 1 1

Solution: The previous approach to this problem required the user to list the product terms associated with the function in longhand notation. Even with cutting and pasting on an editor, the previous solution was somewhat tedious. The new approach to this problem hopefully makes your generic decoder implementing life a bit more comfortable. The first thing to note about the problem is that it is presented in truth table form. In order to make the solution more straight-forward, you should first convert the problem to a more compact representation. In other words, this problem cries out for compact minterm form shown in Equation 8-2. You don’t really need to take this step, but if you don’t be careful you don’t flip a bit somewhere.

F3 (L, M, N) = ∑ (1,6,7)

Equation 8-2

Figure 8.28 shows the final solution to Example 8-8. Listed below are a couple of new thoughts regarding the solution. • The VHDL model once again makes no attempt to reduce the code. Any reduction of the code is thus a responsibility of the VHDL synthesizer. • The entity declaration happens to describe the inputs as single signals. This is not the best approach to the coding style used in this problem. The solution is to create a bundle out of the individual input signals and use that bundle in the selective signal assignment statement. This indicates another common situation when an intermediate signal must be used. The intermediate bundle signal is created by the signal declaration. Assignment of the L, M, and N signals to the bundle is accomplished using the concatenation operator: “&”.The moral of this story is that you should strive to use bundle notation in your VHDL operators whenever possible. It is rare that using individual signals are a better choice than bundle notation. • There are two concurrent statements in the solution. It may initially feel like the concurrent signal assignment statement (the statement using the concatenation operators) is taking up space and doing something in hardware. The truth is that this is typical VHDL programming practice. The VHDL synthesizer does not interpret the concurrent signal assignment statement as requiring new hardware. In essence, this technique is a simple tool that you can use to “do what you need to do” in your VHDL models. • Only the TRUE cases (the cases where the function outputs are ‘1’) are listed in this solution. The when others clause is used to handle the all of the other cases. This approach saves listing 214

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all of the cases where the function output is ‘0’. If there were fewer “0’s” listed in the truth table, you would list the maxterm designators instead of the minterm designators and adjust the VHDL model accordingly. • Once bundle notation is used, the literals are assigned constant binary values using double quotes. Recall that single quotes were used when a single bit was assigned as can be seen in this example.

entity my_ckt_f3 is port ( L,M,N : in std_logic; F3 : out std_logic); end my_ckt_f3;

architecture f3_8 of my_ckt_f3 is signal t_sig : std_logic_vector(2 downto 0); -- declaring the bundle begin sig_s <= (L & M & N); -- assigning the bundle using concatenation operator with (sig_s) select F3 <= ‘1’ when “001” | “110” | “111”, -- listing the implicated minterms ‘0’ when others; end f3_8;

Figure 8.28: The no-nonsense solution to standard function implementation problems.

And finally, Figure 8.29 shows one final solution to Example 8-8. This solution differs from the previous solution in that bundle notation was chosen to represent the three inputs signals instead of the previously used single signal entries. This approach allows for the model to be implemented using a shorter piece of VHDL code. This may or not be considered a better approach. This example does highlight the fact that if you’re the designer and you have the option of using bundle notation, you should always use bundle notation if it’s an option.

-- a slightly different entity declaration entity my_new_ckt_f3 is port ( LMN : in std_logic_vector(2 downto 0); F3 : out std_logic); end my_ckt_f3;

architecture f3_1 of my_new_ckt_f3 is begin with (LMN) select F3 <= ‘1’ when “001” | “110” | “111”, -- listing the minterms ‘0’ when others; end f3_1;

Figure 8.29: The no-nonsense solution to standard function implementation problems.

8.4.2

Conditional Signal Assignment for Generic Decoders

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Conditional signal assignment can also be used when using the generic decoder approach to modeling functions. This is probably not the optimal choice for generic decoders but an example is provided here for completeness18.

Example 8-9 Write VHDL code to implement the decoder modeled by the accompanying truth table. Use conditional signal assignment in your solution. L 0 0 0 0 1 1 1 1 M 0 0 1 1 0 0 1 1 N 0 1 0 1 0 1 0 1 F3 0 1 0 0 0 0 1 1

Solution: Figure 8.30 provides the solution to Example 8-9. Note that this example simply does not have the easy feel as the selective signal assignment had.

entity my_example is port ( L,M,N : in std_logic; F3 : out std_logic); end my_example;

architecture my_soln_exam of my_example is signal LMN: std_logic_vector(2 downto 0); begin LMN <= L & M & N; -- group signals F3 <= '1' when LMN = ("001" or "110" or "111") else '0'; end my_soln_exam;

Figure 8.30: A signal assignment implementation of a generic decoder.

8.4.3

Process Statement for Generic Decoders

Implementing generic decoders using process statements follow approaches similar to selective signal assignment and conditional signal assignment. Once again, there are two approaches to takes when using process statements: case statements and if statements. The tired example is redone using each of these statements. The one important thing to note here is that the solution using the case statement strongly resembles the selective signal assignment statement while the solution using the if statement

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This is a wimpy justification for wasting space.

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group signals my_proc: process (LMN) begin if (LMN = "001" or LMN = "011" or LMN = "111") then F3 <= '1'. F3 : out std_logic). else F3 <= '0'. Figure 8. 217 . architecture my_soln_exam of my_example is signal LMN: std_logic_vector(2 downto 0). end if. Provide a solution using both if and case statements. there are many ways to do the same thing in VHDL. begin LMN <= L & M & N. entity my_example is port ( L. end my_example. This is not coincidental.N : in std_logic. end my_soln_exam.31 provides the solution to Example 8-10 using an if statement while Figure 8. end process my_proc.31: A process-based implementation of a generic decoder using an if statement.M. these types of statements do have a strong correlation. many times it’s up to you to decide the best approach. Example 8-10 Write VHDL code to implement the decoder modeled by the accompanying truth table. L 0 0 0 0 1 1 1 1 M 0 0 1 1 0 0 1 1 N 0 1 0 1 0 1 0 1 F3 0 1 0 0 0 0 1 1 Solution: Figure 8. Yes.32 provides the other solution using a case statement. Use a process statement in your solution. -.Digital McLogic Design Chapter 8 resembles the conditional signal assignment.

end process my_proc.32: A process-based implementation of a generic decoder using a case statement. In this way. Often times in algorithmic type programming. you simply pre-calculate and pre-store all the required calculations somewhere in memory. F3 : out std_logic).4.Digital McLogic Design Chapter 8 entity my_example is port ( L. But in some situations20. for example. end my_soln_exam. you’ve generally have been using a truth table to represent this input/output relationship. This is done often in digital land. You’ve actually been doing them for most of this chapter but this fact will become more obvious in the example that follows. Up until this point. when others => F3 <= '0'. This approach worked well for single functions but will become overly tedious when the number of input and/or the number of outputs becomes so large that you start to question whether you really want to be a digital designer or not.N : in std_logic. be sure to keep this fact in mind when you’re asked to design various circuits. begin LMN <= L & M & N. from there you would transfer this information into a K-map and then implement the circuit. As you’ve already seen the in the previous examples. end my_example. you’ll have a need to perform some calculation over and over again. 19 20 In case you may have not noticed this awesome power in the previous examples. When you see the word “add” you may think you’ll need to include a ripple carry adder into your circuit (extra hardware).4 Generic Decoders Implementations The power of VHDL to model generic decoders is more apparent19 when modeling functions with multiple outputs. you opt to use a look-up table (LUT). With a LUT. This is the LUT approach and is a well known trick in digital design-land. 8. you simply “look-up” the answer based on a given set of inputs: this approach is fast and simple. The generic decoder examples that follow highlight the fact that the generic decoder paradigm is something you should be familiar with from your experience with higher-level programming languages. -. But instead of tying up processor resources by grinding out the calculation each time you need it. You can also perform look-up table-like operations in VHDL. Figure 8. 218 . you’ll sometimes need to add one value to another value.M. end case. the generic decoder provides a method to bypass some of the more tedious parts of the design process.group signals for case statement my_proc: process (LMN) begin case LMN is when "001" | "110" | "111" => F3 <= '1'. you can simply use a generic decoder to “assign” the answer to the outputs instead of actually doing the calculation. architecture my_soln_exam of my_example is signal LMN: std_logic_vector(2 downto 0). If the cases of numbers being added are limited. For example.

Using a standard approach to digital design would require that you generate three K-maps. Also note that the bundle names conveniently relate to the columns in the original truth table.33 shows the black box diagram for this solution.34: The entity declarations associated with Example 8-11. T123 : out std_logic_vector(2 downto 0)). Figure 8. This example shows two of the more intelligent approaches. there are many different approaches you can take with your VHDL model.33: Dark box diagram for Example 8-11. end dcdr. entity dcdr is port ( ABCD : in std_logic_vector(3 downto 0). Use a generic decoder in your VHDL model. As with most circuits. reduce them. 219 . this will make the implementation of the subsequent VHDL models more straight-forward. Provide both a dataflow a behavior description of the non-standard decoder. Figure 8.Digital McLogic Design Chapter 8 Example 8-11 Provide a VHDL model that implements the functionality described in the following truth table. Figure 8. Note that we have opted to represent both the inputs and outputs as bundles.34 shows the associated entity declaration. Modeling the circuit with VHDL is a much better option. Your job is to design a circuit that would implement the three functional relationships shown in the truth table. Figure 8. A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 T1 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 T2 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 T3 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Solution: The provided truth table represents a circuit with three inputs and three outputs. and generate three Booleans equations.

Both of these cases represent short cuts in the model and are generally applied when working with VHDL.35 shows two different models that implement the input/output relationship of Example 8-11. when “0001” => T123 <= “000”. “000” when others. when others => T123 <= “000”. when “0101” => T123 <= “101”.35(b). (a) (b) Figure 8. but that would only have served to increase the length of the VHDL model which is this case would be pointless. does in fact look somewhat like a table21.35(b) is a behavioral model. It would have been possible to represent all of the rows in the truth table. “010” when “1000”. end dec_bahavioral. the entire truth table is not directly represented. “010” when “0011”. 220 . Both of these truth tables also contain another interesting feature. Note that for both of these cases. “101” when “0111”.Digital McLogic Design Chapter 8 Figure 8. “000” when “0110”. “101” when “0101”. The VHDL architectures shown in Figure 8. “100” when “0010”. end process. The model in Figure 8. you should convince you of that fact.35(a).35(a) is a dataflow model while the model in Figure 8. when “0100” => T123 <= “000”. architecture dec_dataflow of dcdr is begin with ABCD select T123 <= “110” when “0000”. “000” when “0100”. Both of these models effectively restate the information presented in original truth table but in a different form. end case. when “0110” => T123 <= “000”.35(b). when “0111” => T123 <= “101”.35: A dataflow (a) and behavior (b) model of a decoder implementing the truth table shown in Example 8-11. architecture dec_behavioral of dcdr is begin dec: process(ABCD) begin case ABCD is when “0000” => T123 <= “110”. The same type of statement appears in Figure 8. 21 Squinting your eyes may help you see this mo better. end dec_dataflow. when “0010” => T123 <= “100”. the when other statement is used to cover the last set of cases in the truth table. and particularly the information presented in these architectures. when “1000” => T123 <= “010”.35(a) and Figure 8. when “0011” => T123 <= “010”. “000” when “0001”. In the model of Figure 8. this is possible because the output associated with the final rows in the truth table are all “000”.

but by far the easiest approach is shown in Figure 8. there are many ways you could solve this problem. Use a generic decoder in your VHDL model.36 shows the required modification to the dark box diagram to support this solution. Figure 8.37 is classic VHDL. 221 .37. when the CE input is a ‘0’. A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 T1 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 T2 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 T3 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Solution: This problem has only seemingly slight modification from the previous problem. the outputs of the circuit are all ‘0’s. This example is therefore the same as the previous example except the inclusion of the enable input. The solution shown in Figure 8. Figure 8. One other major difference between this problem and the previous problem is that this problem did not state how to model the solution. This is definitely the best way to model an “enable” input in VHDL. The body of the case statement was borrowed (cut and pasted) from the solution of the previous example. The CE input essentially “enables” this decoder to do something meaningful.Digital McLogic Design Chapter 8 Example 8-12 Provide a VHDL model that implements the functionality described in the following truth table.36: Dark box diagram for Example 8-11. Not listed in the following table is a CE input. Note that the solution embeds a case statement into an if statement. But of course. the table below is used. otherwise. Once again.

end process. end if. when "0110" => T123 <= "000". end dec_behavioral.CE) begin if CE = '1' then case ABCD is when "0000" => T123 <= "110". when "0100" => T123 <= "000". CE : in std_logic. when "1000" => T123 <= "010". T123 : out std_logic_vector(2 downto 0)). when "0010" => T123 <= "100". when "0101" => T123 <= "101".Digital McLogic Design Chapter 8 entity dcdr is port ( ABCD : in std_logic_vector(3 downto 0). architecture dec_behavioral of dcdr is begin dec: process(ABCD.37: The entity declarations associated with Example 8-11. end dcdr. when "0001" => T123 <= "000". when "0111" => T123 <= "101". 222 . else T123 <= "000". end case. when others => T123 <= "000". Figure 8. when "0011" => T123 <= "010".

and case statements.Digital McLogic Design Chapter 8 Chapter Summary • The idea of a “function” is being replaced by the more generic term “decoder”. • • • • • • • • 223 . The if statement has a direct analogy to the conditional signal assignment statement used in dataflow modeling. Structural modeling is different from the other two model types in that it is used to gather design units and glue them together. Most complex designs use a combination of these model types. if statements. The main design consideration in VHDL modeling supports the fact that digital circuits operate in parallel. and 3) structural models. selective signal assignment. 2) behavioral. Structural models can employ both dataflow and behavioral model types. Dataflow and behavioral models are used to describe circuit operation on the concurrent statement level. respectively. The various design units communicate with each other through the use of signals. of how a digital circuit behaves. and signal assignment statements are considered low-level statements. These statement types are primarily designed to model digital logic at a low level. Structural models are used to describe circuits on the black box level. There are three major model types in VHDL: 1) dataflow. Use of a process statement indicates that you’re using a behavioral model. The entity/architecture pair form the interface and functional description. Intermediate signals are declared in the declarative region of the architecture body. Dataflow models cannot appear in process bodies. conditional signal assignment. The process statement is primarily used to describe the behavior of circuits on a high level (higher than then other three types of concurrent statements). There are three types of sequential statements: signal assignment statements. Intermediate signals are similar to signals declared in entities except that they contain no mode specifier. and selective assignment statements indicate you are using a dataflow model. The body of the process statement can contain any number of sequential statements. The official definition of a decoder is: any non-sequential digital device that establishes a functional relationship between the device input(s) and output(s). In general. the various design units in a digital design process and store information independently of each other. The four major signal assignment types in VHDL are concurrent signal assignment. Signals that are declared as OUTs in the entity declaration cannot appear on the right side of a signal assignment operator. and process statements. In other words. This definition defines a generic decoder which is not to be confused with the standard decoder defined in a later chapter. conditional signal assignment. The if statement is a sequential statement while the conditional signal assignment statement is a concurrent statement. Concurrent signal assignment. Use of concurrent signal assignment. These statements are referred to as concurrent statements in that they are interpreted as acting in parallel (concurrently) to all other concurrent statements. often referred to as intermediate signals. conditional signal assignment. dataflow modeling describes how the circuit should look in terms of gates whereas behavioral modeling describes how the circuit should act.

Concurrent. there is no need to reduce the function before implementing it with a generic decoder. When using VHDL. The case statement is a sequential statement while the selective signal assignment statement is a concurrent statement. The table on the following page is a summary of the information presented in this chapter. When using generic decoder in VHDL. VHDL uses generic decoders are to implement functional relationships. Both the case statement and the if statement can be nested. • • • 224 . and selective signal assignment statements cannot be nested. It is part of the well-known VHDL cheat sheet.Digital McLogic Design Chapter 8 • The case statement has a direct analogy to the selective signal assignment statement used in dataflow modeling. conditional. there is no limit on the number of inputs and outputs that can be represented by the VHDL model.

“10”. “01”. target <= expression. target <= expressn when condition else expressn when condition else expressn. “00”. elsif (B = ‘1’ and C = ‘1’) then F_OUT <= ‘1’. A <= B AND C.Digital McLogic Design Chapter 8 Concurrent Statements Concurrent Signal Assignment (dataflow model) ⇔ Sequential Statements Signal Assignment target <= expression. end process proc1. expression when choices. DAT <= (D AND E) OR (F AND G). else F_OUT <= ‘0’. DAT <= (D AND E) OR (F AND G). D(6). “111”) then “110”) then “101”) then “000”) then <= ‘0’.B. F3 <= ‘1’ when (L=‘0’ AND M=‘0’) else ‘1’ when (L=‘1’ AND M=‘1’) else ‘0’. F_CTRL F_CTRL F_CTRL F_CTRL <= <= <= <= D(7). if (SEL = elsif (SEL = elsif (SEL = elsif (SEL = else F_CTRL end if. ‘1’. F_OUT F_OUT F_OUT F_OUT <= <= <= <= ‘1’. proc1: process(A. D(1). Process (behavioral model) opt_label: process(sensitivity_list) begin {sequential_statements} end process opt_label. Selective Signal Assignment (dataflow model) ⇔ case statements case (expression) is when choices => {sequential statements} when choices => {sequential statements} when others => -. ‘1’.C) begin if (A = ‘1’ and B = ‘0’) then F_OUT <= ‘1’. case ABC is when “100” => when “011” => when “111” => when others => end case. Conditional Signal Assignment (dataflow model) ⇔ if statements if (condition) then { sequence of statements } elsif (condition) then { sequence of statements } else --(the else is optional) { sequence of statements } end if. end if. 225 . with chooser_expression select target <= expression when choices. others. ‘0’.(optional) {sequential statements} end case. with SEL select MX_OUT <= D3 when D2 when D1 when D0 when ‘0’ when “11”. A <= B AND C. D(0).

C.7) F(A.15) F(W. B. B.13) (m) F(A.1.7) F(A. B. C) = M1 ⋅ M6 ⋅ M7 (k) F(L.5. C) = (o) (p) ∏ (0.2. D) = ( A + B) ⋅ (B + C + D) ⋅ ( A + D) ⋅ (C + D) 226 . write VHDL models that implement these functions using concurrent signal assignment. B. C) = ∏ (0.6) (l) F(A.7) F(W. Y. M. X. B. C. (a) F(A.5) ∑ (4. S. D) = AC + BC + BC (d) F(W.1.4.7) (c) F(A. Z) = ∏ (5. D) = (d) ∑ (2. C) = (b) F(A. B. C) = (g) (h) (i) (j) ∑ (5.3. Y) = (e) F(A. B. X. D) = (A + B) ⋅ (B + C + D) ⋅ (A + D) (n) F(A. B.4.2) F(W.5) F(W. B. write VHDL behavioral models that implement these functions using both a case statements and if statements (two separate models for each function). C. N) = ∏ (1.7) F(R.3. B.8. B.6) ∏ (1. X. Y. B. Z) = ∏ (1. C) = M2 ⋅ M5 (f) F(A.Digital McLogic Design Chapter 8 Chapter Exercises 1) For the following function descriptions.6. C. B. C) = m2 + m5 (c) F(A. C. D) = ACD + BC + BCD (f) F(A. Y.2. (a) F(A. B. Y) = ∑ (2. T) = ∑ (0.4.15) (e) F(A.7) 2) For the following function. B.14. X.3. C) = (b) F(A.3. C) = m1 + m6 ∑ (0. Z) = ∑ (12. X. C) = ∏ (1.

conditional. and selective signal assignment as well as a process statement. and selective signal assignment. (a) (b) 4) For the following function. (a) (b) 6) Provide a VHDL model of an 8-input AND gate using concurrent. 227 . conditional. (a) (b) 5) Implement the following functions using concurrent. write VHDL behavioral models that implement these functions using both a case statements and if statements (two separate models for each function).Digital McLogic Design Chapter 8 3) Implement the following functions using concurrent signal assignment.

228 . 8) Provide a VHDL model for a 5 input NAND gate using concurrent. and selective signal assignment as well as a process statement. conditional. conditional. and selective signal assignment as well as a process statement.Digital McLogic Design Chapter 8 7) Provide a VHDL model of an 8-input OR gate using concurrent.

The “modular” portion of the design approach allowed us to overcome the 1 2 If you’re still bored with digital design. (Bryan Mealy 2011 ©) 9. Our initial digital design problems were primarily solved with an iterative-based or brute force design (BFD)approach. STANDARD DIGITAL MODULES: This chapter introduces three standard digital design modules: 1) the comparator. digital design does not have much to do with the implementation of Boolean functions. VHDL MODELING: Presentation of the three standard digital modules is facilitated with the use of VHDL models. These modules are explained on gate-level but also implemented as VHDL models. The main goals of this chapter are to 1) present a formal structure for digital design. The VHDL models include detailed descriptions using various forms of dataflow. It’s true that we’ve done iterative modular designs. Once we add more standard digital modules to your digital design bag of tricks. Although this approach is valid. The problem is that we’ve been basing our designs primarily on low-level logic implementations.2 Design Techniques Up to this point in your digital design journey. 2) iterativemodular-based. 3) modular-based. 229 . 2) the multiplexor. and 3) the non-standard decoder. Main Chapter Topics DIGITAL DESIGN APPROACHES: This chapter summarizes the three main generic approaches used for solving digital design problems: 1) iterative-based. And as you would guess. We’re at the point now where we’re ready to perform our designs at a higher level. Recall that the ripple carry adder was designed using the iterative-modular approach. behavioral. Once again. then blame it on these limitations.1 Chapter Overview Our approach to digital design up until now has been somewhat limited1. and 2) develop and describe some standard digital modules. but not too many (yet).Digital McLogic Design Chapter 9 9 Chapter Nine 9. This iterative approach to problem solving was based on defining the input/output relationship by using a truth table. you’ll be able to solve design problems on a level higher than the gate-level designs we’ve been mired in. The first two of these approaches were covered in previous chapters. and structural models. we’ve dealt with two forms of design. Implementing functions can be considered somewhat of a low-level approach to digital design. Our approach to digital design became more versatile with the introduction of iterative-modular-based (IMD) design techniques2. digital design performed at a higher level of abstraction is generally more efficient in most contexts. it is limited by the effort the designer would put into a truth table and defining the resulting logic in a K-map.

we did not necessarily require a truth table or any supporting logic.3. In this design approach. you been exposed to three standard digital modules: the half adder (HA). In other words. the full adder (FA). 230 . The problem now is that your bag does not present a lot to work with. Figure 9. you no longer need to think about the underlying gates. Although we could consider VHDL-based designs a design approach on its own. the output of the gate. That’s about all there is to a MUX. you need to think selector. This chapter aims to increase the content of your digital bag of tricks3.1 shows a gate-level depiction of this relationship. you no longer need to draw bunches of gates to represent these devices. VHDL can be used to support any type of standard digital design approach. Similarly. 9. the output of the OR gate is then always be ‘1’. As promised. and the ripple carry adder (RCA). and 3) the multiplexor. they’re actually standard digital circuits. respectively. The iterative-modular digital design approach released us from designed primarily at a low-level by creating higher-level designs based on previously design lower-level modules. if you connect one of the inputs to a AND gates to a ‘0’. you’re only interested in the basic function of the device. regardless of the state of any of the other inputs. The modularbased design approach is similar to the iterative-modular approach in terms of avoiding gate-level designs in favor of modular design. is always be ‘0’.1 Multiplexors The multiplexor is yet another standard and highly used digital circuit. but you already have started collecting this bag of digital modules: the half-adder. This section introduces three more standard modules in digital design land: 1) the comparator. Figure 9. We’re almost ready to bump our design up to yet a higher level: modular-based design. A MUX is a generally a circuit with many inputs and one output. And finally. VHDL on its own is not considered a design approach.Digital McLogic Design Chapter 9 truth-table constraint inherent in purely iterative designs. At this higher level of abstraction.1(a) shows an inverted arrowhead is used to indicate a connection with 3 They’re not really tricks. the nice thing about VHDL is that it supports all three of these design approaches. if you connect one input of an OR gate to ‘1’. 9. in your circuit diagrams. we also present a full gamut of VHDL models describing these modules. and the ripple carry adder (RCA) are currently in that bag. When you hear the word multiplexor. the output of the device generally represents the direct transfer of one of the inputs.3 Standard Digital Modules Up to this point in digital design. Similarly. The first thing we need to look at is a specific function of the basic AND and OR logic gates. or MUX as it is more commonly referred to. We actually need to take a look at the internals of a simple MUX in order to give you a solid understanding of how they work. The approach you have taken to learn these devices is to design the modules on a gate level and then abstract it to a higher level. You may not realize it. you only need to draw a box and label it with the device name. The general approach to modular-based design is to collect a bag full of standard digital modules and assemble those modules in such a way as to solve digital design problems. The gatelevel circuitry in a MUX is also shared by other standard digital components and is worth taking a look at here. 2) the standard decoder. You can effectively kill the output of a AND and OR gates by tying their outputs to ‘0’ and ‘1’. the full-adder. In other words. we’re opting to view VHDL as a tool to implement one of the three standard design approaches. The MUX also has historical significance at the gate-level so you’re generally expected to know how they work at both a high and low level.

1(b) shows the slanted T symbol is used to indicate a connection to the circuit’s high voltage (‘1’). the only hope that the circuit output F will be a ‘1’ is if the D input on the non-dead AND gate is a ‘1’. the OR gate will have an input of ‘1’ and the OR gate output F will be a ‘1’. Figure 9. In this circuit. Note that each of the four AND gates are connected such that they will each have different input values based on the state of the selection variables. if the D input on the non-dead gate is a ‘0’. Once again. in official MUX language. Knowing that three of the AND gates are officially dead (they have an output of ‘0’). The D input that appears on the F output is dependent upon which AND gate is un-dead which is inherently dependent on the values of the S1 and S0 variables (the selection variables). then the non-dead AND gate output will be a ‘1’. only one of the P outputs will be a ‘1’ at any given time while all other P inputs will be ‘0’. three of the AND gates will be dead. In other words. The next step in developing the MUX is assembling the selection circuitry shown in Figure 9. 231 . In as simple terms as possible. all of the AND gates will be dead and the F output will be a ‘0’. (a) (b) Figure 9. there are two variables S1 and S0 that are referred to as selection variables. What this effectively is doing is transferring the value of one D input to the output F. In relation to Figure 9.Digital McLogic Design Chapter 9 ground (‘0’). the S1 and S0 inputs are the data selection inputs while one of the D inputs is being selected to appear on the outputs. In terms of the MUX. the output of three of the AND gates will ‘0’ while the other AND gate will have an output of ‘1’. the D input on the nondead gate is a ‘1’. the selector input chooses which data input will appear on the output.2(a). To put this in MUX language. Convince yourself that one and only one AND gate will be a ‘1’ at any given time before reading on. In this circuit. In other words. Figure 9. The effect this creates is that at any given time. one of the D inputs is selected to appear on the F output. the S1 and S0 inputs are referred to as the data selection inputs while the D inputs are the data inputs.1: Killing the AND (a) and OR (b) gates.1(a).2(b) shows the final portion of the MUX circuitry. the inputs to the AND gates will all be different based on the method used to connect the selection variables. If however.

selective signal assignment. MUXes come in many different flavors and quickly become complicated enough such that you’ll want to avoid modeling them with gate-level logic.2(b) is referred to as a 4:1 MUX because is chooses between one of four inputs to appear on the outputs. . let’s start this problem off with a black box diagram shown in Figure 9. 232 . There arguably no best approach to modeling a MUX using VHDL. if statement. A MUX is a complicated enough circuit such that we want to steer clear of low-level data flow models. The truth is that you rarely need to model MUXes in anything other than VHDL. As you’ll see later on. Being good digital designers. there are many ways to model a MUX. In reality. Figure 9.Digital McLogic Design Chapter 9 (a) (b) Figure 9.3: Black box diagram of bundle-based 4:1 MUX. Consider the data inputs and selection inputs to be bundles. Solution: As the problem implies. Figure 9. 4:1.3. Example 9-1 Provide the following VHDL models for a 4:1 MUX: conditional signal assignment. Each of the requested models follow the entity declaration with some of the important points listed.2: The MUX input circuitry (a) and the complete MUX (b). The MUX shown in Figure 9. 16:1 etc.4 shows the entity declaration for the 4:1 MUX using bundles for the data and selection inputs. Common flavors of MUXes include 2:1. MUXes generally have that binary relationship between the number of selection variables and the number of data inputs. and a case statement. this is the most basic form of a MUX. but the worst way would definitely be to use concurrent signal assignment. 8:1.

the MUX needs to apply a single signal to the output F. you should clearly provide all the options in the code and not rely on a catch all statement for intended signal assignment. This is similar to the concurrent signal assignment statement where the statement is executed any time there is a change in any of the signals listed on the right side of the signal assignment operator. 233 . The data inputs to the MUX were specified as a bundle which requires the use to the bundle access operator. This would be functionally equivalent to the solution shown in but not nearly as impressive looking. Just for the heck of it. • The bundle access operator “( )” (the parenthesis) are used to specify signals within a bundle.4: The entity declaration associated with the VHDL models of Example 9-1. Remember. Figure 9. the conditional signal assignment statement is executed any time a change occurs on the conditional signals (the signals listed in the expressions on the right side of the signal assignment operator).5 shows the conditional signal assignment model of a 4:1 MUX.Digital McLogic Design Chapter 9 entity mux4t1 port ( D SEL F end mux4t1. Figure 9.5: Conditional signal assignment model of 4:1 MUX. • For the sake of completeness. • The “=” is an equivalence operator is a relational operator is used in conjunction with a bus signal. Generally speaking. Generally speaking. or bundles. We could have changed the line containing ‘0’ to D0 and removed the line associated with the SEL condition of “00”. Figure 9. we’ve included every possible condition for the SEL signal plus a catch-all else statement. In this case. There are a couple of items worth noting in this solution. a conditional signal assignment is a type of concurrent statement. • The solution looks somewhat efficient compared to the amount of logic that would have been required if concurrent signal assignment statements were used. end mux4t1a. you should.6 shows an alternative solution not using bundles for the SEL lines. else else else else Figure 9. The concept of working with bundles is massively important in VHDL. In this example. : out std_logic). single quotes are used to describe values of single signals while double quotes are used to describe values associated with multiple signals. architecture mux4t1a of mux4t1 is begin MX_OUT <= D(3) when (SEL = “11”) D(2) when (SEL = “10”) D(1) when (SEL = “01”) D(0) when (SEL = “00”) ‘0’. The VHDL code appears nice and is pleasing to the eyes which are qualities required for readability. the values on the bundle SEL lines are accessed using double quotes around the specified values. In this case. is : in std_logic_vector(3 downto 0). if you can use a bundle as opposed to individual signals. In other words. : in std_logic_vector(1 downto 0).

Adding the when others clause is considered good VHDL modeling practice and has ramifications in the simulation of VHDL models. there’s no real advantage to using one approach over the other. use of an if statement is similar to conditional signal assignment. This makes sense in that the output of the MUX could change anytime a change in the data or select inputs occurred.8 are very similar. D(0) when “00”.8 shows two flavors of behavioral models for the 4:1 MUX: Figure 9. D(1) when “01”. although the case statement is generally accepted as being a more straight-forward solution.Digital McLogic Design Chapter 9 architecture mux4t1b of mux4t1 begin MX_OUT <= D(3) when (SEL(1) D(2) when (SEL(1) D(1) when (SEL(1) D(0) when (SEL(1) ‘0’. D(2) when “10”. the process statement is re-evaluated.8(b) shows a case statement model. is = = = = ‘1’ ‘1’ ‘0’ ‘0’ and and and and SEL(0) SEL(0) SEL(0) SEL(1) = = = = ‘1’) ‘0’) ‘1’) ‘0’) else else else else Figure 9.5. ‘0’ when others. both solutions are organized and clear. architecture mux4t1c of mux4t1 is begin with SEL select MX_OUT <= D(3) when “11”. The two models of Figure 9.7 shows the selected signal assignment model of a 4:1 MUX. Once again. The process sensitivity lists include both the D and SEL inputs. Figure 9. The truth is that each possible value of the SEL was previously listed so the when other clause should never be evaluated. Convince yourself of this. end mux4t1b. Figure 9.6: An alternative conditional signal assignment solution. It’s more than worthwhile to list some useful observations regarding these two models. there are a few items of interest regarding this solution. • • The VHDL code has several similarities to the conditional signal assignment solution of Figure 9.8 are also similar to the dataflow model implementations. This being the case. This means that anytime state of D or SEL change. A when others clause is used as the catch-all statement. Specifically. • The two models of Figure 9. • • 234 . Figure 9. the output is assigned a ‘0’ in case each of the other options fail. end mux4t1c. The general appearance is the same.8(a) shows an if statement model while Figure 9.7: Selected signal assignment architecture for 4:1 MUX. use of a case statement is analogous to selected signal assignment. For this solution.

<= D(1). (a) (b) Figure 9. and generally more good.8: 4:1 MUX modeled with if statements (a). you can model any conceivable digital circuit.Digital McLogic Design Chapter 9 architecture mux4t1d of mux4t1 is begin mux: process(D. using the various VHDL constructs. <= D(3). the CE input is a chip enable.SEL) begin if (SEL = “00”) then F <= elsif (SEL = “01”) then F <= elsif (SEL = “10”) then F <= elsif (SEL = “11”) then F <= else F <= ‘0’. D(2). the output behaves as a standard MUX. When CE = ‘1’. When CE is ‘0’. Moreover. 235 .SEL) begin case SEL is when “00” => F when “01” => F when “10” => F when “11” => F when others => end case. end mux4t1d. more understandable. the better4 your VHDL models will appear. Example 9-2 Provide a VHDL model that describes the 8:1 MUX as shown below. end process. end process. D(1). end if. Model this MUX using if statements. So if you haven’t noticed by now. we mean more clear. F <= ‘0’. <= D(2). mux4t1 is <= D(0). more readable. D(3). end mux4t1e. the output of the MUX is ‘0’. the better you understand the basic VHDL concurrent statements. using digital circuit using VHDL is massively powerful. 4 By better. architecture mux4t1e of begin mux: process(D. In other words. In the black box diagram shown below. D(0). and case statement (b).

One of the nice things about a comparator is the fact that modeling a comparator in VHDL is effortless while implementing the functionality in lowlevel logic is a giant pain it the ass.3. end process my_mux. in std_logic. For this design example. else if (SEL = “111”) then F_CTRL elsif (SEL = “110”) then F_CTRL elsif (SEL = “101”) then F_CTRL elsif (SEL = “100”) then F_CTRL elsif (SEL = “011”) then F_CTRL elsif (SEL = “010”) then F_CTRL elsif (SEL = “001”) then F_CTRL elsif (SEL = “000”) then F_CTRL else F_CTRL <= ‘0’. end if. The single output of this circuit indicates when the two 2-bit inputs are equivalent. out std_logic). end my_8t1_mux. the derivation of the standard gatelevel implementation of a comparator provides you with some useful practice in dealing with exclusive OR-type functions. Note that in Figure 9. Data_in(1). But the comparator is a standard digital module and you need to make sure you understand exactly what they’re made of. let’s design a 2-bit comparator.10. For this example. architecture my_8t1_mux of mux_8t1_ce is begin my_mux: process (Data_in. Data_in(6). Data_in(2). bundle notation is used to show that both the A and B signal are actually comprised of two bits 5 It’s OK to assume this since it was not explicitly stated in the problem.10.CE) begin if (CE = ‘0’) then F_CTRL <= ‘0’. 236 .9: The VHDL model for Example 9-2. let’s first design one using an iterative-based (truth table) approach.2 Comparators The comparator is a commonly used device in digital land. Figure 9. Step one in this design is drawing the black box which is shown in Figure 9. in std_logic_vector (7 downto 0). in std_logic_vector (2 downto 0). Solution: Although the problem description does not state it directly. In comparator lingo. end if. Example 9-3 Design a circuit that compares the values of two 2-bit inputs and indicates when the input values are equal. Data_in(4). Data_in(5). Data_in(0). 9.SEL. <= <= <= <= <= <= <= <= Data_in(7). let’s restrict the two 2-bit inputs to be unsigned binary numbers5. Data_in(3). Once of the other nice features about a comparator is the fact that it presents a great chance to apply the iterative-modular design technique that you applied when creating the ripple carry adder (RCA) in a previous chapter. a 2-bit comparator is a device that compares two 2-bit binary numbers. For this solution.Digital McLogic Design Chapter 9 entity mux_8t1_ce is port ( Data_in : SEL : CE : F_CTRL : end mux_8t1_ce. Moreover. we need to design what is referred to as a 2-bit comparator.

The truth table shown in Figure 9. all choices will lead to the same answer. A1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 EQ 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 Figure 9.10: The black-box diagram for the 2-bit comparator. As shown in Figure 9. 237 .11 has been filled in to indicate when the two inputs are equal. we’ve arbitrarily listed the A inputs as the two left-most columns in the truth table.12 shows the associated K-map. Since this problem has two 2-bit inputs. In other words. In this diagram the A1 and B1 inputs are considered to have a higher weighting (in terms of the weights of the digits) than the A0 and B0 inputs6. Figure 9. as long as you’re consistent with the number values. the truth table will have 24 or 16 rows. Step two the design process is generating a truth table and enter the output values in such a way as to provide a solution to this problem. Figure 9. 6 The reality is that the inputs could be placed in different columns the truth table.11: The truth table for the 2-bit comparator.Digital McLogic Design Chapter 9 each. the EQ output is listed with a ‘1’ when the A and B inputs are equal.11.

you should make sure that you completely understand every step of it because you’ll occasionally need to perform such algebraic manipulations out in digital design land7. The key thing to realize in this K-map is that there seems to be an opportunity to extract exclusive OR functions from the resulting equations since the groupings in Figure 9.14.13 is really important.12 seem to have diagonal components to them. The nice thing about this derivation is that it primarily uses factoring as opposed to Boolean algebra theorems8. you can then continually factor the equation as shown in Figure 9. 238 .13. 7 One thing you may want to try for this problem is to change the column-order of the independent variables and verify that you arrive at an equivalent Boolean expression.12 seems to have no opportunity for reduction since no groupings larger than one cell can be formed. At first glance. The derivation shown in Figure 9.14: The final circuit for the 2-bit comparator as equation (e) in Figure 9. 8 Yet more proof that you can in fact be a good digital designer without scars left from applying endless Boolean algebra equations. Figure 9.13. The really important thing here is noticing the relationship between the final equation of Figure 9. (a) (b) (c) (d) (e) F = ( A1⋅ A0 ⋅ B1⋅ B0) + ( A1⋅ A0 ⋅ B1 ⋅ B 0) + ( A1⋅ A0 ⋅ B1 ⋅ B0) + ( A1⋅ A0 ⋅ B1⋅ B0) F = ( A1⋅ B1)( A0 ⋅ B0 + A0 ⋅ B0) + ( A1 ⋅ B1)( A0 ⋅ B 0 + A0 ⋅ B 0) F = ( A1 ⋅ B1)( A0 ⊕ B0) + ( A1 ⋅ B1)( A0 ⊕ B0) F = ( A0 ⊕ B0) ⋅ ( A1 ⋅ B1 + A1 ⋅ B1) F = ( A0 ⊕ B0) ⋅ ( A1 ⊕ B1) Figure 9. Once you notice this attribute of the K-map.13 and the circuit implemented in Figure 9.Digital McLogic Design Chapter 9 Figure 9.12: The K-map for the 2-bit comparator.13: The ugly details of the final equation derivation for the 2-bit comparator. the K-map in Figure 9.

at the very least. First. being that there were only four inputs. First. Would anyone really do it? No. In this circuit. it’s used in many flavors of digital circuits.13. we would require a truth table having eight independent variables or 256 rows (28). If we were to take the same approach as the previous example. Recalling that an XNOR function is sometimes considered an equivalence gate. you’re generally expected to be able to generate the circuit from the truth table. this problem was not too bad. it was only a 2-bit comparator.14 seems to be nothing special. remember that a comparator is comprised of a special combination of primarily exclusive OR type functions. you simply need to add XNOR gates that will compare each of the added bit positions. This approach is a classic application of the iterative-modular (because you’re using the same element over and over again) design approach9. The truth behind the comparator is that it has historical significance. the comparator is a massively important circuit in digital design land. each of the inputs to the AND gate are an output of the individual XNOR functions. In terms of the listed hardware. Secondly.15 shows the final circuit diagram for a 4-bit comparator. an iterative approach was borderline doable. The funny part about this is the contrast to modeling the 9 Recall that the ripple carry adder was previously designed using the iterative-modular design approach. Figure 9. you’re generally expected to. Would this be possible? Yes. the circuit has two 4-bit inputs for a total of 8 inputs. As you’ll soon see. 9. But then again. So in the end. including the factoring of the equations as we did in Figure 9.Digital McLogic Design Chapter 9 Although the circuit shown in Figure 9. apply some horse-sense to understanding this circuit.3. The reality in digital design is that anytime you can apply the iterative-modular approach.15: The final circuit for a 4-bit comparator. But who has any use for a 2bit comparator? Example 9-4 Design a circuit that compares the values of two 4-bit inputs and indicates when the input values are equal. Solution: For this problem. What it is saying is that each of the bits of equal weighting must be equal in order for the two numbers to be equal. it implicitly indicates a possibility to apply the iterative modular digital design technique. each of the bit positions being compared must be equivalent in order for the final number to be equivalent.3 Comparators via VHDL Modeling As was previously stated. Figure 9. The key here is realizing that to make a 4-bit comparator. you’ll be saving yourself a bunch of time. the AND gate is only satisfied when each of its inputs are a ‘1’. 239 .

Figure 9.Digital McLogic Design Chapter 9 circuit with VHDL. Although the problem did not specify which type of dataflow model to use. Figure 9. we’d have a giant Boolean equation to implement. end comp8b. Figure 9. And although there probably is way to model a comparator using selected signal assignment. For this model.Circuit interface for 8-bit comparator entity comp8b is port (A. 240 . an if statement was used.B : in std_logic_vector(7 downto 0). As excitement mounts. -. architecture cond_sig of comp8b is begin EQ <= ‘1’ when (A = B) else ‘0’. Once again. One valuable item to note from this solution is that the ease of working with bundles in VHDL. we opted to use conditional signal assignment since it is by far the most straight-forward approach.16 shows the entity declaration for the 8-bit comparator. Solution: The first order of business is generating an entity declaration for this example.16: Entity declaration for 8-bit comparator.17: Conditional signal assignment model of 8-bit comparator. end cond_sig. Be sure to notice the connection between conditional signal assignment and an if statement. Example 9-5 Model an 8-bit comparator using both a dataflow and behavioral model. it would not be as clear as the conditional signal assignment shown in Figure 9. you should.17. Once again. EQ : out std_logic). unless you have a compelling reason not to.17 shows a conditional signal assignment used to describe the 8-bit comparator. In other words if were to implement this circuit using concurrent signal assignment. there probably is a way to model a comparator using a case statement but is would not be as clear as the if statement. Even more excitement mounts as we meander towards the architecture bodies. The VHDL models for comparators are some of the simplest VHDL models around. We’ll now exploit this simplicity by showing comparators implemented in various flavors of VHDL models.18 shows the 8-bit comparator modeled using a process statement. Figure 9. Figure 9. any time you can use a bundle.

19: Black box diagram for Example 9-6 solution.21 shows an alternative solution for Example 9-6. This solution also demonstrates a massively important point in VHDL10. Example 9-6 Provide a VHDL model of a 12-bit comparator that has three outputs: EQ to indicate when the 12-bit inputs are equal. This being the case. The problem did not specify the type of model to use so we’ve opted to use a behavioral model as shown in Figure 9. all the statements in the process statement are evaluated. This is not a problem in VHDL as the synthesizer officially acts on the most recent assignment to any signal. end if. end process_statement. a black box diagram is shown in Figure 9. Note that the three outputs are “pre-assigned” inside of the process statement before the start of the if statement. else EQ <= ‘0’. we’ll provide two.20. This approach works because the statements inside of a process statement are sequential. The main difference between this solution and the solution of Figure 9.20 is the fact that this solution uses only one if statement. end.Digital McLogic Design Chapter 9 architecture process_statement of comp8b is begin c8b: process (A.19. Figure 9. there is a possibility that the three signals originally assigned to ‘0’ will later be re-assigned a value of ‘1’. and GT to indicate when one input is greater than the other input.18: A process statement model of 8-bit comparator. 241 . To clarify this problem’s interface requirements. 10 This is actually a massively massive point. Figure 9.B) begin if (A = B) then EQ <= ‘1’. this is important and we’ll be dealing with it more in later VHDL models. Note that in each case. Once again. When the process statement is evaluated. LT to indicate when one input is less than the other input. Figure 9. the three outputs are specified for cases when the conditions test as true and false. This solution uses three separate if statements to model the comparator’s behavior. Solution: There are many approaches to this solution.

end comp12b. . Once you have an intuitive feel for gates. LT <= ‘1’. Figure 9. architecture proc_12bb of comp12b is begin c12b: process (A.LT.B) begin if (A = B) then if (A <= B) then if (A >= B) then end.GT : out std_logic). So plan on placing these items in your digital bag of tricks. of comp12b is EQ <= ‘1’. end if. the output will always be zero. GT <= ‘0’. 9. Check on the details in Figure 9. But. Figure 9. elsif (A <= B) then LT <= ‘1’.Circuit interface for 12-bit comparator entity comp12b is port ( A. You’ve killed the gate. Gates are useful items in that they form the basis of digital design. end if. end proc_12ba.20: A model of a 12-bit comparator with extended output features. they’re quite useful in a more intuitive sense. else EQ <= ‘0’.B : in std_logic_vector(11 downto 0).4 Digital Design Oddities Although you may think you know all there is to know about gates. end proc_12bb. GT <= ‘1’. EQ. end. else GT <= ‘0’. end if.B) begin -.Digital McLogic Design Chapter 9 -. you probably don’t know as much as you think you know.pre-assign outputs EQ <= ‘0’. .22. no matter how many inputs there are and no matter what the state of these inputs are. if (A = B) then EQ <= ‘1’.21: An alternative solution to Example 9-6. This section highlights some of the not so obvious things about basic gates and hints at where these things can be used in digital designs. architecture proc_12ba begin c12b: process (A. elsif (A >= B) then GT <= ‘1’. Gate Configuration Timing Example Comments When you ground an input to an AND gate. you can use them in many digital designs in clever manner. LT <= ‘0’. 242 . end if. else LT <= ‘0’.

This creates a passthough effect for the signal in the case where there is only one other input.22: Everything you didn’t want to know about basic gates. 243 . EXOR gates by definition only have two inputs. This is the opposite of tying an AND gate high which gave a pass-through effect. This case is similar to the AND gate with one input tied low. the gate effectively acts as an inverter for the other signal. None of the other inputs to the OR gate matter at this point. the gate effectively becomes a pass-through for the other signal. the other input becomes an inverter. EXOR gates by definition only have two inputs. this input will essentially have no effect on the output of the AND gates. The NAND gate is dead when one input is grounded. Tying one input of an OR gate low prevents the input from having an effect on the output. Figure 9. This is similar to tying an input to an AND gate high. Tying one input of a NOR gate to ‘0’ effective disables that input in that is can no longer effect the output. Tying an input to an OR gate ‘1’ effectively kills the gate by forcing the output to always be ‘1’. Tying a NOR gate to ‘1’ effectively kills the gate in that the output is always low. The output is thus stuck at ‘1’ in this case.Digital McLogic Design Chapter 9 When you tie one input to an AND gate high. When an input to a NAND gate is tied high. When one input is tied to ‘1’. When one input is tied to ‘0’. This is similar to tying the OR gate high.

you can create complex digital circuit designs by connecting a set of standard digital circuits in an intelligent way. you simply started tossing down blocks. In other words. It is the much the same from any digital design in that. As you’ll seen in this chapter’s design examples. One of the many great attributes about VHDL is its support of modular design and module reuse. This approach is not new to you. you have the solution sitting in front of you. You’ve already seen the iterative-modular design approach with the ripple carry adder and the comparator. if you don’t have a strong command of the standard digital modules presented so far. go back and reuse as much of your old design as possible. that means you should always aim for the modular design approach which necessarily incorporates all of your previously designed digital modules. that’s about it. you’ll be well on your way to be coming a great digital designer. Step 1) Read the problem carefully in order to determine the modules that the problem requires and draw some black boxes representing those modules. even if you did not know what you were doing. Modular-based design is not much different from iterative modular designs. if you stop and think about the problem for a few minutes. clues to the solution start coming out of the woodwork and soon. There are two basic steps to using modular design. modular-based design is not overly complicated in that it draws so much upon previously design modules. even the most complex digital circuit can be subdivided into a set of the relatively few standard digital circuits. Step 2) Connect the modules decided upon in Step 1) in such a way as to solve the given problem. If you find yourself reinventing the wheel in each of your digital designs. once you learn the few basic digital circuit types out there and become fluent with their use. What you’ll hopefully see when you finish this course is that there are simply not that many different types of digital circuits out there. the design problems somewhat solve themselves. We’ll be using these steps in the example problems that follow. 244 . please be aware that there are better approaches. But if you take that previous statement and look at it in the opposite way.5 Modular-Based Digital Design One of the underlying themes in digital design is the use of modularity. Now that you have a greater set of modules in your digital bag of tricks. In terms of the three design techniques we’ve discussed thus far.Digital McLogic Design Chapter 9 9. Recall that there are simply not that digital modules in your bag of digital tricks. you’re ready to bump up to modular-based digital designs. Well. If you follow these steps. Recall that with modular design. Listed below are the two steps for using modular design. To put this statement in other terms. The general approach to becoming an efficient digital designer is always designing on the highest level possible. modular-based design is going to be more challenging than it needs to be for you. But then again. we actually introduced this approach in Chapter 1. If you need to use one of those standard digital circuits in your particular design.

24. this circuit must add some special logic. when we assign the UNLOCK signal a ‘0’. If we shoot a bullet into the device. 245 . In most combination locktype problems such as this one. Solution: Once again. This problem can be divided into two sections as follows: the LOGIC_A and the LOGIC_B block as shown in Figure 9.23: The black-box diagram of the final circuit. a simple 4-bit comparator could have been used. Figure 9. The idea here is that when we assign the UNLOCK signal a ‘1’. the game ends quickly. Had it been the case where the user needed all of the buttons correct in order to unlock the door. the code that unlocks the door has been hard-coded into the circuitry. The UNLOCK output is considered a signal that is directed to some lock mechanism responsible for locking and unlocking the door.24: Lower-level block diagram of circuit solution. The car door has four pushbuttons that are used to actuate the unlocking mechanism of the car door. But instead of an AND gate on the output of the comparator. In order for the door to unlock. Figure 9. the door unlocks. the code the user inputs must be the same was the code that is hard-coded into the circuitry. The solution to this problem is similar to a comparator. This diagram simply lists the inputs and outputs to the circuit. the rest of the solution involves deriving a relationship between the output and inputs in such a way as to solve the given problem. the first step is generating a block diagram of the final circuit.But in this design. only three of the four buttons need to be in the correct position in order to unlock the door.Digital McLogic Design Chapter 9 Design Examples Example 9-7: In the Dark Car Alarm Design a digital circuit that will control the unlocking of a car door. The key to understanding this problem is knowing that somewhere inside of this circuitry. the door locks. The catch in this problem is that the user only needs to have three of the bits of the code correct in order to open the lock. the user must have all four of the buttons in the correct position (thus inputting the correct combination).

Figure 9. In this case. Note that each of the EXNOR gates simply compare the outputs of each of the buttons which is the expected comparator action.26: The truth table for the final solution. each of the external button outputs is compared to the internal preset combination to the lock. BEQ3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BEQ2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BEQ1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BEQ0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 UNLOCK 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 Figure 9. The comboX values are internal to the circuit which is indicated by the dotted line.27 provides a VHDL model for the LOGIC_B block. Equation 9-1 shows an expression describing the final solution.26 shows the truth table for this circuit.25 shows a diagram of this circuit.25: A detailed look at the LOGIC_A block. Figure 9. 246 . The LOGIC_B block is a circuit that has an asserted output when at least three of the inputs are in a ‘1’ state. And finally.Digital McLogic Design Chapter 9 The LOGIC_A block is similar to the comparator. And just in case you wanted to implement this function in real hardware. Figure 9. Equation 9-1 shows a reduced expression implementing this functionality. Figure 9.

architecture my_ex_arch of my_ex is begin with BTN select UNLOCK <= ‘1’ when “0111” | “1011” | “1101” | “1110” | “1111”. Figure 9. the EQ3 output of the circuit will be a ‘1’. Solution: The main constraint in this problem is the required use of standard comparators in the solution. as always.28. UNLOCK : out std_logic). You mission is then to translate that probable intuitiveness to digital hardware. is drawing a black box diagram as shown in Figure 9.Digital McLogic Design Chapter 9 F = (BQ3 ⋅ BQ2 ⋅ BQ0) + (BQ3 ⋅ BQ2 ⋅ BQ1) + (BQ3 ⋅ BQ1 ⋅ BQ0) + (BQ2 ⋅ BQ1 ⋅ BQ0) Equation 9-1: Boolean expression describing the solution circuitry. end my_ex. Use any support logic you may require but minimize the amount of hardware used in this circuit. end my_ex_arch. otherwise it will be a ‘0’. Use only standard comparators in this design. ‘0’ when others. Figure 9. Example 9-8: Three-Value 10-Bit Comparator Design a circuit that compares three 10-bit values. A good start. what would you do? It’s an old math thang to say. you should stand back for a minute and view this problem from a wider perspective. If all three 10-bit values are equivalent. ------------------------------------------------------------------------. Other than that.27: The VHDL model for Example 9-7.A standard decoder-type function implementation -. 247 .for the LOGIC_B block.28: Black box diagram for Example 9-8 solution. “if A = B and B = C then A = C”. Use the modular design approach for this problem and provide both a block-level diagram and the VHDL structural model for the solution. -----------------------------------------------------------------------entity my_ex is port ( BTN : in std_logic_vector(3 downto 0). If someone were to asked you to determine if three numbers were equivalent.

29 shows the final block diagram for this problem. Figure 9. you’ll need two comparators to determine if all three inputs are equivalent.29: The final circuit for Example 9-8. In particular.29.30 contains two component instantiations and one concurrent signal statement. 248 . Each of these two VHDL solutions is worth a thorough examination. note that the structural model solution shown in Figure 9.30 and Figure 9.30. Figure 9. Figure 9. Note that the block diagram directly implements the quoted statement in the previous paragraph. And just for the record.Digital McLogic Design Chapter 9 From here. The order of the component instantiations and concurrent signal assignment statement in the architecture body make no difference on the overall function of the circuit. This entire problem could be solved with just the few lines of VHDL code shown in Figure 9. you need to reconsider the standard comparator constraint on this problem.31 by using a behavioral model.31 show a structural model and behavioral model solution to this problem. From this point in this problem. Note that the solution shown in Figure 9. the required extra logic in the problem is stated directly in the quoted statement in the previous paragraph: the “and” indicates that this solution requires an AND gate.31 is associated with the entity declaration of the top-level module shown in the VHDL model of Figure 9. Since a standard comparator only compares two numbers. The concurrent signal assignment statement provides the AND gate as shown in Figure 9.

EQ : out STD_LOGIC).Digital McLogic Design Chapter 9 entity comp2 is Port ( A. end. end component. else EQ3 <= ‘0’. end if. -.B : in STD_LOGIC_VECTOR (9 downto 0). else EQ <= '0'. Figure 9.basic logic EQ3 <= eq1_s AND eq2_s. end process. end process.component instantiation eq1: comp2 port map (A => A. Figure 9.B) begin if (A = B) then EQ <= '1'.B. end if. eq2_s : std_logic. begin -. EQ : out STD_LOGIC).component declaration component comp2 Port ( A. -. end comp3. -. architecture my_comp3 of comp3 is -.C) begin if ((A = B) and (A = C)) then EQ3 <= ‘1’. 249 . B => C. EQ => eq2_s). end.B : in STD_LOGIC_VECTOR (9 downto 0). B => B. EQ => eq1_s).B.31: A behavioral model solution for Example 9-8. architecture my_comp2 of comp2 is begin my_comp: process(A. end my_comp2. EQ3 : out STD_LOGIC).component instantiation eq2: comp2 port map (A => A.C : in STD_LOGIC_VECTOR (9 downto 0). entity comp3 is Port ( A.30: Structural model solution for Example 9-8. end comp2. architecture my_comp3x of comp3 is begin cmp3_proc: process(A.intermediate signals signal eq1_s.

Figure 9.33: A diagram of the HA-based (a) and FA-based (b) ripple carry adder. You’ll also need to recall all the information you learned regarding binary number and particularly signed binary numbers. For this problem. When the SUB input is high. Otherwise.33(b) shows RCA with a FA in the MSB position. The key to completing this problem is noting that the subtraction is done using the indirect subtraction by addition approach. So… let’s first review some of the properties of the RCA. that means doing a two’s complement. they differ by the inclusion of the carry-in (Cin) for the RCA shown in Figure 9. half adders. we’re going to try not to go that long and arduous design route with this problem and its requirement of doing a subtractor circuit. Assume that you have no reason to worry about the carry-out from the adder. Figure 9. the 8-bit circuit output indicates the result of B subtracted from input A. standard decoders. ripple carry adders (RCAs). this is shown in Figure 9. These include MUXes. In other words. the output of the circuit indicates of addition of the A and B. and comparators. What is going to save us is the fact we’ll remember that subtraction in binary can be done by first multiplying the appropriate operand by -1 and then adding the result to the other operand. As you can see by comparing these circuits. (a) (b) Figure 9.32. the subtraction is going to be done by first taking the two’s complement of the operand that is being subtracted and adding the result to the other operand. The approach we took to designing the RCA was to have the least significant bit location as a half adder and all of the other elements as full adders.Digital McLogic Design Chapter 9 Example 9-9: 8-Bit Adder/Subtractor Design a circuit that acts as both an adder and subtractor.33(b). Although we took a thorough approach to designing the RCA. For this problem we’re going to use full adders for all of the adder elements. This circuit has a control input SUB and two eight-bit inputs A and B.32: Black-box diagram of the Adder/Subtractor circuit. full adders. Solution: The point behind this problem is gathering up all of the standard circuits you’ve learned about up until now. the first step in this solution is drawing a black-box diagram of the circuit. As you no doubt know.33(a) show the RCA with a HA as the MSB and Figure 9. And as always. the two’s complement is obtained by taking a 1’s complement (complementing all the 250 .

entity b_logic is port ( input : in std_logic_vector( (n-1) downto 0).34. the SUB input to the circuit has two functions: 1) to select the complemented or non-complemented operand to one of the RCA’s inputs. sub : in std_logic. architecture b_logic of b_logic is begin process (input. and 2) to select a ‘1’ for the Cin input on the RCA_FA. it will have no effect on the final result. the SUM output of the circuit shown in Figure 9. The final circuit is thus going to look like something shown in Figure 9. Another way to look at this is that the value of the SUB signal is always included in the addition operation of the RCA_FA. then a ‘1’ is added to the two operands. The last thing you need to do here is define what is in the B_LOGIC block shown in Figure 9. output : out std_logic_vector( (n-1) downto 0)). Also note that the same ‘1’ is used to complement the B operand before it enters the input to the RCA. The best way to do this is with a VHDL model.1 lists the overall operation of the RCA_FA module.35 shows the associated VHDL model which shows that when the SUB input is a ‘1’.33(b) represented the result of the addition operations shown in Equation 9-2. 251 . end b_logic.Digital McLogic Design Chapter 9 bits) and adding 1. else output <= input. Figure 9. Figure 9. Figure 9. The cool thing to notice here is that Equation 9-2 shows the final result of the entire RCA in Figure 9. SUM = A + B + Cin Equation 9-2: What exactly the RCA is adding. In other words.34: The final circuit. end end b_logic.sub) begin if (sub = ‘1’) then output <= not input.34. So.33(b). If the SUB input is a ‘0’. Table 9. end if.35: The VHDL model for the B_LOGIC block.

there is no one standard digital circuit that you know of that solve this problem. In 252 . you need think on a higher digital level in order to solve this problem. The problem most beginning digital designers have when doing these types of problems is the lack of a structured approach. is would be impossible to do this any other way. From the problem statement. Example 9-10: Special Arithmetic Circuit Design a circuit that has three 8-bit inputs A.1: Tabular view of RCA_FA operation. B.Digital McLogic Design Chapter 9 SUB value ‘0’ ‘1’ RCA_FA operation Comment A+B A-B SUB = A + B + 0 SUB = A + B + 1 Table 9. Step 2) Connect the modules decided upon in Step 1) in such a way as to solve the given problem. Use the modular design approach for this problem and provide a circuit diagram that solves this problem. You’ll soon find out that the best approach to take in problems such as this one is a two-step approach. Figure 9. you can see that the final circuit is going to require two RCAs in order to perform the two required addition operations (A + B and B + C).36. assume that the addition of the two input values will never cause a carry out. Solution: Once again. Step 1) Read the problem carefully and determine the modules that the problem requires. What this means to you is that you’ll generally need to decompose the problem into smaller parts based on the digital modules in your bag of tricks. Obviously. The second clue given in the problem statement is that something needs to be compared. and C. With the eight inputs.36: Block diagram of the final circuit. The single output of the circuit indicates whether the sum of A and B is equal to the sum of B and C. for this problem. For this problem. The key to step one is decomposing the problem. So… first step is drawing a block diagram of the final circuit as shown in Figure 9.

add some modifications to the comparator in a later example. the diagram appears in Figure 9. Keep in mind that for this problem. The bit-width of these devices for this problem was not really a big deal. you’ll need to check whether the results of the two addition operations are equivalent. you know how to create a RCA and a comparator (the module labeled COMP is an 8-bit comparator in this problem. And that’s it.Digital McLogic Design Chapter 9 this case. The second key to this problem is that we have some “selection” stuff going on in order to “select” the correct inputs to feed to the correct outputs. 253 . If the A input is greater than or equal to the B input. you can use iterative modular design or VHDL modeling to overcome the problems presented by the wider data paths.38. and two 8-bit outputs GT and LT. Figure 9. Otherwise. let’s start with a block diagram of the solution. Recall that our basic comparator design only had an EQ output that indicated when the two inputs where equal. The basic comparator circuit needs some modifications in order to make the device usable in this problem. The required connections of the three modules are based upon the requirements of the final circuit. Solution: The key to this classic sorting circuit problem is noticing that there is something similar to a comparator present in the problem as well as some selection logic. This implies that there will be a MUX in this design. however.37: The final circuit solution for this problem. the B input will appear on the GT output and the A input will appear on the LT output. Example 9-11: Sorting Circuit Design a circuit that has two 8-bit inputs A and B. Support your solution with a block diagram and any required VHDL modules. We did. For this problem you’ll need two RCAs and one comparator. As always. Figure 9. the A input will appear on the GT output and the B input will appear on the LT output.37 shows the final result of Step 2) and the entire problem. Note that in this solution the carryin and carry-outs of the RCAs are not specified which implies they are irrelevant to this solution.

(a) (b) Figure 9. Since the circuit we’re trying to design has two outputs. end process. if (A > B) then GT <= ‘1’. A MUX is known as a data selection device which means that the output can be one of several “buses” on the MUX input. We did this in a previous example so we’ll not need to say too much about it here.B : in std_logic_vector(7 downto 0).B) begin -. LT <= ‘0’. if (A = B) then EQ <= ‘1’. if (A < B) then LT <= ‘1’. Figure 9.pre-assign output values EQ <= ‘0’.LT.39 shows the VHDL model and block diagram for the required comparator. end my_comp. end if. entity comp is port ( A. end comp. GT. What we’ll need to do is modify the standard comparator circuit for this problem. GT <= ‘0’. The comparator we design for this problem does not actually have all three of the outputs shown in Figure 9. This heavily implies a MUX of some type. end if. The next consideration is the data selection portion of the circuit.38: Block diagram for Example 9-11.39: Black box diagram for out new comparator (b).40.39 but we included it in the modified comparator design because it will be useful for other problems. it looks as if we’re going to need two MUXes. The next consideration is dealing with the “comparator-type” circuit. Once again.EQ : out std_logic). architecture my_comp of comp is begin process(A. and the MUXes we know about have only one output. 254 .Digital McLogic Design Chapter 9 Figure 9. the key here is the fact that we have used the word “selection” to roughly describe the solution. and VHDL model for new fullfeatured comparator circuit (a). end if. This is exactly the type of MUX used on the second example and is shown again in Figure 9.

What we need from the MUXes is to always have them choose different outputs.41 shows a diagram of the final circuit.Digital McLogic Design Chapter 9 entity mux2t1 is port ( A. this entire problem is easily describable with a simple VHDL model. F2 : out std_logic_vector(7 downto 0)). Figure 9. What we’re interested in is the condition where the A input is greater than or equal to the B input.B : in std_logic_vector(7 downto 0). architecture mux2t1 of mux2t1 is begin F2 <= A when (SEL = ‘1’) else B when (SEL = ‘0’) else ‘0’. end mux2t1. 255 . The “>=” operator has been used (greater than or equal to) which is one of the many operators in VHDL. Figure 9.41: The diagram of the final circuit. A better solution would be to skip the inverter and connect the inputs to the MUXes differently. Note that this solution advertises the power of modeling circuits using VHDL in that this entire circuit was modeled with only a few lines of VHDL code. And finally. The final trick in this problem was to be careful when setting up the MUX select signals: it would be easy to get them backwards in this case. What we could do for the final circuit is control the data selection function of the two MUXes with an ANDing of the comparator’s GT and EQ signals. But a more clever way to do this would be to use the LT signal on the comparator to directly control the MUX. We could do this by connecting the circuit’s inputs identically to the MUXes and complementing the MUX control signal from one of the MUXes. SEL : in std_logic. end mux2t1. (a) (b) Figure 9.42 shows the final solution as a single VHDL entity architecture pair. Figure 9. Another thing to note here is that the “less than or equal to” operator is the now infamous “<=” symbol. The only other issue we need to contend with is how we’re going to control the two MUXes. as you may have noticed.40: 2:1 MUX with bundle inputs and outputs: VHDL model (a) and block diagram (b) So we’re to the point where we know that we’ll need two 2:1 bus-type MUXes.

B : in std_logic_vector(7 downto 0).Digital McLogic Design Chapter 9 entity sort is port ( A.LT : out std_logic_vector(7 downto 0)). end sort. 256 . Figure 9. end if. LT <= B. LT <= A. else GT <= B. GT.42: The entire solution as a VHDL model. end process.B) begin if (A >= B) then GT <= A. end my_sort. architecture my_sort of sort is begin process(A.

Various types of VHDL models can be used to describe larger MUXes. and 3) modular-based design. Iterative-based designs are low-level designs while modular-based designs are high-level. The functionality of a decoder is broken into non-standard and standard decoders: this chapter discussed only non-standard decoders. is a standard digital circuit used to “select” a value. Comparators are constructed using primarily exclusive NOR gates. In general. 2) iterative-modular-based design. • • • 257 . The comparator is a standard digital circuit used to compare the value of two inputs. Comparators of any input sizes with various outputs are easily described with VHDL behavioral and dataflow models. the output of the MUX is one of the data inputs as chosen by the selector inputs.Digital McLogic Design Chapter 9 Chapter Summary • There are generally three approaches to digital design problem: 1) iterative-based design. or MUX. The multiplexor. The efficiency of digital design is generally greater on a higher-level. The derivation of the Boolean equations describing comparators is somewhat tedious but rather important. The non-standard decoder is used primarily to implement Boolean functions and is extremely useful in describing functions with many dependent variables. The decoder is a standard digital circuit. Simple MUX designs are possible using gate-level implementations.

258 .Digital McLogic Design Chapter 9 Chapter Problems 1) Use the listed circuit to complete signal F in the following timing diagram.

you’ll need to use a new flavor of MUX. B. You’ll need to use a bus-type MUX for this problem. they perform the same data selection function with buses (as shown below). use no more than one adder. B.Digital McLogic Design Chapter 9 Design Problems 1) Design a circuit on a block diagram level that performs one of several mathematical operations. The circuit operates as follows: • • if input SEL equals ‘1’. D. make the following assumptions: • • Assume inputs A. then the circuit outputs the result of the operations A + B + C if input SEL equals ‘0’. For this problem. Your design should use the standard circuits you’ve learned about thus far in CPE 129. 259 . the single output should reflect the result of one of the following operations. C. C and the output are all 12-bit values Assume there will no issues or problems with carry out values 2) Design a circuit on a block diagram level with an output that represents either a mathematical operation or another input. Be sure to label everything! The circuit operates as follows: • Depending on the value of the two select inputs. and the output are all 12-bit values Assume there will no issues or problems with carry out values 3) For this problem. Although you learned about MUXes in the context of single signals. It does not matter which select values select which operation but make sure the combinations associated with the select inputs can generate each of the following operations: RES = A + A RES = A + C RES = A + B RES = B + C For this problem. then the circuit outputs the value of D directly. make the following assumptions: • • Assume inputs A. Minimize the use of hardware in your design. Your design should use the standard circuits you’ve learned about thus far in CPE 129. Minimize the use of hardware in your design.

5) Design the following digital circuit. design a circuit on a block level that has the following characteristics: • If the two 8-bit inputs J_IN and K_IN are equivalent. their sum is directed to the 8-bit output M_OUT • Otherwise. Be sure to completely label your diagram. the 12-bit output of the circuit is the sum of A and B. If the A and B inputs are equal. Be sure to completely label your diagram. Your design should be on a block level using standard digital modules. minimize your use of hardware modules for this design. the 12-bit circuit output is the sum of C and D. Don’t worry about overflow in this design.Digital McLogic Design Chapter 9 data selection of single signals data selection of buses black-box diagram of solution Using any standard digital module. consider all inputs to be 12-bit unsigned binary numbers. 260 . they are added and the result of the addition becomes the 8-bit output of the circuit. the value of J_IN is directed to the 8-bit output M_OUT 4) Design the following digital circuit: if the two 8-bit binary numbers (RC) are both positive. and the C and D inputs are equal. minimize your use of hardware modules for this design. Otherwise. Otherwise. Your design should be on a block level using standard digital module. the circuit’s 8-bit output is set to 0.

Although most introductory digital circuit design courses deal with idealized models (timing considerations are ignored).2 Real Digital Devices One common aspect of the digital circuits we’ve discussed thus far is the fact that we’ve omitted some of the most important aspects of digital reality in order to smooth-out the learning curve. Main Chapter Topics GATE-LEVEL MODEL: This chapter introduces the concept of switching times in circuits. This chapter presents some of the non-idealized characteristics of gates. speed. we’ll be dealing with these issues in the context of implementing functions with the techniques we’ve learned thus far. this chapter deals primarily with glitches resulting from static logic hazards. A digital circuit is comprised of logic devices which can be modeled at many different levels.Digital McLogic Design Chapter 10 10 Chapter Ten 10. gates were modeled as ideal devices. In this chapter. In previous chapters. A course in world history would most likely not need to model these devices at all. most digital circuit design generally deals with as assortment of timing considerations.1 Chapter Overview The previous chapters were primarily concerned with digital circuits based idealized gate-models. CIRCUIT GLITCHES: The chapter describes glitches and outlines their effect on digital circuit. These considerations are particularly critical when the timing characteristics associated with physical devices start pushing the speed limits of the devices. Although glitches are caused by many different circuit conditions. In the previous chapters. This chapter presents techniques to remove static logic hazards from circuits. A course in semiconductor devices may model these devices at the transistor level. you preformed a gate-level modeling of these devices when you applied the iterative-based design approach. Representing these physical attributes is best done using timing diagrams which turns out to be an art form of its own. You’ve also modeled circuits on a 261 . or how fast your digital circuit operates. (Bryan Mealy 2011 ©) 10. Robust digital design requires that the digital designer take into account the actual device parameters that will affect the real world application of the circuit. is an important attribute out there in digital design-land. we never really considered some of the physical attributes associated with the actual devices themselves. As you know. Although we expended considerable effort describing the operation and representation of many different types of circuits. Courses in semiconductor physics may model these devices at the molecular level. TIMING DIAGRAMS: This chapter revisits timing diagrams and introduces a method for providing useful annotations to increase the readability and understandability of timing diagram.

Timing diagrams show the values of signal as a function of time. In reality. the output can either be “high” or “low”. Time is therefore the independent variable (horizontal axis) while the signal value is the dependent variable (vertical axis). the timing diagram is the primary output of many standard digital design and test tools such as simulators and logic analyzers. This delay from the input to the output is the main topic of this chapter. a signal can’t simultaneously be high and low. ignored some timing considerations. The circuits you have modeled up to this point have. for the most part. 10.4 Gate Delays and Gate Delay Modeling Up until now. Timing diagrams are able to highlight circuit operation beyond a circuit schematic in that timing considerations such as propagation delays. you’ve used an idealized model for the logic gates you’ve worked with. Creating and analyzing timing diagrams is an important area of digital design. The concept of a gate that is modeled as “ideal” and its comparison to a non-idealized model provides a great vehicle to introduce timing diagrams and the concept of low-level device modeling in general. it won’t work in all cases. In terms of an adder. Timing issues are a critical in the design of most meaningful digital circuits.3 Timing Diagrams Again We discussed timing diagrams in a previous chapter so a quick overview won’t be too painful. the circuits you’ve designed have the ability to operation at speeds in the nano-second range (10-9 seconds) yet you were considering them from a functional level only. this would mean that you would want to perform as many calculations as possible in the shortest period of time. We’ll view them slightly different starting with this chapter. To put all of this in other words.Digital McLogic Design Chapter 10 module level and implemented them using VHDL structural modeling using the iterative-modular and modular-based approaches. 10. The general theme in most areas of digital design is to create circuits that are able to operate as quickly as possible while generating the correct result. etc. The usefulness of timing diagrams ranges from producing a visual explanation of how a circuit operates1 to providing a valuable debugging tool. In the context of our previous designs. The problem is that digital logic gates are physical devices and they require a minimum amount of time for changes in circuit inputs to effect circuit outputs. for example. Another main topic is the extended use of timing diagrams which are used to provide a visual representation of circuit delays. Moreover. A model is nothing more than a convenient description of something (as opposed to the real thing). And because signals are true functions in the mathematical sense of the word. you have been considering the gates you’ve been using to be idealized models. 262 . set-up and hold time. The throughput increases as the amount of time it takes inputs to generate the correct output decreases. The general thought here is to increase the amount of information your circuit can process. Although this approach works well for many applications. Since we are working with digital signals. Knowledge of circuit delays and proper use of timing diagrams forms the foundation of proper digital circuit design. you generally would prefer your RCA to produce a result as fast as possible. are easily indicated by the visual nature of the timing diagram. The use of timing diagrams becomes increasingly important as the operating speed of the circuit increases. 1 Recall that a timing diagram is considered a viable method to model digital circuits. The model essentially refers to the characteristics of the devices that are important to your particular need or application. The common approach in these methods is the use of models. The underlying goal of practically any digital circuit is to increase the amount of useful information any circuit can process (referred to as throughput).

The ramifications of using an idealized model are that there are no delays shown in the timing diagrams.1: using an idealized model for the devices. Timing diagrams generally show both the inputs to the device and the outputs.2 Time is represented on the horizontal axis. Moving from left to right on this axis represents the passing of time.1: The standard inverter and NAND gate. timing diagrams become less readable as the number of listed inputs and outputs increase. and usually are. The actual circuit requires a finite amount of time to switch from ‘0’ to ‘1’ and from ‘1’ to ‘0’. these levels will differ depending on the family of ICs used. signals require a finite amount of time to transition from high to low and thus are sometimes somewhere inbetween high and low.1: shows the schematic symbols for an inverter and NAND gate. the outputs respond immediately to the inputs. Time is generally understood to be the horizontal axis and is rarely labeled in timing diagrams. The concept of ‘1’ and ‘0’ is a model too. For more complicated circuits. For these simple devices. Modeling devices with an infinite slope is generally represents the functionality of a digital circuit and not its true operating characteristics. you’ll only list the most interesting signals in the timing diagram. in the interest of readability. (a) (b) Figure 10. 2 Timing diagrams represent a mechanism to show the input and output relationship between particular signals of interest: uninteresting signals should be.Digital McLogic Design Chapter 10 Figure 10. There are several important things to note about the timing diagrams in Figure 10. The high and low values generally represent voltage levels. the timing diagram may not show all the inputs and outputs. Figure 10. Ideal models are nice to work with but not always appropriate especially in the case where the operating speed of the circuit increases to the point where idealized models don’t accurately represent the functionality of the circuit. 263 . Once again. the exact values for high and low are usually not listed. all the circuit inputs and outputs are shown. In other words. Generally speaking.2 shows two example timing diagrams associated with the schematic symbols of Figure 10. omitted.2. the model we’re using opts to represent voltage levels as high and low which correspond to high and low positions on the given signals. Modeling these signal as only high or low is arbitrary but matches the definition of digital we’ve been working with. As you’ll soon find out. In reality. Each of the listed signals is modeled as being either “high” or “low”.

or prop delays.2: Timing diagrams associated with idealized models for the inverter and NAND gate. These times are most often labeled as tphl and tplh.3. The actual value of these delays is not given.3 are used to model delay times. (a) (b) Figure 10. In official digital terms.4. The timing diagrams in Figure 10. 10.3(b) with the difference in delay times of Δt3 and Δt4. Different flavors of digital devices will have different delay times. In actuality. The timing diagrams shown in Figure 10. There are several important things to note about the timing diagrams in Figure 10. this information is found in the datasheet associated with the device you are using. changes in the input signals require a finite amount of time to propagate to the output.3 use a non-idealized model for the circuit elements.1 Timing Diagram Annotation 264 .Digital McLogic Design Chapter 10 (a) (b) Figure 10.3: Timing diagrams for inverter and NAND gates that includes delays. respectively (or something similar). different flavors of transistors are used to implement these actual gates. Δt1 and Δt3 are examples of tphl while Δt2 and Δt4 are examples of tplh.3. the device characteristics such as propagation delays and voltage characteristics are primarily dependent upon the underlying transistor implementations of the gates. In Figure 10. The values for tphl and tplh are not necessarily equal for a given digital device which is modeled in Figure 10. This means that there are delays associated with the signal transitions that are indicated in the timing diagram. In other words. The prop delay times are further broken down into high-to-low transitions and low-to-high transitions. These delay times are referred to as propagation delays. These delays represent the amount of time required for an output signal to respond to a change in an input signal.

In other words. 10.5(b) show that the high-to-low transition of signal F is caused by the state of A and the low-to-high transition of signal B. interesting and important features that are present in the timing diagram often only occur in relatively small areas of the provided time span.2 The Simulation Process 265 . Figure 10. Figure 10. The state of each signal listed in the timing diagram is generally present for the entire listed time span in the given timing diagram.5(b) indicates that the current state of B and the low-to-high transition of signal A causes the low-to-high transition of signal F. In actuality. (a) (b) Figure 10. In order to draw the viewer’s attention to the important portions of the timing diagram. Figure 10.Digital McLogic Design Chapter 10 By their nature. (a) (b) Figure 10. The annotation symbols on the left of Figure 10. The non-timing lines and arrows drawn in Figure 10. The output transition from high-to-low occurs when both the input signals are high (plus some time delay as indicated in the timing diagram). the target symbol indicates when two or more signals are required to cause the switching of another signal.4 shows the symbology used to indicate causality in timing diagrams.4(b) indicate a relationship between the two timing events.5: Timing diagram notation for a multiple input device. In this case.4. The first arrow shows the low-to-high transition on signal A causes the subsequent high-to-low transition on the output of the inverter. signal A “and” signal “B” must both be high in order for the output to be high.5 shows a slightly more complicated timing diagram. timing diagrams provide an abundance of information for a given circuit. a special type of timing diagram annotation is always used. The right annotation symbol in Figure 10.4(b) also shows that the high-to-low transitions on signal A causes the low-to-high transition on the output of the inverter. This annotation style shows the relationships between signal transitions throughout the timing diagram. This symbol roughly represents a logical AND relationship between the two signals in that both the signals are involved in the listed transition. Don’t confuse this with a bit-wise AND operation.4: Timing diagram notation for a single input device. Similarly.

First. The approach you’ll use also serves as a good review of K-map techniques and a bolstering of your K-map skills. The numbers in the cells of the K-map represent the output value of 266 . if devices use simpler models.1 Static Logic Hazards Static logic hazards fit in nicely with the other material discussed so far in this chapter. Though “guessing” is not much of a technical term. On the other hand.5 Glitches in Digital Circuits A glitch in a circuit is generally defined as a momentary error condition. problems can be detected and corrected before the actual circuit is built. the digital output of some circuit element is momentarily high when it should be low (or vice versa).6(a) is shown in Figure 10. The models used for circuit elements can range from simple to sophisticated depending on your particular requirements.5. the timing diagram of Figure 10.Digital McLogic Design Chapter 10 The simulation of a digital circuit involves “guessing” how an actual circuit would operate if it were actually implemented. Glitches in circuits can be caused by many different conditions such as switch bounce. we’re only interested in signal A changing while signals B and C remain constant at their high levels. In particular. electro-magnetic interference.8(a). 10. These two transitions are shown in the timing diagram of Figure 10.6(a). The interior signals of the circuit contain labels that are used the timing diagram of Figure 10. sun spots. Secondly. In other words. In other words. it is a valuable design tool in that circuits can be designed and tested before the circuit is actually implemented. simulation time is reduced. the more sophisticated models require more processing power by the device performing the simulation and thus the simulation requires more time to complete. it’s basically what the simulation process is doing. you’ll learn to detect and correct for those conditions.7. and apathetic lab partners.7 shows the input transitions of ABC = “111” to ABC = 011” and ABC = “011” to ABC = 111”. An arbitrary example function has been entered in the K-map of Figure 10.8(a) are generated when the A input changes while the B and C inputs remain at their high values. thus saving valuable engineering costs and irreplaceable party time. The circuit associated with the reduced equation generated from the K-map of Figure 10. circuits which have been implemented can be modeled in order to debug portions of the circuit that may not be directly available to the outside world. 10. we’ll only be considering glitches caused by static logic hazards. The presence of a hazard in your circuit is an indication that a glitch may occur in your circuit under certain circuit conditions. In this way. In this case. As you probably can imagine.6(b). The two transitions shown in Figure 10. The timing diagram in Figure 10. Circuit simulation serves two main functions. The root cause of static logic hazards is unequal circuit delays in the devices used to implement the circuit. the model of a device is essentially a description of the device that the simulator can use when the device is considered in a circuit. demonic possession. Although there are many causes of glitches in digital circuits. This K-map shows the groupings that are associated with standard K-map reduction techniques. The presence of glitches in your circuit can be of grave concern in that these unwanted signal transitions can cause incorrect and intermittent errors in the operation of your circuit. In this section. The probability that the guesses made by the simulator are correct generally increase if the devices used in the circuit are accurately modeled by the simulator.7 highlights two input signal transitions and the effect these transitions have on the output and interior signals of the circuit.7 and the little arrows in Figure 10. The timing diagrams generated from circuit simulations can be compared against the output from other test devices such as Logic Analyzers for the verification of proper circuit models and the correct circuit outputs. The basic rule of thumb when using a simulator is that the simulation is only as good as the models used for the devices being simulated.

you would expect the output of the circuit to remain in its high state. As you can see in Figure 10.6(b). 267 .7 provide the explanation of the undesirable event.7. Signal Y is an ANDing of signal A and C. In the timing diagram. This is once again due to the fact the F is formed by an ORing of signals X and Y.Digital McLogic Design Chapter 10 the function. The numbers listed below reference the circled numbers shown in Figure 10. 1) This signal is the inversion of signal A. this transition is caused by the high-to-low transition of signal A after an appropriate delay. Since the output does not change (remains at ‘1’) during the two transitions listed.6: The standard K-map approach to function reduction and the resulting circuit. This is because the output signal F is an ORing of signal X and Y. F is the output of the given function. 3) The signal labeled X is an ANDing of signals A and B The low to high transition of signal A causes the low-to-high transition of signal X. As indicated in the Figure 10. the output temporarily goes to its low value before returning to the expected high state. The glitch in the output is caused by unequal circuit delays in the path of the signal in the circuit. 5) The low-to-high transition of signal X causes the low-to-high transition of the output signal F. (a) (b) Figure 10.7. the prop delays for the various circuit elements are model as being equivalent.7. 4) The high-to-low transition of signal Y causes the high to low transition of the output signal F. The annotations labeled in Figure 10. As indicated in Figure 10. This unexpected signal transition in the circuit output is the glitch we’ve been talking about. 2) The high-to-low transition of signal A causes the high-to-low transition of signal Y.

This particular hazard is referred to as a static ‘1’ hazard. it would be referred to as a function hazard.Digital McLogic Design Chapter 10 Figure 10.7 is referred to as a static logic hazard. There are two major types of hazards: function hazards and logic hazards. The previous example is referred to as a static logic hazard because the output was not expected to change as a result of the input change (in other words. Logic hazards can be broken into two sub-types: static hazards and dynamic hazards. These terms describe the desired state of the output when an input change occurs. east. These two types of hazards differ by the number of input changes that cause them. A unit distance move in a K-map is (a move in the compass directions: north.6. If more than one input changed simultaneously and caused a hazard. it was supposed to remain static). Any move in the K-map that is not from one cell to an adjacent cell is associated with a changing of more than one input variable. The hazard in the previous example was caused by a change in a single input which is what makes it a logic hazard. south. it’s not a big deal locate and correct logic hazards because of the unit distance property of K-maps. As you’ll soon see. The previous example was a static ‘1’ hazard because 268 . The glitch shown in signal F of Figure 10. or west) is defined to be caused by a change in a single input variable.8: The transition of interest and the associated cover term for the function.7: The timing diagram generated from the circuit of Figure 10. there are also static ‘0’ hazards which are associated with ‘0’ to ‘0’ transitions in the POS circuit implementations. (a) (b) Figure 10.

9 shows two examples of removing potential glitches with the inclusion of cover terms in the K-map reduction.8. The reason this approach works is that the each of the input variable transitions are covered by a product term due to the way the variables were grouped.Digital McLogic Design Chapter 10 the output was expected to remain high. Figure 10. This approach ensures that each change in input variable is contained in a grouping of its own. This ensures that each input transition is connected to a gate that is not affected by the change in that input variable. Another way to view this approach is that you must include some nonessential prime implicants in your grouping. In Figure 10.9. 269 . Glitching could also occur in when the output is expected to change as a result of the input transitions in which case the hazard would be referred to as a dynamic logic hazard. the normal product terms from the reduction are listed in the associated expression without parenthesis while the product terms associated with the cover terms are listed with parenthesis. Although your function will no longer be in reduced form. Note that by the inclusion of the cover terms. The static logic hazard in the above example is removed by including the grouping indicated with dotted lines in Figure 10. it will be free of static logic hazards. The key to removing static logic hazards is to ensure that all input transitions between the circled variables terms in a K-map remain in the same grouping. This essentially requires that you include other groupings in addition to the groupings that provide the best possible minimization of the function. the resulting circuit will be free of static ‘1’ logic hazards.9: Two more examples of removing potential glitches with cover terms (in parentheses). every ‘1’ to ‘1’ transition is included in a K-map grouping. While the resulting equation is less reduced when the cover terms are included. F = C D + BD + ( BC ) F = ABC + ABD + ABC + ( ACD ) + ( BC D) (a) (b) Figure 10.

Figure 10. Solution: The only tool you currently know of to detect static logic hazards is the K-map. ABC + ACD Equation 10-1: Product terms required to remove static logic hazards.10(b) shows the K-map with the standard groupings (solid lines) and the groupings required to remove the static logic hazards. Equation 10-1 shows the product terms required to remove the static logic hazards from the original circuit.10(a) shows the K-map model corresponding to the circuit model shown in the problem description. These two product terms can now be modeled on the gate-level and included in the original circuit. Figure 10. 270 .10: The initial (a) and completed (b) K-maps for Example 10-1. (a) (b) Figure 10. The mode of attack for this problem is to first translate the circuit model provided in the problem to a K-map representation.Digital McLogic Design Chapter 10 Example 10-1 List the product terms that need to be included in the following circuit that remove all static logic hazards.

Extra hardware can be strategically added to a circuit to remove static logic hazard. • • • • 271 . Although some applications do not need to consider delay characteristics of real devices. Digital device delays can be clearly modeled using timing diagrams. Static logic hazards are a potential causes of glitches in digital circuits. Special annotation techniques are available to increase the readability and understandability of timing diagrams. this extra hardware is generally referred to as adding cover terms. Glitches are caused by many different conditions present in digital circuits. Timing diagrams are useful for describing circuit behavior and verify correct circuit operation in simulation and actual circuit testing. Glitches are momentary error states in the outputs of digital circuits. Static logic hazards can be detected in K-map representations of circuits. Timing diagrams can quickly become large and messy.Digital McLogic Design Chapter 10 Chapter Summary • Timing diagrams show the state of digital signals as a function of time. The key to annotating timing diagrams is to direct the reader’s eye to the important portions of the timing diagram. these factors become more important as the operating speed of circuits increase. Real digital circuit elements necessarily have delays associated with their operation. Circuit operation in general cal be modeled using a timing diagram.

show what term(s) need to be included to remove any static logic hazards. Don’t use XOR type gates. B.8. explicitly show whether the given circuit contains glitches due to static logic hazards.5.3.12) 272 .4.11. F = (A. D) = ∏ (1. D) = ∑ (1. F = (A. Don’t use XOR gates.10.13) 7) Write an expression for the following function in reduced SOP form. Make sure the function contains no static logic hazards.8.9.3. re-implement the circuit in such a way as to remove the static logic hazards.7. Write the final expression such that the implemented circuit will contain no static logic hazards. F(A. C.5.11.5.14. C.7. D) = ∑ (0.6. C.6.15) 3) List the cover terms that would be required to eliminate the static-1 logic hazards from the following function if it was implemented in reduced SOP form.7.11. F(A.14) 5) Reduce the following function.2. B.6.3.13) 4) Write an expression for the following function in reduced SOP form. B.3. B.12. D) = ∑ (1. Add product terms to prevent glitches caused by static logic hazards.Digital McLogic Design Chapter 10 Chapter Exercises 1) Using the timing diagram below. Then.10.10. If glitches are present.10.11.4.9. B.8. C.15) 6) Reduce the following function.2. C. B.13. (a) (b) 2) Generate a timing diagram that shows the static-1 logic hazard present in the maximally reduced SOP implementation of the following function: F = (A. D) = ∑ (1.9. F(A. C.14. D) = ∑ (0.

D) = ∑ (2. 273 . B.7.6. C. Assume each of the circuit elements contain equivalent propagation delays.Digital McLogic Design Chapter 10 8) Write an expression for the following function in reduced SOP form.13. Make sure the function contains no static logic hazards.8. show whether the listed circuit contains a static logic hazard. and are indicated with vertical dotted lines in the provided circuit diagram. tpd. If the circuit does contain a logic hazard.10) 9) Using the timing diagram provided below. F(A. use the provided timing diagram to explicitly show the associated glitch.15) +∑ md(0.

Assume each of the circuit elements contain equivalent propagation delays. show whether the listed circuit contains a static logic hazard. tpd. 274 .Digital McLogic Design Chapter 10 10) Using the timing diagram provided below. and are indicated with vertical dotted lines in the provided circuit diagram. If the circuit does contain a logic hazard. use the provided timing diagram to explicitly show the associated glitch.

If the circuit does contain a logic hazard. show whether the listed circuit contains a static logic hazard. Assume each of the circuit elements contain equivalent propagation delays. and are indicated with vertical dotted lines in the provided circuit diagram. use the provided timing diagram to explicitly show the associated glitch. 275 . tpd.Digital McLogic Design Chapter 10 11) Using the timing diagram provided below.

276 . One of the aspects that made these implementations efficient was the fact that VHDL models could be used to describe the functions without first requiring the associated functions to be reduced. One of the basic notions of digital communications is the concept of parity. Parity generators and parity checkers form two more standard digital circuits that every digital designer knows about and uses. 2 In this context. Before the advent of cheap computers. The notion of parity generation covers several aspects of digital communications as well. the standard decoder has fixed and structured output values which are useful for controlling some other standard digital circuits1. Although some of the topics associated with map entered variables are obsolesced. (Bryan Mealy 2011 ©) 11. The use of map entered variables does have some interesting uses despite the fact that the introduction of programmable logic devices has somewhat reduced the need to apply those uses.1 Chapter Overview The non-standard decoder was a standard digital circuit introduced in a previous chapter. The standard decoder is similar to the non-standard decoder but has less flexibility in the output. A significant portion of digital design is centered around digital communications2. This attribute is commonly used to indicate whether an error occurred in the transmission of the data from one point to another. they do form the underlying theme for several other subtopics discussed in this chapter including K-map compression and implementing functions using K-maps. the K-map was the primary method used for reducing Boolean equations. The nonstandard decoder is used to implement generic input/output relationships which is quite useful in many digital design applications. We’ll not discuss this topic until a much later chapter.Digital McLogic Design Chapter 11 11 Chapter Eleven 11. The reality is that there are two types of 1 Standard decoders are typically used in controlling memory chips. the use of map entered variables could partially bypass this limitation under certain conditions. Main Chapter Topics DIGITAL DESIGN APPROACHES: This chapter introduces two standard digital circuits: the standard decoder and the parity generator. Parity is used to describe an “attribute” of a given set of signals. In other words. MAPPED ENTERED VARIABLE: This chapter also introduces the notion of map entered variables. Generally speaking. Although the practical use of K-maps is limited by the number of input variables in the function.2 Standard Decoders The topic of non-standard decoders was covered in a previous chapter. Recall that the primary use of non-standard decoders was to implement “sets” of functions in an efficient manner. digital communications is defined as the transmission of digital data from one device to another. the nonstandard decoder represented a somewhat generic device.

The bulleted item listed below highlight these main attributes: • Standard decoders always have a binary-type relationship between the inputs and outputs. the small numbers associated the circuit inputs and outputs are used to indicate a weighting on those inputs and outputs. F2 or F3 will be a ‘1’. The standard decoder is nothing more than a special type of non-standard decoder. The good news is that we’ve already implicitly studied the standard decoder when we were looking at a portion of the circuitry associated with a MUX. when the word decoder is used. Note that this circuit forms a major portion of the circuitry of a 4:1 MUX. at any given instance in time.2(b) is an adequate approach to describing a standard decoder. there is special relationship between standard and non-standard decoders. In reality. The condition that makes this a standard decoder is the relationship between the number and attributes of the inputs and outputs. Attaching these numbers is absolutely required unless you are using the bundle notation shown in Figure 11. the first digit refers to the number of control variables that the circuit contains while the second variable refers to the number of outputs the circuit contains. • 3 A more complete explanation of this circuit appears in the MUX description in Chapter 7. This ordering is implied by the bundled case. The approach described in this text highlights the two general uses of a decoder: a non-standard decoder is look-up table (LUT) while a standard decoder has a special relationship that we’ll describe in the next few paragraphs.1 shows this relationship. you probably won’t ever find a reference to a non-standard decoder and standard decoder in other digital logic textbooks. Figure 11. 4:16. note that due to the configurations of the inputs S1 and S0. while the three others will be a ‘0’3. the standard decoder also established a relationship between circuit inputs and outputs. only one of the outputs F0. 3:8.1: The Venn diagram overview of decoders As with non-standard decoders. For example.Digital McLogic Design Chapter 11 decoders out there. Also note that n input variables (binary) can be arranged in 2n unique binary combinations. As a result. Note that this progression has a n:2n relationship.2(c) is used more often. Although the schematic diagram of circuit of Figure 11. Note that in Figure 11. F1. it does not actually refer to a specific type of circuit as was generally true with MUXes. the schematic diagram of Figure 11. only one of the AND gates will be active at a given time. Decoders come in one of two flavors: the standard decoder and the non-standard decoder discussed previously. Figure 11. 277 . standard decoders always come in flavors such as 1:2. Figure 11. particularly in the context of VHDL.2(a) shows a gate-level diagram of a 2:4 standard decoder. the standard decoder has a more rigid definition. In all honesty. In this notation.2(b). In other words. As a reminder of how the circuit in Figure 11.2(c). The main difference is that the number and function of circuit outputs are essentially fixed by the definition of the decoder. We’ll take another look at that circuitry in the explanation of a decoder. etc. 2:4. Without these numbers in the non-bundle case. there would be no way of knowing the ordering associated with either of the inputs. While the non-standard decoder was used to establish a specific relationship between circuit inputs and outputs.2(a) operates.

4 This is an overly simplified description. The bubbles on the output of the Figure 11. Along these lines. a decoder can also use NAND gates instead of AND gates for the internal circuitry. The final result of the NAND-based decoder is the opposite of the AND-based decoder in that only one of the outputs is ‘0’ at a given time while the other outputs are in a ‘1’ state.2: A standard 2:4 decoder in schematic and circuit forms. Figure 11. We’ll be describing the entire story in a later chapter. there’s actually a lot more to it. (a) (b) (c) Figure 11. In this approach all of the outputs except one are high at a given time while the other output is low. This is true because the control variables are arranged such that only one of the internal AND gates is non-dead at a given time.3 shows the circuit and the associated schematic diagram for a NAND gate-based standard decoder.Digital McLogic Design Chapter 11 • Only one of the outputs of the standard decoder is active at a given time.3(b) can for now be thought of a being the same bubbles on the NAND gates4. 278 .

entity dec4t2 is port ( SEL : in std_logic_vector(1 downto 0).2 and Figure 11. As specified by the entity declaration.3.4: Entity declaration for standard 2:4 decoder. F : out std_logic_vector(3 downto 0)). Figure 11. end dec4t2. Since the bundle notation used the “downto” notation (as opposed to the “to” notation).5(b) implements the decoder using one conditional signal assignment statement.3: A standard 2:4 decoder with inverted outputs. There are a few important items to notice in both of these cases. both the control signals and output signals were declared as bundles. Standard decoders can be nicely modeled using VHDL. the left-most bits in the bundle are the most significant bits.5(a) shows the decoder implemented using one selective signal assignment statement while Figure 11. Figure 11. As you’ll find out in later chapters. For both of the VHDL models of Figure 11.5. The following figures show dataflow and behavioral models for the associated architecture. The catch-all clause is handled with the “when other” clause for selective signal assignment and with the final “else” in the conditional signal assignment. The result of this notation is that a SEL of “00” is the lowest valued selection input value which corresponds to data outputs of “0001” which shows the least significant bit in a ‘1’ state. This implied numbering is true for all bundle signals. Both dataflow model are similarly structured in that they both listed every possible case based on the two input signals and they both contain a “catch-all” clause. Figure 11. Dataflow and One important feature to note from the VHDL models is that a default case is always provided.4 shows an entity declaration for a standard 2:4 decoder using bundle notation.Digital McLogic Design Chapter 11 (a) (b) Figure 11. the when others statement is • 279 . • There is an implied weighting used by the bundle signals. the presence of some type of catch-all statement is massively important in VHDL models. Figure 11.5 shows two forms of dataflow models for the standard decoder. Examining the VHDL model provides a viable approach to understanding the input/output relationship of the circuit if your understanding is still unclear from the associated circuit diagrams of Figure 11.

“0100”. Both models list every possible combination of the SEL inputs (with desired outputs) followed by a catch-all statement. “0010”. "0000" when others. "1000" when "11".6: Behavioral models for the standard 2:4 decoder. for both models the four lines previous to the when others statements provides every possible input combination for the SEL inputs. 280 . The dataflow and behavioral implementations of these two devices clearly shows the analogy between the selected assignment and the case statement and a similar analogy between the conditional signal assignment and the if statement. Figure 11. when “01” => F <= “0010”. the final else is the catch-all statement while the when others statement is the catch all statement for the case statement. when “10” => F <= “0100”. A few other important items are listed below. (a) (b) Figure 11. "0010" when SEL = "01" else. providing the when others line proves to be a great debugging tool in that if you detect the output of the decoder lines to be all zeros. you know there is a problem with your model. "1000" when SEL = "11" else. end dec_a. Both behavioral models contain catch-all statements. These implementations are surprisingly similar to the dataflow implementations of Figure 11. "0010" when "01". Listing every possible case is not required but is considered good VHDL programming practice. architecture dec_d of dec4t2 is begin dec: process(SEL) begin case SEL is when “00” => F <= “0001”. the process statement is reevaluated each time a change in the SEL signal is detected. • • Because the process sensitivity list contains the SEL signal.Digital McLogic Design Chapter 11 technically not required but it is considered good VHDL programming practice to include in the model. The catch-all assignments of “0000” is arbitrary since this output is by definition not specified by the description of the standard decoder. (a) (b) Figure 11. there is technically no need to include the when others line. end dec_c. In other words. end dec_b. when “11” => F <= “1000”. architecture dec_b of dec4t2 is begin F <= "0001" when SEL = "00" else. "0100" when "10". "0100" when SEL = "10" else. end dec_d. In this particular case. when others => F <= “0000”. “1000”.6 shows two behavioral model implementations of a standard 2:4 decoder. end process.5. <= <= <= <= “0001”. For the if statement. architecture dec_a of dec4t2 is begin with SEL select F <= "0001" when "00". "0000".5: Dataflow models for a standard 2:4 decoder. end case. • architecture dec_c of dec4t2 is begin dec: process(SEL) begin if (SEL = “00”) then F elsif (SEL = “01”) then F elsif (SEL = “10”) then F elsif (SEL = “11”) then F else F <= “0000”. end process. Because of this.

When the EN input is ‘1’. EN 0 1 1 1 1 (a) S -00 01 10 11 (b) F 0000 0001 0010 0100 1000 Figure 11. a decoder with an enable input is sometimes referred to as a DMUX5 but this is not a commonly used term. a timing diagram with partial annotations is also provided. We’ll not include it here either but we provide a table that describes the behavior of such a circuit along with a VHDL model. Note the ease at which the circuit is modeled by embedding a case statement inside of an if clause. As an added bonus for your viewing enjoyment. 5 And. A schematic symbol and a table describing the operation of a standard decoder with an enable input are shown in Figure 11.7(b). I’ve never understood exactly why.7: A 2:4 decoder with an enable (a) and its behavior described in tablature format (b). Although this device could have been modeled using a dataflow model. In this model. the underlying circuitry becomes more complicated and is rarely included in digital design textbooks. The VHDL model is a prime example showing the versatility of behavioral modeling. it would have been tricky and the resulting code would have been less understandable. For the record.7(a) and Figure 11. Once more input control signals are added to the standard decode. One of the typical controls on the decoder’s inputs is an enable signal (or several enable signals). 281 . calling it a DMUX generates confusion. the decoder outputs follow the accepted definition of a standard decoder.Digital McLogic Design Chapter 11 Example 11-1 Design a standard 2:4 decoder that has an EN input (enable). decoders often have more control inputs.8 show the associated VHDL model. respectively. In reality. Figure 11. When the EN input is ‘0’. Solution: This section has described the attributes associated with a standard decoder in that the standard decoder has one set of inputs that directly control the outputs. circuit operation is easily described with a few sequential statements. the decoder outputs are all ‘0’.

Figure 11. end process. This characteristic provides a quick but excellent method to verify proper operation of the decoder. There are two main features worth noting in this timing diagram. S : in std_logic_vector(1 downto 0). when “10” => F <= “0100”. For this timing diagram. end decoder. a few annotations have been added to show which input signals caused the changes in the output signals. one and only one of the F bundle output signals are ‘1’ while the remainder of the signals are ‘0’.Digital McLogic Design Chapter 11 -. when “01” => F <= “0010”. architecture decoder of decoder is begin dec: process(SEL) begin if (EN = ‘0’) then F <= “0000”. end decoder.2:4 standard decoder with enable input (DMUX) entity decoder is port ( EN : in std_logic. end case. Figure 11. F : out std_logic_vector(3 downto 0)). 282 . only a few arrows are included. when “11” => F <= “1000”. when others => F <= “0000”. Any time the EN input is ‘1’.8: VHDL model of 2:4 decoder with enable input. In order to keep the diagram from becoming too messy.9 shows a timing diagram that describes the behavior of the circuit described in Example 11-1.9: An example timing diagram for Example 11-1. Figure 11. end if. else case SEL is when “00” => F <= “0001”. • • The F bundle output is only all ‘0’s when the enable input (EN) is ‘0’.

Digital McLogic Design Chapter 11 The following is another example of a standard-type decoder. The selected signal assignment statement is evaluated each time there is a change in the chooser_expression listed in the first line of the selective signal assignment statement. Once your circuit works. The output bus. The only comment for the VHDL model for Example 11-2 of is that the vertical bar is used as a selection character in the choices section of the selected signal assignment statement. Figure 11. 283 . the selected signal assignment statement is one form of a concurrent statement. Example 11-2 Write the VHDL code that implements the following circuit. Use a selected signal assignment statement in the solution. SZ_OUT. The boundaries begin to get a little fuzzy in digital design.10: The black box diagram for Example 11-2.10 shows the black box diagram for the solution while Figure 11. but this example does show some useful VHDL syntax. This is verified by the fact that there is only one signal assignment statement in the body of the selected signal assignment statement.11 shows the entire VHDL model. The more important thing is to do what you need to do to make the design work. The table below shows the desired relationship between the input and output. input range of D_IN 0000 0011 0100 1001 1010 1111 unknown condition output value for SZ_OUT 100 010 001 000 Solution: This is another example of a standard decoder circuit. The circuit contains an input bundle containing four signals and an output bundle containing three signals. The input bundle. . you can name if George if you really want to. D_IN. represents a 4-bit binary number. is used to indicate the magnitude of the 4-bit binary input number. Don’t go overboard on trying to place the proper label on a circuit. Figure 11. This increases the readability of the code as it does with the similar constructs in algorithmic programming languages Once again. Not that there is too much more to say about standard decoders.

Figure 11. The set of bits that the parity concept is applied to in Figure 11. The concept of parity is generally applied to a set of bits. 284 . SX_OUT : out std_logic_vector(2 downto 0)). Moreover. 11.12: An example of parallel signals and serial signals. the set of bits considered for the application of the parity concept are values of the five signals circuit in Figure 11.A standard decoder-type circuit for using selective signal assignment -----------------------------------------------------------------------entity my_sz_ckt is port ( D_IN : in std_logic_vector(3 downto 0).12(b) shows an example of both parallel and serial configurations. end my_sz_ckt. This set of bits can either exist at one moment in time in a parallel configuration or the bits can exists over several set times in a serial configuration. others. Figure 11. The important thing to note here is that the concept of parity is applied to a set of bits: this set of bits can either bit collected in a parallel or serial format as shown in Figure 11.12(a). The concept of parity can also be applied to a single signal over a given time span.12(a). “1010” | “1011” | “1100” | “1101” | “1110” | “1111”.12(a) and Figure 11. (a) (b) Figure 11. The concept of parity in used quite often in digital communications which is why both the concept itself in addition to the circuitry that handles parity is so important.11: The VHDL model solving Example 11-2. In Figure 11. the application of parity is slightly more complicated but is also on the doable side. The concept of parity is relatively simple. it is one of those standard circuits that every digital designer should understand and be able to design. In other words. my_sz_ckt is “0000” | “0001” | “0010” | “0011”. architecture spec_dec of begin with D_IN select SX_OUT <= “100” when “010” when “001” when “000” when end spec_dec.Digital McLogic Design Chapter 11 -------------------------------------------------------------------------.12(b) are the values of the SIG signal at five different instances in time.3 Parity Generators and Checkers Parity generators and parity checkers are twp of the standard digital circuits that everyone who is anyone in digital-land knows about. the values of the bits in question are considered to exist at one instance in time. “0100” | “0101” | “0110” | “0111” | “1000” | “1001”.12. respectively.

This example shows four bits that are being transferred in parallel across some type of medium. For this example. you’ve actually worked with similar circuitry in the case of the Full Adder. Although modulo-2 addition sounds intimidating. The concept of parity simply refers to the notion of whether the sum of the set of bits was odd (odd parity) or even (even parity). the Parity Generator circuit assigns the output (the parity bit) to make sure that the set of data and parity bits are either odd or even parity. What is important in this problem is the notion that a total of four data bits are being transferred: three data bits and a parity bit. The circuitry for parity generators and checker is not overly complicated. let’s design the Parity Generator such that it generates even parity based on the data bits A.13: An example of parity generation and checking. the result of the addition was even. The Parity Generator box is a circuit that imposes either an odd or even parity to the three data lines and is then sent with the data bits. To perform a modulo-2 addition on a set of bits. there is a good chance that there was not an error during transmission6. If the bits are sent with even parity and arrive with odd parity. As you will find out soon. you should take a look at the XOR gate’s truth table to convince yourself of this fact. The probability that two bits are erroneous is significantly less that the probability that one bit was in error which is why parity is an effect error detecting measure. Figure 11. The concept of parity is particularly useful in digital communications. and C. the data being transferred is generated by the Data Generator box which again is not important for this problem. If the bits were sent with odd parity and arrives with odd parity. the parity would still be correct but two of the bits would be incorrect and thus your entire message was garbage.Digital McLogic Design Chapter 11 The concept of parallel and serial is probably more complicated than the concept of parity itself. it sometimes indicates an error on the PR output of the Parity Checker. just keep in mind that the concept of odd and even parity has nothing to do with odd and even numbers in the event that you’re considering the set of bits in question to represent some type of number. As you would probably guess. This circuit provides error detection for the data bits sent across the medium. B. the concept is straight-forward.13 shows a simple example of a communication system that uses the concept of parity. if the sum of the set of bits is ‘0’. Once the bits in question are gathered. 6 285 . there is obviously an error generated somewhere during transmission. That’s about it for the concept of parity. In other words. The circuitry on the receiving end expects either odd or even parity (as set by the circuitry). the XOR gate inherently performs modulo-2 addition on its two inputs. Once these bits are transferred across the medium. The medium in question is immaterial for this problem. Figure 11. For ease of representation in this circuit. parity refers to the result of a modulo-2 addition of the bits. if two bits change. if it receives a message with the wrong parity. In other words. the result was odd. the parity better be the same as it was before the bits were transferred. If the sum of your addition was odd. Modulo-2 addition refers to a bit-oriented addition operation: the result of this addition is either ‘0’ or ‘1’. For this example. you add all the bits and your result is either ‘0’ or ‘1’.

B. The truth table in Figure 11. C. C. Although at first glance the truth table of Figure 11. In other words.14: An example of parity generation. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 (a) (b) Figure 11. Figure 11. C.1. and D with even parity.14(a) does not appear to have any reduction possibilities. B. and C) + ‘1’ (from the parity bit D) which is ‘0’. B. The K-map associated with the truth table shown in Figure 11.14(a) shows this concept in tabular form. What we need to do in this problem is assign D to ensure that the set of bits A.14(b). The equation generated from Figure 11. The approach we’ll take to do this is to examine bits A.1: Derivation of the even parity generating circuit. if these bits have odd parity. B. In this way. the parity of bits A. and C.14(a) is provided in Figure 11. and D have even parity. With a final modulo-2 addition of ‘0’ for all the bits. the modulo-2 some of all the bits will be ‘1’ (parity from bits A.13(b) can then be factored to extract the XOR values as is shown in Table 11. B. the parity bit is set to ‘1’.15 shows the final resulting circuit. (a) (b) (c) (d) D = A BC + ABC + ABC + ABC D = A( BC +BC ) + A( BC + BC ) D = A( B ⊕ C ) + A( B ⊕ C ) D = A ⊕ (B ⊕ C) Table 11. the D column is assigned to ensure that modulo-2 sum of all the columns is ‘0’ thus provided the set of bits A. but upon further inspection you’ll notice that the K-map contains bunches of diagonals. and D is even.Digital McLogic Design Chapter 11 we’ll represent the parity bit with the variable D. 286 .

Since the bits were sent with even parity. Note that this truth table contains characteristics similar to the truth table of Figure 11. As a final note in this saga of parity generation. Figure 11. the final equation is listed in Figure 11. This design can be nicely done with a truth table of all things.14(b).16(a) is that the PR column is assigned to generate an even parity based on all of the sent bits. the arrival of bits having an odd parity indicates that an error occurred in transmission (at least of the bits was toggled). For this problem. we need to design a circuit that checks the incoming bits to ensure that they are even parity as was sent by the sending end of the circuit. If you were to grind out the equations for this truth table. you should notice a similarity between the final equation of Table 11. 287 . The results are definitely interesting but not overly surprising. This design technique is one of the standard design approaches and is expected in digital design-land.17(a). Figure 11.15: An example of parity generation.Digital McLogic Design Chapter 11 Figure 11. we arbitrarily produced a bit that generated even parity for the entire set of four bits. All four bits were sent across the medium. we generated a parity bit (D) based on the four data bits (A. And what about odd parity generation? It would be a great exercise to take a look at a circuit that generates odd parity. you can apply the iterative-modular design technique to easily form parity generators of more than four bits.16(b). To summarize the previous process. Another way of looking at the PR column in Figure 11. The resulting K-map is shown in Figure 11. B. On the receiving side of the circuit.16(a) shows the resulting truth table. In this truth table. you should actually grind out these equations to increase your competence level in Boolean algebra. The approach is similar to the approach take in the even parity generation.17(b) shows the resulting circuit. From this similarity. Note that the only difference between a 3-bit even parity generator and a 4-bit even parity generator is the addition of one more XOR term.1 and equations in Figure 11.17(a). and C). This circuit essentially needs to generate the modulo-2 sum of the four received bits. the PR column indicates an error if the parity of the received bits was odd.

Also. In summary. the topic of MEVs is less applicable.Digital McLogic Design Chapter 11 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PR 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 (a) (b) Figure 11.4 Map Entered Variables Without doubt. PR = ( A ⊕ B) ⊕ (C ⊕ D) PR = A ⊕ B ⊕ C ⊕ D (a) (b) Figure 11. map entered variables (MEVs) are an important topic in digital design. you realize this one day if you continue onwards into digital design. But it’s important enough to require that you have a few MEV skills. In current digital design courses where students are actually implementing real circuits (using VHDL modeling). MEVs were more important because they provided a topic that was easy to test students on. Back in the days when a digital design course was mostly paper designs. this is an important topic.16: The truth table and K-map for the 4-bit even parity generator. 288 .17: The equations and circuit for the 4-bit even parity generator. 11. it builds your familiarity and skills with K-maps.

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MEVs are, as the name implies, variables that are entered directly into a K-map. Up until now, we have only entered 1’s and 0’s into K-maps. One of the major drawbacks of a K-map is the fact that once your function in question has more than four variables, your K-map becomes real ugly and you start regretting ever getting into digital design. Using MEVs somewhat mitigates this problem. This is of course not a great justification because in reality, a computer with the proper software is going to do a better job of reducing functions than you and your K-maps. To develop these ideas, consider a three variable K-map with input variables A, B, and C. A general expression for such a K-map in standard SOP form can be written as shown in Equation (a) of Figure 11.18. If we AND both sides of the function with the Boolean variable F, no algebra rules are violated and we preserve the inequality. The resulting equation is shown in Equation (b) of Figure 11.18. From the Equation (b), we can now substitute in the actual values of a given function for the variables F that appear as part of the product terms on the left-hand side of the equation. For this example, we’ll use the function: F = ∑ (2,3,5,6) . The result of these substitutions appears in Equation (c) of Figure 11.18. From this point, we can massage the resulting equation to the new look of Equation (d). Note that in Equation (d) every value of F is represented but we’ve factored out the A and B terms. Using this notation, the AB-type terms are referred to as sub-minterms and include every possible combination of the two most significant variables from the associated truth table. Equations (e) and (f) are derived by grinding out the math associated with the non-sub-minterm expression. The final equation presented in (f) presents a combination of both the sub-minterms and the MEV terms (the MEV terms are shown in the square brackets).

(a) (b) (c) (d) (e) (f)

**F = ABC + ABC + ABC + ABC + ABC + ABC + ABC + ABC
**

F ⋅ F = F = ABC F + ABCF + ABC F + ABCF + ABCF + ABCF + ABC F + ABCF

F = A BC (0) + A BC (0) + ABC (1) + ABCF (1) + A BC (0) + A BC (1) + ABC (1) + ABC (0) F = A B ⋅ [C (0) + C (0)] + AB ⋅ [C (1) + C (1)] + A B[C (0) + C (1)] + AB[C (1) + C (0)] F = A B ⋅ [0 + 0] + AB ⋅ [C + C ] + A B[0 + C ] + AB[C + 0] F = A B ⋅ [0] + AB ⋅ [1] + A B[C ] + AB[C ]

Figure 11.18: The derivation of the sub-minterm and MEVs.

The results from the derivation shown in Figure 11.18 are typically not the way MEVs are generated. A better way, although not the best way, is shown in Figure 11.19. Note that Figure 11.19 was originally the truth table associated with the function in the previous derivation. This truth table was then divided into two-row pairs; each of the two-row pairs in the truth table are associated with a sub-minterm. Note that for each of the two-row pairs, the A and B values are identical. Be sure to note that these values are associated with a 2-bit binary count. The MEVs associated with this example are shown in the MEV column. This example was carefully construction to show each of the four possibilities for the MEVs. The approach we’re taking in this truth table is to make the C variable into an MEV. This requires that we draw upon the relationship between the C and F columns in the truth table. In this manner, there are only four possible MEVs as shown in the MEV column of Figure 11.19: 0, 1, C, and a complemented C. From this point, it should be clear that we can enter the MEVs into a two-variable K-map. The resulting K-map is provided in Figure 11.19(b).

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(a) (b) Figure 11.19: A truth table shown MEVs and sub-minterms (a) and the associated 2-variable truth table. The technique of generating MEVs from a truth table works fine for the least significant variable in the truth table but that’s about it. There is actually a better technique that can be used to convert any input variable into a MEV and we’ll look at that next. There is a one interesting thing about the K-map shown in Figure 11.19(b) that is worth mentioning here. Although this K-map appears the same as any other 2variable K-map that you’ve worked with, it is actually significantly different. With a normal K-map, each cell represented one output value. Each cell in the K-map of Figure 11.19(b) now represents two output values as you can see from Figure 11.19(a). Another way to look at this is that every cell in the K-map of Figure 11.19(b) is now a miniature K-map all its own; each of the mini-K-maps that are represented by these cells are one-variable K-maps. While we have never had the need to work with a one-variable K-map, such a K-map would contain two cells. In other words, the K-map of Figure 11.19(b) is actually comprised of four two-variable K-maps. This is sort of strange but sort of cool at the same time. 11.4.1 Karnaugh Map Compression

The term K-map compression comes from the fact that when generating MEVs, the resulting K-map shrinks by at least one variable. Shrinking the K-map is one of the great advantages of using K-maps in that you suddenly have the ability to reduce a six-variable K-map down to a manageable size (such as a four-variable K-map). You saw this compression in the example in Figure 11.19. What we want to do now is present a technique that can be used to compress a K-map for any variable instead of just the least significant variable as was done in the Figure 11.19 example. For this example, let’s compress the function shown in Figure 11.20. There is nothing special about this function; it’s just another generic function used for the sake of this example. The approach we’ll take in this example is to compress this function for each of the input variables. Keep in mind that although this technique is presented for a 3-variabl K-map, it works great for K-maps of any reasonable size.

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A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 0 1 1 0 0 0 1 1

Figure 11.20: A generic function we’ll use to describe the K-map compressing technique. The heart of this technique is to use the K-map to identify the sub-minterms. Once the sub-minterms are identified, they can be easily placed into a K-map. The one thing to keep in mind when using this technique is that there are only the four possibilities presented in the example of Figure 11.19: 0, 1, the MEV, and a complemented MEV. Example 11-3 Compress the K-map of Figure 11.20 for the C variable.

Solution: The first step in the solution is to identify the sub-minterms. This is shown in Figure 11.21(a) by the dotted lines. For the C variable, the sub-minterms are associated with the A and B variables. Another way to look at this is that the dotted lines are locating all the product terms associated with standard K-map groupings of the sub-minterm variables. This means that in Figure 11.21(a), the dotted lines represent the four possible AB-type K-map grouping. Yet another way to view this approach is do identify groupings that cut the boundaries of the variable you’re compressing. In Figure 11.21(a), the dotted lines are accompanied by the decimal equivalent of the binary number associated with the subminterm variables. These decimal numbers are used as indexes into the compressed K-map. The compressed K-map with MEVs entered is shown in Figure 11.21(b).

(a) (b) Figure 11.21: A truth table shown MEVs and sub-minterms (a) and the associated 2-variable truth table.

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The important thing to keep in mind in this problem is that each of the sub-minterms in Figure 11.21(a) generates a Boolean equation. Table 11.2 shows these four equations. Once again, these equations represent the four possibilities. Keep in mind that the outputs associated with both the complemented and uncomplimented C terms comes from the K-map of Figure 11.21(a). The truth is that you may want to generate these equations for the first couple of times you compress a K-map. After that, you’ll probably develop your own technique for employing this approach that is more direct than writing out the equations for every sub-minterm. Sub minterm # 0 1 2 3 Sub minterm Sub-minterm Equation Final Term

AB

AB AB

C ⋅ 0 + C ⋅1 C ⋅1 + C ⋅ 0 C ⋅0 + C ⋅0 C ⋅1 + C ⋅ 1

C

C 0

AB

1

Table 11.2: Boolean equation explanation of Figure 11.21.

Example 11-4 Compress the K-map of Figure 11.20 for the B variable.

Solution: The first step is to identify the sub-minterms. In this example, the sub-minters are associated with the A and C input variables. The associated K-map-type groupings are then associated with these sub-minterm variables as shown in Figure 11.22. The transferring of the MEVs from the sub-minterm grouping to the compressed K-map is slightly more complicated in this example than it was for compressing the K-map for the C variable in the previous example. Since some of the sub-minterm groupings are broken off the K-map in Figure 11.22, confusion may set in; try hard to prevent this. Boolean equations similar to those of Table 11.2 can be generated for this example.

Figure 11.22: K-map compression for the B variable of a 3-input K-map.

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Example 11-5 Compress the K-map of Figure 11.20 for the C variable.

Solution: This example is once again similar to the previous two examples. Once again, the key to performing this type of compression is the use of the sub-minterms indexes to generate positional information into the compressed K-map. For the solution to this problem, shown in Figure 11.23, two flavors of K-maps are shown. The overall approach here is to do what you need to do to compress the K-map. There are many ways to approach this; choose the way that makes the most sense to you.

Figure 11.23: A truth table shown MEVs and sub-minterms (a) and the associated 2-variable truth table. You can use this K-map compressing technique to compress four-variable K-maps also. There are some exercise problems that do this but no examples are provided here. Another thing worth noting is that you can compress a K-map that has already been compressed by also applying this technique. In this case, each of the K-map cells represents more than two non-compressed K-map cells. This is not a complicated topic but it does not have much use in modern digital design so we’ll not speak too much about it here.

**11.5 Implementing Functions Using MUXes
**

Implementing functions using actual digital devices has been the name of the game for many years now. Back in the old days, before there were programmable logic devices that could do just about anything, people actually implemented functions using discrete logic. If you ever have had the opportunity to rip apart old electronic devices, you’ll generally come across boards that contained an exceeding number of integrated circuits, or ICs. These ICs were generally digital devices of various sorts; and often times they were simple devices such as discrete logic gates. The truth was that this design was tedious and time consuming and the resulting circuits ate up a lot of power. A partial solution for this problem was to implement functions using devices such as MUXes. Since some of the required logic was already built into the MUX (recall the underlying circuit diagram for a MUX), less external circuitry was required. But things have changed these days. Programmable logic devices are massively powerful and can, in conjunction with supporting software, easily implement even the most complicated digital devices. The need to implement functions on devices such as MUXes is obsolete. We’ll take a brief look at it here

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because the topic does arise occasionally out there in digital design land. It does have some relation to the compressed K-map which provides an opportunity to practice those types of problems. A MUX is known as a selection device: under the control of the selector inputs, one of the several inputs is selected to appear on the single output. The approach for having a MUX implement a function to have the function’s independent variables connected to the selector inputs of the MUX and to have the output variable connected to the other inputs of the MUX. Connecting the MUX in this way allows the selector variables to select one of the inputs (which are associated with the function’s output) to appear on the output of the MUX. The best way to see this is through a simple example. We’ll borrow the example we were working with in the section on compressed K-maps. Example 11-6 Implement the following function on a 8:1 MUX: F ( A, B, C ) = ∑ (2,3,5,6)

Solution: The compact minterm form of the function indicates where the 1’s of the circuit live. For this problem, we simple need to connect power to the 2, 3, 5, and 6 inputs on the 8:1 MUX. Inputs that are not connected to power are the 0’s of the circuit and are connected to ground. The final circuit is shown in Figure 11.24. The triangular symbol on the bottom is a ground signal which is generally taken to be the ‘0’ value in digital circuit land. The bent-T is generally taken to be the power connection and in this case is labeled “Vcc” for mostly historical reasons.

Figure 11.24: A MUX-based implementation of a function.

Example 11-7 Implement the following function on a 4:1 MUX: F ( A, B, C ) = ∑ ( 2,3,5,6) . Provide three different solutions to this problem by using AB, AC, and BC and the selector inputs to the 4:1 MUX.

Solution: The trick to this flavor of problem is to realize that there are three independent variables and only two control variables on the 4:1 MUX. The way around this is to compress the K-map before implementing it on the MUX: the compressed variable then appears as a MEV on the inputs to the MUX. Herein lies the connection between K-map compression and implementing functions on MUXes. 294

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This used to be a big deal in digital design; it’s not any more but it’s still sort of cool. Instead of actually redoing this problem, we’ll pull the solutions directly from Figure 11.21, Figure 11.22, and Figure 11.23. Figure 11.25 show the final MUX-based function implementations for this problem.

(a)

(b)

(c)

Figure 11.25: A MUX-based implementations for three different sets of control variables as specified in Example 11-7.

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Chapter Summary

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Standard decoders are similar to non-standard decoders but have more limitations in the outputs. Standard decoders can be easily modeled used various types of VHDL concurrent statements. A standard decoder is a specialized non-standard decoder; a non-standard decoder is basically look-up table. The notion of parity is used to describe a characteristic of a set of signal or a sequence of signals. Parity is defined as the modulo-2 addition of the ‘1’ bits of the signals in question. Parity can either be even or odd. Parity generators are used to generate a parity bit that states whether signals have even parity or odd parity. Parity checkers are essentially the same circuit as parity generators: both are implemented on the gate-level using a set of exclusive-OR type gates. Map entered variables provide another method of representing functions. A MEV is a variable that associated with more than one cell in a K-map, or equivalently, more than one row in a standard truth table. One main use of MEVs is to effectively reduce the number of independent variables in for a given function which increases the possibility that a K-map reduction can be applied. MUXes can be used to implement functions. In these cases, the independent variables act as the control inputs to the MUX while the MUX output represents the function output. K-map compression facilitates the use of MUXes to implement functions. In real digital circuits, functions are rarely implemented on MUXes but the topic serves as yet another aid to understanding K-maps.

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Chapter Exercises

1) Provide a VHDL model of a 3:8 decoder using conditional signal assignment, selective signal assignment, and a process statement; consider the decoder’s outputs to be active high. Provide a VHDL model of a 3:8 decoder using conditional signal assignment, selective signal assignment, and a process statement; consider the decoder’s outputs to be active low. Based on the standard 2:4 Decoder shown below, complete the following timing diagram by entering the values for signals s1 and s2 that would generate the listed output waveforms. Assume that propagation delays are negligible. Be sure to completely annotate this problem.

2)

3)

4)

Use the listed circuit to fill signal F in the following timing diagram.

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5)

Use the following circuit to complete the listed timing diagram.

6)

Use the following circuit to complete the listed timing diagram.

7)

Compress the K-map on the left for variable B.

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8)

Compress variable B and draw the corresponding Karnaugh map for the following function:

F(A, B, C) = ∑ (1,2,4,5) .

9)

Draw a circuit that implements the following function using only NAND gates and inverters.

10)

Write a reduced equation in NAND/NAND form for the following circuit.

11)

Implement the following circuit (draw the circuit) in reduced form using only NAND gates.

F (A, B, C, D) = ∑ (1,4,5,10,11,14,15)

12)

The following timing diagram completely defines a function F(A,B,C) that has been implemented on an 8:1 MUX. The control variables are A, B, and C (A is the most significant bit and C is the least significant bit) and the output is F. Write an expression for this function in reduced NAND/NAND form. Assume propagation delays are negligible.

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8. C. and C. Compress of each of the four variables for each K-map. and C.8.2. D) = d) F = (A.6.5.11.6.B.2.15) 300 . B.2. Feel free to use the empty K-maps listed below.15) 15) Compress the K-maps represented by each of the following four functions. a) F = (A.4. B.C.7) c) F = (A. B. D) = ∑ (0.2. B.C. 14) Generate a compressed K-map for the following function (compress for variable B): F(A. D) = ∑ (0.5.B.Digital McLogic Design Chapter 11 13) The diagram on the lefts shows an implementation of a function F1(A. C. C.6.5) ∏ (0. C) = b) F = (A.9. B. B.9.15) ∏ (5.D) on an 8:1 MUX using control variables of A.10.12.8.3.1. B.D) on the right MUX using control variables A. C) = ∑ (1. Re-implement the F1(A.

c) BCD.11. b) ACD.5. C.10.7. B.Digital McLogic Design Chapter 11 16) Implement F(A.4.3. D) = of: ∑ (1. 301 . d) ABD.12.15) on a 8:1 MUX with control variables a) ABC.

1. add one to it in order to make it even. the output will be even. 2) 3) 4) F 0( A. For this design. This circuit has three inputs: 1) an 8-bit number A that will be operated one.4. The output of this circuit should always be an 8-bit unsigned number. the output will be odd). provide both gate-level and VHDL models.7) F1( A. if the 8-bit input number is odd parity. For this problem. if ODD = 1. If the number is already even parity. HINT: implement the functions with a nonstandard decoder. and 3) a control input ODD that directs whether the circuit output will be either an odd or even number. use one standard decoder and one non-standard decoder. If the two input numbers are equal. Design an even parity generator circuit. B. the circuit passes the 8-bit input to the 8-bit output. Design this circuit on the block level only. otherwise. If the EN input is 0. For this circuit. otherwise. the circuit output will either be even or odd number based on the ODD input (if ODD = ‘0’. F0 is provided as a circuit output. The functions output by this circuit are listed below.4. Design a circuit that outputs one of two functions based on the value of two 8-bit input numbers. Design this circuit on the block level but provided some VHDL code that describes the logic used to toggle the bit in question. Design an even-number or odd-number generator circuit. 2) an enable input EN that directs the action of the circuit. Don’t worry about overflow in the adder portion of this circuit.Digital McLogic Design Chapter 11 Chapter Design Problems 1) Design an even-number generator circuit. The output of this circuit is an 8-bit number. you’ll probably need to design some special logic blocks. do nothing.5. For this circuit. F1 is provided as a circuit output. B. C ) = ∑ (0. If the EN is ‘1’. For this logic. the input number is not altered before being sent to the output. C ) = ∏ (2.6) 302 . make it even parity by toggling the lowest order input bit in the 8-bit number that is set to a ‘1’. if the 8-bit input number (unsigned binary) is an odd number.

Digital McLogic Design Chapter 11 303 .

304 .Digital McLogic Design Chapter 12 12 Chapter 12 12. Although mixed logic is a topic present in just about any digital logic circuit. While it is true you can a long way by only pretending you understand mixed logic. I think I’m making headway into understanding mixed logic. This introduction includes a description of the underlying theory which is later applied in both circuit design and analysis problems. you’ll eventually run into it and be really bummed that you don’t really understand it. you generally only deal with mixed logic if you really need to and expend a significant amount of effort attempting to avoid dealing with it. This is particularly a problem when you’re seeing the material for the first time as is the case with beginning digital design students. Your knowledge and experience with digital design is such that you can certainly digest this material now. But the chapter verbage has not thus far presented the entire story regarding the ins and outs of digital logic design. The comment was: “nobody really understands mixed logic”1. although the stuff is strange. What I’ve come to realize is that the reason that “nobody understands” this stuff is two-fold. it’s a topic that is not overly used in modern digital design. (Bryan Mealy 2011 ©) 12. Martin Kaliski. we’ve covered a lot of digital design topics. In reality. you generally build up a repertoire of techniques to deal with it when you run into it.2 Mixed Logic The one thing that stands out most in my mind regarding mixed logic was a comment one of my teachers made to me when I was taking digital design. Although it has been a struggle for me. These techniques are generally good enough because you rarely run into mixed logic in any great depth. spoken sometime in the haze of the late 1980’s. Secondly. It’s highly unlikely that any system you work with will only use one type of logic. This chapter aims to provide what could be considered the final piece of the basic logic puzzle as well as another great piece of the digital story. Main Chapter Topics MIXED LOGIC: This chapter provides an in-depth summary of mixed logic digital design. More likely than not. so you really need to be able to face the dilemma of designing digital circuits in a mixed logic environment. 1 Dr. First. you need to have a complete understanding of digital logic. During the previous several chapters. but odds are that you’ll eventually run into it. you’ll act like most digital designers and find yourself hoping that you can avoid dealing with mixed logic in all of your digital circuit designs. it’s becoming more and more doable each time I look at it. My latest spin on the topic is that. I’ve never run into a text that explains the topic in a manner that I could understand.1 Chapter Overview If you truly want to be a digital design goddess or god.

• Mixed logic: a term referring to the use of both negative and positive logic in a digital circuit or system. In yet other words. and not voltage levels. Thus. A signal in a digital circuit is either at a high or low voltage level2. The entire strangeness that encircles mixed logic is that fact that sometimes ‘1’ does not represent the active state. when the circuit inputs represented a combination that we were looking for. • Assertation levels: assertation levels are an indirect reference to the form of logic used in a circuit. We’re presenting these definitions here so that we can use them throughout this chapter. These definitions lead to a common digital vernacular in referring to a signal as being “asserted” or “not asserted” (defined below). digital logic gates are really dumb. In other words. You’ll for sure want to refer back to them as you read on in this section. this is a really important distinction. The choice is up to you. the ‘1’ or the high state.Digital McLogic Design Chapter 12 12. digital circuits are really dumb: the gates in a digital circuit can be modeled as doing nothing more interesting than having outputs that react to the gate inputs. you’re faced with not just coming up with a digital design. your faced with coming up with a mixed logic design. You need to be able to both understand and handle both of these cases.2. The same argument can be said for the outputs of your circuit: sometimes the outputs of your circuit must be used to drive a circuit that is interpreting the 1’s in 0’s different from your design.1 Mixed Logic Basics The underlying theme of all digital logic deals with how a signal is interpreted. We’ve been modeling these high and low voltage levels thus far with a ‘1’ or a ‘0’. The concepts that were mentioned in the previous paragraphs can be summed up with a few short definitions. This signal is generally the output of one gate or device in the circuit. they only react to voltage levels. this signal is generally the input to another device in the digital circuit. sometimes you need to design your circuit to interface with another circuit that is interpreting the 1’s in 0’s in a different manner than your circuit does. • Negative logic: negative logic is when the ‘0’ state of signal represents the active state. it’s suffice to leave it at high and low voltage. It’s your mission as a digital designer to ensure that your circuits are reacting in a way that lands you a promotion after your company has finished its next design. • Positive logic: positive logic is when the ‘1’ state of a signal represents the active state. Remember. While you have a choice of designing your circuits anyway you want (with either ‘1’ or ‘0’ being the active state). Sometimes the ‘0’ state is the active state and ‘1’ represents the inactive state. was generally taken to mean something affirmative or positive. The terminology is quite common out in digital-land so being familiar with them is considered a good thing: a real good thing. 2 305 . Your digital circuit designs are based on logic levels. • Asserted high: Another way of referring to a positive logic signal • Asserted low: Another way of referring to a negative logic signal • Logic levels: same thing as assertation levels Note that we stay general here by not mentioning the exact voltage levels. Here’s the whole story in a few sentences: the way we’ve been modeling our circuits so far is that a ‘1’ represented the action state or active state of things while ‘0’ represented the non-action state or inactive state. In truth. we assigned a ‘1’ to the output.

A positive logic signal is not-asserted when it is low while a negative logic signal not asserted when it is high.1 look similar. • Not-asserted signal: a signal that is currently in its non-active state (independent of logic levels). An example of a similar circuit that uses mixed logic is shown in Figure 12. they can represent either 1’s or 0’s. we need to model it in a different form in order to gives us a foundation for understanding mixed logic. These two forms of notation are used to indicate that we’re longer thinking of the inverter as a device that toggles a signal value. The first thing we need to do here is to convince you that the circuits you’ve been working with thus far have all been positive logic circuits. Figure 12. and F. they perform different logic functions. note that in this circuit that two of the inputs contain overbars. For example. Since these variables are Boolean variables. What you may not realize is that by the way the circuit is shown in Figure 12. (a) (b) Figure 12. a ‘1’ appearing on the circuit inputs and/or the circuit output indicates an active state.1: Some generic circuits just for the heck of it.1(b). In other words. Assuming there is a good place to start in mixed-logic land.1(a) contains three input variables and one output variable. The PLC uses overbars on signals to indicate that they are negative logic (with positive logic being represented by not having an overbar). The circuit shown in Figure 12. This indicates that while signal A is a positive logic signal. What exact logic functions they perform is what we’ll try and figure out in the remainder of this section. some positive condition is indicated by the circuit (vice versa for a ‘0’ appearing on the circuit outputs). The question that should arise is how exactly is negative and positive logic represented in a circuit? There are actually two ways: the Positive Logic Convention (PLC) and Direct Polarity Indicators (DPI).2 shows our new approach to modeling an inverter.Digital McLogic Design Chapter 12 • Asserted signal: a signal that is currently in its active state (independent of the logic levels). The new view of an inverter is to 306 . When a ‘1’ appears on the output of the circuit. A positive logic signal is asserted when it is in a high state while a negative logic signal is asserted with it is in a low state. the inputs to the circuit and the output of the circuit are all positive logic. Mixed logic once again refers to the fact that sometimes a ‘1’ and a ‘0’ have different meanings. The approach we’ve taken to inverters up to this point is to think of them as devices that change 1’s to 0’s and 0’s to 1’s. For this discussion we’ll only be dealing with DPI since it is easier to deal with in the learning phase of mixed logic. The thing that is somewhat new about this diagram is the PLC and DPI indicators provided above and below the signals. respectively. taking another look at the inverter would be that place.1(a) looks like a typical circuit you’ve been working with for awhile now. signals B and C are negative logic signals. C. Since none of these variables have overbars on them (and they don’t have direct polarity indicator either) then they are interpreted as being positive logic.1(a). although the two circuits shown in Figure 12. Figure 12. the circuit in Figure 12. The important point here is that all the signals listed in both of these diagrams are represented using Boolean variables: A. The reality is that you’ve been dealing with PLC ever since your introduction to digital logic. B. The confusing aspect of mixed logic design lies in the fact that the logic gates only react to voltage levels and know nothing of the logic levels intended by the circuit designers. And in the end. While this model of an inverter is absolutely valid.2(a) shows an inverter drawn as you’re used to seeing it.

Figure 12.3(b)). What we’re trying to do here is present some tools to effectively deal with the more complex mixed logic circuits that arise later.2: A different approach to modeling an inverter. But let’s reanalyze it using our budding love of mixed logic. the logic expression AB is implemented. you may want to read them again or have some friends read them to you as you contemplate the vastness of the concept. the direct polarity indicator changes to L (indicating negative logic). In reality. Once you understand the DPI convention. You’ve drawn bunches of circuit diagrams already and many of them used inverters. both inputs and the single output are positive logic signals. The inverter changes the logic level of the B signal before it enters the AND gate. Once it passes through the inverter. the output of the inverter is a negative logic signal. we’ll only discuss the DPI convention due to the fact that the polarity indicators are somewhat easier to working with when you’re first struggling with these concepts.2(a) is used to indicate this notion. as you’re used to thinking about it.Digital McLogic Design Chapter 12 consider the inverter a device that changes the logic level. The same model can be expressed with the DPI notation which is listed under the signal in Figure 12.4 has an output that only becomes a ‘1’ when both inputs are ‘1’. The intentions here are good even though it all may seem strange at this point. In other words. the AND gate used in Figure 12. the A with out the overbar indicates the signal is positive logic. the A signal is clearly indicated with a directly polarity indicator of H (indicating positive logic) on the input of the inverter. These are important points. The notation included in Figure 12.3 shows the terminology we need to work with.4(a) is therefore nothing new. Figure 12.2(a). A two-input AND gate with an inverter sitting in front of one of the inputs as is shown in Figure 12. (a) (b) Figure 12. That was not too painful. but they become worth dying for later. Note that we suddenly magically switched to PLC notation which is what you’re used to dealing with. if the input to an inverter is a positive logic signal.3 are saying is that there is more than one way to represent both negative and positive logic using the DPI convention. was it? Now we need to pass a slight amount of terminology by you. the A has an overbar which indicates it is then a negative logic signal. A( H ) = A( L) A( L) = A( H ) (a) (b) Figure 12. The equations of Figure 12. What the equations in Figure 12.3(a)) and a negative logic signal can be equivalently written as a positive logic signal (Figure 12. For the sake of this discussion. On the output of the inverter. Now let’s apply these concepts in a manner that you’ve already seen. We’ve attached a DPI convention to the inputs and outputs of this device. In other words.3 are referred to as equivalent forms of the signals. The question that arises is this: what is the relation between the product term AB and having both inputs being a ‘1’ in order for 307 . a positive logic signal can be equivalently written as a negative logic signal (Figure 12. In the end.4 shows a simple circuit implementing a product term. With the PLC convention (the notation above the signal lines). These probably don’t seem to useful now. using either DPI or PLC (or both) is not a problem.3: Equivalent signals relating to inversion. With the DPI notation.

OR. OK… we’ve driven the inverter analysis into the ground. As you can see from the equations shown on the left. And to sum this all up in one statement. an inverter is not really a logic gate. Figure 12. ‘0’ will then be the active level of the signal. The solution here is to change the logic level of the B signal. the gate on the left is the AND form of an AND gate. We’ve also implemented designs on the block diagram level but we won’t be dealing with that in this section. you’ll be on your way to understanding mixed logic. the signal is active low. Since there are no bubbles on the back of the gate (you’ll see some bubbles in next gate described). the output of the gate is asserted when the both the A and B inputs are asserted. The problem is that B is listed as a positive logic signal. this is a device that provides an AND function with a positive logic output. 3 In reality. 308 . we’ll be generating some alternative forms of these gates. Using a strange mixture of mixed logic concepts and Boolean algebra. This means that we need to have A be positive logic and B to be negative logic as they are input to the AND gate. Once the logic level of B is changed from the original positive logic to negative logic. We’ll be using these alternative forms later in our foray into mixed logic concepts. NOR gates and inverters3. The theme of the following circuits is to take what we know about the gates we know and start to look at them differently and particularly in the concept of mixed logic. the AND gate performs an AND function on the two positive logic inputs. F = A⋅ B F ( H ) = A( H ) ⋅ B( H ) Figure 12.Digital McLogic Design Chapter 12 the output to be a ‘1’? What we need to do in this product term is have the output be a ‘1’ when both inputs are in their active state. It just so happens that the B input is asserted low as it enters the AND gate because its logic level was changed by the inverter in the circuit. NAND. What you see now is an AND gate. Until now we’ve implemented our gatelevel designs using primarily AND. this AND gate expects positive logic inputs. or to put in our new terminology. Remember those bubbles on the outputs of the NAND and NOR gates (and inverters too)? They’re actually significantly important and if you understand their actual purpose.3. This is all good and fine but now we want to re-examine it from another angle.4(b) shows the logic levels of the signal after it passes through the inverter written in with equivalent forms as presented in Figure 12. OR. NOR).5: A mixed logic view of an AND gate. The simplest approach to understanding mixed logic is to examine the most basic form of logic: the logic implemented with the basic gates used in digital design.4: A mixed logic approach to analyzing familiar functions. You’ve grown to love this gate as a device that has a high output when both of its inputs are high. This will make more sense as we take a look at the next gate. And to be consistent with the following diagrams. but it’s a cool and useful device anyway. This is the ever-so friendly AND gate. The simplest digital device is the inverter which is why we started the discussion there. (a) (b) Figure 12. NAND. The following figures describe mixed logic concepts at the gate level. now let’s go back and look at the logic gates we’ve dealt with up to this point: (AND.

The bottom two equations on the left are used to generate this distinctive symbol. it performs an OR function on those inputs and generates a negative logic output. once you do this.7: A mixed logic view of an OR gate. this OR gate expects positive logic inputs. the equations are written in both PLC and DPI forms. these equations are listed in PLC and DPI forms. The negative logic inputs (as indicated by the (L) polarity indicators) and negative logic output of the final equation on the left is indicate with the bubbles in the resulting gate. F = A+ B F ( H ) = A( H ) + B( H ) This is the ever-so familiar OR gate. This gate is officially know as the OR form of a AND gate. 309 . In summary.6: A different mixed logic view of an AND gate. doesn’t it? Here’s the truth: if you feed this gate two negative logic input. You may want to read that again. the gate on the left is the OR form of an OR gate. this gate delivers a positive logic output. Figure 12. In other words. This is shown in the equations on the left. This gate provides a high output when either of the gates two inputs is at a high state. The reality here is that you can use an AND gate to perform an OR function. you can alter the form of the gate based on the equations you derived. it performs an OR function and generate a positive logic output. Another way of looking at this gate is if you provide it with positive logic inputs. Since there are no bubbles on the back of the gate. Figure 12. this is an AND gates that performs an OR function. Why is it an AND gate? Because you can use DeMorgan’s theorem to generate a different equation describing the gate. The key to understanding this gate is to interpret both the bubbles and the gate form.Digital McLogic Design Chapter 12 F = A⋅ B F = A⋅ B F = A+ B F ( L) = A( L) + B( L) The gate shown on the left is also an AND gate. Since there is not a bubble on the gate outputs. It sort of looks like an OR gate. The new form of this gates is derived from double complementing the equation describing an AND function and DeMorganizing the resulting equation.

we can derive this from applications of Boolean algebra axioms and DeMorgan’s theorems. The final two equations on the left describe this gate in the context of mixed logic: this gate performs an OR function on its two negative logic inputs and returns a positive logic output. Figure 12. This gate is officially known as the AND form of a NAND gate. In a mixed logic sense.8: A different mixed logic view of OR gate. The negative logic inputs (as indicated by the (L) F = A⋅ B polarity indicators) and negative logic output of the final equation is indicate with the bubbles in the resulting gate. these equations are listed in F = A+ B PLC and DPI forms. The logic level of this gate’s inputs and output is shown with the polarity indicators in the final equation on the left. The inputs are considered positive logic due to the absence of bubbles on the inputs. you F ( L) = A( L) ⋅ B( L) can use an OR gate to perform an AND function (as the equations show). You may have come to know this gate as a AND gate with an inverted output. F = A⋅ B F ( L) = A( H ) ⋅ B( H ) The gate shown on the left is a NAND gate. This gate is officially known as the OR form of a NAND gate. The new form of this gate is derived from double complementing the equation describing the OR function and DeMorganizing the resulting equation. 310 . The key to understanding this gate is to interpret both the bubbles and the gate form. The fact that an OR function will be performed is listed by the distinctive OR symbol. Figure 12. F = A⋅ B F = A +B F ( H ) = A( L) + B ( L) The gate shown on the left is also a NAND gate. this gate performs an AND function on its positive logic inputs and returns a negative logic output.10: Yet another mixed logic view of an NAND gate. the positive logic output is indicated by the absence of a bubble on the output. Figure 12. This gate is officially know as the AND form of an OR gate. it performs an AND function on those inputs and generates a negative logic output. this gate only performs an OR function if the two input values are provided in negative logic format. this gate performs an OR function on its negative logic inputs and returns a positive logic result. The bottom two equations are used to generate this distinctive symbol. Once again. The negative logic input format is indicated by the presence of bubbles on the inputs. this is an OR gate that performs an AND function. Note that if we apply DeMorgan’s theorem to the gate we can arrive at a slightly different looking equation describing the gate. this definition is not too far from a mixed logic view of this gate.Digital McLogic Design Chapter 12 The gate shown on the left is also an OR gate. It sort of looks like an AND gate F = A+ B but the reality is this: if you feed this gate two negative logic inputs. One way to look at this circuit is that the output of ‘0’ is now the active state rather than the ‘1’ output that is the active state from a normal AND gate. Not surprisingly. the output is considered a negative logic output since there is a bubble on the output. this gate performs an AND function on the two positive logic inputs and provides a negative logic output. In other words.9: A mixed logic view of an NAND gate.

This gate is officially known as the OR form of a NOR gates. In reality. It sort of seems like we were doing OK with the few gates forms we knew about before breeching the topic of mixed logic. Since the output contains no bubble. you will have nothing to fear. Another way of looking at this gate is directed by the bubble placement: since there are bubbles on the inputs. there are still only AND and OR functions out there. In other words. we need a certain amount of flexibility in implementing logic functions. this gates actually performs an OR function on its two positive logic inputs and outputs a negative logic result. If you understand the basics of mixed logic. the result of the AND operation is delivered in positive logic. Figure 12. In a mixed logic context. if two positive logic signals are provided to this gate.13 shows a summary of all the standard gates forms. the gate performs an OR function and returns a negative logic result. Figure 12. 311 .Digital McLogic Design Chapter 12 F = A+ B F ( L) = A( H ) + B ( H ) The gate shown on the left is a NOR gate. this gate performs an AND function if it is provided with negative logic input and subsequently provides a positive logic output. this gate only performs the advertised AND operation if the two inputs are negative logic. To state this magic directly: this gate performs an AND operation (note the AND symbol being used here) if two negative logic signals are provided as inputs. the gate performs an OR function with an asserted low result. From here we’ll do some examples to solidify these concepts.11: A mixed logic view of an AND gate. the gate’s output is considered a positive logic output due to the presence of the bubble on the output. The relatively large set of gates guarantees that we’ll be able to accurately display the actual logic functions we’re performing in a mixed logic environment. This gate’s attributes are nicely described in equation form on the left. you may have a working circuit but no one will know what the heck you’re really doing4. The final two equations on the left describe the operation of this gate in the magical world of mixed logic. F = A+ B F = A⋅ B F ( H ) = A( L) ⋅ B( L) The gate shown on the left is also a NOR gate. Figure 12. In other words. we need to draw our circuits such that they express whether we are performing an AND function or an OR function. At this point you may be wondering why there are some many different forms of gates out there. The reason we have so many different and sometimes equivalent gates is that we need to always choose the gate that most appropriately represents the actual logic function we are performing. This gate is officially known as the AND form of the NOR gate. Then again. Note that we can apply DeMorgan’s theorem to the equation describing the NOR gates and arrive at a new and even more wonderful equation. the output of the gate is a positive logic signal. Note that the inputs are considered positive logic due to the absence of bubbles on the inputs. 4 It’s well known that such mystery designs establish job security of sorts for the circuit designer. You probably are used to thinking of this gate as an OR gate with an inverted output. this becomes even more tricky in a mixed logic environment.12: A mixed logic view of an AND gate. We’ve done OK up to now but there are some situations where a mixed logic approach can’t be avoided. The short answer to this question is that in some situations. if you don’t use the proper gate in your design. In yet other words.

if you were to input a B(L) signal to the AND gate. The solution to this dilemma is to use an equivalent signal representation for the B(L) signal. passes through an inverter before entering the AND gate. the logic level of the output is indicated with the direct polarity indicator. the AND gate is still expecting a positive logic input. 312 .14(b)). the output logic level is considered to be positive logic. For this example. Although the inverter changes the logic level from positive to negative. take a look at Figure 12. The first thing you should note is that the both inputs in this circuit are positive logic. however.14(a). If they did not match. The case where the output is positive logic is shown in Figure 12. This gate is an AND gate and performs an AND function on the two inputs if they are both provided as positive logic (note the absence of bubbles on the gate inputs). The important thing to note here is that the polarity indicator on the output of the gates matches what the gate states it is providing: since there is no bubble on the gate. The next step is to write the inputs such that each of the input signals is listed in a positive logic form.14(b). Once both inputs are written in positive logic form. Since the logic level of the output is not listed. it would not look correct would lead to mass confusion and hysteria. For an example in mixed logic analysis. The important thing to note about this equation is that the polarity indicators on both sides of the equation match. The B signal. The second thing you should notice is that the logic level of the output is not listed. we’ll examine both cases. We can officially list this signal as a positive logic signal by listing the signal name in complemented form.14. The A input is in correct form already because it is a positive logic signal. you are asked to analyze the circuit shown in Figure 12.Digital McLogic Design Chapter 12 Standard Gate Forms AND functions OR functions AND form of AND gate OR form of OR gate OR form of AND gate AND form of OR gate AND form of NAND gate OR form of NOR gate AND form of NOR gate OR form of NAND gate Figure 12. the equation would make no sense. In other words. For this example. we can write the down the resulting equation (shown under the circuit in Figure 12.13: The giant summary of the strange new gate forms. you can assume it to be either negative or positive logic.

the output of the gate is rewritten to show that it is negative logic. we do not need to perform any modifications. one input both positive and negative logic.15(a) has two inputs.14(c) shows the resulting equation below the circuit diagram. The equivalent signal names contains a polarity indicator that indicates the gate receives a negative logic signal as requested. when we replace it with an equivalent gate.14(c). respectively.14(c). The new gate form is going to perform an OR function when both of the two gate inputs are provided in negative logic. This requires that we rewrite the input logic levels in forms that reflect the negative logic levels.Digital McLogic Design Chapter 12 F ( H ) = ( A ⋅ B )( H ) F ( L) = ( A + B)( L) (a) (b) (c) Figure 12. F ( L) = ( A + B)( L) (a) F ( H ) = ( A ⋅ B)( H ) (c) (b) Figure 12. Since the output level of the device is not stated. The inputs to the new gate form need some modification also. the approach we’ll take is to rewrite the signal with an equivalent signal name as shown in Figure 12. The B input is provided in positive logic and the inverter changes it to negative logic. The circuit in Figure 12. Figure 12.15 shows another example of mixed logic analysis. The circuit shown in Figure 12. we want to know what logic function is being executed if the output is interpreted as negative logic. Since the A input is provided in negative logic. respectively. now let’s re-analyze this circuit as having a negative logic output.15: An example of mixed logic analysis. let’s analyze this problem assuming the output logic level is asserted high and asserted low. we are officially not changing the circuit in any way. Note that once the gate is replaced and the bubble appears on the output. for this input.14: An example of mixed logic analysis where (a) shows the original circuit and (b) and (c) show positive and negative logic interpretations of the output. The first step in doing this is to redraw the gate such that there is a bubble on the output. the gate provides an OR function with an asserted low output under the conditions that the two inputs are provided in positive logic. Once again.15(b) assumes the output is asserted low which is the implication from the original drawing of the gate (because of the bubbled output of the gates). In this case. we 313 . In other words. there is a question of the output level of the circuit so this example will once again examine both cases of output logic levels. The A input is provided in positive logic but needs to be listed in negative logic as directed by the bubbled input to the gate. This example is slightly different in that the inputs are provided in a true mixed logic form: the A and B inputs are provided in negative and positive logic forms. Since there is no inverter on this input. The equivalent gate form for an AND gate is the OR form of an AND as shown in Figure 12. Figure 12. OK. We need to replace the original AND gate with an equivalent gate.

But have no fear. It would be evil confusion. Note that in both of the two previous examples we were given the choice of how to interpret the output of the circuit. the equation would not make sense. we were able to consider the function as implementing two different functions. we did not carry around the polarity indicators for the internal signals. Here are a few key things to notice about this form of analysis. This is true but the two final equations for these circuits were based on our interpretation of the circuit’s output. In other words. Although we only had one circuit. the gates was providing a negative logic signal. the equivalent gate is the AND form of a NOR gate as shown in Figure 12. this is done by using an equivalent signal for the A input. Figure 12. In this case.16 shows a slightly more complicated example. Once the two inputs to the circuit are listed in negative logic forms. The B input is provided in positive logic but has its logic level changed to negative logic by the inverter. we do this by using an equivalent gate form for the NOR gate as listed in Figure 12. if there was a bubble on the output of the gate. the inputs to the gate are satisfied and the equation for the circuit can be written (shown under the circuit in Figure 12. The analysis of the circuit entailed using equivalent gates and equivalent signals in order to easily discern what logic function was being performed by the gate. depending on how we interpreted the logic level of the circuit output. • The output logic level always matched the gate output level. Once the two inputs are both written in positive logic forms. we can write the equation performed by the gate. The A input requires no modification since it already is in a negative logic format. 314 . the gate was providing a positive logic signal. we seemed to have generated two equations from it. The reality is that the two equations have sort of a complementary relationship (think DeMorgan’s theorem). • • • Figure 12. If there was not bubble on the gate output. Once again. The B input is originally in positive logic format but the logic level is changed to negative logic by the inverter.15(c). the polarity indicators matched. In the final equation. we rewrite the negative logic signal for B in positive logic form using equivalent signals.15(a). If they did not match. But what if the output was actually a positive logic output? We first need to represent that condition with a gate that has no bubble on the output. the analysis approach is exactly the same as the simple gate: match the logic levels to the gate inputs and outputs using equivalent gates and equivalent signals. This gate performs an AND function with a positive logic output if the two inputs are provided in a negative logic format. it would not really be an equation. The assumption being made here is that we matched all the interior logic levels so there is not need to include them in the final equation.Digital McLogic Design Chapter 12 must re-write it in positive logic form in order for us to know what logic function the gate is performing. The polarity indicators were only used in the final equation for the output.15(b)). In other words.16: A slightly more complicated mixed logic example.

all other inputs are positive logic. C . D ) = AC D +B D . The best approach to problems such as these is to start at the output and work backwards. An example design problem is provided below. the F output can be represented as F(L). draw a bubble and label it in such a way as it support the original problem description. Up to now.Digital McLogic Design Chapter 12 F ( L) = [( A + B) ⋅ (C + D)]( L) (a) F ( H ) = ( AB +CD)( H ) (b) Figure 12. Example 12-1 Design a circuit that implements the following function: F ( A. B(L). Since this example does not specify which type of gates to use. 315 . Step 1: Draw and label the output. The negative logic signals can be represented by A(L). Since we know the output is asserted low. Implement this function with any type of gate. Solution: The first thing to do with this solution is to clearly write down all the parameters in DPI form.17: The total mixed logic analysis approach. In this example. For this problem consider the A and B inputs and the output to be asserted low. the required logic function is an OR function so we draw a gate that looks something like an OR gate. The two positive logic signals are represented by C(H) and D(H). we have been analyzing mixed logic circuit. B. The step by step approach is shown below. Step 2: Draw a gate such that it satisfies the logic function requested by the equation given in the problem description. we’ll use a NOR gate which provides an OR function with a negative logic output. Let’s switch to the opposite approach and design some circuit based on mixed logic.

Recall that A and B are provided in negative logic form while C and D were positive logic. but this time restrict our gate usage to NOR gates and inverters. What makes an AND gate appropriate is that the input to the OR gate used is expecting positive logic inputs (note the absence of bubbles on the input). we’ve included the input signals with the logic levels as stated in the input problem. 316 . Since there was no restriction on the types of gates used in this problem. all of the inputs have been listed in positive logic form. it is usually the case were functions are implemented using only one type of gate. We’ve written in the logic that the AND gates are expecting based on the original equation provided by the problem. As you’ll see in the section on circuit forms. an inverter is required in order to switch the logic levels. Let’s redo this problem. Step 6: From the previous step. Note that since the AND gates are expecting positive logic inputs. The AND gates provide an AND function with positive logic outputs. they are drawn to make reference between what each AND gates needs relative to the original equation and the logic levels of the inputs from the outside world. Note that in some cases we have switched the logic levels directly and in other cases we have rewritten the signals using equivalent signal forms. One of the key elements in the previous problem is that we had the luxury of using any type of gate we could in the implementation. The final word is that the bubbles (or lack there of in this case) match and every thing is happy up to now. For this problem the product terms can be implemented with some form of AND gates. choosing an AND form of an AND gate is sufficient.Digital McLogic Design Chapter 12 Step 3: The other part of the equation includes two product terms. Step 5: In this step. For these cases. Step 4: We’re now ready to assign some logic for the inputs to the AND gates. The dotted lines mean nothing in particular. you can see that some of the input signals are not in the correct logic form as required by the AND gates.

One of the good things about the second solution is that it uses fewer devices than the first solution. One of the distant morals of this story is that you can tweak the gates around and end up with many different equivalent solutions but 317 .Digital McLogic Design Chapter 12 Example 12-2 Design a circuit that implement the following function: F ( A. The signal requirements as they relate to the original problem are shown. The input requirements of the signal we’re implementing are listed on the inputs of the NOR gates. all other inputs are positive logic. The difference in this problem is that we need to choose NOR gates for the input gates rather than the AND gates of the previous problem. D ) = AC D +B D . we can choose the AND form of an NOR gate. For this problem consider the A and B inputs and the output to be asserted low. This gate performs an AND function if the inputs are provided in a negative logic format. B. Although we essentially did the same problem twice. Implement this function using only NOR gates and inverters. Step 6: The last step is matching the logic levels of the provided signals to those of the require function. We need to make sure that we align the provided signals and their logic levels to the function we’re implementing. Lucky for us. C . we jump in at Step 4 because the first three steps are the same as the previous problem. Note that all of the polarity indicators on the signals have been listed as L as required by the gate inputs. Solution: We’ll take a few short cuts in this problem since we already choose a NOR gate for the output stage of this circuit in the previous problem. The key here is that we need to choose a NOR gate that performs an AND function. There is something really important to note in these previous two examples. Step 4: For this problem. Step 5: This step is mostly a bookkeeping step. we ended up with two different solutions.

Digital McLogic Design Chapter 12 some of the solutions can be implemented at a lower cost than others5. This is sort of cool. 5 It another version of the minimum cost concept idea as previously discussed 318 . Well. at least some people think it’s cool.

the design is considered to be positive logic while if the ‘0’ is the action state. If a ‘1’ is considered the action state. either the ‘1’ or ‘0’ state is considered to be the action state if a digital signal. then the design is considered to be negative logic. A mixed logic system is a digital system that uses both negative a positive logic in the design. Most gate-level circuits deal with mixed-logic concepts at some level. In all cases.Digital McLogic Design Chapter 12 Chapter Summary • The concept of mixed logic is based upon the “action” state of a digital signal. having a basic understanding of the mixed logic is generally enough for survival in digital design land. • • 319 . Although mixed logic concepts are often initially confusing the digital designers. Logic levels in digital circuits are represented by either the Positive Logic Convention (PLC) or Direct Polarity Indicators.

Digital McLogic Design Chapter 12 Design Examples Example 12-3: Generic Switch Controller Design a circuit that controls an unspecified output according to the following description. Since we’re more used to dealing with positive logic.18: Truth table for design example. SW1 and SW2 are active high. If both the override switches are not asserted. The problem with this problem is that we need to deal with mixed logic. Although there are many approaches to dealing with mixed logic. Figure 12. Specify the solution using POS form. the output is always asserted. 320 . the approach we’ll take here is somewhat more straightforward than other approaches. We’ll not have to do anything with the inputs at that point since the inputs still reflect the order (but not the numbering) required to use a truth table. the output is also asserted. Otherwise if the LOCAL_OVERRIDE switch is asserted. consider the output to be active low. let’s convert the negative logic signals to positive logic before we assign the output values. we’ll complement it before we generate the subsequent logic. We’ll also convert the negative logic out to positive logic. Once we’ve specified the output. Solution: This problem is similar to other switch problems you’ve done but with the twist added of working with both negative and positive logic.18 shows the empty truth table. you can take the truth table approach to designing this problem. The two override switches are active low also. Since there are not too many inputs. For this problem. the output is only asserted when SW1 and SW2 are both asserted. MO 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LO 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F Figure 12. If the MASTER_OVERRIDE switch is asserted.

321 .20: The final equation for this problem.19: The modified truth tables with negative and positive logic outputs. you’ll arrive at the POS equation shown in Figure 12. Once you toss the column for F into a truth table. F = ( MO ⋅ LO)( S1 + S 2) Figure 12. The final logic we’re looking for is specified in Figure 12.Digital McLogic Design Chapter 12 !MO 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 !LO 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 !F 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 !MO 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 !LO 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 (a) (b) Figure 12.19(b).20.

C(H). 13) 14) Write an equation for F(L) that describes the following circuit using DPI. E(L). D(H). B(L). Consider the inputs to be: A(L). F(L). Consider the inputs to be: A(H). B(L). 12) Implement the following equation using any type of gate and inverters. use only standard gates and inverters in your solution. D(L).Digital McLogic Design Chapter 12 Chapter Exercises 11) Write an equation for F(H) that describes the following circuit. Consider the inputs and outputs to be: A(H). use only standard gates and inverters in your solution. 16) 322 . D(L). C(H). B(L). Write an equation for F(W. 15) Draw a circuit that implements the following function: F(L) = ( A BD + BC)(L) . C(L). Minimize the device count in your implementation. Put your answer in DPI form. F(L) = [( A + B + C)( D + E)](L) .X.Z) in NAND/NAND form. Draw a circuit that implements the following function: F(H) = [(A + B + D)(A + C)](H) .Y.

Consider the inputs and outputs to be: A(L). 18) Using only NAND gates and inverters. draw a circuit that implements F(H) = (AB + BCD)(H) . Minimize device count where possible. F(L). Consider the inputs and outputs to be: A(L). C(L). 19) Without altering the function implemented by the circuit below. Minimize device count where possible. D(H). F(H). 20) Using only NOR gates and inverters. B(H). redraw the circuit using only OR gates and inverters. B(L).Digital McLogic Design Chapter 12 17) Without altering the function implemented by the circuit below. C(L). redraw the circuit using only NAND gates and inverters. 323 . draw a circuit that implements F(L) = ( AB + BCD)(L) . D(H).

Digital McLogic Design Chapter 12 Design Problems 1) A logic network is to be designed to implement a seat belt alarm that is required on all new cars. You are to design and draw schematics for a decoding system that will generate a low output voltage if and only if there are two (or more) adjacent vacant slots. provided that either of the front seats is occupied and the corresponding seat belt is not fastened. A switch is placed under each front seat and each will turn of if someone sits in the corresponding sear. the sensor’s output is at a high voltage. executive parking area. a switch is attached to each front seat which will turn on if and only if the seat below is fastened. Finally. Otherwise. A set of senor switches is available to supply the inputs to the network. Alarm (sound) .A(H) Ignition (on) – I(L) Gearshift (engages) – G(L) Left Front Seat (occupied) – LFS(H) Right Front Seat (occupied) – RFS(H) Left Seat Belt (fastened) – SBL(H) Right Seat Belt (fastened) – SBR(H) There are four parking slots in the Acme Inc. One switch will be turned on if the gear shift is engaged (not in neutral). 2) 324 . Each slot is equipped with a special sensor whose output is active low when a car is occupying the slot. An alarm buzzer is to sound (LED display light) when the ignition is turned on and the gear shift is engaged.

Digital McLogic Design Chapter 12 325 .

or combinational circuits. our digital circuit design exercises will become slightly more interesting than the other stuff3. MEMORY REPRESENTATION USING VHDL: This chapter introduces and concept of modeling storage elements in using VHDL.Digital McLogic Design Chapter 13 13 Chapter Thirteen 13. Main Chapter Topics SEQUENTIAL CIRCUITS: There are two types of digital circuits: combinatorial and sequential. These types of circuits could be easily modeled as having outputs that react directly to the circuit’s inputs. This chapter describes gate-level models of basic digital storage elements which are referred to as latches.1 Chapter Overview There are two major classes of digital circuits. 326 . Up to this point in your studies. Modeling memory in VHDL is a unique but a straight-forward process. (Bryan Mealy 2011 ©) 1 The term sequential used in the context of digital circuit should not be confused with sequential statements in the VHDL language: they are completely different concepts. While there are applications where you would use either a combinatorial or sequential circuit. you’ve been dealing with only one of these types: combinatorial. STATE REPRESENTATIONS: Circuits that have memory are be characterized by the “state” of the circuit. 2 And if you only remember one thing about digital design. Sequential circuits are primarily characterized by having the ability to store information. 3 This is not an admission that previous design exercises are not currently massively interesting. Our design exercises up to this point have been somewhat limited in scope due to the fact that we have been limited to using combinatorial circuits. All previous chapters have dealt only with combinatorial circuits. referred to as flip-flops. Hopefully after this point. The other major type of digital circuit is referred to as a sequential1 circuit2. SEQUENTIAL CIRCUIT REPRESENTATION: Basic digital storage elements can be represented in various ways. This chapter outlines the analysis and representations methods of basic sequential circuits. The state of the circuit is defined by the values stored in the circuit’s storage elements. these two digital circuit classifications should be it. the reality is that most digital circuit designs represent a combination of both types of circuits. FLIP-FLOPS: This circuit describes the three basic types of edge-sensitive latches.

the same input may cause a different change in the circuit outputs. Please take a look at these definitions before reading on. the difference between combinatorial and sequential circuits should be that thing. the outputs of a sequential circuit are based on the sequence of inputs to the circuit. 4 An example of this would be truth table where a change in one variable may be associated with cells in the truth table that contain the same output value. come back and reread it after you get the whole sequential story with all the gory details. We earlier claimed that Figure 13. it has been 100% correct: the outputs of our all the circuits that we’ve dealt with up to this point had circuit outputs that were direct functions of the circuit inputs. The name sequential gives a hint as to the major attribute of a sequential circuit in terms of the input/output relationship. the input/output relationship in sequential circuit is based on the sequence of inputs and not simply the inputs themselves as was the case with combinatorial circuits. we’ll be elaborating on these definitions in the upcoming sections.1 shows the true differences between sequential and combinatorial circuits. To put in the simplest of terms. The truth is that this is a common interview question and one that is easily asked by a Human Resource person doing the interview.1 provided a high-level model of all the circuits that we’d used in digital design. In other words. If you only remember one thing from this journey into digital design. this change in the circuit’s input would directly cause a change in the circuit’s output. 327 .Digital McLogic Design Chapter 13 13.2 Sequential vs. These are the high-level definitions of digital circuit types. an input change may cause a certain change in circuit outputs. In other words. Relative to a combinatorial circuit. Understanding the two basic circuit types in VHDL is extremely important and we’ll dedication a section in this chapter to the sequential circuits in VHDL. Figure 13. if one of the circuit’s inputs were to change. Before we modify this definition. Table 13. we’ll start filling in the details in the verbage that follows. this definition means that at one point in time. Please remember this table. A more accurate description of all the circuits we’ve worked with up until now (keeping in mind that they’re all combinatorial circuits) is that a change in the circuit’s input will always cause the same reaction (change or no change) in the circuit’s output.1: Digital Design in a nutshell The input/output relationship in a sequential circuit is not as simple as the input/output relationship in a combinatorial circuit. be aware that up until now. let’s look back at one of the first figures we used in this course. Combinatorial Circuit As an introduction to sequential circuits. The differences between the two types of circuits are distinct enough that someone who knows nothing about digital logic could still judge whether you know the difference between these circuit types. This is an important statement but it is not 100% correct because a change in the circuit’s input may not cause a change in the circuit’s outputs4. but at another point in time.

as you will see. We’ll therefore model the propagation delays with the box labeled td in Figure 13. it does contain one distinct difference: note that there is a connection between the output of the circuit and the input of the circuit. But since we also need to consider how the value of Q changes.3 Sequential Circuit: The Whole Story The best place to start examining a sequential circuit is by analyzing the seemingly simple circuit shown in Figure 13. we need to consider the circuit elements as non-ideal devices.1. The output that we’re interested in is Q as it is the true output of the circuit. to say the least. let’s instead lump the delays associated with the circuit elements into one delay. In other words. Figure 13.1: The main attributes of sequential and combinatorial circuits. The symbology Q+ is used to represent the new value of Q. In other words. huh?). 328 . considering them different signals allows up to successfully analyze the circuit5. In order for us to analyze this circuit.3 has essentially provided is a time delay between two of the circuit signals: Q+ and Q. The signal names of Q+ and Q are somewhat special signal names with somewhat special symbology.2 is a sequential circuit.3.Digital McLogic Design Chapter 13 Sequential Circuit Properties • • The circuit has some memory element The circuit has a feedback path from the memory element to the circuit inputs • • Combinatorial Circuit Properties The circuit outputs are strictly a function of the circuit inputs No feedback paths can exist from the circuit’s output to the circuit’s inputs Table 13. the Q output is fed back around and becomes a circuit input. we’ll need to consider both the value of Q and the S and R inputs. Even though Q+ and Q are essentially the same signal. After familiarizing yourself with Table 13. What the circuit model of Figure 13. the results of the analysis would be worthless. you should somewhat suspect that the circuit shown in Figure 13. it does have some interesting properties. 13. In order to simplify the analysis of this problem. While this circuit does not appear too different from other circuits we’ve been dealing with so far (two NOR gates? Big wup. we need some way to represent the new value of Q. if we were to ignore the propagation delays in the NOR gates. In order to analyze this circuit. let’s not consider each element having a delay. This will make more sense after we analyze this circuit.2. 5 Success is considered by many to be a good thing. Our next step is to analyze this circuit because.2: A seemingly simple circuit.

3 has three inputs: Q. The R input is also has a ‘0’ value. The circuit shown in Figure 13.3: The seemingly simple circuit modeled in such a way as to facilitate analysis.Digital McLogic Design Chapter 13 Figure 13. The R input value is also ‘0’ which causes the output of the second NOR gate a ‘1’. For this row. • • Q 0 0 0 0 1 1 1 1 S 0 0 1 1 0 0 1 1 (a) R 0 1 0 1 0 1 0 1 Q+ Q 0 0 0 0 1 1 1 1 S 0 0 1 1 0 0 1 1 (b) R 0 1 0 1 0 1 0 1 Q+ 0 0 1 0 1 0 1 0 Figure 13.5(a). The truth table shown in Figure 13. since the second NOR gate’s inputs are both ‘0’.4(b) can be translated to the more useful form which is shown in Figure 13. Figure 13. To fill in the Q+ column of this truth table.4 shows an empty truth table we’ll use in this analysis. • Truth Table Row #0: Since both Q and S are ‘0’. we can fairly easily analyze this circuit using a truth table approach. the output of the first NOR gate is ‘1’. Since the inputs to this circuit are somewhat limited in number. we will not need to consider the value of the R input. you should redo this example on your own. the output is ‘0’. if you actually have any6. the Q+ output value is a ‘1’. the independent values have been rearranged in an order to more clearly show the relationship between the Q and Q+ variables. Anytime there is a ‘1’ on the input of a NOR gate.4: The empty (a) and completed truth table (b) for the seemingly simple circuit. The one output of the circuit is Q+. the output for this row: Q+ is ‘0’.3. Therefore. Truth Table Row #2: Since the S input is a ‘1’.4(b) shows the completed truth table for the circuit of Figure 13. the Q+ output is therefore a ‘1’. the output of the first NOR gate must be ‘0’. We’ll do a couple of rows and you can do the others at your leisure. we’ll apply the signals provided as independent variables and use them to generate the final value of Q+. Although we’re jumping the gun but about two paragraphs. Figure 13. In this new truth table. 329 . we need to talk about the concept of state. Truth Table Row #6: Since one of the inputs to the first NOR gate is a ‘1’. In order to best model the characteristics of this circuit. and R. the output of the first NOR gate must be a ‘0’ and there is no need to consider the Q input value. the concept of memory in a circuit is synonymous with the concept of the state of the 6 This is really important. S.

the value of Q represents the current or present state of the circuit while the value of Q+ represents the new state of the circuit after a time delay. In official sequential circuit terms.Digital McLogic Design Chapter 13 circuit.5(a) indicates the concept of memory in a circuit. but the truth table shown in Figure 13. we’ll describe these changes by referring to the “state changes” of a circuit. In other words. Keep in mind that this analysis is sort of wordy and that comparing and contrasting this analysis to the timing diagram shown in Figure 13.4 in normal (a) and compressed form (b). You may not have guessed it yet. From now on. the value of Q represents the current state (or output) of the circuit while the value of Q+ represents the state of the circuit after a given time delay. The rows of the truth table of Figure 13. The terms “present state” and “next state” are most likely be the two most used terms from now until the end of this text.5: A more useful form of the truth table of Figure 13. we instead talk about the state of the circuit. you’re digital world is defined by the “state changes” in your circuit. When describing such circuits. In other words the state of a sequential circuit is defined by the values that circuit is remembering. 330 . More specifically.5(a) are described in greater detail below. we’ll now become particularly interested in how the circuit inputs affect the circuit outputs. Sequential design represents a major portion of digital design and understanding the following analysis is your key to understanding sequential design. we don’t usually talk about “the value the circuit is memorizing”. Note that these definitions are written in the context of state changes of the circuit. The values of Q and Q+ represent the output of the circuit but at different times7.6 will really help you assemble all these facts in your mind. This paragraph is probably the most important paragraph written in this all of this text. (a) (b) Figure 13. or the next state. 7 Recall that this approach was taken in order to successfully model the circuit.

(c)1.5(b). state changes of 0 → 0. if a circuit output is set. Therefore. 8 331 . and 1 → 1 are referred to as state changes even though the output does not really change. Therefore. Table 13. the next state of the circuit will always be a ‘1’ no matter what the state of the output was before the SR = “10” condition appeared on the circuit inputs. The reason this state is forbidden is mentioned soon. clearing of a sequential circuit refers to the act of making the circuit output a ‘0’. As a noun. In other words.5. In other words. As a noun. the truth table of Figure 13.2: Detailed explanation of the main points in Figure 13. This state is most often referred to as the hold condition for the circuit. This state is referred to as the set state. or reset state. If the word set is used as a verb. Note that in this state. (a) (b) (c) (d) And finally. This is referred to as a hold condition by examining the Q and Q+ columns of the two (a) rows of Figure 13. it refers to the action of placing the circuit output into the ‘1’ state. If the S and R inputs are equal to ‘1’ and ‘0’. the next state of the circuit will always be a ‘0’ no matter what the state of the output was before the SR = “01” condition appeared on the circuit inputs.Digital McLogic Design Chapter 13 Row Comment This is the do-nothing state. the present state is being “held” and it thus becomes the next state. (b)0. the output is currently a ‘1’. respectively. sometimes the output is being held in the ‘1’ state and sometimes the output is being held in the ‘0’ state as indicated in Figure 13. if the S and R inputs are equal to ‘0’ and ‘1’. This is the forbidden state.3 is shown in Figure 13. The compressed truth table for this the circuit of Figure 13. setting the circuit refers to the act of making the output a ‘1’. In other words. Note that in this state. If the word clear is used as a verb. and 1 → 18. Besides various altered states. way too many professors spend way too much time in this state. the next state (Q+) is always ‘1’ and is independent of the present state (Q) of the circuit. The output in the Q+ column of Figure 13. The word “set” is another massively important world in digital design. The state changes (Q → Q+) associated with these inputs conditions are 0 → 0. it is used to refer to the ‘1’ condition of a circuit output. Note that in these two rows.5(a). One last thing to note is that the next state is dependent on the present state since it’s the next state that is being “held”. the circuit output is currently in a ‘0’ state. if the circuit output is cleared. This state is referred to as the clear state. and 1 → 0. respectively. The state changes (Q → Q+) associated with these inputs conditions are 0 → 1. it then refers to the action of placing the circuit output into the ‘0’ state. The word “clear” is a massively important world in digital design. you need to make sure your S and R circuit inputs do not simultaneously have the values of ‘1’. The state changes (Q → Q+) associated with these inputs conditions are 0 → 0. the next state (Q+) is always ‘0’ independent of the present state (Q) of the circuit.5(b) are (a)Q. the do nothing state is definitely the state I prefer to be in. Nothing dangerous happens if this condition occurs in your circuit but the digital gods will definitely be annoyed. it is used to refer to the ‘0’ condition of a circuit output.5(a) can arguably be made more clear by compressing it. In other words.5(a). the output does not change from the present state (Q) to the next state (Q+). and (d)0. and 1 → 1. Unfortunately. The Q in the (a) row refers to the fact that Generally speaking. To stay out of the forbidden state.

6 tells the whole story. Table 13. we’re describing a sequential circuit which. by definition.6: A timing diagram showing the three states of the given circuit. 9 The something that is being remember here is a digital value. let’s start referring to the “state” of the circuit which is another way of referring to the value the circuit is currently storing.Digital McLogic Design Chapter 13 the next state (Q+) is the same as the present state (Q). If you remember way back.5 are not overly obvious. It does not matter what’s going on in the (d) state since you should not be there anyway (after all. 332 . The timing diagram shown in Figure 13. it is the forbidden state). Instead of speaking of remembering things. Figure 13. let’s not use this “remembering something” vernacular again. The thing that is “being remembered” is a single bit (one digital value). The ‘0’ and ‘1’ in the (b) and (c) rows refer to the fact that the next state will always be ‘0’ and ‘1’ respectively.3 provides an analysis of this timing diagram. The true ramifications of Figure 13. has the ability to remember something9.

In other words. Note in this case that ‘0’ is being remembered.6. The values of S and R are now ‘1’ and ‘0’. It would not provide any useful information to include both a Q and Q+ in a timing diagram because the Q value inherently contains both of these values. respectively. It is important to note here that the initial value of Q was provided by the timing diagram: in other words. For any given time shown in the timing diagram of Figure 13. the present state is the state of Q at those times. the output Q transitions from ‘1’ to ‘0’. the output that was set between the (a) and (b) time slots remains on the output. As you can see. the SR inputs now equal “00” which is again a hold condition. 333 . the S input is cleared (goes to ‘0’). In other words. We’ll be using the present and next state concept extensively in the remainder of this text. Referring back to Figure 13. the appearance of SR=”01” on the circuit inputs causes an output state transition from ‘1’ to ‘0’. The output of the device is “cleared” by this action and remains cleared at least as long as the SR=”01” conditions remains on the circuit inputs. respectively. At the boundary between the (a) and (b) time slots. Referring back to Figure 13. At the boundary between the (b) and (c) time slots. At the boundary between the (d) and (e) time slots. someone needed to provide you with the initial state of the circuit (the output).5. The fact that the ‘1’ remains on the output is the “memory” we’ve been talking about for so long now (‘0’ can also be remembered). the R input is set (goes to ‘1’).5). The output was initially set at the beginning of the (b) time slot and remains in the (c) time slot because the circuit has returned to the hold condition. a hold condition is present on the circuit inputs. Since the both the S and R inputs are once again ‘0’. Note that this hold condition causes no change from the present circuit outputs. you’ll see that these inputs represent the set condition for the circuit and thus cause the output Q to transition from ‘0’ to ‘1’.Digital McLogic Design Chapter 13 time slot Comment This is a hold condition. The concept of Q and Q+ are used to model the present and next state of the circuit.3: Detailed description of the timing diagram in Figure 13. the R input is cleared. refer back to Figure 13. This means that the present-state of the output (Q) is not changing. Table 13.6 is that only the Q output is provided. we used both a Q and a Q+ value.6. The next state is simply the state of the circuit after the current present state. The output state is held for the duration of this SR = “10” condition on the circuit inputs.5. the S input is set (goes to ‘1’). The output will not change so long as both the S and R inputs are both ‘0’ (which is why they call it a hold state. At the boundary between the (c) and (d) time slots. (a) (b) (c) (d) (e) One final fact to note about the timing diagram in Figure 13. Recall that when we first model the original circuit. the concept is hard to describe in terms of a timing diagram. we only developed these definitions in order to generate a special model of the original circuit. Since the SR input combination is now “01” which represents a clear condition for the circuit. Once again. Thus. this SR input combination represents the clear condition for the circuit and thus cause the output Q to transition from ‘1’ to ‘0’.

We’ll be using state diagrams a lot in the remainder of this text so let’s take a look at it now in the context of the simplest possible sequential circuit: the NOR latch. Figure 13. or you can do nothing to it (make it hold its present output state). or store. the NOR latch. We as humans are more adept at viewing more expressive images such as a state diagram as opposed to information in tabular formats.7: The cross coupled NOR cell (a) and its black box representation (b).2 State Diagrams Since we are now settling in with the concept of the state of a circuit.3. Once you draw this circuit a few times. The way the circuit appears in Figure 13. one bit. The control you have over this circuit is that you can set it (make it store a ‘1’). The state associated with this circuit is either a ‘0’ or a ‘1’ depending on which value is being stored at a given time. The concept is not overly complicated but it does take some getting used to.7(b). One common name for this circuit is the cross coupled NOR cell. Note that the lower output of the diagram in Figure 13. This circuit is rarely drawn in the form seen in Figure 13.2 is one of the classic circuits in digital design. 334 . The term “latch” also somewhat closes the loop on this discussion. In other words. Although they are jam-packed with fun information.2 however. the state diagram is without doubt the best way to express the operation of sequential circuit. the information is not presented in an overly useful form. you get really tired of it and instead abstract it to a higher-level and draw it with the schematic diagram shown in Figure 13.3. or simply latch. The term “latch” is once again a massively common term used in digital logic-land. they’re also sort of boring to look at. the circuit shown in Figure 13.1 The NOR Latch The circuit shown in Figure 13. This circuit has a few commonly used names. And since this circuit has the ability to store a bit.7(b) has been drawn with a bubble on one of the Q outputs to indicate that the Q output is active low. we can help our understanding along with the aid of a state diagram. This is truly the same circuit but it has been drawn in slightly differently and another output has been labeled. You saw this storage capability in several forms but probably most clearly in the timing diagram of Figure 13. In other words. Jokes aside.6. clear it (make it store a ‘0’). (a) (b) Figure 13. especially as your sequential circuits become more involved.2 had only a Q output listed.Digital McLogic Design Chapter 13 13. What we’ve described here is a device that is capable of storing a single bit. While the diagram of Figure 13.7(a) shows the more common depiction of this circuit. the Q output of the NOR cell is available in both positive and negative logic forms. While tabular representations of sequential circuits are both useful and interesting. is a circuit that can remember.7(a) has both a Q output and a complemented Q output. 13.7(a) does indeed make it seem like there is a cross in there between a couple of NOR cells. The state of a digital circuit directly refers to that is being stored by the various memory elements of the circuit. How convenient. we can talk about this circuit as having a state. or simply latch. This circuit is also referred to as NOR latch.

8 have some important features. the state of the circuit does not actually change. Each state transition is accompanied by the conditions that make that transition occur. Here they are: • Each circle in state diagram refers to a different state in the circuit. 2) 0→1.8 shows two versions of the state diagram associated with the NOR latch. If you use some strange techniques while drawing your state diagrams. But then again. 335 .8: Two state diagrams representing the NOR latch. 3) 1→0. Being that the NOR cell stores one bit of information. you’ll probably draw most of your state diagrams that way. There is an explanation that follows but first we must issue this disclaimer. In these cases. the forms used in the circuit of Figure 13. The other transitions are represented by arrows emanating from one state bubble to another. There are four possible state transitions in the NOR cell: 1) 0→0. In these cases. The arrows in the state diagram represent the state transitions. the state of the circuit does change. The state diagrams shown in Figure 13. if you’re already used to drawing state diagrams. (a) (b) Figure 13. We’ll be looking at other forms later as the circuits become more complicated and meaningful. there are two states in the associated state diagram: the Q=0 and the Q=1 state. be sure to adequately explain them10.Digital McLogic Design Chapter 13 Figure 13. 4) 1→1. be sure to annotate your state diagrams. once you get used to seeing one way. then you may not want to learn a different way. The state diagram is representing each of these states with its own state bubble. the best state diagrams are the ones that are the most clear. Unlike something like a syntactical language such as C or VHDL. • • 10 In other words. These conditions can be written in a variety of forms.8(a) happen to be logic-type form. there are no set rules for drawing state diagrams. There is one rule that you should follow though: the right way to draw a state diagram is the way that transfers the most information in the shortest amount of time. The 0→0 and 1→1 transitions are represented by the self-loops in the diagram (arrows ending in the same state they started from). The idea is still the same no matter how you draw it. There are many ways to draw state diagrams.

the table of Figure 13.3 PS/NS Tables The present state/next state (PS/NS) table is yet another important sequential design element. characteristic tables are generally used to define simple devices while state diagrams are used to define more complex sequential circuits.4(b) is a basic PS/NS table.4 Excitation Tables Excitation tables are one of the more useful tables used to describe the operation of sequential devices. The PS/NS table is a common tool in describing relatively simple digital circuits such as the NOR latch we’ve described in this section. We’ve already worked with a PS/NS table in the design of the NOR latch.9(b). The excitation table is fairly straight forward in that they represent a rearranging of the columns in a compressed PS/NS table for a device. A compressed PS/NS table is shown in Figure 13. they are usually not used to describe more complex sequential devices. the input conditions are listed accordingly. The state transitions are listed as the change from the present state (Q) to the next state (Q+).8(b) is the same as the state diagram of Figure 13. Also worth noting about the diagram of Figure 13. The state diagram of Figure 13.4. These eight product terms correspond to the eight rows of the truth table shown in Figure 13. In other words. This table is presented more formally with the PS and NS notation include in Table 13.4(b).8(a) but some Boolean reduction has taken place and the forbidden states are not included.8(a) the forbidden states of the circuit inputs are also included (but crossed out). 13. 336 . While excitation tables are used often to describe the most basic sequential devices.5. Please take a look at these and convince yourself that this is true. This table is essentially nothing more than a truth table that lists both the present and next states of the circuit in question.3.Digital McLogic Design Chapter 13 • In the state diagram of Figure 13. A detailed description of the excitation table is provided in Table 13. What the excitation table provides is a list of input conditions that will cause a given state transition. • 13. It’s massively important to be able to read and understand excitation tables.8(a) is the fact that there are eight product terms included in the diagram.9(a) and the associated excitation table is shown in Figure 13. PS/NS Table NOR Latch (PS) Q 0 1 0 1 0 1 0 1 (NS) Q+ 0 1 0 0 1 1 x x S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Comment hold condition reset condition set condition forbidden Table 13. we’ll talk more about that later but it is included in this state diagram for some wicked form of completeness. PS/NS tables are often referred to as characteristic tables since they completely define the set of characteristics associated with a given device.4: The PS/NS table for the NOR latch. Once again.3.

Another way of looking at this case is that this state transition occurs when the R input is ‘0’. 13. In other words. 337 . The clear condition is sometimes referred to as a “reset condition”. the state of the S input does not matter because either a ‘1’ or a ‘0’ will cause the associated state transition (representing the set and hold conditions.9: A compresses PS/NS table (a) and a excitation table (b) for a NOR latch. Setting an already set circuit does not cause a change in the state of the circuit outputs. This is the “set condition” of the NOR latch.3. this state transition can occur when the circuit inputs represent a hold or set condition. we won’t need to go through these same step for a similar bit-storage circuit known as the NAND latch. This is the clear condition of the NOR latch.Digital McLogic Design Chapter 13 S 0 0 1 1 R 0 1 0 1 Q + state transitions Q 0 0 1 1 Q+ 0 1 0 1 input conditions S 0 1 0 (b) R 0 1 0 Comment (a) (b) (c) (d) Q 0 1 x (a) Figure 13. (a) 0→0 (b) 0→1 (c) 1→0 (d) 1→1 Table 13. Another way of looking at this case is that this state transition occurs when the S input is ‘0’. row state change Q → Q+ Comment There are two SR input conditions that cause this state transition: either a hold condition (SR = “00”) or a clear condition (SR = “01”). the state of the R input does not matter because either a ‘1’ or a ‘0’ will cause the associated state transition. There is only one SR input combination that causes this transition: SR = “01”. respectively). There is only one SR input combination that causes this transition: SR = “10”. This state transition occurs when the SR inputs are in the “01” state. This terminology is somewhat confusing but heavily used in digital land.5 The NAND Latch Since we’ve gone through the design and description steps for the NOR latch at a fairly detailed level. There are two SR input conditions that cause this state transition: either a hold condition (SR = “00”) or a set condition (SR = “10”).9(b).5: An explanation of the NOR cell excitation table of Figure 13. This state transition occurs when either a hold or clear condition is present on the circuit inputs.

10(b). 338 .10(a) shows a diagram of the NAND latch. Figure 13. There is one major difference between the NOR and NAND latches (besides the fact that one is made from NOR gates and the other is made from NAND gates): the inputs to the NOR latch are active high while the inputs to the NOR latch are active low. This is clearly shown by the bubbled input in the block diagram of Figure 13. 13. (a) (b) Figure 13. The following sections summarized all these facts and characteristics.3.6 provides the big summary of the various representations of NOR and NAND latches.6 NOR and NAND Latch Summary Table 13.Digital McLogic Design Chapter 13 There are a significant amount of similarities in the derivation machinations of the NOR and NAND latch so we’ll leave the derivation of the NAND latch as an exercise.10: A more useful form of the truth table of Figure 13.4 in normal (a) and compressed form (b).

6: The Big Summary of NOR and NAND latches. 339 .Digital McLogic Design Chapter 13 Item NOR Cell NAND Cell Circuit Form PS/NS Table S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ 0 1 0 0 1 1 x x Comment hold reset set forbidden S 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ x x 1 1 0 0 0 1 Comment forbidden set reset hold S Compressed PS/NS Table 0 0 1 1 R 0 1 0 1 Q+ Q 0 1 x S 0 0 1 1 R 0 1 0 1 Q+ x 1 0 Q Q Excitation Table 0 0 1 1 Q+ 0 1 0 1 S 0 1 0 - R 0 1 0 Q 0 0 1 1 Q+ 0 1 0 1 S 1 0 1 - R 1 0 1 Block Diagram State Diagram Table 13.

R. The truth table. Figure 13. The next column is the next state output Q+.11: The initial evolution of the NOR centered cell. The approach to designing this logic is the standard truth table approach but there are some really important elements we need to comment on in this approach.11(b). you’ll in fact find yourself spending a lot of time making sure you VHDL models are written in such a way as they do not generate latches. the output of the NOR cell acts normally under the control of the S and R inputs. The output that is fed back to the input is listed as the present state of the device. Although we could design any logic we wanted to give us ultimate control over the SR latch. These are listed and described below: • The first four columns are the inputs to the logic block we’re designing. While this condition is sometimes a good quality to have. if the C input is ‘0’.7. stick with this and you’ll soon find out where we’re going. If the C input is a ‘1’. we’ll settle with an S. There are three major portions to the truth table shown in Table 13. Latches are referred to as level-sensitive devices because the outputs can change anytime the inputs change (they of course will not change during a hold condition). This output is also considered to be the next state of the circuit as listed. The C input controls whether the S and R inputs will affect the SR latch.Digital McLogic Design Chapter 13 13.4 Gated Latches Latches are not that useful in digital design. 340 . (a) (b) Figure 13. Keep in mind that we’ll be designing the logic with an ultimate goal in mind.11(a) shows the general form of the desired solution to the level sensitivity problem. From this point. The S and R inputs have been changed to S’ and R’ so as not to confuse them the S and R inputs of the NOR latch. In other words. we can start with a truth table design. up to this point is a standard 4variable truth table. This output is the dependent variable which means it depends on the state of the independent variables for its value. and C input as is shown in Figure 13. We also have opted to feed back the Q outputs (both negative and positive logic forms) from the output to the input. The problem with level-sensitivity is that it is susceptible to noise and can lead to strange outputs due to irregular inputs. no output changes occur in the NOR cell. most of the time it is something to avoid11. The approach shown here is to add some logic in front of the memory element to add some type of control to the circuit. Many of these choices are arbitrary. Note that we’ve included the output of the circuit as an input which is to be expected since we’re working with sequential circuits that are known to have feedback issues. • 11 Needless latches provide extra complexity to circuits and possible slow down circuit operation. You’re used to thinking of these as the independent variables of the circuit.

The excitation table for the NOR latch is shown in Figure 13.9(b). S = C ⋅ S' (a) S = C ⋅ R' (b) Figure 13. In other words. 341 .12: The K-maps for the S (a) and R (b) NOR latch inputs and associated logic.7: The table used to develop the logic required for the gated latch. in order for the device to have a Q → Q+ as listed. The inputs to the logic block How we want the device to act under the given input conditions NS Q+ 0 1 0 1 0 1 0 1 0 1 0 0 1 1 - What we need to input to the NOR cell in order to provide the logic in the NS column PS C 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S’ 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R’ 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 S 0 0 0 0 0 0 0 1 - R 0 0 0 0 0 1 0 0 - Table 13.Digital McLogic Design Chapter 13 • The final two columns are the values that S and R need to be (the inputs to the NOR latch) in order for the state changes in the PS and NS columns to occur on the NOR latch. what do the values of S and R need to be? The answer to this question is taken from the excitation table for the NOR latch.

12. noting that main difference between NOR and NAND latches is the logic levels on the input. at least the standard flip-flops that we’ll be dealing with. 13. thus allowing state changes to occur on the output of the NOR latch. the gated NOR cell is still effectively a level sensitive device. a flip-flop is essentially a latch that is edge-sensitive. This means that the outputs of the flip-flop can only change on an active-edge. Figure 13.Digital McLogic Design Chapter 13 The logic derivation is shown in Figure 13. Since the inputs to the NAND latch are required to be active low.11(a) to form standard devices known as flip-flops. so take a look if you’re totally bored. the diagram shown in Figure 13. Some type of clock signal is thus an input to all flip-flops. (a) (b) Figure 13. When the value of the signal C is a ‘1’. The edge-sensitivity in flip-flops is generally based on a clock edge. And here’s where we skip a lot of work and description… The next step in this evolution is to generate logic that goes in the “cool logic” module of Figure 13. an active low output from the AND gates is provided. there is an input that is commonly referred to as a clock input. the C input is used to enable the two AND gates. 342 . When you say “flip-flop” everyone knows it’s a edge-sensitive device and not a level sensitive device. Engineering in general is often referred to as “constructive laziness”. This creates a “00” condition for the SR inputs to the latch which is conveniently the hold state of the NOR cell and therefore no state changes will take place on the memory cell. More specifically.13: The final circuit for the gated NOR latch (a) and the no-brainer approach to substituting the NOR latch with a NAND latch (b). then the outputs of the AND gates will both be ‘0’. The derivation of the actual circuitry here is found in most digital logic texts.11(b) is be induced with much less effort12. you note that this is the normal K-map stuff for the S and R inputs of the NOR cell. the C input kills the two the AND gates when it is not asserted.13(a) shows the final circuit. A similar analysis can be performed using a NAND latch. if the state of signal C is a ‘0’. The final circuit shows that the inclusion of two AND gates on the inputs of the latch adds a simple degree of control.5 Flip-flops While the latches we’ve been working with are inherently level-sensitive. An AND gate with an active low output is of course a NAND gate. In other words. But alas. we did so using an input referred to as the C input. On the other hand. there can be no state changes on the output of the circuit. When we derived the circuitry for the gated latch. The circuitry that achieves the edge triggering is somewhat complicated but is something 12 Reducing the amount of effort placed into a particular digital design is a major theme of digital design. the outside S and R signals appear on the outside of both AND gates. The reality is that in most sequential devices. when the gates are disabled. The above description is about as simple as it can get as far as the controlling logic goes. In words we’ve used previously.

Figure 13. The characteristic of a D flip-flop is that the output of the flip-flop follows the D inputs. The new and possibly shocking thing to notice about this symbol is the triangular shape on the CLK inputs. try not to forget this. Since this is a D flip-flop (a DATA flip-flop). There are three main types of flip-flops out there in digital land: the D. The characteristic table of the D flip-flop is shown in Figure 13. the device is a rising-edge-triggered (RET) D flip-flop.14(a) is nicely demonstrated by using a timing diagram as shown in Figure 13. The initial state of the D flip-flop (Q) must be provided by the timing diagram otherwise you would not know what the initial state of the device was. you can see what the value of the D input needs to be in order to force the listed state change to occur. The D stands for Data. Note that during the time interval between the first and second rising edges. The operation of the RET D flip-flop shown Figure 13. At the second rising edge. For the case of Figure 13. The only times the outputs of this device can possibly change are on the rising edge of the clock signal. the D input is a ‘1’ and the state of this input is transferred to the output. A schematic symbol of a simple D flip flop is shown in Figure 13. the initial state of the flip-flop is ‘0’.14(c) shows the excitation table for the D flip-flop. The term edge-sensitivity in context of a clock signal means that the output can only change on a rising edge or falling edge of the signal. the D input is high once again so no state change in the flip-flop occurs. D 0 0 1 1 Q 0 1 0 1 Q+ 0 0 1 1 Q 0 0 1 1 Q+ 0 1 0 1 D 0 1 0 1 Q+ = D (a) (b) (c) Figure 13. We’ll do short definitions and derivations of each of these flip-flops in this section.Digital McLogic Design Chapter 13 we can skip over13 without too much worry. T. and JK flip-flops.1 The D Flip-Flop The D flip-flop is probably the most commonly used flip-flop. This triangle means that the device is edge-triggered.5. and excitation table for the D flip-flop. so this is a data flip-flop.14(b). Had there been a bubble on the CLK input.14(a). this device would have been a falling-edge-triggered (FET) device. Let’s now move into the land of flip-flops.15. you can generate the characteristic equation which is also listed in the Figure 13. More importantly.15. At the first rising edge.14: The schematic symbol (a). By inspection of the characteristic table.14(b). 13. 343 . It’s somewhat instructive to see where these devices come from. the D 13 We’re not skipping it… we’re abstracting the concept to a higher level. characteristic table and characteristic equation (b). the output follows the D input. From this table. What this table shows is that the next state (Q+) of the flip-flop follows the D input to the flip-flop. The rising edges of the clock are outlined across the timing diagram using the dotted lines. since there is no bubble attached to this triangle.

the output of this device can only change on the rising clock edges which are nicely delineated in Figure 13. Changes such as these are ignored because the output can only change on the active edge (rising-edge) of the clock. the output of the T flip-flop toggles state on the active edge of the clock.2 The T Flip-Flop The T flip-flop is another of the standard flip-flops out there in digital land. the state of the T input is a ‘1’. the D input is in a low state which causes the output of the flip-flop to change from high to low.16: The schematic symbol (a). At the fourth rising clock edge. The excitation table of for the T flip-flop. If the T input is a ‘0’.5. Figure 13. and excitation table for the T flip-flop. is provided in Figure 13. Once again. Figure 13. And that’s it for the analysis of this device.17. Note that in the characteristic table. You should definitely verify this verbal description of the T flip-flop with both the characteristic and excitation tables shown in Figure 13. At the first rising clock edge. the D input is high which in-turn causes the state of the flip-flop to change from low to high. At the fifth clock edge. 13. T 0 0 1 1 Q 0 1 0 1 Q+ 0 1 1 0 Q 0 0 1 1 Q+ 0 1 0 1 T 0 1 1 0 Q+ = T ⊕ Q (a) (b) (c) Figure 13. the output is low again and the flip-flop remains in a low state.16(a) is nicely demonstrated by the timing diagram shown in Figure 13. At the third rising edge. characteristic table and characteristic equation (b). The initial state of the T flip-flop output Q is a ‘1’ as shown in the timing diagram. The T in flip-flop is referred to as a toggle flip-flop because when the T input is a ‘1’. you can write the characteristic equation associated with the T flip-flop (it sure does look like an exclusive OR function). which is a simple rearrangement of the characteristic table. The operation of the RET T flip-flop shown in Figure 13.17. the state of the flip-flop does not change. the output only changes state when the T input is a ‘1’.16(b) shows the characteristic table for the T flip-flop.16(a) shows the schematic diagram of the T flip-flop while Figure 13.15: An example timing diagram for the D flip-flop.16(c).Digital McLogic Design Chapter 13 input changes twice.16. this 344 . Note that by inspection of the characteristic table.

18(c) show the excitation table for the JK flip-flop. For example. For the JK = “10” condition.17: An example timing diagram showing the operation of the T flip-flop.5. And for the JK = “11” condition. the output toggles again because the T input is once again at a high state. Figure 13. These two conditions result in the listed JK = “0“ condition of Figure 13. the output of the flip-flop toggles its current state.18(b) shows the associated characteristic.18(a) shows the schematic symbol for the JK flip-flop while Figure 13. 13. On the second clock edge. Since the T input is a ‘0’ at the third clock edge.18(b).18(c). The JK flip-flop operates as follows: there are four possible input combinations of the J and K variables. the T input is at a high state. For JK = “00”. the output of the flip-flop does not change state (hold condition). Note that the output of flip-flop transitions from ‘1’ to ‘0’ as a result of the rising clock edge and the fact that the T input is in a high state. the JK flip-flop shares many of the same operating characteristics as the SR latch.3 The JK Flip-Flop The JK flip-flop is the final standard flip-flop that we’ll examine. the output of the flip-flop does not change state. The main difference here is that the JK flip-flop uses the JK = “11” input condition to toggle the current output state of the flip-flop. 345 . On the third and fourth clock edges. the output once again changes state because in both of these instances. You should also note that the first three JK conditions are exactly the same as the first three conditions for the SR latch. You should be able to see these actions from examining the characteristic table of Figure 13. The changes in value of the T input between the first and second clock edges are ignored because the T flip-flop is only active on the rising edge of the clock. the out put of the flip-flop always resets (clear condition). a state change of (0 → 0) can occur as a result of either a JK = “01” (reset condition) or a JK = “00” (hold condition).Digital McLogic Design Chapter 13 causes the output of the T flip-flop to toggle state (thus the name toggle flip-flop). The accompanying characteristic equation can be generated by dropping the Q+ column of the characteristic table into a K-map. For JK = “01”. And that sums up the operation of the T flip-flop. No one really knows what exactly the JK stands for but as you will see. The important thing to note in this table is that the each of the four possible state changes can be caused by two different input conditions on the JK inputs in a way that was similar to the SR latch. the output of the flip-flop always sets (set condition). Figure 13. Figure 13.

the flip-flop’s state is already at ‘1’. At the third clock edge. The fifth clock edge has no effect on the state of the flip flop due to the fact that despite the presence of a set condition (JK = “10”).19: An example timing diagram for the JK flip-flop. JK = “00” which is the hold condition for the flip-flop and thus no output conditions occur.19. The true operation of the JK flip-flop can be demonstrated by using a timing diagram.18(a) is a RET device which means the JK flip-flop’s outputs can only change on the rising edge of the clock. and excitation table for the JK flip-flop. you must be provided with the initial state of the Q output. At the second clock edge. the output of the JK flip-flop toggles due to the fact that both the J and K inputs are ‘1’ (the toggle condition for the JK flip-flop).Digital McLogic Design Chapter 13 J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q+ 0 1 0 0 1 1 1 0 Q 0 0 1 1 Q+ 0 1 0 1 J 0 1 K 1 0 Q + = J Q + KQ (a) (b) (c) Figure 13. characteristic table and characteristic equation (b). Another way of saying this is that the output transitions of this device are synchronized to the rising edge of the clock. In the case of the Figure 13. The fourth clock edge finds that JK = “11” which is yet another toggle condition and cause the flip-flop to change state. the output is in a low state. The JK flip-flop of Figure 13. Figure 13. In order to provide a Q output waveform. the output is reset because of the clear condition (JK = “01”) on the flip-flop inputs. At the first rising clock edge. 346 .18: The schematic symbol (a).

But wait. The truth is that.Digital McLogic Design Chapter 13 13. T. it gets worse. This fact should become more obvious as we examine a few VHDL models. Such an endeavor would not be overly taxing in that these devices simply make sense if you stare at them for a few minutes. 347 . Moreover. This discussion is somewhat strange because we toss out a bunch of what we’ve just been working on as we switch over to modeling sequential circuits with VHDL. in general. and JK flip-flops. While it is possible and in some cases desirable to use dataflow models to describe storage elements in VHDL. VHDL models sequential circuits at a higher level than the level we used to describe those circuits in the previous sections.4 The Big D. understanding the basic operation of the standard flip-flops provides you with a solid foundation in sequential circuit design. the approach we’ll take now is to limit our discussion to VHDL models for D flip-flops. 13. and JK Flip-Flop Summary Table 13. This is good because you’ll never need to use VHDL to model a simple latch on the gate-level. Characteristic Equation Type Symbol Characteristic Table D Q 0 1 0 1 Q 0 1 0 1 Q+ 0 0 1 1 Q+ 0 1 1 0 Q+ 0 1 0 0 1 1 1 0 Excitation Table Q Q+ 0 1 0 1 Q+ 0 1 0 1 D 0 1 0 1 T 0 1 1 0 D 0 0 1 1 T Q+ = D 0 0 1 1 Q T 0 0 1 1 Q+ = T ⊕ Q 0 0 1 1 J 0 0 0 0 1 1 1 1 K 0 0 1 1 0 0 1 1 Q 0 1 0 1 0 1 0 1 Q Q+ 0 1 0 1 J 0 1 - K 1 0 JK Q + = JQ + KQ 0 0 1 1 Table 13. clocked storage elements such as flip-flops are best described using behavior models.6 VHDL Models for Basic Sequential Circuits This section shows the some of the various methods used to model basic sequential circuits.8: The major characteristics of the D. As you for sure know by now. it would not be too tough for you to memorize this stuff. VHDL is a massively versatile language based on its ability to described digital circuits. In theory.8 shows everything you were hoping not to know about flip-flops. T.5. Although you’re hopefully well on your way to understanding each of the three standard types of flip-flops.

In other words.6. The rising_edge() construct is actually an example of a VHDL function which has been defined in one of the included libraries. The way the VHDL code is written makes the circuit synchronous since changes in the circuit’s output are synchronized with the rising edge of the clock signal. 348 .20. • The rising_edge() construct is used in the if statement to indicate that changes in the circuit output only on the rising edge of the CLK input. the statements within the process are executed each time there is a change in logic level of the D or CLK signals. the action is a transfer of the logic level on the D input to the Q output. Example 13-1 Write the VHDL code that describes a D flip-flop shown on the right. Use a behavioral model in your description. The process is executed each time a change is detected in any of the signals in the process’s sensitivity list. the architecture body is comprised primarily of a process statement. The statements within the process are executed sequentially. In this case. Solution: The solution to Example 13-1 is shown in Figure 13. Listed below are a few interesting things to note about the solution. This is not required by the VHDL language but the addition of process labels promotes a self-commenting nature of the code and increases its readability and understandability.Digital McLogic Design Chapter 13 13. The VHDL examples presented are the basic edge-triggered D flip-flop. The general approach to learning about how simple storage elements are modeled in VHDL is to examine a simple model of a D flip-flop. • The given architecture body describes the my_d_ff version of the d_ff entity. the study of VHDL descriptions of storage elements starts at the D flip-flop. • The process is given a label: dff.1 Simple Storage Elements Using VHDL The general approach to learning about simple storage elements in digital design is to study the properties of a basic cross-coupled cell. In this case. • Because example requested the use of a behavioral model.

In terms of the D flip-flop shown in Example 13-1. The way that the VHDL code listed in Figure 13. as strange and interesting as it sounds. a quick way to tell if you’ve induced a memory element is to look for the presence of an else clauses associated with the if statement. there will be conditions where the changes in the output are not defined.20: Solution to Example 13-1. The typical method used to provide a catch-all condition in case the if condition is not met is with an else clause. Even if you’ll only be using VHDL to design combinatorial circuits. end if. we were only dealing with combinatorial circuits. if the if condition is not met. the only time the output is specified is for that delta time associated with the rising edge of the clock. however. the concept of inducing memory in VHDL is massively important to digital circuit design. the outputs associated with the previous set of inputs can be thought of as being remembered.CLK) begin if (rising_edge(CLK)) then Q <= D. constitutes the famous bit storage quality of a flip-flop. 349 . Figure 13. if you did not intend to generate a latch. We’ve been referring to this condition as the “catchall” condition.20 is able to store a bit is not obvious.Model of a simple D Flip-Flop ------------------------------------------------------------entity d_ff is port ( D. Q : out std_logic). you should strive modify your VHDL code 14 Recall that up until this chapter. architecture my_d_ff of d_ff is begin dff: process (D. remember) a single bit. Once again. By definition. that is used to induce memory in VHDL. Despite the fact that this is “only a warning”. end my_d_ff. or state. This somewhat cryptic method used by VHDL to induce memory elements is a byproduct of behavioral modeling based solely on the interpretation of the VHDL source code. The bit-storage capability in the VHDL is implied by the both the VHDL code and the way the VHDL code is interpreted. By definition. In these cases. This is the mechanism. This is also why we were so careful to always provide a “catch-all” condition for our previous VHDL models. In other words. the modeling of all sequential circuits is dependent on this concept. The previous two paragraphs are vastly important to understanding VHDL. CLK : in std_logic. One of the classic warnings generated by the VHDL synthesizer is notification that your VHDL code has generated a “latch”. the device does not change the current value of Q and therefore must “remember” that current value. In this case. it is the else statement that provides the “catch-all” characteristic of the model. The remembering of the current value. It was the inclusion of the catch-all condition in our models that assured us that we were not inducing memory elements14. The D flip-flop is best known and loved for its ability to store (save. Generally speaking. end d_ff. The implied storage comes about as a result of not providing a condition that indicates what should happen if the listed if condition is not met.Digital McLogic Design Chapter 13 -------------------------------------------------------------. the option taken by VHDL is not to change the current output. end process dff. you will be faced with understanding these concepts. if the inputs change to an unspecified state. If you have not specified what the outputs should be for every possible set of input conditions. the outputs remain unchanged.

This is OK though because we can then abstract the concept to a higher level and deal with it there. 13. Let’s take a look at a few examples of flip-flops with asynchronous inputs. There are a few important items worth noting about this solution. • The R input is included in the process sensitivity list. T. the D. since there are two different things you can do to a flip-flop’s output. the set input is sometimes listed as a “preset”. Dealing with asynchronous flip-flop inputs is somewhat troubling because the actual circuitry that implements these asynchronous features is beyond the scope of an introductory digital design course. Generally speaking. Assuming you did not intend to generate a latch. Example 13-2 Write the VHDL code that describes a D flip-flop shown on the right. most flip-flops out there in digital land have the ability to change state either synchronously (generally based on the clock input) or asynchronously. In this section. The first thing you should notice about this solution is that it is amazing similar to the VHDL model for the standard D flip-flop. some action occurs on the output of the flipflop. In the case of the flip-flops we’ve been developing.21 show the VHDL model for this solution. the effect that these asynchronous signals have on the flip-flops occurs immediately. Use a behavioral model in your description. your circuit will need to remember the previous output state so that it can provide an output in the case where you’ve not explicitly listed the current input condition. Most often an “S” is used to represent the input that asynchronously sets the state of the flip-flop while an “R” is used to represent the input that resets the state of the flip-flop. Not surprisingly. Because of this. regardless of whether a clock edge is present or not. In reality. For the record. Generally speaking. namely make it a ‘1’ or make it a ‘0’. asynchronous input that clears the D flip-flop outputs when asserted. Consider the R input to be an active-low.6. As you would probably guess. the reset input is sometime listed as a “clear” input. In other words. the cause of your problem is that you’ve not explicitly provided an output state for all the possible input conditions. there are usually two different asynchronous inputs to a flip-flop: the set and reset input. these inputs are usually active low which means when the asynchronous input signal is low. we want to briefly take a look at a few of those cases. 350 .Digital McLogic Design Chapter 13 in such as way as to remove this warning. In the context of flip-flops. and JK flip-flops we’re dealing have inputs that force the state of the flipflop to change at a time other than on the active clock edge. the flipflop would not operate properly (but it probably would synthesize). some inputs can cause state changes that are not synchronized with the clock. If R was not included here. The logic level of the input is indicated with a bubble on the device. For the asynchronous case. Solution: Figure 13. changes in the state of the flip-flop were synchronized to the rising clock edge.2 Synchronous and Asynchronous Flip-Flop Inputs The flip-flops we’ve described up to this point have been what are considered synchronous circuit. “synchronous” refers to the fact that the changes in the state of the flip-flop are synchronized to the active clock edge.

• -------------------------------------------------------------------. Figure 13. ------------------------------------------------------------------entity d_ff_nr is port (D. Once this occurs. The active low nature of the flip-flop is modeled by making the action state of R to be ‘0’ as shown in the conditional portion of the if clause. a few fantastically interesting thing to note regarding this timing diagram. • • 15 There is actually an associated propagation delay associated with this state transition but we’re still modeling these flip-flops using an ideal model. if the first if clause evaluates are true. the elsif clause is not evaluated and the statement associated with the if clause is executed.21: VHDL model of D flip-flop with active low asynchronous clear.21 is nicely demonstrated by using our friend the timing diagram. The operation of the flop-flop modeled in Figure 13. Q : out std_logic). when R is ‘0’. the R input has precedence of the CLK input in this case.Digital McLogic Design Chapter 13 • The associated VHDL code evaluates the reset input (R) before the CLK input. end my_d_ff_nr.R. In other words. end if. Because of the sequential nature of the statements inside of process statements. the R input goes low. • Since the R input is low at the start of the timing diagram. This is typically how synchronous set and reset inputs act on flip-flops.CLK : in std_logic. end process dff. the output of the flip-flop will be reset if it is currently set. the D flip-flop acts as you expect. In other words. In this case.22 shows a timing diagram associated with this example. Between the second and third clock edges. elsif (rising_edge(CLK)) then Q <= D.RET D Flip-flop model with active-low asynchronous reset input. architecture my_d_ff_nr of d_ff_nr is begin dff: process (D. Using the R input in this manner is typical in timing diagrams and should be feature you always look for when asked to deal with timing diagrams. Returning to the non-active state has no effect on the state of the flipflop. 351 .R. The R input returns to its non-active state (the ‘1’ state) soon afterwards. the output of the flip-flop is in the reset state. And our course. end d_ff_nr.CLK) begin if (R = ‘0’) then Q <= ‘0’. Figure 13. the R input is a ‘1’ so it is passed over in the VHDL model and the other two inputs are evaluated. the output is reset immediately15. On the first rising clock edge. What makes the R input of the flip-flop asynchronous is the fact that the condition of the R signal is evaluated before the CLK signal.

23 shows the solution to Example 13-3. There are a few things of interest regarding this solution. Both of these pulses are negative pulses (high-to-low-to-high) and both pulses cause the output of the flip-flop to reset.Digital McLogic Design Chapter 13 • The timing diagram of Figure 13. synchronous input that sets the D flip-flop outputs when asserted. Consider the S input to be an active-low. Solution: Figure 13. once one condition evaluates as true. Use a behavioral model in your description. none of the other conditions are checked. • The S input to the flip-flop is made synchronous by only allowing it to affect the operation of the flip-flop on the rising edge of the clock. • 352 . On the rising edge of the clock. In other words. the S input takes precedence over the D input because the state of the S input is checked prior to examining the state of the D input.22: Timing diagram associated D Flip-flop with asynchronous active low clear. In other words. This once again emphasizes the sequential nature of statements appearing inside process statements. Figure 13. In an if-else statement.22 is said to have two reset “pulses”. Example 13-3 Write the VHDL code that describes a D flip-flop shown on the right. the D input is transferred to the output only the rising edge of the clock and only if the S input is not asserted. the S input only acts on the flip-flop outputs on the active clock edge.

The flip-flop output sets on the fifth clock edge due to the fact that the S input was in its active state at the arrival of the active clock edge. Figure 13.24 shows a timing diagram associated with Example 13-3. end if.24: Timing diagram associated with Example 13-3. end if. The same is true of the S pulse between the third and fourth clock edges. ----------------------------------------------------------------entity d_ff_ns is port (D.CLK : in std_logic. Figure 13. In other words. • • Figure 13. end process dff.23: Solution to Example 13-3.RET D Flip-flop model with active-low synchronous set input. Here are the cool things to note about the timing diagram in Figure 13.S. the starting state of Q was provided in the timing diagram.CLK) begin if (rising_edge(CLK)) then if (S = ‘0’) then Q <= ‘1’. architecture my_d_ff_ns of d_ff_ns is begin dff: process (D. 353 .S. end d_ff_ns. Q : out std_logic). there was no way you could figure out what it was from the problem statement. • For this example timing diagram. The S pulse between the first and second rising clock edge was ignored because the S input in this example is synchronous (meaning that its actions are synchronized to the clock edge). else Q <= D.24. end my_d_ff_ns.Digital McLogic Design Chapter 13 -----------------------------------------------------------------. you had to be provided with this information.

Note that these inputs are active low (the negative logic thing). The second low pulse on the R signal does not affect the state of the flip-flop since the flip-flop is current in a ‘0’ state. and JK flip-flops.26 is based on the schematic diagram of Figure 13. the examples provided insight in to modeling asynchronous and synchronous inputs using VHDL. Note that when the R signal returns to the ‘1’ state. this is a common approach in these types of problems and sequential-based digital design in general.Digital McLogic Design Chapter 13 The previous two examples are important for several reasons. the output of the flip-flop remains set after the low pulse of S returns to the high state. If this is the case. The output of the device once again follows the D input on the next two clock edges. Once again.3 Flip-flops with Multiple Control Inputs Often times flip-flops are modeled with both preset and reset inputs.6. T. (a) (b) (c) Figure 13. 13. The timing diagram in Figure 13. this represents normal flip-flop operation for asynchronous inputs. For each of the following three timing diagrams. As with these examples. and JK devices with asynchronous presets and clears are shown in Figure 13. and JK flip-flops that include both preset and reset inputs. The following timing diagram analysis is primarily concerned with the affects the asynchronous inputs have on the outputs since these are more often used in digital design land. examining a few timing diagrams should drive home how both the asynchronous and synchronous inputs affect the output of the flip-flops. The output of the D flip-flop is put into an initial ‘1’ state by the low pulse on the S input. go back and closely compare these two VHDL models.25 has S and R inputs which are asynchronous inputs.25: The fully loaded set of D. Once again. If you totally have nothing better to do.25. The final set of D. T. These two examples are once again massively important.25. First. This operation is clearly shown in the timing diagrams associated with the two examples. much of sequential circuit design deals with timing issues associated with where to place control signals relative to the active clock edge. The final low pulse on the S signal sets the output of the flipflop. T. the output of the device remains in the ‘0’ state.25(a): a RET D flip-flop with active low asynchronous preset and clear. As you’ll find out. The first low pulse of the R signal represents a reset which makes the state of the device a ‘0’ independent of the active edge of the clock. We’re not going to do that now but we are going to do a final few examples regarding D. The D. The first and second clock edges transfer the D inputs of ‘0’ and ‘1’ to the output of the device. the initial state of the flip-flop is unknown until one of the synchronous signals put the flip-flop into a known state. you need to be careful to specify the flip-flop operation when both of these inputs are asserted. Secondly. T. and JK inputs are considered synchronous. 354 . you need to keep in mind the sequential nature of VHDL behavioral modeling as you’re generating your VHDL models in order to ensure proper circuit operation. The next three examples are based on the flip-flop models shown in Figure 13. Each of the flip-flops of Figure 13.

The clock edge following the S pulse and the high state of the T input cause the device to reset once again.25(b): a RET JK flip-flop with active low asynchronous preset and clear. does cause the device to change state from a reset state to a set state. The timing diagram in Figure 13.27 is based on the schematic diagram of Figure 13.27 is based on the schematic diagram of Figure 13. The JK=”10” causes the flip-flop to set on the next active clock edge. The final low pulse on the flip-flop causes a similar change near the end of the timing diagram. The initial low pulse on the S input forces the output of the flip-flop into the ‘1’ state. The timing diagram in Figure 13. the flip-flop remains in this state after the low R pulse returns to its high state.25(b)).27: Example timing diagram for a RET T flip-flop with active low asynchronous preset and clear (see Figure 13.Digital McLogic Design Chapter 13 Figure 13. The first active clock edge causes the output of the flip-flop to toggle. Because the flipflop is already set when the first low pulse arrives on the S input. Since the output of the device is currently in the low state. 355 . Figure 13. however. The final pulse on the R input causes the flip-flop to return to the ‘0’ state. The second pulse on the S signal. The initial low pulse on the R inputs forces the output of the flip-flop into the ‘0’ state. The second low pulse on the R input causes a state change in the flip-flop from high to low. the first low pulse on the R signal does not change the flip-flop’s output.25(b): a RET T flip-flop with active low asynchronous preset and clear.25(a)).26: Example timing diagram for a RET D flip-flop with active low asynchronous preset and clear (see Figure 13. the device output does not change.

29 shows the solution to Example 13-4. This example has some massively important techniques associated with it that are well worth mentioning below. The following example has some interesting properties. Sad but true: academic exercises make us more academically fit. and you’ll discover it when you take a look at this problem. The output of a D flip-flop is only dependent upon the D input and is not a function of the present output of the flip-flop. Use a behavioral model in your description.25(c)). The output of a T flip-flop is dependent upon both the T input and the current output of the flip-flop. Consider the S input to be an active-low. The bad news is that modeling T flip-flops with VHDL is more of an academic exercise rather that something that is useful or done often in digital design land. • A unique quality of the D flip-flop is demonstrated in this implementation of a T flip-flop.29. This adds a certain amount of extra complexity to the T flip-flop model as compared to the D flip-flop as is shown in Figure 13. The good news is that we’ll be able to take a look at these interesting properties and maybe learn something useful from it. The truth is. Example 13-4 Write the VHDL code that describes a T flip-flop shown on the right. 356 . Solution: Figure 13.Digital McLogic Design Chapter 13 Figure 13. The T flip-flop model in Figure 13.28: Example timing diagram for a RET JK flip-flop with active low asynchronous preset and clear (see Figure 13. asynchronous input that sets the T flip-flop outputs when asserted. since Q appears as a port to the 16 Except in the problem set associated with this chapter. is that D flip-flops are so much easier to model in VHDL that you’re rarely see T or JK flipflops models16.29 uses a temporary signal in order to use the current state of the flip-flop as in input. In other words.

Q : out std_logic). • ------------------------------------------------------------------.RET T Flip-flop model with active-low asynchronous set input. output changes in sequential circuits generally only occur on an active clock edge. Note that in the key statement in the solution shown in Figure 13.temp output assignment end if. elsif (rising_edge(CLK)) then t_tmp <= T XOR t_tmp. If you don’t have a specific reason for using some type of flip-flop other than a D flip-flop.29: Solution to Example 13-4. • This code uses the characteristics equation of a T flip-flop in its implementation. Q <= t_tmp. become one with it. -----------------------------------------------------------------entity t_ff_s is port ( T.29 that the intermediate signal appears on both sides of the signal assignment operator. We technically used a characteristic equation when we implemented the D flip-flop but since the characteristic equation of a D flip-flop is relatively trivial (Q+ = D). get used to it. The approach is to not only manipulate the intermediate signal in the body of the architecture but to also use a concurrent signal assignment statement to assign the intermediate signal to the appropriate output. Where there are certain advantages to using T flip-flops in some conditions. In other words. The standard approach to bypassing this apparent limitation in VHDL is to use intermediate signals which. 357 .Digital McLogic Design Chapter 13 entity it must be assigned a mode specifier. it has been assigned a mode specifier of “out”. you probably shouldn’t unless you’re friends are easily impressed17.6. Behavior Modeling A major portion of digital design deals with sequential circuits. you may not have been aware of it. end process tff. do not have mode specifications and can thus be used as either inputs or outputs (can appear on both sides of the signal assignment operator) in the body of the architecture. architecture my_t_ff_s of t_ff_s is signal t_tmp : std_logic. -. Figure 13.S. and in this case. most sequential circuit design is synchronized to a clock edge. D flip-flops are generally the storage element of choice using VHDL.final output assignment end my_t_ff_s. as opposed to port signals. 13.S.CLK : in std_logic. We’ve seen this coding style before. end t_ff_s. -. The introduction to memory elements in VHDL presented 17 If you actually have any friends. Generally speaking. -.CLK) begin if (S = ‘0’) then Q <= ‘1’. Signals that are declared as outputs can therefore not appear on the right side of a signal assignment operator.intermediate signal declaration begin tff: process (T.4 Inducing Memory: Dataflow vs.

most knowledgeable people examining your VHDL code would not initially be clear as to what exactly you’re doing. Although it would be possible to generate flip-flops using dataflow models. And on this note. This approach utilizes the flexibility of the language and is arguably a valid approach to learning a new language. probably more so in VHDL than other languages. but this is not the case. One common approach to learning the syntax and mechanics of new computer languages is to implement the same task in as many different ways as possible. checking for unintended memory element generation is one of the duties of the digital designer. This is one area not be clever with. the methods outlined in this section are simply the optimal method of choice. As you would imagine. 358 . The same concept of inducing memory holds for dataflow modeling as well: not explicitly specifying an output for every possible input condition generates memory.Digital McLogic Design Chapter 13 in this section may lead the reader to think that memory in VHDL is only associated with behavioral modeling. This is also the case in VHDL. memory elements add an element of needless complexity to the synthesized circuit. As far as generating synchronous memory elements go. But. there are specific ways of doing things and these things should always be done in these specific ways.

the device must remember the previous output. The concept of present state and next state is used to describe changes in the values being stored by the circuit at the present time. a higher level view of these latches. Flip-flops are generally considered synchronous circuits in that the state of the flip-flop is synchronized to the active clock edge. Transitioning from any of these representations to any other of these representations is a straightforward process. When modeling circuits that are sensitive to clock edges. Latches are considered the most basic storage elements in digital logic. When special control inputs are added to latches. There are three main types of flip-flops: the D. excitation tables. the circuit is considered to be a flip-flop. behavioral models are generally used. and JK flip-flops. The storage ability of sequential circuits is obtained by feeding output signals back to the circuit’s inputs. and state diagrams.Digital McLogic Design Chapter 13 Chapter Overview • The two main types of digital circuits include combinatorial circuits and sequential circuits. Specifying catchall conditions in VHDL models prevent the VHDL synthesizer from inducing memory. Memory in VHDL can be induced with both dataflow and behavioral models. The state of a sequential circuit is determined by the value(s) that the circuit is currently storing. name a clock input. • • • • • • • 359 . Memory in VHDL is model as incompletely specified input condition. T. Although the latches are constructed with different logic gates. these inputs are referred to as asynchronous inputs. Sequential circuits have the ability to store bits of information while combinatorial circuits do not. Since sequential circuit can store information. If an output is not specified by every possible input condition. Probably the most useful of these representations is the state diagram. characteristic equations. and changes in the state of the circuit can only happen on a clock edge. Sequential circuits are typically described by PS/NS tables. Flip-flops can also contain inputs whose effects are not synchronized to the clock edge. they are considered to have a “state”. they differ only the logic levels of the two inputs. The two main types of latches are the NOR latch and the NAND latch. While a latch is considered a level-sensitive device since the outputs can change any time the inputs change.

Digital McLogic Design Chapter 13 Chapter Exercises 1) Provide the Q output (sometimes labeled as OUTPUT) signal using the associated flip-flops listed below. Consider all S and R inputs to be asynchronous. Assume that propagation delays are negligent and that all set-up and hold times have been met. (a) (b) (c) 360 . The asynchronous inputs take precedence over the synchronous inputs.

Digital McLogic Design Chapter 13 (d) (e) (f) 361 .

Digital McLogic Design Chapter 13 (g) (h) (i) (j) 362 .

Digital McLogic Design Chapter 13 (k) (l) (m) (n) 363 .

Assume both the S and R inputs will never be asserted simultaneously. If both the S and R inputs are asserted simultaneously. The S and R inputs are synchronous preset and clear. 6) Provide a VHDL behavioral model of the T flip-flop shown on the right.Digital McLogic Design Chapter 13 2) Provide a VHDL behavioral model of the D flip-flop shown on the right. The S and R inputs are an active low asynchronous preset and clear. 4) Provide a VHDL behavioral model of the D flip-flop shown on the right. The S and R inputs are an active low asynchronous preset and clear. Assume both the S and R inputs will never be asserted simultaneously. Assume both the S and R inputs will never be asserted simultaneously. 3) Provide a VHDL behavioral model of the D flip-flop shown on the right. 364 . The S and R inputs are an active low asynchronous preset and clear. The S and R inputs are an active low asynchronous preset and clear. The S and R inputs are an active low asynchronous preset and clear. 7) Provide a VHDL behavioral model of the T flip-flop shown on the right. Assume both the S and R inputs will never be asserted simultaneously. 5) Provide a VHDL behavioral model of the D flip-flop shown on the right. Implement this flip-flop first using an equation description of the outputs and then using a behavioral description of the outputs. the output of the flip-flop will toggle. Assume the S input takes precedence over the R input in the case where both are asserted simultaneously.

10) Provide a VHDL behavioral model of the JK flip-flop shown on the right.Digital McLogic Design Chapter 13 8) Provide a VHDL behavioral model of the T flip-flop shown at the right. Assume both the S and R inputs will never be asserted simultaneously. Assume both the S and R inputs will never be asserted simultaneously. The S and R inputs are an active low asynchronous preset and clear. Assume both the S and R inputs will never be asserted simultaneously. Implement this flip-flop first using an equation description of the outputs and then using a behavioral description of the outputs. 11) Provide a VHDL behavioral model of the JK flip-flop shown on the right. The S and R inputs are an active high asynchronous preset and clear. Assume both the S and R inputs will never be asserted simultaneously. The S and R inputs are active low synchronous preset and clear. 9) Provide a VHDL behavioral model of the JK flip-flop shown on the right. 365 . The S and R inputs are an asynchronous preset and clear.

Configure a T flip-flop such that it will divide the frequency of a clock signal by a factor of two. Provide the logic to turn a D flip-flop into a T flip-flop. Provide the logic to turn a JK flip-flop into a D flip-flop. 4.Digital McLogic Design Chapter 13 Design Problems 1. 366 . 3. Provide the logic to turn a T flip-flop into a JK flip-flop. 2.

Digital McLogic Design Chapter 13 367 .

2 Finite State Machines (FSMs) The term “Finite State Machine” has many official meanings and definitions in digital land. In the end. This chapter represents an introduction to some of the uses of sequential circuits as well as some of the various techniques associated with both designing and analyzing sequential circuits. Although we went though a couple of major derivations. we did not present much information on what the true purpose and the subsequent power of sequential circuits. The timing associated with state diagrams represents the key to using FSMs for many applications. This is a high-level introduction to FSMs. any circuit that has the ability to remember something (namely bits). One of the interesting features of FSMs relative to their circuit implementations is that they include major elements of both combinatorial and sequential design. Main Chapter Topics INTRODUCTION TO FINITE STATE MACHINES (FSM): This chapter provide the basic theory behind FSMs. The primary focus of this set of notes is the Finite State Machine (FSM) analysis and design. In this course we’ll deal with them primarily in the realm of digital circuitry. FSM AND TIMING DIAGRAMS: FSMs have interesting timing aspects. FSM ILLEGAL STATE RECOVERY: This chapter describes the notion of hang states and provides techniques on how to avoid this unwanted behavior in FSM.1 Chapter Overview The primary focus of the previous chapter was the introduction of sequential circuits. we could not produce a model of its behavior. The term “finite” references the fact that the machine we’re dealing with can be successfully modeled in some tractable form. As you have seen previously. 1 Keep in mind that FSMs and the concept of FSMs are used in many other disciplines. FSM ANALYSIS AND FSM DESIGN: This chapter explains the basic techniques of FSM analysis and FSM design. The term “machine” is used to make the term “FSM” as generic as possible1. can be regarded as having a “state”. Conversely. (Bryan Mealy 2011 ©) 14. The official definition of state (relative to actual logic circuits) is the unique configuration of information within a machine. The examples provided in this chapter provide full explanation of the low-level details regarding FSM analysis and design. a semi-official. 368 . This introduction includes a description of the basic FSM forms and various FSM representations. circuit-oriented definition of a FSM is a circuit whose behavior can be modeled using the concept of state and the transition between these states. we’ll be filling in the details once you grasp the details of FSMs from a top-level point of view. if the machine had an infinite number of states.Digital McLogic Design Chapter 14 14 Chapter Fourteen 14.

Although any digital circuit that contains a memory element is officially a FSM (hence.3 High-Level Modeling of Finite State Machines There are generally two types of FSMs as shown in Figure 14. we’ll start working with more interesting problems in the following chapters. Other FSM representations may be more appropriate for other applications such as implementing a FSM via software. Try not to lose grasp of the ultimate function of FSMs. the state diagram represents the most useful tool to understanding FSM operation2.1 shows a basic model of a Moore-type FSM. Each discipline seems to have its own particular flavor of the FSM. What we’ll hopefully be learning from these steps is a basic understanding of state diagrams and their relation to digital circuitry.2: Moore and Mealy machines. At this level of digital design. As you can see from a brief perusing of these figures. the universal language of state diagrams. we’ll stick to the basics. The terminology used to describe the three basic components of FSM differs widely from source to source but the general function of the three components is equivalent. these two types of FSMs are more similar than they are different so we’ll discuss the similarities first. Creating a state diagram requires learning a new language of sorts: the language of state diagrams. we’ll not be using this broad definition in the following discussion. keep this word in mind in this chapter. Figure 14. If by chance you are lucky enough to delve deeper into the field of FSM design. and 3) the Output decoder. The state diagram is a model of a FSM that visually describes the behavior of the FSM. and 3) developing the state diagram. the fact that the final FSM is used as a controller can be easily forgotten in the details that follow. The problem is that this chapter presents definitions and basic techniques of dealing with FSMs. The key word here is control. we’ll be implementing them using digital circuitry. But since this is simply an introduction. we’ll use FSMs primarily as a circuit that controls other circuits.Digital McLogic Design Chapter 14 FSMs are used in one form or another in many different technical disciplines.1 and Figure 14. 2) analysis and design of FSMs in circuit form and their relation to the state diagram. for lack of a better term. they are generally described using. 369 . a state diagram is a visual tool designed to facilitate human understanding of a FSM’s operation. We developed a few state diagrams to describe the operation of a simple latch in the previous chapter. any sequential circuit). you’ll find that there are some variations in the functioning of these blocks. The first two steps are straight-forward and almost mechanical in nature. Although FSMs in different disciplines are often times implemented in many different ways. The third step is where the engineering is involved. understanding the basic functioning of the blocks is the key to understanding how these blocks interact with each other (it’s the system-level thing all over again) and form the FSM.1 and Figure 14. Table 14. Although a FSM has lots of internal digital circuitry. Our workings with FSMs is divided into three distinct steps: 1) a high-level overview of the concepts and associated terminology. Actually implementing a state diagram can be implemented in many different ways.2. 14. 2 Once again.1 provides a detailed description of these individual blocks of Figure 14. FSMs are amazing devices. You’ll be using this language to solve various engineering problems in upcoming chapters. we can easily abstract the functionality into three separate blocks: 1) Next State Decoder. 2) the State Registers.

1: Model for a Moore-type FSM.2: Model for a Mealy-type FSM. Figure 14. 370 .Digital McLogic Design Chapter 14 Figure 14.

These two sets of values are used to form what is referred to as excitation inputs to the state register flip-flops. The purpose and function of the state registers is identical for both Mealy and Moore-type FSMs. The next state logic generally has two types of inputs: 1) the current value of the state variables. In a Mealy-type FSM.1 and Figure 14. The output decoder is a set of combinatorial logic that is used to generate the external outputs of the FSM. Having a fundamental understanding of the differences between a Mealy and Moore-type FSM is integral to understanding and designing FSM-based controllers. the other two blocks are implemented with combinatorial logic. the external outputs are strictly a function of the state variables. the external outputs are a function of both the state variables and the internal inputs. In the case of the flip-flops. the state of the FSM is dictated by the bits that are being stored in the flip-flops that make up the state registers. Once the active clock edge arrives. The important thing to notice here is that the next state of the flip-flops. This type of cycling occurs every clock edge. As you’ll see in upcoming examples. Keep in mind that the internal inputs are a key feature of the FSM function: the external inputs to the next state decoder essentially function as status signals from the world outside of the FSM.2. the only synchronous portion of the FSM is the state registers. The state registers are the only sequential part of the FSM. and 2) the current value of the inputs from the external world.1: A detailed description of the three main FSM functional blocks. it needs to be aware of the status of what it is controlling. The FSM does this via the external inputs to the next state decoder. The state registers are commonly referred to as storing the state variables of the FSM. Next State Decoder The next state decoder is a set of combinatorial logic that is used to provide input logic to the flip-flops in the state registers. Recall that the inputs to the flip-flops are used to determine the next state of the flip-flops (following the next active clock edge). The next state decoder is sometimes referred to as the next state logic. While the outputs of the next state decoder module are the same for both a Mealy and Moore-type machine. The purpose and function of the state registers is identical for both Mealy and Moore-type FSMs. These bits are most often referred to officially as the value or state of the state variables. the flip-flops act on the excitation inputs and the next state becomes the current state. You may want to read the few previous sentences a few extra times. or the next state of the FSM. The term register in digital-land is term that is implies some type of synchronous storage. The difference between a Mealy and Moore-type FSM is based solely upon the inputs to the output decoder. As you can see from Figure 14. is a function of both the external inputs and the current present state of the state registers. 371 Output Decoder . we’ll be using flip-flops as storage elements and they can store a single bit of information. these differences are shown by comparing and contrasting the output decoder blocks in Figure 14. In a Moore-type FSM. If you think about this in an intuitive sense. when the FSM is controlling something. the inputs have one difference.1.1 only affects the state registers. In other words. or the next state forming logic. The state registers can be implemented by any type of memory device but we’ll only be implementing them with flip-flops.Digital McLogic Design Chapter 14 Module State Registers Description and Comments The state registers represent the memory elements in the FSM. This difference is massively important and one that we’ll be dealing with often in the discussion that follows. The external outputs form the output decoder are generally used as control signals to the device or devices that are being controlled by the FSM. Table 14. the clock signal present in Figure 14.

The next state decoder outputs are formed by the logic internal to the next state decoder and are a function of the present state of the FSM and the external inputs. we’ll fill in the details real soon. The FSM sends the control signals to the outside world via the output decoder. The heart of the FSM is the state registers. Our final goal of analyzing a given FSM is to generate a state diagram. Let’s do it.4 FSM Analysis Probably the best way to understand the functioning of an FSM is to closely examine one.Digital McLogic Design Chapter 14 You should now have somewhat of a feel for the operation of a FSM based on the diagrams of Figure 14. The external outputs from the FSM are a function of the state variables (Moore-type FSM) or a function of both the state variables and the current external inputs (Mealy-type FSM). Example 14-1 Analyze the FSM shown in Figure 14. we can officially refer to our viewing as FSM analysis. The external inputs are generally status signals from the outside world. Since we’ll be taking a real close look at the basic operation of one FSM. the secondary goal of this analysis is to be able to model the behavior of this particular example. On each active edge of the clock. Our initial goal of this analysis is to determine how FSMs really work. we’ll switch over to design-type examples.4. Provide a PS/NS table (including the outputs) and a state diagram that describes the circuit. 14. The excitation inputs to the flip-flops are the outputs of the next state decoder. Read through this description a few times. Once we do a few analysis examples. The state transitions of each flipflop in the state registers is governed by the excitation inputs to those flip-flops.1 and Figure 14.3: A typical Mealy-type FSM.2. 372 . Figure 14. the state of the FSM (the values stored by the flip-flops) can change. the heartbeat of the FSM is the clocking signal that controls the state to state transitions of the FSM.

After we stare at it for a minute. For example. The inverter that complements the X input is not shown. Even though only one of the external output is a function of the external input X.4 which is a cleaner version of this example. The way you know this is by examining the Output Decoder block. “01”. If the FSM contained three flip-flops. The XOR gate to the left of the JK flipflop forms the Next State Decoder logic. This is generally done to keep things simple which is nice when you’re first dealing with FSMs. The truth is that once you know more about how state machines generally operate. once complemented. you’ll change from the X and Z variables to names that are self-commenting and thus more meaningful in nature. • The external inputs. it is still considered a Mealy-type FSM. • The circuit is drawn with a shorthand notation. the state variables. If the 3 This is true for now but will change in later chapters. there could be up to eight unique states. 373 . • This FSM is a Mealy-type FSM. the number of possible states is related to the number of bit-storage elements by a power of two3.Digital McLogic Design Chapter 14 Solution: The circuit shown in Figure 14. the complemented Y1 output also acts as an input the AND and OR gates on the right of the diagram. Y1 and Y2. The presence of the X variable on the input to the AND gates essentially make the external outputs a function of the external input (remembering that the X represented external inputs). The circuit shown in Figure 14. you’ll surely note the following stuff regarding the FSM of Figure 14.3 is obviously a sequential circuit (the flip-flops provide it with memory) which officially makes it a FSM. and the external outputs are represented by X. are referred to as the state variables for the FSM. The AND and the OR gates form the Output Decoder logic. The same story is true of the Y2 output. • The outputs of the flip-flops. • There is one external input (X) and two external outputs (Z1 and Z2) for this FSM. This general form of the FSM is usually followed in most FSM applications. two flip-flops raised to the power of two is four. this FSM has four different unique states. There are two flip-flops and each flip-flop can store one bit of information.3. We’ll then switch over to Figure 14. The two storage elements (the T and JK flip-flops) form the State Registers. But more importantly. The first step in any analysis is to stare at the diagram for awhile to get a feel for the approach you’ll need to take to successfully analyze the circuit. and “11”. Y.3 is a typical FSM implementation. particularly the FSM that we’ll be working with. • The three standard functional blocks of an FSM are not readily apparent from the diagram so that have been explicated listed. “10”. the Y1 output of the T flip-flop acts as an input the XOR gates on the left. it’s in a form that could be considered typical for FSM. there are two flip-flops. For example. So after staring at the FSM for awhile. and Z variables. Generally speaking. this shorthand notation is used to de-clutter the circuit diagram. The means there are four final states for the machine: Y1Y2 = “00”. The X signal acts as an input for the XOR gate and also. These two outputs are used as inputs to other portions of the circuit as listed but not as explicitly connected. Once again. For example. we present a procedure for analyzing the FSM. respectively. acts as an input for the AND gate on the right. the outputs of the T flip-flop are the complemented and uncomplimented values of Y1 (complementary outputs). Since there are two state variables and since the variables are binary in nature.

4: A cleaner looking version of Example 14-1. 374 . The idea here is to drag you through the process one time in excruciating detail and then allow you to decide upon your own personal level of detail when analyzing FSMs. this FSM would then be classified as a Moore-type FSM. The basic steps in the solution to this problem are listed in painful detail below. The following analysis has been broken up into steps that seem to make sense to me. Step 1) Stare at the thing for awhile and note such features as we have previously listed Step 2) Write down the equations for the excitation logic Step 3) Write down the equations for the output logic Step 4) Generate the empty of a PS/NS table Step 5) Provide columns in the PS/NS table for the excitation variables Step 6) Use the excitation equations to fill in the columns representing the Step 7) Provide columns for the next state variables which would be Step 8) Fill in the columns associated with the output logic Step 9) Draw as state diagram Step 10) Allow the celebration to begin (not really a step. and K inputs of the 4 Although following and/or enforcing rules is the hallmark of an academic administrator. Keep in mind that engineering is not a matter of following steps4. following these steps are simply an aid to your understanding of FSM analysis. The main point of this step in general is to discern the following: • • • The number of external and inputs and outputs Whether the FSM is a Mealy-type or Moore-type machine The maximum number of states in the FSM (based on the number of storage elements) Step 2) Write down the equations for the excitation logic. Figure 14. J. You’ll soon be forced to fend on your own. it just sounds good) Step 1) We already went through step one in deep detail. the excitation logic is the logic attached to the flip-flop’s synchronous inputs (the stuff connected to the T.Digital McLogic Design Chapter 14 Output Decoder was not dependent upon the external input. you need to make them make sense to you. For this circuit.

Next State Decoder Inputs Present Ext State Input Y1 Y2 X 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Table 14. In the beginnings of our PS/NS table shown Table 14. the only information that matters to us is the present state and the value of the external input.1 and Figure 14. At this point. Recall from Figure 14. From inspection of the circuit. and the next state (we’ll also list the output variables but not until a later step). we’ll fill these in during subsequent steps. you can generate the following equations: Z1 = Y1 ⋅ Y2 ⋅ X Z 2 = Y1 + Y2 Equation 14-2 Step 4) Generate the initial PS/NS table which is essentially a truth table.2 is that we have a lot of extra columns. From examining the diagram of Figure 14. The present state is formed by the value of the Y1 and Y2 variables only: the X input is not part of the present state of the FSM. the variables that effect the state transition from the present state to the next state. Another way of looking at the PS/NS table is that the number of rows in the truth table is based on the number of inputs to the Next State Decoder. T = Y2 J = Y1 ⊕ X K = Y1 ⊕ X Equation 14-1 Step 3) Write down the equations for the output decoder logic. we’ve listed the present state and the external input as the independent variables in the table. you can generate the equations shown in Equation 14-1.4.2 that the only things affecting the transition from one state to another are the state variables and the external inputs.2: After Step 4). you see that there are two external outputs from the FSM: Z1 and Z2. In this case. One other thing to note in Table 14. The purpose of the PS/NS table is to provide a listing of the present state.2. 375 .Digital McLogic Design Chapter 14 individual flip-flops).

The 1’s and 0’s in the columns are entered directly based on the inputs to the Next State Decoder. 376 . the Y2 column is copied into the T column. each of these inputs receives a column in the PS/NS table as shown in Table 14.4 shows the final results of this step.4: After Step 6). and K columns of the developing PS/NS table. Next State Decoder Inputs Present Ext State Input Y1 Y2 X 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 State Register Excitation Logic T 0 0 1 1 0 0 1 1 J 0 1 0 1 1 0 1 0 K 0 1 0 1 1 0 1 0 Table 14. A better example is the logic for the J and K columns: the data in these columns is generated by an exclusive ORing of the Y1 and X columns from the Next State Decoder Input section of the PS/NS table. State Register Excitation Logic T J K Step 6) In this step.Digital McLogic Design Chapter 14 Step 5) Since we need to find out how the next state decoder outputs affect the flip-flops. There are three inputs to the two flip-flops.3: After Step 5). we need to examine the excitation inputs of the flip-flops. In this step. J. we need to provide columns in the developing PS/NS table to list the logic generated by excitation equations. For example. the excitation logic as generated form the excitation equations of Step 2) are entered into the T.3. Table 14. since the excitation input equation for the T input is T = Y2. Next State Decoder Inputs Present Ext State Input Y1 Y2 X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Table 14. The logic in the Next State Decoder forms the excitation logic for the flip-flops that represent the state variable.

The Z2 output is a Moore output since it is only a function of the present state variables. the present state of the Y2 variable is a ‘0’. The Z1 output is considered a Mealy output because it is a function of both the present state (PS) variables as well as the external input variables X. The logic in the Z1 and Z2 columns in Table 14. make sure you understand how these examples relate to the developing PS/NS table. There are two massively important points here that are typically sticking points when first working with FSMs.Digital McLogic Design Chapter 14 Step 7) Now that we’ve listed the Next State Decoder Information and the excitation equation logic. There are two external outputs for this FSM: Z1 and Z2. A few examples are listed below. This is the toggle condition for the JK flip-flop and thus causes the present state input of ‘0’ to toggle which results in a next state output of ‘1’ for the JK flip-flop. Conversely. Although this FSM is officially a Mealy-type FSM. both Mealy and Moore-types. 377 .5 shows the complete table for this step. Keep in mind that the next state values are the values that the flip-flops will have after the next active clock edge. are always a function of the present state variables (Y1 and Y2). and X) are ‘0’. the current input to the T flip-flop is a ‘0’. make sure to not consider the next state variables (Y1+ & Y2+). we can generated the Next State (NS) values. Next State Decoder Inputs Present Ext State (PS) Input Y1 Y2 X 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 State Register Excitation Logic Next State (NS) + Y1 Y2+ 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 1 • T 0 0 1 1 0 0 1 1 J 0 1 0 1 1 0 1 0 K 0 1 0 1 1 0 1 0 Table 14. don’t try it here. Since we know what the excitation logic is (as generated from the present state and external input values).5: After Step 7). the only time the output is a ‘1’ is when each of the three inputs (Y1. this condition occurs in the final two rows of the PS/NS table shown in Table 14.6. we can consider the outputs as both a Mealy output (Z1) and Moore output (Z2). the current inputs to the JK flip-flop are JK = “11”. Y2. Step 8) Now that PS/NS table is complete in terms of the state transition information. • The outputs. we can tack on the external output logic. Table 14. For Z1. In the second row of the truth table. the present state of Y1 is a ‘0’. A ‘0’ input on a T flip-flop will cause no change in the state of the flipflop so the next state value will thus be a ‘0’. we can generate the next state values based on that logic. • In the first row of the truth table. This is a common mistake.6 is entered by examining the output equations from Step 3. the only time the Z2 output is a zero is when each of the state variables is ‘1’. When entering the logic into the output columns.

it can actually be done in many different ways. Z1 has two different outputs. And speaking of a cluttered PS/NS table… there is a better way to represent the operation of a given FSM. thus there are four unique combinations of the two state 378 . The clock signal is always omitted because it is understood that all state transitions occur on the active clock edge. Since this FSM has two state variables (Y1 & Y2) based on two flip flops. This is because the Z1 output is a Mealy-type output and is a function of both the X input as well as the two state variables. you’ll not need to follow the steps. With the Moore output (Z2). The four states are based on the fact that each of the flipflops can store one bit. A better approach is to use the information in the PS/NS table to generate a state diagram. One last thing to note is that the order of the steps in drawing the state diagram are somewhat arbitrary. There are many approaches to drawing a state diagram. the only time the values on the state registers can change is when the active clock edge arrives. there will be four states in the state diagram. In contrast. The PS/NS table is now officially complete as shown in Table 14. it becomes second nature because you’ll be loving it as well as understanding it. Once you do a few of these problems. it provides the information in an un-friendly manner. since it is strictly a function of the state variables.Digital McLogic Design Chapter 14 • Note that the Moore output (Z2) is always the same per set of state variables (Y1 & Y2). Note that in the first two rows of the PS/NS table. Step 9) The final step is to draw the state diagram. This is the final step in the analysis process. the Mealy output (Z1) can change for a given set of state variables. While the PS/NS table does in fact provide all the necessary information to describe the operation of the FSM. The clock signal could be included in the PS/NS table but it would clutter an already cluttered table and provide no extra information. • Step 9(a): Draw a bubble representing each possible state in the FSM. The drawing of the state diagram is decomposed into a bunch of humongously boring steps in a fashion similar to the development of the PS/NS table. In other words.6. it will not change so long as Y1 and Y2 are the same. There is yet one more important point to remember from the PS/NS table: there is no clock signal listed in the table. Since Y1 and Y2 are formed by the first two columns in the PS/NS table. the most important item is to provide a legend to allow the human viewer to know what is going on. the Moore output is effectively the same for the pairs of rows.6: After Step 8). The state diagram is simply a visual representation of the information provided by the PS/NS table. Next State Decoder Inputs Present State (PS) Y1 Y2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Ext Input X 0 1 0 1 0 1 0 1 State Register Excitation Logic Next State (NS) Y1+ Y2+ 0 0 0 1 1 1 1 0 1 1 1 0 0 0 0 1 Output Decoder Outputs Mealy Z1 1 0 0 0 0 0 0 0 Moore Z2 1 1 1 1 1 1 0 0 T 0 0 1 1 0 0 1 1 J 0 1 0 1 1 0 1 0 K 0 1 0 1 1 0 1 0 Table 14.

the first two rows in the PS/NS table have the exact same state variables. the Moore output variable only changes when the state changes. The Z2 information is found in the Z2 column of the PS/NS table. For example. This is typically done by dividing the state bubble into state information and output information as indicated on the right. Figure 14. The arrows are drawn to reflect the conditions in the individual rows in the PS/NS table. there can be at most two different transition possibilities in the associated state diagram: these two possibilities are associated with the two possible state of X: ‘0’ and ‘1’. First note from the PS/NS table that all state transitions are a function of both the present state variables and the external X input.Digital McLogic Design Chapter 14 variables. Also note that the legend has been updated to reflect the fact that the Z2 output is indicated in the state bubbles. This condition is reflected in the associated PS/NS table. There are several important tasks associated with this step. In other words. Since there is only one external input. Figure 14. The state transitions are represented by drawing arrows.7 shows the results of this step. This forces the Z2 output to follow pairs of rows in the PS/NS table. changes in the external input variable X do not affect the Z2 output. in the first row of the PS/NS table. the arrows originate in the current state and end in the next state. in the context of the PS/NS table. This allows the Moore-type output to be included as part of the state bubbles. Another important task to perform in this step is creating a legend to describe some of the pertinent information in your state diagram. • Step 9(c): Enter the state transition information. Note that because Z2 is a Moore-type output. Figure 14. Note here that the outputs of the FSM are always based on the present state of the FSM. Note that the legend is located on the left.6: The results of Step 9(b). For example. and never the next state.5: The results of Step 9(a). if the X input is a ‘0’ when the active edge of the clock 379 . • Step 9(b): Enter the Moore-type output information into the state diagram. Recall that a Moore-type output is only a function of the present state of the FSM. the present state variables are “00”.

when the X input is ‘0’ in state “00”. These two conditions are somewhat confusing based on the way these conditions are drawn in the state diagram. this must be done in order for someone to understand what the state diagram is really doing. if an active clock edge occurs while X = ‘1’. be sure to note that the state diagram clearly indicates the X and Z variables.7: The results of Step 9(c). Similarly. the Z1 output is ‘1’.7. The state transitions are based on the value of the X input on the active edge of the clock. Since Z1 is a Mealy-type output. 380 .9. what you need to do from this point is continue to transfer information from the PS/NS table into the state diagram. which is somewhat misleading.8 shows the results of entering the third and fourth row from the PS/NS table into the state diagram. The important thing to remember here is that the output drawn with the state transition arrows is associated with the state that the arrow is emanating from and not the state that the arrow is entering. This condition indicates that the FSM does not change state on the next active clock edge. the Z1 output has an immediate response to the X input and is not associated with the clock edge. Also associated with this transition is the value of the Z1 output. Note that in this approach. o Figure 14. the FSM will not change state on the active clock edge if the X input is ‘0’. • Step 9(d): This step is not really a step. when the X input is ‘1’ in state “00”. the FSM will transition to the Y1Y2 = “01” state. The problem is that there is no easy way to reflect both the Mealy-type output and the state transitions in the state diagram. Figure 14.Digital McLogic Design Chapter 14 arrives. The approach shown Figure 14. Since the output decoder is combinatorial.7 is the standard approach. the Z1 output is ‘0’. The first two arrows drawn in the diagram are interpreted as follows. the next state of the FSM will be “00”. for the other arrow in Figure 14. it is a function of the external X input. The complete state diagram is shown in Figure 14. the X input and Z1 output are associated with the state transition arrow. For the first leftmost arrow of Figure 14. And finally. Similarly. Also. For this FSM (as indicated by the first row of the PS/NS table). o Be sure to note that the first row in the truth table forms what is commonly known as a self-loop in the state diagram. and thus can change based on changes in the X input. the Z1 output is a ‘1’. if the X input is a ‘1’ in the Y1Y2 = “00” state the Z1 output is a ‘0’.7. then the X input is ‘0’ in the Y1Y2 = “00” state.

State transitions are represented using arrows. the states are represented by the different combinations of state variables. transitions can occur from one state to that same state or to any other state in the state diagram. • • A legend and legend-type information is always included with the state diagram. Since there are two state variables and each state variable can either be a ‘0’ or a ‘1’. The Moore-type outputs are listed inside of the state bubbles since they are a function of the present state only. there are four possible states.Digital McLogic Design Chapter 14 Figure 14. Each possible state is listed in the state diagram using a bubble. The external input information that causes one state transition compared to another is listed next to the arrows. Here’s a quick summary of this example.9: The completed state diagram. The Mealy-type outputs are listed next to the external inputs conditions controlling the state to state transitions are listed next to the transition arrow. Note that the 381 • • • • .8: The results of Step 9(d). Figure 14.

As you become more fluent with drawing state diagrams. it is never included in either the PS/NS table of the state diagram. and 3) Z2 output information. • • 382 . The starting point of this state diagram is the state in sometime before the first clock edge. you’ll probably alter you approach to drawing them. the entire state column has not been provided: only the first state has been provided. This condition manifests itself in the Z2 output by having changes in the Z2 output always synchronized with the clock edge. This means it can only change when the state changes. To put this in another way. Note that this is only a sample. The Z1 output is Mealy-type output so it can change in between active clock edges. The style that is used drawing the state diagram is not unique. You know what a sequential circuit has memory and that the outputs of a sequential circuit are a function of the “sequence” of inputs to the circuit. It is understood in this timing diagram that the first state has been provided for us (it had to be otherwise we would not know what it was). 2) Z1 output information. Since the FSM is built with flip-flops as the storage elements. Note there are three forms of information that we need to include in this timing diagram: 1) state information (how the states change on the active clock edges). The X input and the current values of the state variables control the state to state transitions. there will be much joy and the world will be happy. it is provided in complete form which somewhat obscures the starting point of the state diagram. There probably is a way to include the clock in one of these representations but I’m not sure what it is and I never seen it listed anywhere. From the initial state and the X input information. there are actually many different ways to draw them. A state diagram without legend is useless. we can complete the timing diagram as shown in Figure 14.10. In the big scheme of things. recall that you have just analyzed a sequential circuit.10 shows a sample timing diagram for this example. A few things to note about this timing diagram are listed below.10. As you can see from Figure 14. The approach shown in this example is probably the clearest approach. state transitions can only occur on the active clock edge. the entire X input is provided also. The only time the X input is considered for the state transitions is on the active clock edge. Since this information is inherent to the operation of the FSM. • The Z2 output is Moore-type output so it is only a function of the state variables. One thing that is glaringly missing from the state diagram and the PS/NS table is the system clock. The key to using a different style to drawing state diagrams is making sure you explicitly state your approach with the legend provided with the state diagram. Figure 14.Digital McLogic Design Chapter 14 Mealy-type outputs are associated with the state that the arrows are emanating from as opposed to the state they are going to. the Z1 output occasionally changes between clock edges as listed in the state diagram. We’ll be spending more time on this subject later but we’ll take an introductory look at it for this example. One of the most important factors in developing a working knowledge of FSMs is understanding how the state diagram relates to some of the timing aspects of the circuit. both the PS/NS table and the state diagram list the state to state transitions of the FSM. This so-called sequence is shown in explicitly with the state diagram. If you are clear with your state diagram style. You characterized the operation of this circuit by generating a state diagram. For this timing diagram. Since these transitions only occur on the active clock edge that controls the flip-flops. explicitly showing this information in the PS/NS table or state diagram would only serve to clutter them.

Time Slot (7): In this time slot. All of the important steps are here but as you will see later.10 are provided below. The timing diagram was competed by examining the value of the X input and state variables in at each clock edge in the timing diagram and using this information in conjunction with the state diagram to glean where the next state value after the active clock edge.10: Example timing diagram associated with the state diagram of Figure 14. the Z1 output.9. the state variables are “10”. counter-design provides a good introduction to the subject of FSM design.Digital McLogic Design Chapter 14 Figure 14. the specification step is greatly simplified. In particular. then the FSM will transition to the “11” state. This is a massively important attribute of the Mealy input. In this context. the final generation of the FSM is pretty much cookbook no matter if you’re 383 . • Time Slot (1): In this time slot. • 14. Once you become fluent at designing simple FSMs such as counters. Keep in mind that the Z1 output is the same value for the other three states in the state diagram which is why you don’t see the Z1 output changing in-between the active clock edges as see in this time slow. For this reason. A spec such as a simple count is generally more straight-forward than designing a FSM that acts as a controller. the Z1 output in the “00” state is the opposite value of the X input. as you can see from the state diagram. is changing between the active clock edges. This is once again because the Z1 output is a function of the X input. The first step in FSM design is defining the state diagram. we’ll move onto designing FSMs that are used to control things that need controlling. These conditions area listed next to the state transition arrows. A few example time slots from Figure 14. this condition is noted by the fact that both arrows leaving the “10” state bubble have Z2 outputs of ‘0’. we’ll be spending much more time with this later. The Z2 output is a ‘0’ independent of the value of X during Time Slot (1). the X input value at the next active clock edge is ‘0’. Also in state “10”. which is the Mealy-type output. Cross referencing this information into the state diagram you see that from state “10”. the specification primarily is the count you’ll need to implement. if X is a ‘0’. the Z1 output is a ‘1’ which is indicated by the number under the line in the “10” bubble.5 FSM Design Designing counters using FSMs is one of the more basic FSM design exercises. Once the state diagram is specified.

Figure 14. the state variables directly represent the count. Also. Show a PS/NS table and state diagram that describes the FSM. The starting value of the Y1Y2 outputs have no significance either. Figure 14. 384 . the changes in the Y1Y2 sequence are synchronized to the rising clock edge.Digital McLogic Design Chapter 14 implementing it with actual gates or with a VHDL model. First. From this wanton gaze you’ll be able to gather the following high level information.3. Once again.11 shows such a timing diagram. In yet other words. This simplifies the problem in that the FSM does not need to have an output decoder. Solution: This is a counter design problem. Step 1) Stare at the problem.2… . the problem did not mention anything regarding active clock edges so we are therefore free to choose either rising or falling clock edge. In this way. the external outputs from this FSM are none other than the state variables.0. Use one T and one JK flip-flop for each of the state variables. there are no external input variables. Provide flip-flop excitation equations in reduced form and draw the final circuit. As you’ll see in the upcoming design. For this case. There are two major items of significance in this drawing. the Y1Y2 row does indeed show the desired sequence listed in binary. there are two characteristics that make this design somewhat straight-forward.11: Example timing diagram for Example 14-2. there are simply less steps in the process. Example 14-2 Design a counter that counts in the following sequence: 0. As mentioned earlier. let’s draw a timing diagram that would represent the output of this problem. the desired count is the direct output of the flip-flops.11 that the FSM outputs are arbitrarily chosen to be Y1 and Y2. the design of FSMs implies that you’re taking a specification and generating a circuit.2. The basic design steps are outlined below. First. Step 1) Stare at the problem Step 2) Generate the states in the state diagram Step 3) Generate the state transitions for the state diagram Step 4) Generate the initial PS/NS table Step 5) Enter the next state information into the PS/NS table Step 6) Generate the excitation logic for the flip-flops Step 7) Generate the excitation equations for the flip-flops Step 8) Draw the final circuit Step 9) Commence celebration: (not a required step) Step 0) This isn’t really a step but it sure is a great idea. Notice in Figure 14. Before we go on with this problem. Y1 is the MSB as judged by the order of appearance. all the state transitions are unconditional which simplifies the entire process. the desired count is implemented as Moore-type outputs of the FSM. In other words. Secondly.1.

Step 2) Generate the states in the state diagram. Figure 14. All four states in the count sequence are represented. you can choose to implement the actual FSM using many different approaches. For this counter. Since there are four states. Step 3) Generate the state transitions for the state diagram. Figure 14. • The numbers in the required sequence are stated in decimal form.14 shows the resulting state diagram. the state transitions occur unconditionally on each active clock edge of the flip-flops. The implication here is that the actual implementation is in binary since the outputs of the flip-flops (where the state variables are stored) hold the count values. From this state diagram.11.13: Initial state diagram for Example 14-2. The state diagram is officially designed once you complete this step. Sometimes this will not be the case but since this is a simple counter it is the case for this problem. you’ll be able to implement this design using two flip-flops (as is implied by the problem statement). we only need to include the state transition arrows in the state diagram. the FSM unconditionally transitions from one state to the next as listed in the state diagram.Digital McLogic Design Chapter 14 • Looking at required sequence. Figure 14. Note that the variables Y1 and Y2 have been chosen for the state variables (which is arbitrary). • After you stare at this problem for awhile.13. This implies that on each clock edge.12: Black box diagram for the FSM of Example 14-2. you would have needed three flip-flops to implement the circuit. you can see that there are only four unique numbers in the sequence. there are no conditions to associate with these arrows. The decimal equivalents of the required binary count are provided below the state variable declarations for each state. As you will see in the remainder 385 . the sequence then repeats itself.13 shows the initial state diagram along with a legend. For this diagram. After each of the four numbers is encountered. Also note that there are no conditions listed on the state transitions in Figure 14.12 shows such a block box diagram. Figure 14. the choice of Y2 and Y1 are arbitrary but these choices nicely match the timing diagram musing of Figure 14. For this step. you realize that drawing block box diagram for this FSM is a really good idea. Figure 14. If there were five numbers in the required sequence.

15 shows the resulting PS/NS table. As you’ll no doubt agree after finishing this example.14: State diagram for the example problem. This “10” represents the state that the FSM will transition to on the next active clock edge. The initial PS/NS table will contain only the present and next state flavors of the state variables. the first of the PS/NS table is associated with the Y1Y2 = “00” state of the FSM (present state). Step 5) Enter the next state information into the PS/NS table. As you get used to the FSM implementation procedures.15: The initial PS/NS table for the example. State diagram design requires a mindset all its own. The remainder to of the PS/NS table is filled in by transferring the information from the state diagram to the PS/NS table. Note that in this table.14. Since there are two state variables (two flip-flops). Figure 14. This state transition represents the 0 → 2 count in the desired sequence. This is a simple example and we’re purposely not attempting to gather an all encompassing understand of FSM (we’ll be doing that soon though). the only complicated step is in the design of the state diagram: this is where the engineering and deep thought is required. Figure 14.16 shows the resulting PS/NS table. you’ll be able to design many powerful circuits. Step 4) Generate the initial PS/NS table. all possible combinations of the state variables Y1 and Y2 are represented in the columns labeled “PS”.14. once you grasp the intricacies of state diagrams (and there’s not that many of them). In reality. all these different approaches are not overly complicated. the PS/NS table will only contain four rows.Digital McLogic Design Chapter 14 of this example. you see that they become cookbook. Figure 14. The next state information is obtained directly from the state diagram of Figure 14. For example. the state variables associated with the next state are “10”. once the state diagram is generated. it becomes no big deal to implement the FSM using a circuit model. 386 . From looking at the state diagram of Figure 14. (PS) Y1 0 0 1 1 Y2 0 1 0 1 (NS) Y1+ Y2+ Figure 14.

We need to use the excitation tables to make these changes happen in our flip-flops. Knowing this information or being able to generate these tables really helps you out when working with these types of flip-flops. T.16 lists the changes in state variables (Y1 and Y2) that are required for this problem. the column labeled “T” is used to actuate the state change in the Y1 state variable for each associated row. The excitation logic is used as inputs to the flip-flops and in terms of the FSM. These tables are vastly important. For our example. and JK) that will cause the listed change (Q → Q+) in state for a given flip-flop. you should know this information by heart (even if it requires that you memorize it). Our main tool for this operation is the excitation tables associated with each flip-flop. T. D Flip-flop Q 0 0 1 1 Q+ 0 1 0 1 D 0 1 0 1 T Flip-flop Q+ 0 1 0 1 (b) Figure 14. columns labeled J and K are used to actuate the state change in the Y2 variable for each associated row. it is typical to include some extra columns with the PS/NS table in order to aid in the implementation of the actual circuit. and JK flip-flops. More specifically. the PS/NS table lists the present-state and next-state for each of the state variables (Y1 → Y1+ and Y2 → Y2+). and JK flip-flops. Even more specifically. 387 . These excitation tables were previously derived and are provided here for your convenience. Q 0 0 1 1 JK Flip-flop Q+ 0 1 0 1 J 0 1 K 1 0 Q 0 0 1 1 T 0 1 1 0 (a) (c) The excitation tables show input values (D. T. This excitation logic forces the flip-flops to output the desired counts in the specified order.Digital McLogic Design Chapter 14 (PS) Y1 0 0 1 1 Y2 0 1 0 1 (NS) Y1+ 1 0 1 0 Y2+ 0 0 1 1 Figure 14. Step 6) Generate the excitation logic for the flip-flops to be used in the FSM implementation. Although the PS/NS table is complete as shown in Figure 14.16.17: Excitation tables for the D. we need to be able to configure the T and JK flip-flops such that these transitions actually occur. we need to make it specific in the context of the T and JK flip-flops. the PS/NS table in Figure 14. we need to generate the excitation logic for these devices. These are once again shown in Figure 14. Since we’ll be implementing this FSM with a T and a JK flip-flop. forms the Next State Decoder. Since the PS/NS table already lists the desired state transitions for each of the two state variables.16: PS/NS table for the example. While the state transition information is somewhat generic.17 for the D.

17(c). From this excitation table.17(b) and search for the (Q → Q+) = (0 → 1) transition.18.18. this problem is a matter of using some of your previous skills to finish the problem. respectively. and K columns of the table represent functions. To obtain this transition on a T flip-flop. J. This value is a ‘1’. a 0 → 0 transition occurs when the JK inputs are values “0“. and K columns in Figure 14. If you successfully get someone else to do your work for you.18: The PS/NS table with logic for the T and JK flip-flops.Digital McLogic Design Chapter 14 We’ve somewhat arbitrarily decided to use a T FF and a JK FF for the state variables Y1 and Y2. in the first row of the PS/NS table. Figure 14. From this point. T = Y1 ⊕ Y 2 J = Y1 K = Y1 Figure 14. the Kmap is used to generate a Boolean expression for the data in each of the T.19 lists the final excitation equations for this example. and K logic shown in Figure 14. this information is then entered into the JK columns of the first row of the PS/NS table for this example. For this step. This is generally the case for two variable K-maps. The K-maps are not shown so as not to bore you to death any more than you’re already facing death by boring pointless problems. The remainder of the table in filled in accordingly.19: The excitation equations for this example. you’ll have the one and only skill necessary to be a academic administrator. this value is then entered in to the T column in the PS/NS table for this problem. J. the value of T that causes this transition is located in the T column of Figure 14. You are encouraged to actually generate these equations for yourself or trying to get some other sucker to do it for you5.17(b). The T and JK flip-flops are slightly more challenging than using a D flip-flop but we’ll redo this problem using D flip-flops after we complete this example. Since the Y2 → Y2+ transition is 0 → 0.18 shows the PS/NS table containing all the T and JK logic. A similar procedure is used for the JK values in the first row of the PS/NS table. For example. J. J. the Y1→ Y1+ transition is a 0 → 1. the J and K values that force this transition are read from the JK excitation table of Figure 14. Figure 14.17(b). you’ll need to generate equations for the T. J. and K columns. You’ll of course want to reduce the equations since you’ll be provided a circuit diagram that implements this example. From here on out. The good news here is that all of these equations can be generated by inspection of the T. The logic that is required for these equations for this problem are listed in the T. 5 388 . You’ll find this transition in the second row of Figure 14. K flip flop inputs. Step 7) Generate the excitation equations for the flip-flops. you see that the T. In this case. you examine the excitation table for T flip-flop shown in Figure 14. this is good because you’re currently an expert at implementing functions using useful tools such as K-maps. (PS) Y1 0 0 1 1 Y2 0 1 0 1 (NS) Y1+ 1 0 1 0 Y2+ 0 0 1 1 T 1 0 0 1 J 0 1 K 1 0 Figure 14.

Figure 14. But… the final circuit is shown in Figure 14.21: Model for a Moore-type FSM.21). The outputs of the flip-flops change and the process continues ad-nausuem. A quick analysis of the circuit shown in Figure 14. Figure 14. You should take a minute and get a feel for this circuit and how it operates. they are the state variables). • The problem never stated which edge of the clock was active. • The active clock edge arrives. the T. 389 . • The external outputs in this case are the state variables. and K inputs to the flip-flops become meaningful and cause state transitions (from the present-state to the next-state). J. then you obviously know what you’re doing. This also means there is no need for an output decoder (see Figure 14.20 cries out the following: • There are no external inputs to the circuit.Digital McLogic Design Chapter 14 Step 8) Draw the final circuit: This is generally a waste of time because if you’ve gotten this far.20 just in case you’re interested. at this point. RET flip-flops were arbitrarily used. • The next-state decoder is comprised of an exclusive-NOR gate.20: The final circuit for the example problem. This FSM is a Moore-type FSM due to the fact that the outputs are only a function of the state variables (in this case.

The D1 and D2 excitation logic can be generated by inspection of Figure 14.2… Solution: The nice thing about his example is that you can reuse most everything from the previous example. This being the case. The nice thing about using D flip-flops is the fact that the NS columns represent the excitation logic for the D flip-flops.23(a) shows the basic PS/NS table.23(b). you were asked to design a counter that counts in the following sequence: 0. We’ve modified the PS/NS table to include the columns for the D flip-flop logic as shown in Figure 14.1. For the previous problem.Digital McLogic Design Chapter 14 Example 14-3 Redo the previous example but use two D flip-flops in your design in place of the T and JK flip-flops. 390 . Up can note this by comparing the D1 and Y1+ columns in the PS/NS table shown in Figure 14.23(b). The state diagram is the same for both of these examples because the count sequence and the number of flip-flops required to implement this design are independent of the type of flip-flops used in the design.17(a) for the D1 and D2 flip-flops.22: State diagram reused for this example problem.24: The excitation equations for Example 14-3. (PS) Y1 0 0 1 1 Y2 0 1 0 1 (NS) Y1+ 1 0 1 0 Y2+ 0 0 1 1 (PS) Y1 0 0 1 1 Y2 0 1 0 1 (NS) Y1+ 1 0 1 0 Y2+ 0 0 1 1 D1 1 0 1 0 D2 0 0 1 1 (a) (b) Figure 14. Figure 14. Figure 14. The D1 and D2 flip-flops are used to implement the Y1 and Y2 state variables. Figure 14.24.0.3.2. D1 = Y 2 D2 = Y1 Figure 14. Since we are implementing this FSM using D flip-flops. Since the state diagram is the same for both examples the PS/NS table necessarily is the same also. this logic is shown in Figure 14.23: The PS/NS table for Example 14-3.23(b).22 shows the state diagram for this example. we use the excitation table shown in Figure 14.

Use one T flip-flop and one D flip-flop in your design. The dotted lines are included to impress upon you the fact that all the outside world needs to know of this circuit is the CLK input and Y1Y2 outputs. Example 14-4 Draw a circuit that implements the following state diagram. An outline of steps required to solve this problem is provided for your enjoyment.25(b) shows the associated block diagram for this FSM. It’s not like this happens too much. (a) (b) Figure 14. this problem takes the opposite approach.25: The PS/NS table for this example.25(a) shows the circuit implementation for this example.Digital McLogic Design Chapter 14 And as the final act of kindness. Often time in make-believe digital-land. This is not overly complicated in that you have previously used the PS/NS table to generate the state diagram. but in case this situation did come up. you’ll be given a state diagram and be asked to implement the state diagram using a specific set of flip-flops. This leads us to the solution in this particular problem: we must generate the PS/NS table. it would be helpful to you if you knew how to proceed when the state diagram is the starting point of your problem as it is in the next example. Solution: this type of problem is essentially an undoing of the previous flavor of design problem. Figure 14. This approach underscores that fact that the PS/NS table and the state diagram contain the same information: they are modeling the same thing. we used the PS/NS table in order to generate the excitation logic for the required flip-flops. If you can recall from a few pages ago. Minimize the amount of required combinatorial logic. What we need to do for this problem is generate the circuit. 391 . Figure 14.

26: The initial PS/NS table for Example 14-4. The FSM has one external input: X. The FSM also has two external outputs: Z1 & Z2. that would include both the present state of the state variables and the external input variable X. This should not be a glazed over stare. Y1 0 0 0 0 1 1 1 1 Y2 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 Figure 14. The important part of this step is to figure out how many rows are required in the associated PS/NS table. The Z2 input is listed with the X input with the state transition arrows. this should be a visual analysis of the information provided to you by the state diagram. In other words. For this FSM. the Z1 output must be Moore-type output. For this example. Some of the items you should be looking for in this step are listed below: • The state diagram contains four states as indicated by those funny little circle jobbers. Since the Z1 is listed with the state bubbles. • • Step 2) Generate the initial PS/NS table. The fact that the Z2 output has different values as associated with the arrows exiting the “11” state indicates that the Z2 output is a Mealy-type output.26 shows the initial PS/NS table. The state diagram includes a legend which is the key to understanding all the funky terminology listed in the state diagram. Note the state diagram list every possible combination of the two flip-flops states. Since there are two flip-flops required. Figure 14. there are going to be two present state variables.Digital McLogic Design Chapter 14 Step 1) Stare at the problem for while Step 2) Generate the initial PS/NS table Step 3) Generate the next state logic Step 4) Generate the excitation logic Step 5) Generate the output logic Step 6) Draw the final circuit Step 1) Stare at the problem for while. the Z2 output is a Mealy-type. This gives a grand total of three inputs and thus eight rows in the truth table. 392 . the Z2 output is different in state “11” which indicates that Z2 is a function of the X input. the independent variables are the inputs that directly affect the circuit. What this should indicate to you is that the circuit that implements this FSM will require two flip-flops. The extra columns that are included in this table are dealt with in later steps. by definition.

For the T flip-flop. (PS) Y1 0 0 0 0 1 1 1 1 Y2 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 (NS) Y1+ 1 0 1 0 0 0 0 0 Y2+ 0 0 1 1 1 0 0 1 Excitati n logic D1 1 0 1 0 0 0 0 0 T2 0 0 0 0 0 1 0 1 Figure 14. (PS) Y1 0 0 0 0 1 1 1 1 Y2 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 (NS) Y1+ 1 0 1 0 0 0 0 0 Y2+ 0 0 1 1 1 0 0 1 Figure 14. Figure 14. 393 . For this example. The data in these columns is taken directly from the state diagram. if the FSM is in the “00” state and the X in put is a ‘0’ when the next active clock edge arrives. the excitation logic for the D flip-flop is identical to the next state logic. apply the excitation tables for the flip-flops specified in the design are used to translate the Yx → Yx+ state transition information to excitation logic for the flip-flop inputs. For this design. This subsequently requires two columns in the PS/NS table.28 shows the resulting PS/NS table. The entire table is completed by using this approach to transfer information from the state diagram to the PS/NS table. For example. the FSM transitions to the “10” state. as read directly from the state diagram. we’ll need to represent the excitation logic with two excitation equations. Step 4) Generate the excitation logic. we’ll use a D flip-flop for Y1 and a T flip-flop for Y2. since there are two state variables. The “10” is then entered in to the table under the Y1+ and Y2+ headings. Similarly. For this step.28: The PS/NS table with including the excitation logic for Example 14-4. Figure 14. the next state will be “00”. This step is dependent upon the type of flip-flops specified in the design.27 shows the results of this step.27: The continued PS/NS table for Example 14-4. if the FSM is in state “00” and the X input is a ‘1’.Digital McLogic Design Chapter 14 Step 3) Generate the next state logic. As stated previously. state changes in the Y2 → Y2+ are represented by entering ‘1’ in the corresponding rows where the Y2 variable changed state.

(PS) Y1 0 0 0 0 1 1 1 1 Y2 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 (NS) Y1+ 1 0 1 0 0 0 0 0 Y2+ 0 0 1 1 1 0 0 1 Excitation Logic Output Logic D1 1 0 1 0 0 0 0 0 T2 0 0 0 0 0 1 0 1 Z1 1 1 0 0 1 1 0 0 Z2 0 0 0 0 0 0 1 0 Figure 14. but please don’t let this happen to you. The excitation logic and output logic was obtained by dropping the D1 and T2 columns into K-maps. the complemented Y2 signal is equal to the Z1 signal.30 is that a buffer circuit element has been used for the Z1 output. This FSM has two outputs: Z1 (Moore-type) and Z2 (Mealy-type). Note that in the original state diagram.29. the details are not shown so as to spare you a slow death from boredom. The buffer is a circuit element that does not alter the logic levels of the signal it processes. Keep in mind that the output is always based on the present state variables as listed in the PS/NS table. The fact that they come in pairs is based on our choice of placing X as the least significant of the independent variables. Note that since Z1 is a Moore-type output. the output values always appear in pairs in the PS/NS table. The Z2 output is a Mealy-type output which means its value can change while in a given state (between the active clock edges). you can see that the Z1 input is a ‘1’ when in states “00” and “10”. Step 6) Draw the final circuit. So for this signal. the Z1 output is not a function of the X input which is what we’d expect from a Moore-type output. Although the logic for these outputs is typically not part of the PS/NS table. the only time the Z2 output is a ‘1’ is in the “11” state under the condition that X equals ‘0’. The final circuit is shown in Figure 14. One thing worthy to note in the circuit diagram of Figure 14. 394 . This information is entered directly into the table in the Z1 column as shown in Figure 14. On the other hand. Figure 14. This results in the only ‘1’ being in the Z2 column of the output logic is located in the Y1Y2X = “110” row. It’s a common mistake to base the output logic on the next state logic.29: The PS/NS table with including the excitation logic for Example 14-4. Note that our Z2 output logic does in fact contain an X on the input which is what we would expect since Z2 is a Mealy-type output. it sure is handy to include it in the table. The next state columns represent the state the machine enter on the next active clock edge. From the state diagram.Digital McLogic Design Chapter 14 Step 5) Generate the output logic.29 shows the complete PS/NS table.30.

we really have not mentioned too much about FSM timing considerations. And finally. T. The study of FSMs can be broken into three parts. but these advantages are mitigated in FPGA-land (because FPGAs have a lot of D flip-flops on-board). and JK) when implementing our FSMs6. the FSM would be used to control some other circuit. both outputs were a function of the present state of the FSM but Mealy-type outputs were also a function of external inputs. Moore FSM Our FSM discussion up to this point has been primarily centered on both design and analysis. The FSMs were defined with either a PS/NS table or a state diagram (both presented the same information but in a different format). You know the first part: the design and analysis of FSMs.6 Timing Diagrams: Mealy vs. The other problems are too numerous to mention here (and painfully well-known by all).30: The PS/NS table with including the excitation logic for Example 14-4. an associated timing diagram that adheres to the state diagram can be easily generated. 7 The inadequate treatment of timing diagrams by most digital design textbooks is well-known. We also had several flip-flops to choose from (D. And since FSMs are defined rather nicely with state diagrams.Digital McLogic Design Chapter 14 Figure 14. PLD-based implementations primarily use D flipflops (more on this later). The T and JK flip-flops have their advantages. this is found in a later chapter. there is more to FSMs than designing counters of various types. In reality. We knew that the storage elements (the flip-flops) were edge-triggered which allowed transitions between states to only occur on the associated clock edges. The final part is to design a FSMs from a given specification. we knew that ultimately. This section is primarily concerned with timing diagrams and their relation to FSMs. Up until now. The FSMs had external inputs and external outputs which were generally named with X and Z variables. Possibly our only mention of the timing associated with the FSMs was that the state transitions only occurred on a clock edge. 6 Although we could choose between the three different types. The importance of timing diagrams is typically passed over by standard digital logic textbooks7. The external inputs (X) would provide information to the FSM which would subsequently be used to synthesize control signals on the FSM’s output variables (Z). And despite what several other cal poly faculty members think. 395 . respectively. 14. The second part is to develop a basic understanding of state diagrams which is also dealt with in this chapter. you’re missing a big part of the story: the underlying timing diagram. The external outputs could either be Moore-type or Mealy-type. From any state diagram. this is the best place to start this discussion.

In my opinion. This section is centered around a few example problems that will hopefully help you understand FSMs on an intuitive level. Example 14-5 Draw a state diagram that could be used to generate the timing diagram shown in Figure 14. X is an external input and Z1 and Z2 are external outputs. Consider CLR to be an active low signal that resets the FSM.31: Timing diagram for Example 14-5. Solution: The first thing to do with a problem like this is to stare at it and try to figure things out. you’ll be able to take the final plunge in FSM-land: generating your own timing diagram from a set of specifications. you’d notice items such as the things listed below.Digital McLogic Design Chapter 14 14. 396 . Figure 14. understanding this relationship is the most challenging part of developing a solid understanding of FSMs. The good thing about exploring this relationship is that it clearly shows the relationship between the Mealy outputs listed in state diagrams and the effect they have on the associated timing diagrams. If you were to do this for long enough. • The FSM has one external input: X. Understanding FSMs on this level is the key to being able to design real FSM circuits that actually do something other than count (did I already deliver that insult?).1 Timing Diagrams and State Diagrams There are some classic problems associated with the relationship between timing and state diagrams. • The FSM has two external outputs: Z1 and Z2. But once you have this understanding. under most circumstances. you should be able to generate a state diagram from a timing diagram and/or vice-versa. The thought here is that.6.31.

32: The results after the first step of Example 14-5 solution. In later examples we’ll look at some Mealy-type outputs. • The outputs Z1 and Z2 are both Moore outputs. Figure 14. The problem is now ready to be solved. Note that in this step. Step 1) The first real step in the process of solving this problem would be to generate a simple state diagram that lists only the states and the state transitions. This means you should group the variables into some order such as Y1Y2Y3. it is obvious from examining the timing diagram: notice that all the state changes occur on the risingedge of the clock signal. the ordering does not matter. This fact is not only listed by the CLK signal. Be sure to note the method used to represent the asynchronous CLR input. The task you should do is to explicitly list the states in terms of the state variables.31. But upon further examination of the timing diagram you’ll notice that only one of the three state variables is in a high state at one time. Initially you may start thinking that there are eight possible states in this FSM which is not a bad thought because there is a possibility that this FSM uses binary encoding. 397 . Figure 14.31. • The clock is rising-edge triggered (RET). you can glean a lot of information. Keep in mind that the hardest part of doing this problem may be to stay neat and organized. • There are three state variables.Digital McLogic Design Chapter 14 • The FSM is put into a known state by the CLR signal in the first time slot and then has no effect later in the timing sequence. The results of this preliminary step are shown in upper left portion of Figure 14. You know this because all of the changes in these outputs occur at the same time as changes in the state variables. You should do the same for the output variables such as Z1 and Z2. This is a straight-forward process that is accomplished by reading the information from the state variables and the associated transitions from the timing diagram of Figure 14. In order to stay organized.32 shows the results of this step. you may want to explicitly list the state variables in each of the time slots of Figure 14. This indicates that the FSM is one-hot encoded. What does matter is that you document what you’re doing in a legend that is included with your state diagram.32. This should be your approach of choice for all of these problems because a solely mechanical approach can sometimes bypass true understanding of the problem and is certainly not an approach taken by most engineers. So without really doing much work with this example.

you can see that the output Z1 is a ‘1’ except in state “100” and output Z2 is a ‘1’ in all states except “001”. Figure 14.33: The results after Step 2 in the Example 14-5 solution. since there are two arrows leaving each state bubble. Figure 14. The value of the outputs for each state is determined by examining the timing diagram for each output. 398 . As you would expect.Digital McLogic Design Chapter 14 Step 2) Now that you have listed all the possible state transitions. they can be (and should be) included with the state bubbles. Consider CLR to be an active low signal that resets the FSM. It appears that the person who generated this problem did a fine job. Step 3) The final step is to include the outputs in the state diagram. If the person who drew the state diagram did a decent job. Example 14-6 Draw a state diagram that could be used to generate the timing diagram shown in Figure 14.35.34 shows the final solution for this example.33 shows the results of this step. Since these are Moore outputs. the state transitions are based on external input. Figure 14. Figure 14. list the external conditions that allow the state transitions to occur. X1 is an external input and Z is an external output. When you perform this step. then there should be no ambiguities in the outputs in the context of the various states.34: The final solution for Example 14-5.

Step 1) Draw a legend and a state diagram that shows only the state transitions. In other words. 399 . taking a quick look at the problem (which always should be your first step in solving these problems) should yield the following information: • The FSM has one external input: X1. it is obvious from examining the timing diagram: all the state changes occur on the rising-edge of the clock signal. But besides that. In this way. You can see this by the fact that changes in this output occur at places other then the active clock edges. can be ignored. unlisted state transitions.Digital McLogic Design Chapter 14 Figure 14. you don’t need to worry about what bits are representing the states. The information required for this step is taken from the state line of the timing diagram shown in Figure 14. • The FSM is put into a known state by the CLR signal in the first time slot and then has no effect later in the timing sequence. • The clock is rising-edge triggered (RET). This fact is not only listed by the CLK signal. • The output Z is a Mealy output. You can make the assumption in these types of problems that the provided timing diagram provides all the information you need to do the problem. The outputs in Example 1 were Moore-type and changed with the states (on the clock edge).35. The main difference between these problems is that Example 14-6 lists symbolic names for the states rather than listing the state variables as was done in Example 14-5. should they actually exist. • The FSM has one external output: Z. Solution: The approach to solving Example 14-6 is similar to Example 14-5.35: Timing diagram for Example 14-6. • There are three states in this FSM which you can derive by counting the different letters in the state row of the timing diagram. The Z output in this example are sometimes synchronized to changes in the X1 input (and with the state variables which change on the active clock edge) which implies that Z is a function of X1.

400 . Step 3) Add the values for the output variable. Note that there are two conditions associated with the transition from state c to state a. Figure 14.36: The results of Step 1 for Example 14-6.38(b). This information is derived from examining the X row of the timing diagram. And the example is complete. Step 2) In the state diagram. the output may be different depending on the X1 input. Figure 14. We’ll check for this condition in the next step.38(a) shows the results of this step.37 shows the results of the current step.Digital McLogic Design Chapter 14 Figure 14. you need to wait until you see what the output is doing. Figure 14. The output variable Z is a Mealy-type output its value should be placed along side the input values in the state diagram. Notice that the value of the input variable does not matter for state (c) to state (a) state transition: the output Z is always a ‘0’ which is listed in a more intelligent manner with the don’t care symbol appearing in Figure 14. it is an unconditional transition from state c to a. list the conditions that cause the various state transitions listed in Figure 14.36. In other words.37: The results of Step 2 for Example 14-6. Although this may seem like a condition where you would place a don’t care (a transition that happens on the clock edge regardless of the input conditions). but.

If you are so bold as to take this step. X1 and X2 are external inputs and Z is an external output. Figure 14.38: The results of Step 3 for Example 14-6.40. Consider CLR to be an active low signal that resets the FSM. Solution: This example is slightly different from the previous two examples.39 to complete the timing diagram shown in Figure 14. Example 14-7 Use the state diagram in Figure 14.Digital McLogic Design Chapter 14 (a) (b) Figure 14. The timing diagram is missing information for output Z and as well as the values of the states in each of the time slots. It is the same basic FSM idea but the state diagram is given and you are asked to complete the timing diagram.39: The state diagram for Example 3. The approach to solving this problem is similar in that before you start. you should stare at the problem and see what is going on. you will be able to discern the following: 401 .

40: The uncompleted timing diagram of Example 14-8. The fact that the Z output has two different values associated with state (a) indicates that the output is Mealy-type output. • There are three states in this FSM which you can gather by counting the different letters in the state diagram. To fill in the other empty state boxes. The output from the other two states essentially acts like a Moore-type output since they are for the given transitions from that state. • The FSM has one external output: Z. the FSM is initially reset in the time slot before the first clock edge. This is shown by the empty boxes in the state row of Figure 14. Figure 14. you first need to establish a starting point. you need to consider the present state and the input values that control the transitions from that state.Digital McLogic Design Chapter 14 • The FSM has two external inputs: X1 and X2. it is obvious from examining the timing diagram: all the state changes occur on the rising-edge of the clock signal. This fact is not only listed by the CLK signal. The key point to remember here is that the outputs are associated with the state that the arrow is leaving. state (a) would be entered into the first box in the state row in the timing diagram. Luckily for us. • The clock is rising-edge triggered (RET). • The FSM is put into a known state by the CLR signal in the first time slot and then has no affect later in the timing sequence. this CLR signal places the output into state (a). this characteristic is only true of state (a) . • The output Z is a Mealy output. You should expect to see this characteristic in the timing diagram once it is completed. Thus. You can see this by examining the state diagram. transitions from this state are controlled by 402 . By examining the state diagram. You can thus expect the Z output to be changing with the X2 input because the output is a function of the X2 input which is indicated in the state diagram. To do this. the initial state of this example. Notice that the two transition arrows leaving state (a) have different values of the Z output. Step 1) The first step in this solution is to once again fill in the state transitions.40. For state (a).

in the first time slot (where the resent takes place). the FSM is in state (a). the value of the Z output is based on the value of the X2 input. For example. This approach is taken for the entire Z row in the timing diagram. 403 . you’ll notice that the output is always a ‘0’ which is independent of any input variable. Figure 14. This approach is continued for every state in the state row. in state (a). you need to examine the state diagram for each state. From the state diagram. The second time slot is associated with state (c). You’ll also notice that state (b) has the same condition.41 shows the results of this step.Digital McLogic Design Chapter 14 the X2 input. To do this step. if X2 input is a ‘1’. Notice that the state transitions associated with states (a) and (c) are dependent upon the X2 variables while state transitions associated with state (b) are associated with the X1 variable. the FSM transitions from state (a) to state (b). What makes it a true Mealy-type output is the output conditions associated with state (a). Figure 14. Figure 14. In state (c). in state (a) the Z output is dependent upon the value of the X2 input. if X2 is a ‘1’. In states (b) and (c). In other words. you’ll see that this input is a ‘1’ so the FSM transitions to state (c). If X2 is a ‘0’. Step 2) The second and final step associated with this example is to fill in the Z output based the present state and the X1 and Z2 inputs. the output Z actually has Moore-type qualities. Examining the state diagram. the FSM transitions from state (a) to state (c). A viable approach to these problems is to fill in the Moore outputs first since they require less neurons to successfully complete. To discern the state transition on the first clock edge. Therefore the Z output would state in the ‘0’ state. the Z output is a ‘0’. you must first check the state of the X2 input in the associated state diagram. More specifically.41: The results after the first step in the solution of Example 3.42 shows the final results.

3. we will need three flip-flops. The next example sheds light on the problem. The tendency here is to draw the desired sequence first as shown in Figure 14.5… For this example. Now consider the case where we have a count sequence of five numbers that we want to implement using a FSM. 404 . The question that arises is what exactly happens to the other states? The answer is illegal state recovery.6.0. 14. Figure 14. The potential problem here is that with three flipflops.42: The final result for Example 3. Solution: This problem is similar to the other counter problems except there are more numbers in the count sequence. we can represent up to eight states.43.5. For this case.7. The first step in problems such as these is to draw the state diagram. provide a PS/NS table only.43: The initial state diagram for Example 14-8. For example. Make sure all unused states are directed to state 0. Note that out FSM designs up to this point have magically used every code available in the count sequence or state diagram. This problem is special in that we need to represent the states not listed in the counting sequence.Digital McLogic Design Chapter 14 Figure 14. Use only D flip-flops in your design. Example 14-8 Design a counter that counts in the following sequence: 0.7 FSM Illegal State Recovery The state machines we’ve examined at this point have had a certain quality that is not always present in all FSM design. both of the examples we’ve explored contained four states which was the maximum number of states that could be represented using two flip-flops.

It just may happen that the noise places you in a state that is not part of the desire sequence. but it is not known which state until equations for the excitation logic is completed. the “100” state is a self-looping hang state. Figure 14. if life is good. meaning we did not care about them. the unused states of 1. the unused states would be directed to some other state. The FSM is thusly hung because it is stuck in a hang state. In this way. If we had not listed these states. After that. Figure 14.45 shows an example of a state diagram with hang states. we may end up with a state diagram that has hang states. FSM never strays from that sequence. 2. The “001”-“010” pair is a small cycle. The thought here is that there is some magic entity that assures your FSM will always start in a certain state in the desired sequence.45 we do indeed have the desired sequence. In either case.Digital McLogic Design Chapter 14 The first attempt to represent the unused states would maybe appear something like what is shown in Figure 14. A loud stereo will most likely have not effect on your digital circuit designs. the unused counts in the sequence appear as “don’t cares” in the excitation input columns in the PS/NS table. Note that in Figure 14. but we also have the unused states included in a pattern that could actually be implemented as a result of our particular choice for the excitation logic.44. Keep in mind that the excitation logic for these examples is completed using K-maps. 405 . But in reality. Figure 14. In the state diagram.45 shows two flavors of hang states. and 4 are shown but it is initially unclear what to do with them. That means they are susceptible to various types of noise8. we could don’t cares into the associated row of the PS/NS table. FSM are implemented with actual circuits (it’s the electronic thing). if we do not explicitly direct all the unused states back to the desired counting sequence. Recall that it is the K-map groupings that decided if the don’t cares are assigned a ‘1’ or a ‘0’. If this happens. In this state diagram. you’ll never make it back to the desire sequence. What we’re trying to avoid in this problem is the generation of as hang states. Bummer! 8 This refers to unwanted electronic effects.44: The PS/NS table for Example 14-8. there is no path back to the original counting sequence.

46: The final PS/NS table for Example 14-8. Figure 14. you’ll quickly (in one clock cycle) return to a count in the sequence.Digital McLogic Design Chapter 14 Figure 14. Figure 14. The problem description states that you should direct all of your unused states back to state “000”.47: The state diagram with hang-state recovery. The approach that saves the day is to direct the unused states back to a state in the desired count sequence. But all is not lost. Figure 14. if for some reason you do find yourself in a hang state. 406 . it is not a big deal to generate the PS/NS table using techniques we’ve used in previous examples. From this point. In this way. (PS) Y1 0 0 0 0 1 1 1 1 Y2 0 0 1 1 0 0 1 1 Y3 0 1 0 1 0 1 0 1 Y1+ 1 0 0 1 0 1 0 0 (NS) Y2+ 0 0 0 1 0 1 0 1 Y3+ 1 0 0 0 0 1 0 1 Excitation Inputs D1 D2 D3 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 Figure 14.45: A state diagram containing hang states and other terrible things.47 shows the resulting state diagram.46 shows the final PS/NS table for this example.

8 Modeling Counters with VHDL Now that you’re on the last few pages of a long chapter. you’ll be able to easily see how to modify the counters to fit your needs in many different digital situations. But the first step as always is to draw the black box diagram of the circuit as is shown in Figure 14.Digital McLogic Design Chapter 14 (PS) Y1 0 0 0 0 1 1 1 1 Y2 0 0 1 1 0 0 1 1 Y3 0 1 0 1 0 1 0 1 Y1+ 1 0 0 1 0 1 0 0 (NS) Y2+ 0 0 0 1 0 1 0 1 Y3+ 1 0 0 0 0 1 0 1 Excitation Inputs D1 D2 D3 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 Figure 14. the FSM is said to be self-correcting. 9 A “nothing fancy” counter would be a counter that counts up or down by a set value (generally up (+1) or down (1)). you don’t need anything fancy9. you’re going to have unused states in your FSM as a result of the binary nature of the elements that are used to store the state variables. A special counter would be all the other counters that did not count in this manner.50. The idea here is to look at the problem description and then look at the solution and see how things are done. This means that if the FSM were to find itself in some undesired state. 407 . There is nothing new in this diagram so we’ll switch over to the description of the VHDL model appearing in Figure 14. Making you FSM designs self correction is important because statistically speaking. This counter should contain a parallel load and an asynchronous reset capability also.48: PS/NS table for the Example 14-8. The good news is that non-fancy counters are particularly straight-forward to model in VHDL. Solution: This is actually somewhat tough to state as a problem. the FSM would eventually find it way back to the desired portion of the FSM. it turns out that most of this chapter has been somewhat of an academic exercise. While there are occasions when you’ll need some type of counter that counts with a special count. This section describes two generic counters that you see quite often out there in digital land. From these descriptions. most of the time when you need a counter. Example 14-9 Provide a VHDL model for an 8-bit up/down counter.49. Now that we included illegal state recovery in our FSM design. 14.

CLK.50: VHDL model for 8-bit up/down counter with assorted features. Figure 14. end if. RESET) begin if (RESET = '1') then t_cnt <= (others => ‘0’).UP : in std_logic. -. -.asynchronous clear elsif (rising_edge(CLK)) then if (LD = '1') then t_cnt <= DIN. -. COUNT : out std_logic_vector (7 downto 0)).decrement end if. COUNT <= t_cnt. architecture my_count of COUNT_8B is signal t_cnt : std_logic_vector(7 downto 0).LD.1.parallel load else if (UP = '1') then t_cnt <= t_cnt + 1. The VHDL model for the up/down counter has some fun aspects. end COUNT_8B. end my_count.asynchronous reset ----------------------------------------------------------------------entity COUNT_8B is port ( RESET. -. A few of the more important aspects are described below for you comfort and enjoyment. -----------------------------------------------------------------------.49: Black box diagram for 8-bit up/down counter. begin process (CLK. end if. 408 . DIN : in std_logic_vector (7 downto 0). end process.Digital McLogic Design Chapter 14 Figure 14.model for 8-bit up/down counter with parallel load and -.increment else t_cnt <= t_cnt .

they can count either up or down. This also works with assigning all ‘1’. By the way this model is written. By the way this model is written. Figure 14. It is mostly self-explanatory. the parallel load is synchronous. The term: “others => ‘0’” is a shorthand notation meaning “assign all 0’s to something”.51 shows a model for a generic clock divider that takes in one input and provides two outputs of slower frequencies. This notation can be somewhat confusing if you’re looking for a “DOWN” signal. 409 . There is a lot of fun and new VHDL stuff that I’ll someday describe but I just don’t feel like writing it all down now. they make people think you’re a digiot (pronounced “dij-ee-it”). or all Z’s. 11 Try to avoid long names such as this one. This is a good practice in VHDL as it makes your code generic which is generally considered a good thing.Digital McLogic Design Chapter 14 • This counter looks a lot like the standard D flip-flop model. That’s because a counter is just another sequential circuit but with some added features. This means that the math associated with the “+” plus operator is done automatically in this context. The fact that the statement “tcnt <= tcnt + 1” works is that the “+” (and “-“)10 operator has been overloaded. if UP = ‘0’. ask questions if you have them. he Counters such as this are referred to as up/down counters because. This allows you to assign all zero’s to a signal without having to know the exact bit-length of the signal. Please not the similarities. but this could have been written differently also. the parallel load signal takes precedence of the up/down count control signal. • • • • • • Another application for counter is clock dividers. The description of the RESET signal is such that this signal is asynchronous. This context includes the fact that you’re added a constant to a STD_LOG_VECTOR type. If the “UP” signal was active low. it would be label something like “N_UP” or “UP_N” or “UP_NOT” or “THIS_UP_INPUT_IS_NEGATIVE_LOGIC”11. the counter is counting down. It could have been made into a synchronous RESET instead. The “UP” signal is implied to be active high so that then UP = ‘1’ the counter is counting up. No surprise. 10 As well as a lot of other operators that we’re purposely not mentioning here… check your VHDL source for the full story. The “UP” input controls whether the counter is incrementing (counting up) or decrementing (counting down). but this is all fairly typical out there in VHDL counter-land. This is massively important to know in the case where you plan on continuing on in VHDL land. It could have also been made into a synchronous or asynchronous SET instead. This of course could have been written to be asynchronous instead.

SCLK <= tmp_clks.Digital McLogic Design Chapter 14 -----------------------------------------------------------------------. div_cnt := 0. begin if (rising_edge(clk)) then if (div_cnt = MAX_COUNT_FAST) then tmp_clkf <= not tmp_clkf.SCLK : out std_logic).clock divider Figure 14. end process my_div_slow.tmp_clks) variable div_cnt : integer := 0. FCLK. div_cnt := 0. signal tmp_clks : std_logic := '0'. end my_clk_div.Module to divide the clock ----------------------------------------------------------------------entity clk_div_fs is Port ( CLK : in std_logic. end clk_div_fs. -. signal tmp_clkf : std_logic := '0'.clock divider -. end process my_div_fast. else div_cnt := div_cnt + 1. begin my_div_slow: process (clk. end if. else div_cnt := div_cnt + 1.tmp_clkf) variable div_cnt : integer := 0.51: VHDL model a clock divider model that divides the output by two different values. end if. end if. end if. FCLK <= tmp_clkf. begin if (rising_edge(clk)) then if (div_cnt = MAX_COUNT_SLOW) then tmp_clks <= not tmp_clks. constant MAX_COUNT_FAST : integer := (1100). architecture my_clk_div of clk_div_fs is constant MAX_COUNT_SLOW : integer := (9000000). 410 . my_div_fast: process (clk.

FSMs can be designed such that they contain no hang states by designing them to have illegal state recovery attributes. 2) the State Variables. The two major types of FSMs include the Mealy machine and the Moore machine. The state variables are generally implemented with flip-flops and represent the only sequential part of a FSM. and 3) the Output Decoder. FSM designs that do not contain hang states are said to be self-correcting. • • • 411 .Digital McLogic Design Chapter 14 Chapter Summary • The basic model of a FSM includes three major parts: 1) the Next State Decoder. These two FSM types differ in only the output decoder: the outputs on a Moore machine are a function of the state variables only while the outputs of a Mealy machine are a function of both the state variables and the external inputs. FSM analysis starts with a circuit diagram and generates a state diagram and/or a PS/NS table. FSM design starts with either a state diagram or PS/NS table and generates a circuit diagram.

Output sequence = 2.6. and a JK flop-flop for the LSB (least significant bit).1. 3) For the following output sequence. design a synchronous counter that repeats the given sequence indefinitely. 4) 412 . provide a PS/NS table and a state diagram that describes the circuit. Make sure all excitation equations are in reduced form.Digital McLogic Design Chapter 14 Chapter Exercises 1) Analyze the following circuit and provide a PS/NS table and a state diagram associated with the circuit. design a synchronous counter that repeats the given sequence indefinitely. A Moore output Z is high only when the count is less than 3 in the intended counting sequence. Include the output variable Z in both the PS/NS table and the state diagram.3. Make sure all excitation equations are in reduced form. Show a PS/NS table and state diagram that accounts for used states. 2) For the following circuit. Don’t draw the circuit – just provide the required excitation equations. Output sequence = 2. Don’t draw the circuit – just provide the required excitation equations. Include the Z output in both the PS/NS table and state diagram. a T flip-flop for the middle bit. Use a D flip-flop for the MSB (most significant bit). and a JK flopflop for the LSB (least significant bit). Show a PS/NS table and state diagram that accounts for used states. You should only provide illegal-state recovery from state 7 (direct this state to state 5). For the following output sequence.5.0. a T flip-flop for the middle bit. Be sure to provide a legend for you FSM.0.4. You should only provide illegal-state recovery from states 3 and 4 (direct these states to state 6). Use a D flip-flop for the MSB (most significant bit). A Moore output Z is high only when the count is less than 3 in the intended counting sequence.5.

Include the Z1 and Z2 output variables in both the PS/NS table and the state diagram. Output sequence = 2. 413 . Use a D flip-flop for the MSB (most significant bit). You should only provide illegal-state recovery from state 2 (direct this state to state 7). Output sequence = 0.6. provide a PS/NS table and a state diagram that describes the circuit. and a JK flop-flop for the LSB (least significant bit). design a synchronous counter that repeats the given sequence indefinitely.7. provide a PS/NS table and a state diagram that describes the circuit. Be sure to provide a legend for you FSM. Make sure all equations are in reduced form.1. Show a PS/NS table and state diagram that accounts for used states. For the following output sequence.0. design a synchronous counter that repeats the given sequence indefinitely.3.5. a T flip-flop for the middle bit. You should only provide illegal-state recovery from states 3 and 4 (direct these states to state 2). Make sure all excitation equations are in reduced form.6. A Moore output Z is high only when the count is an odd number in the intended counting sequence. For the following circuit. and a JK flopflop for the LSB (least significant bit). 5. Don’t draw the circuit – just provide the required excitation equations. Use a D flip-flop for the MSB (most significant bit). Don’t draw the circuit – just provide the required excitation equations.Digital McLogic Design Chapter 14 5) For the following output sequence. Include the output variables Z1 and Z2 in both the PS/NS table and the state diagram. 6) 7) 8) For the following circuit. A Moore output Z is high only when the count is less than 3 in the intended counting sequence.4. Show a PS/NS table and state diagram that accounts for used states. a T flip-flop for the middle bit.

10) Draw a circuit that implements the following state diagram. 414 . Use one T flipflop and one JK flip-flop in your design. provide a PS/NS table and a state diagram. 11) For the following circuit.Digital McLogic Design Chapter 14 9) Draw a circuit that implements the following state diagram. Use only D flipflops in your design. Include the output variable Z in both the PS/NS table and the state diagram. Minimize the amount of required combinatorial logic. Minimize the amount of required combinatorial logic.

and a JK flop-flop for the LSB (least significant bit).6.2.5. a T flip-flop for the middle bit.3. Show a PS/NS table and state diagram that accounts for all states.4. Sequence = 1. Use a D flip-flop for the MSB (most significant bit). Use positive edge triggered flip-flops and use a D flip-flop for the MSB (most significant bit). Provide illegal-state recovery by directing all unused states to state 6.4. provide a PS/NS table and a state diagram. For the following output sequence. design a synchronous counter that repeats the given sequence indefinitely. design a synchronous counter that repeats the given sequence indefinitely. Make sure all excitation circuitry are in reduced form.7. Make sure all excitation circuits are in reduced form. Provide illegal-state recovery by directing all unused states to state 1. Show a PS/NS table and state diagram that accounts for all states. design a synchronous counter that repeats indefinitely. Don’t draw the circuit – just provide all excitation equations. Don’t draw the circuit – just provide all excitation equations.5. Include the output variables Z1 and Z2 in both the PS/NS table and the state diagram. Show a PS/NS table and state diagram that accounts for all states. Use a D flip-flop for the MSB (most significant bit).5. Make sure all excitation circuits are in reduced form. Sequence = 2. Provide illegal-state recovery by directing all unused states to state 7.Digital McLogic Design Chapter 14 12) For the following circuit. 13) For the following output sequence. Sequence = 7.6.1. and a JK flop-flop for the LSB (least significant bit).2. a T flip-flop for the middle bit. a T flip-flop for the middle bit. and a JK flop-flop for the LSB (least significant bit). 14) 15) 415 . For the following output sequence. Don’t draw the circuit – just provide all excitation equations.

Y 2. 17) Design a counter that counts in the following sequence: 0. Show the old state diagram and the new state diagram and account for all possible states. Y 3) = ∑ (0. Don’t draw the circuit.7) D 2(Y 1.0.2. Show a PS/NS table and state diagram that describes the FSM. Y 3) = ∑ (2. Y 2. Don’t draw the final circuit. Include the output variable Z in both the PS/NS table and the state diagram. redesign the counter and make it self-correcting by sending unused states to any state in the 5-number sequence.3. Use T or JK flip-flops for each of the state variables and use binary encoding. Don’t draw the final circuit. Y 2.0… Provide illegal-state recovery into state 3.3. D1(Y 1. 18) The following equations describe a counter that steps through a 5 number sequence. Write the reduced excitation equations for the D flipflops and the equations for the Z1 and Z2 outputs.4. The counter only uses D flip-flops. Using the equations below.6.2.6.Digital McLogic Design Chapter 14 16) The following state diagram is to be implemented using D flip-flops and any type of discrete logic gates.6) 19) For the following circuit. Y 3) = ∑ (1. Provide new D excitation equations in compact minterm form.4. provide a PS/NS table and a state diagram.3.3. Provide flip-flop excitation equations in reduced form. 416 .7) D3(Y 1.

provide a PS/NS table and a state diagram. 22) For the following circuit. Don’t draw the final circuit. provide a PS/NS table and a state diagram. Include the output variables Z1 and Z2 in both the PS/NS table and the state diagram. Include the output variable Z in both the PS/NS table and the state diagram. 21) The following state diagram is to be implemented using D flip-flops and any type of discrete logic gates. 417 . Write the reduced excitation equations for the D flipflops and the equations for the Z1 and Z2 outputs.Digital McLogic Design Chapter 14 20) For the following circuit.

provide a PS/NS table and a state diagram. Include the output variable Z in both the PS/NS table and the state diagram. 24) For the following circuit. Include the output variable Z in both the PS/NS table and the state diagram.Digital McLogic Design Chapter 14 23) For the following circuit. provide a PS/NS table and a state diagram. 25) For the following circuit. Include the output variable Z in both the PS/NS table and the state diagram. 418 . provide a PS/NS table and a state diagram.

provide a PS/NS table and a state diagram. 419 . provide a PS/NS table and a state diagram. Include the output variables Z1 and Z2 in both the PS/NS table and the state diagram. Include the output variable Z in both the PS/NS table and the state diagram. 27) For the following circuit. 28) For the following circuit. Include the output variable Z in both the PS/NS table and the state diagram.Digital McLogic Design Chapter 14 26) For the following circuit. provide a PS/NS table and a state diagram.

420 .Digital McLogic Design Chapter 14 29) For the following circuit. 31) For the following circuit. provide a PS/NS table and a state diagram. Include the output variables Z1 and Z2 in both the PS/NS table and the state diagram. provide a PS/NS table and a state diagram. Include the output variable Z in both the PS/NS table and the state diagram. 30) For the following circuit. provide a PS/NS table and a state diagram. Include the output variable Z in both the PS/NS table and the state diagram.

Include the output variables Z1 and Z2 in both the PS/NS table and the state diagram.Digital McLogic Design Chapter 14 32) For the following circuit. Assume state transitions occur on the rising edge of the clock signal. Show how the inputs affect the state transitions and output Z by filling in the “state” and “Z” lines in the timing diagram. Assume CLR is an asynchronous. active low input. 33) Use the following state diagram to complete the timing diagram provided below. 421 . Assume all setup and hold times have been met and that propagation delay times are negligible. Be sure to include a legend for your state diagram. provide a PS/NS table and a state diagram.

Assume CLR is an asynchronous. active low input. Assume state transitions occur on the rising edge of the clock signal.Digital McLogic Design Chapter 14 34) Use the following state diagram to complete the timing diagram provided below. 422 . Assume all set-up and hold times have been met. Show how the inputs affect the state transitions and output Z by filling in the “state” and “Z” lines in the timing diagram.

Assume state transitions occur on the rising edge of the clock signal. Show how the inputs affect the state transitions and outputs Z1 and Z2 by filling in the “STATE”. Assume all setup and hold times have been met and that propagation delay times are negligible. Assume all setup and hold times have been met and that propagation delay times are negligible. active high input. Show how the inputs affect the state transitions and outputs Z1 and Z2 by filling in the “STATE”. 423 . “RD”. Assume INIT is an asynchronous. active low input. Assume state transitions occur on the rising edge of the clock signal. Assume INIT is an asynchronous. and “CS” lines in the timing diagram. and “Z2” lines in the timing diagram. “Z1”.Digital McLogic Design Chapter 14 35) Use the following state diagram to complete the timing diagram provided below. 36) Use the following state diagram to complete the timing diagram provided below.

Digital McLogic Design Chapter 14 424 .

The idea of behind engineering notation is to restrict the form that numbers can be written in. We need to take a look at some the timing/clocking issues associated with FSM design. they are important to creating FSMs that not only work.7 x 10-4 can be represented in an infinite number of equivalent ways. we’ll apply some prefixes to the units involved in order to do away with the exponential notation. PRACTICAL DEVICE ASPECTS: Digital circuit elements are physical devices are therefore have basic limitations based on device physics. This chapter describes some of the attributes in the context of clocking basic FSM circuits. In this day and age.2 Engineering Notation As you are probably finding out by now. DIGITAL DESIGN OVERVIEW: Many useful digital circuits contain what is generally considered to be a system clock.1. The topic of FSMs is a deep subject and there are many issues we have not dealt with and won’t be dealing with in this course. This chapter therefore describes some of the basic terminology associated with clocking signal. there are a few other issues are that we need to deal with in order to provide you with a wellrounded foundation of FSM design and analysis. engineering notation is the standard used in the engineering profession. Also. Although we’ve dealt with timing issues. (Bryan Mealy 2011 ©) 15. For example. most of this emphasis was focused at the timing details and differences of Mealy and Moore-type outputs. but work with the fastest possible clock speeds. The solution to this problem is create some sort of standard for representing numbers. Generally speaking. then it must be a good circuit. typically in the area of digital design. it generally has little to do with the quality or robustness of your circuit.15 Chapter Fifteen 15. problems arise when attempting to represent a number. In order to reduce their workload and thought-load. A few of the valid representations of this number are listed in Table 15. Although clock speed is a great selling point in digital design land.1 Chapter Overview Designing and analyzing finite state machines (FSMs) represents the majority of the work we’ve done in the last few chapters. engineers typically use what is referred to as engineering notation when representing physical values out there in engineering land. 1 They’re actually constructively lazy which is a really good thing. Main Chapter Topics ENGINEERING NOTATION: This chapter reviews the notion of engineering notation and describes it general use in digital design and engineering (and bowling). the number 34. The problem is that it’s hard to obtain a good feel for these numbers if they can be written in all of these different forms. engineers are lazy1. running all your digital circuits at the fastest possible speed is a popular topic. 425 . While these issues are not overly complicated. But then again. The thought here is that if your circuit can operate with a high clock speed.

3 KHz. now is your chance to learn some lingo that will impress your non-technical friends2. So unless instructed otherwise.2 lists the only prefixes that you need to know. This means we’ll need to use the K prefix. Value Prefix Abbrev. 2. You could make up your own prefixes if you wanted but that would pretty much guarantee that no one would know what the $%#&! You were talking about. Solution: The value 452300 is greater than 1000 (103) but less than 1000000 (106).0347 x 10-1 347 x 10-5 Table 15.47 x 10-3 34. Note that the prefixes in engineering notation only come in multiples of three. You should be familiar with most of these prefixes already. and allow you to freely converse with your technical friends3 (real or imaginary). Real or imaginary.7 x 10-4 0. The final answer is 452.000034. A prefix is used for the units.347 x 10-2 3. 1. The advantages of using engineering notation are that it allows you to get a quick feel for the magnitude of numbers based on the designated unit prefix as well as the magnitude portion. but if not. This range can be officially listed as [1.00034. The magnitude portion of the number should be between 0 and 1000.7 x 102 0. Example 15-1 Represent the value 452300Hz in engineering notation. always use engineering notation. The given number is then divided by 1000 to obtain the proper magnitude portion of the number and the K prefix is attached. Exponential notation is not used in engineering notation.Digital McLogic Design Chapter 15 0. 2 3 If you actually have any friends. Example 9 10 Giga G GHz 106 Mega M MHz 103 Kilo k kHz 10-3 mili m ms 10-6 micro μ μs 10-9 nano n ns Table 15.00347 0.7 x 10-4.2: Engineering Notation prefixes.1: A few of the ways to represent 34.1000). Table 15.7 x 101 0. 426 . The rules to using engineering notation are listed below.

1 shows both a periodic (CLK1) and a non-periodic waveform (CLK2).3. Solution: The first order of business here is to convert the exponential portion of this value to a multiple of three. Figure 15. In other words. most of the circuits we’ll be dealing with use the more “predictable” waveform of CLK1 over the seemingly random waveform of CLK2. But to compensate for this multiplication. To do this we divide the exponential portion of the number by 10 to obtain 10-9 and then multiply the magnitude portion of the number by 10 in order to compensate.1: A periodic (CLK1) and non-periodic (CLK2) waveform. 15. If we multiple the number by 100 (102) the exponential portion of the number becomes -6 which is OK.1 The Period 427 . But in reality. this will not be proper engineering notation. The result is 843ns. We’ll define this in more technical terms later (once you know the more technical terms) but for now we’ll define a periodic clock signal as one that does not change in form over time. we have not dealt with the clock signals much other than to acknowledge that they exist and that changes in the state of the FSM are synchronized to one of the clock edges (either the rising or fall edge). But since this value is less than 1. Note that either of these signals could be used as the clock input to a flip-flop since they both contain the required rising and falling edge. Our only other choice is to adjust the exponential part in the other direction. 15. There are some common clocking terms that everyone in any technical field needs to know of in order to be able to converse with your friends (real and imaginary) at the many parties you generally attend (real and imaginary). One aspect of clocking waveforms is that the clock signal is generally considered to be periodic.3 x 10-8 s in engineering notation.3 Clocking Waveforms As you know from your previous experience with FSMs. The term synchronous refers to the fact that changes in the state of the flip-flops representing the state variables are synchronized to the clock edge.Digital McLogic Design Chapter 15 Example 15-2 Represent the value 84.843. This section introduces those terms. Up until now. the memory elements in FSM are synchronous circuits. we must also divide the magnitude portion of the number by 100 (102). no matter where in time you view the waveform. it always appears to have the same form. Figure 15. The resulting magnitude value is then 0.

This waveform is considered periodic because the waveform between (a) and (b) is exactly the same as the waveform between (b) and (c). Often times we may not be specifically interested in the period of the waveform.3.2 shows a periodic waveform with one of the periods clearly delineated. Figure 15. Figure 15.Digital McLogic Design Chapter 15 The more technical definition for a periodic waveform is that the waveform repeats itself “every so often”. This definition is actually somewhat more generally then we usually work with so we want to refine it somewhat to make it more usable.2. Period and frequency have a reciprocal relationship when the amount of time considered is one second. but we are interested in how many times the waveform repeats itself in a given space of time. it is not always the best approach to describing a periodic signal. Using this one second time slot simplifies the translation of period to frequency. Period = T = 1 = ( frequency) −1 frequency frequency = 1 1 = = (T ) −1 Period T Units: time (seconds) Units: Hz (seconds)-1 (a) (b) Figure 15. which refers to the number of times a given signal repeats itself over time. what we most always are interested in knowing is the number of time a signal repeats itself in one second of time.3: The calculations and units for Period and Frequency. The units used for frequency are generally Hertz.2 The Frequency Although the period is a useful measurement. Hertz is technically defined as cycles per second.2: The variable T is typically used to represent the period of a waveform. 15. What is the frequency of this waveform? Solution: Taking the reciprocal of the period provides the frequency.3. The calculation is shown below. or Hz for short. Example 15-3 A given waveform has a 40ns period. The number of times a signal repeats itself over a given amount of time is referred to as the frequency of the waveform. The variable T is often used to represent the time required for the waveform to repeat itself as shown in Figure 15. The space of time we’re usually interested in is one second (1s). 428 . The amount of time required for the waveform to repeat itself is referred to as the period of the waveform. The term Hertz has units of s-1 which underscores its reciprocal relationship to the period (which is measured in time). These relationships are shown in Figure 15. Keep in mind that the units associated with period of a waveform are time.

4(a) shows the official looking equation for duty cycle.Digital McLogic Design Chapter 15 frequency = 1 1 = = 25 x106 Hz = 25MHz 40ns 40 x10−9 Example 15-4 A given waveform has a 50M Hz frequency. In these cases. let’s now describe some of the attributes associated with periodic waveforms. we use the term duty cycle to describe the waveform. this means that the portion of time the signal was high was equal to the portion of time the signal was low. In technical terms. there are no units associated with duty cycle. the duty cycle refers to the portion of the period that the signal is high. All the periodic waveforms we’ve dealt with up to now have been symmetrical. The calculation is shown below. In rough terms. the duty cycle is usually stated in terms of the percentage of the period the signal is high. Figure 15.3 Periodic with Attributes It’s been established that we’re interested in periodic waveforms. Note that since the duty cycle refers to a ratio. These equivalent times are not always the case. Period = T = 1 1 = = 20 x10 −6 s = 20μs 6 −1 50 MHz 50 x10 s 15. Sometimes the clock signal high times and the clock signal low times are not equivalent.3. What is the period of this waveform? Solution: Taking the reciprocal of the frequency provides the period.4: Duty cycle calculations and units. (b) 429 . Strangely enough. dutycycle = th T Units: none (a) Figure 15. the duty cycle is the ratio of the time the signal is high to the period of the signal.

the control input generally needs to remain stable for a given amount of time both before and after the active clock edge. the flip-flop trolls need to be fed. Find the frequency of the waveform.5ns. 4 And yet again. There are a lot of factors that will prevent our circuits from working properly so our main focus will be on two major timing considerations that you’ll more than likely run into as you continue in digital design-land.4 Practical Flip-Flop Clocking Although we seemingly delved deeply into the subject of flip-flop. Namely what we’re interested in here are timing considerations that must be taken into account in order for our sequential circuits to work properly. The frequency is the reciprocal of the period. therefore the period of the waveform is 50ns. Flip-flops are considered to be synchronous circuits in that the change in the flip-flop’s output are synchronized to the clock edge. Most of our discussion thus far has been centered about the notion of idealized flip-flops which allowed us to focus on the basic functioning of the devices. The amount of time the control input needs to remain stable before the active clock edge is referred to as the setup time and the amount of time the control input needs to remain stable after the active clock edge is referred to as the hold time. than 12. a timing diagram associated with a flipflop clock signal is shown in Figure 15. The problems arise due to the fact that flip-flops are actual semiconductor devices which have many insidious factors associated with them that will make the operation of the flip-flop less than ideal. In other words. Solution: If the waveform is high 25% of the period. This means that the output of the device will be neither high or low. we need to take a look at some of the practical aspects of working with flip-flops. As it turns out. Now that we’re familiar with the basic function of flip-flops. Out there in digital-land. signals need to propagates through flip-flops. there are more factors involved when using actual flipflops. One of the end results is that you need to be nice to the control inputs temporally near the active clock edge. 15.5ns represents ¼ of the period. T. a digital design word makes it out of digital design land. it will be somewhere in-between and it may stay there for an extended length of time. This is best shown with a diagram. the type you’ll do best to steer clear of. More specifically. your flip-flop stands the chance of becoming metastable4. and JK inputs) and clock inputs. this would be un-good. If the control input were to change during these time intervals. it is well known that if you violate a setup or hold time. The control input of the flip-flop must also be stable for the duration of the hold time.Digital McLogic Design Chapter 15 Example 15-5 A waveform with a 25% duty cycle is high for 12. The entire period is then four times longer than the amount of time the signal is high. or 20MHz. In the context of a digital circuit. there are many aspects of flip flops that we have not actually touched upon. The control input of the must be stable (it must not change) for the duration of the setup time. etc.5(a) shows the setup and hold times associated with a rising-edge triggered flip-flop while Figure 15. things don’t happen immediately with flip-flops. Recall that flip-flops generally have control inputs (namely the D. the output of the flip-flop would be indeterminate. The word metastable is often used to describe people who are unpredictable.5(b) shows the setup and hold times associated with a falling-edge triggered flip-flop. 430 . Figure 15.5.

for a given circuit. a model of a Moore-type FSM is provided in Figure 15. They idea is always the same: keep a signal stable for a given amount of time before some critical clock edge. What does matter is the propagation delay though the Next State Decoder. This includes both the sequential elements and the Next State Decoder. As a reminder. the maximum clock frequency becomes lower. the shortest period possible for the clock signal becomes greater. and you’ll have saved the day once again. As you know.5 Maximum Clock Frequencies of FSMs In this modern age. Setup and hold times are associated with many different types of digital circuits. 15. we need to take a closer look at some of the timing aspects. it will magically work. there are propagation delays associated with all types of logic5. The Output Decoder generally has no effect on the maximum clock frequency so we’ll not need to consider it here. it’s somewhat intuitive that the items that are going to lower the clock frequency are the items in the circuit that require time. what is maximum frequency that the flip-flop clock can run without hindering the operation of the circuit by violating nasty things such as setup and hold time.6. But mark my words… someday you’ll be working on a circuit that does not seem to want to work properly. the setup times associated with the flip-flops and some combination of the flip-flops hold time and/or the propagation delay through the flip-flop. and hence. faster is generally associated with better even though this is usually the case in real life. There is not too much more to say about setup and hold times. Since flipflops are all we know about. there is always a question of how fast you can clock the circuit and still have the circuit operate properly. as you just found out. there are factors such as setup and hold times associated with sequential logic. These items require time: as the time accumulates. Namely. You’ll toil over it for awhile and then it will hit you: you violated a setup and/or hold time. and in particular sequential circuits. 431 .6.Digital McLogic Design Chapter 15 (a) (b) Figure 15. In other words. we’ll center our discussion around them. In order to provide you with a deeper understanding of digital circuits. From the diagram of Figure 15. What we’ll do now is consider some other practical aspects of a sequential circuit which use the setup and hold times. 5 Keep in mind that sequential circuits were basically combinatorial circuits that contained feedback paths from the circuit outputs to the circuit inputs.5: Setup and hold time definitions for rising edge (a) and falling edge (b) triggered flipflops. Each of the given boxes is comprised of either sequential or combinatorial logic. You’ll do a quick redesign on your circuit.

Tmin = t NS _ dec +t slop + t setup + t pd _ ff Frequencymax = 1 Tmin Figure 15. Another factor include in this diagram is the tslop value.8: Official calculations for minimum period and maximum clock frequency. the propagation delay through the Next State Decoder. These attributes are most easily seen in a diagram such as the one shown in Figure 15. there are four time slices that we need to deal with. we’ll also make some other assumptions about this circuit. the only factors affecting the maximum clock frequency (or minimum period) for the circuit are the setup time.7. 432 . the minimum period can be calculated from the totals of these four times as is shown in Figure 15. This allows the hold time value to be excluded from the calculation. also shown in Figure 15. The minimum period is the reciprocal of the maximum clock frequency.7. The tNS_dec value is shown twice but there is actually only one of these values. we know we have both a hold time and a propagation delay time that we need to deal with. It is shown twice because it is continued from the portion of the waveform ending with the falling edge on the right side of the diagram to the portion of the waveform starting with the falling edge on the left side of the diagram.6: Model for a Moore-type FSM. For a given flip-flop. and the propagation delay through the flipflops. Figure 15. you always want to throw in a safety margin to guard against circuit conditions that may adversely affect the circuit. we’ll assume that the propagation delay for the flip-flop is great than the hold time. In order to simplify the analysis of FSM circuits. In the end. The idea here is that you never want to design to the absolute operating boundaries of your circuit.8. Once again. As you can see from Figure 15.Digital McLogic Design Chapter 15 Figure 15.8. For these problems.7: Model for a Moore-type FSM.

Inverters have propagation delays of 6ns and logic gates have propagation delays of 8ns. It is also stated in the problem that the Z outputs are yet another item we don’t need to worry about for this problem. Since there are two gates (one AND gate and one OR gate). 433 . in the longest path through the Next State Decoder. add a safety margin of 12ns. the flip-flops have a setup time of 10ns and a propagation delay of 13ns.6MHz Tmin 51ns Figure 15. The safety margin of 12ns makes of the tslop value. Tmin = t NS _ dec +t slop + t setup + t pd _ ff Tmin = (8ns + 8ns ) + (12ns ) + (10ns ) + (13ns ) = 51ns Frequencymax = 1 =1 = 19. Solution: The first thing to notice about this problem is that we don’t need to worry about the X input. Assume the propagation delay for the flip-flops is greater than the hold time. What we need to do for this problem is total up the gate delays on the longest path in the excitation logic in order to give us the tNS_dec value.Digital McLogic Design Chapter 15 Example 15-6 What is the maximum system clock frequency at which the following sequential circuit can operate? For this problem. the tNS_dec value is twice a standard gate delay. The final solution is shown in Figure 15.9. For this problem.9: The calculations: plug and chug. Assume the X input is stable and the Z1 and Z2 outputs drive a circuit that is not sensitive to the maximum clock frequency.

These attributes are described in devices that include clocks by the setup and hold times. the propagation delay of the flip-flop. Periodic signals are also described by the frequency which is defined to be the reciprocal of the period. • • • • 434 . Periodic signals can be described by a given waveform that repeats itself after a given amount of time referred to as the period of the signal. All clocked digital devices have physical attributes that govern their performance. The hold time is the amount of time that the input signal needs to remain stable after the active clock edge. and usually some margin of safety. The numerical value can be floating point but must be greater or equal to 1. the maximum clock frequency is a function of the propagation delay of the next state decoder. Waveforms in digital design are usually periodic in nature. Engineering notation uses a numerical value followed by a prefix. The setup time is the amount of time that an input signal need to remain stable before the active clock edge of a device. On major concern of FSMs is the maximum clocking frequency that can be used while not compromising the operation of the FSM.Digital McLogic Design Chapter 15 Chapter Summary • Engineering notation is generally used to represented fixed values in various engineering fields including digital design. Periodic waveforms are also described by their duty cycles which is defined to be the ratio of the time in the period that the signal is in a high state to the period of the signal. Using a simple model. The prefixes represented multiples of powers of three and are given alpha-type names. the setup time of the flip-flop.0 and less than 1000.

A system clock signal with a 70% duty cycle is in a high state for 14ns of its period. A system clock if running at 50M Hertz. Find the duty cycle.355 x 107 2.3 x 108 d) -33.146 x 108 g) 0. frequency.8 x 10-4 e) 0. and duty cycle of the waveform. Find the duty cycle. tb = 20ns 6. and frequency (its OK to only setup the frequency calculation). For the system clock signal displayed below with tx=30ns and ty=25ns. and frequency (its OK to only setup the frequency calculation). The following clock waveform is in a high state for a 40% of the period. Convert the following values to engineering notation. period.00303 x 10-4 f) 0. and frequency (its OK to only setup the frequency calculation). 4.Digital McLogic Design Chapter 15 Chapter Drill Problems 1. find the period.0000000253 x 104 h) 8. The following clock waveform is in a low state for a 80% of the period. What amount of time is the signal high if the system clock has a 40% duty cycle? (1 M Hertz = 1x106 Hertz) 5. a) 235500000 b) 45 x 10-4 c) 241. (1ns = 1x10-9 seconds) 3. Find the duty cycle. period. ta = 20ns 7. What is the period and frequency of the clock? (1ns = 1x10-9 seconds). period. The following clock waveform is in a high state for a 40% of the period. ta = 20ns 435 .

Use the listed circuit parameters for this problem: flip-flop propagation delay: 17ns inverter propagation delay: 4ns gate propagation delay: 9ns flip-flop set-up time: 8ns flip-flop hold time: 7ns 436 . it is now desired to add a margin of safety to the clocking operation of the circuit. tb = 60ns 9. The following clock waveform is in a low state for a 20% of the period. period. tslop. Also assume that the propagation delay of the flip-flops is much greater than the flip-flops set-up time. Assume the output Z drives a circuit that is not sensitive to the maximum clock frequency. What is the new minimum clock period and new maximum clock frequency? 10. and frequency (its OK to only setup the frequency calculation). Redo problem 7 and add a 20ns margin of safety. For problem 7. The diagram is not drawn to scale. Find the duty cycle. to the minimum clock period. Use the listed circuit parameters for this problem: flip-flop propagation delay: 20ns inverter propagation delay: 4ns gate propagation delay: 10ns flip-flop set-up time: 6ns flip-flop hold time: 7ns 11. The following circuit was designed to operate at 20MHz (20x106Hz). Under these conditions. add a safety margin that is 10% of the minimum clock period based on the timing values stated below. how much of a safety margin (if any) has been added to the circuit? Assume the X input is stable and the output Z drives a circuit that is not sensitive to the maximum clock frequency. What is the maximum clock frequency that can be used by the following circuit? For this problem.Digital McLogic Design Chapter 15 8.

Use the listed circuit parameters for this problem: flip-flop propagation delay: 20ns inverter propagation delay: 4ns gate propagation delay: 8ns flip-flop set-up time: 5ns flip-flop hold time: 7ns 437 . What is the maximum clock frequency that can be used by the following circuit? For this problem.Digital McLogic Design Chapter 15 12. Assume the output Z drives a circuit that is not sensitive to the maximum clock frequency. add a safety margin that is 20% of the minimum clock period based on the timing values stated below.

Digital McLogic Design Chapter 15 438 .

2 FSMs Using VHDL Behavioral Modeling 1 Despite this fact. You’re now to the point where your designs still don’t have much point but you’ll be able to implement and test them using actual hardware if you so choose. How state variables are encoded. the use of One-Hot Encoding using VHDL models. you’ve probably designed quite a few state machines on paper. FSMs are digital circuits that are used to control other digital circuits. The first step in this process is to learn how to model FSMs using VHDL. has a high fun factor rating. and in particular. Main Chapter Topics FSMS MODELS USING VHDL: The approach to representing FSMs using VHDL is straight-forward. Modeling FSMs using VHDL behavioral modeling is similar to FSM design and analysis in that once you read the material and do a few problems. however. But have no fear. simple FSM designs are just a step beyond the sequential circuits described in the section dealing with storage elements in VHDL. In other words. 439 . that’s when the real fun begins2. It’s a simple circuit that does some powerful stuff. you’ll most likely experience some trouble in the upcoming material. The power of VHDL and its behavioral modeling capabilities allows FSMs to be represented at a high-level. If you did not. The VHDL approach allows for direct modeling of the state diagram and thus avoiding dealing with implementation details such as next-state and output decoding logic. but not as fun as bowling. But as you probably discovered after attempting a few problems on your own. SHIFT REGISTERS: Probably the single most useful circuit in digital land is the shift register. you’ll begin to view the topic as somewhat trivial. As you’ll see later in this chapter. The techniques you learn in this chapter allow you to quickly and easily model relatively complex FSMs which can then truly be used as controllers in digital circuits. FSMs are generally used as controllers in digital circuits. ONE HOT ENCODING OF STATE VARIABLE: The encoding of state variables is an important subject that has been passed over up to now. is briefly covered in this chapter. 2 This chapter. After working through the previous chapter. (Bryan Mealy 2011 ©) 16. This chapter also covers material that is considered cookbook. the theme of upcoming chapters are to use FSMs as they are intended to be used. it gave the appearance that the techniques were complicated. and.Digital McLogic Design Chapter 16 16 Chapter Sixteen 16. but there was no real point for the design. you hopefully found the design and analysis techniques rather cookbook1. it’s painfully straight-forward to model in VHDL (including the many variants).1 Chapter Overview A previous chapter presented an over view of FSMs as well as some FSM design and analysis techniques. Since the chapter was rather lengthy. As previously mentioned. you should have still developed a deep understanding of the general form and function of FSMs.

Figure 16. Figure 16. The state registers block is storage elements that store the present state of the machine.1: Block diagram for a Moore-type FSM. Although the model in Figure 16. There is some new lingo used in the description of signals used in Figure 16. understanding the other approaches is not a big deal and you are encouraged to seek these out. The inputs are decoded via combinatorial logic to produce the external outputs. the versatility of VHDL behavioral modeling removes the need for large paper designs of endless K-maps and endless combinatorial logic as you may have grown used to in a previous chapter. One process. the Combinatorial Process. In other words. The circuitry in Next State Decoder is generally the excitation equations for the storage elements (flip-flops) in the State Register block. the outline below described this new lingo: There are many sources available describing other approaches to FSM modeling in VHDL. The approach we use divides the FSM into two VHDL processes.Digital McLogic Design Chapter 16 Figure 16. it does not adequately describe FSMs as we will model them in VHDL.1.1 shows the block diagram of a standard Moore-type FSM as we were working with in a previous chapter.1 are both comprised of solely of combinatorial logic. Although it does not look that much clearer. The next state becomes the present state of the FSM when the clock input to the state registers block becomes active. Once you understand the basics presented in this chapter. There are several different approaches used to model FSMs using VHDL. Because the external outputs are only dependent upon the current state of the machine. you’ll soon be finding the FSM model in Figure 16. this FSM is classified as a Moore FSM. What we’ll describe in this section is probably the clearest approach for FSM modeling using VHDL3. handles all the matters associated with the Next State Decoder and the Output Decoder of Figure 16. The many different possible approaches are a result of the general versatility of VHDL as a hardware description language. referred to as the Synchronous Process.2.2 shows a block diagram of the approach we’ll use for FSM behavioral modeling using VHDL. The other process. the inputs to the Next State Decoder block are decoded and to produce an output that represents the next state of the FSM. As you’ll see. The true power of VHDL starts to emerge in its dealings with FSMs.1 accurately describes the FSM in the context of the low-level design techniques we presented in the previous chapter.2 to be a straight-forward method to implement FSMs. The inputs to the Output Decoder are used to generate the desired external outputs. The Next State Decoder is a block of combinatorial logic that uses the current external inputs and the current state of the FSM to decide upon the next state of the FSM. handles all the matters regarding clocking and other controls associated with the storage element. Recall that the Output Decoder and Next State Decoder blocks in Figure 16. 3 440 .

These inputs would include enables. there are many times where you’ll need this level of control of the storage elements. they control the values of the external output signals. More information on the other FSM coding styles is found in various VHDL texts or on the web. 4 Recall that we combinatorial process in the current FSM model now has the functionality of both the Next State Decoder and Output Decoder blocks of the previous FSM model.2 also shows that the Present State variables can also be provided as outputs to the FSM but is not required.Digital McLogic Design Chapter 16 • The inputs labeled Parallel Inputs are used to signify inputs that act in parallel to each of the storage elements. if you’re modeling FSMs with VHDL. are not used as outputs to the outside world. This model of the FSM lumps them together into one block4. and not individually. The model shown in Figure 16. 2) in the case of Mealy machines. The Present State signals are used by the Combinatorial Process box for both next state decoding and output decoding. you’re handing over a lot of control to the VHDL synthesizer. The thought here is that these input types control all of the storage elements as a group. As opposed to the Present State signals. Their sole purpose is to provide a means for the two processes to communicate. As you see in more complex FSM designs. presets. One you understand the dependent PS/NS style of VHDL FSM modeling.2: Model for VHDL implementations of FSMs. The inputs labeled State Transition Inputs include external inputs that control state transitions. The Next State signals are truly VHDL signals. clears.2.2 is actually a model of the dependent PS/NS style of FSMs. 441 . etc. One final comment before we begin… Although there are many different methods that can be used to described FSMs using VHDL. We’ve opted to only cover the dependent style in this chapter because it is clearer than the independent PS/NS style when you’re first dealing with VHDL behavioral models of FSM. • • • Figure 16. understanding of the independent PS/NS style or any other style is relatively painless. Generally speaking. the Next State signals shown in Figure 16. two of the more common approaches are the are the dependent and independent PS/NS styles. The diagram of Figure 16. Recall that the external inputs to a FSM can have two functions: 1) they control the state transitions.

Often times with FSM problems.3: Black box diagram for the FSM of Example 16-1. In this case. The black box diagram is shown in Figure 16. 5 Also. Solution: This problem represents a basic FSM implementation. since there are so many ways to draw state diagrams. it sometimes becomes challenging to discern the FSM inputs from the outputs. particularly when the state diagrams become more complex5. you may be dealing with an approach that you’re not used to. Figure 16. 442 . It is somewhat instructive to show the black box diagram which as an aid in the writing the entity description. draw a black box diagram for sure. Use a dependent PS/NS coding style in your implementation. Drawing a diagram partially alleviates this problem.4.3 while the solution to Example 16-1 shown in Figure 16.Digital McLogic Design Chapter 16 Example 16-1 Write the VHDL code that models the FSM shown on the right. Starting design problems by drawing a black box diagram is always a healthy approach particularly when dealing with FSMs.

end process sync_proc. As with enumeration types in other higher-level computer languages. else NS <= ST0.NS. when ST1 => -.Moore output if (TOG_EN = ‘1’) then NS <= ST0. begin sync_proc: process(CLK. -.the catch-all condition Z1 <= ‘0’. Z1 : out std_logic).take care of the asynchronous input if (CLR = ‘1’) then PS <= ST0. -. end if. Figure 16. The key thing to note here is that a state_type is a type that we’ve created and is not a native VHDL type. The only difference is we’ve substituted PS and NS for D and Q.NS : state_type. end my_fsm1. end fsm1. end if. architecture fsm1 of my_fsm1 is type state_type is (ST0.4: The final solution for Example 16-1. comb_proc: process(PS. 443 .arbitrary. signal PS. else NS <= ST1. This is an example of how enumeration types are used in VHDL. elsif (rising_edge(CLK)) then PS <= NS.pre-assign output case PS is when ST0 => -.items regarding state ST0 Z1 <= ‘0’.make it to these two statement end case. • We’ve declared a special VHDL type. there are internal numerical representations for the listed state types but we only deal with the more expressive textual equivalent. CLK. In this case.CLR : in std_logic.ST1).Digital McLogic Design Chapter 16 entity my_fsm1 is port ( TOG_EN : in std_logic. respectively.CLR) begin -. state_type. this solution has many things worth noting in it.Moore output if (TOG_EN = ‘1’) then NS <= ST1. the type we’ve created is called a state_type6 and we’ve declared two variables of this type: PS and NS (which stand for present state and next state). -. end if. it should never NS <= ST0. • The synchronous process is equal in form and function to the simple D flip-flops we examined when we were dealing with basic storage element representations using VHDL.items regarding state ST1 Z1 <= ‘1’. to represent the states in this FSM. when others => -. -. The more interesting things are listed below. The key thing to note here 6 The name is arbitrary but it does nice describe the purpose of the new type. And of course. -. end process comb_proc.TOG_EN) begin Z1 <= ‘0’.

due their nature. • The case statement in the combinatorial process provides a when clause for each state of the FSM. • Because the two processes operate concurrently. are assigned inside the if statement. The true values of the state variables are represented internally and its precise representation is not important since the state variable is not provided as an output. Note that PS is not specified for every possible combination of inputs which is why VHDL models it as a storage element. In an effort to keep the example simple. Keep in mind that process statement is a concurrent statement. And so on and so forth. There is one final thing to note about the solution shown in Figure 16. This is expressed by the fact that the assignment of the Z1 output is unconditionally evaluated in each when clause of the case statement in the combinatorial process. Pre-assigning it in this fashion prevents the unexpected latch generation for the Z1 signal. you would not know. you can see that everything is nicely compartmentalized in the solution.Digital McLogic Design Chapter 16 is that the storage element is associated with the PS signal only. the changes in the PS signal causes the combinatorial process to be evaluated. • The Moore output is a function of only the present state. Note that it is the external input that controls which state the FSM transitions to from any given state. they can be considered as working in a lockstep manner. When the changes are actually instituted in the synchronous process on the next clock edge.3 by the fact that the only output of the FSM is signal Z1. the Z1 variable is inside the when clause but outside of the if statement in the when clause. there is a natural tendency for the FSM designer to forget to specify an output for the Z1 variable in each of the states. the “execution” of the process statement occur concurrently. In other words. The combinatorial process handles the outputs not handled in the synchronous process. Pre-assigning it prevents latches from being generated and can arguably make the VHDL source code seem neater. and the generation of the next state of the FSM. 7 8 Catch-all statements used in this manner are also helpful when used to debug VHDL models. But if you examine it closely. The signal assignments that are part this catch-all clause is arbitrary since the code should never actually make it there. this is due to the fact that we used a VHDL enumerated type to represent the state variables and have thus handed control over to the VHDL synthesizer. This is course because the Moore outputs are only a function of the states and not the external inputs. It’s a tough concept. This statement is provided for a sense of completeness and represents good VHDL coding practice7. only the final assignment is considered once the process terminates8. Once again. When dealing with FSMs. So if someone were to ask you how many flip-flops were associated with a VHDL model such as this one. This is the standard approach for the dependent PS/NS coding style. • Even though this is about the simplest FSM you could hope for. There are two processes. Changes to the NS signal that are generated in the combinatorial process forces an evaluation of the synchronous process. the code looks somewhat complicated. 444 . The pre-assignment does not change the function of the VHDL model because if multiple assignments are made within the process.4. only the final assignment takes affect. we disregarded the true digital values of the state variables. the outputs. A when others clause is also provided. • The Z1 output is pre-assigned as the first step in the combinatorial process. You’ll see later that Mealy outputs. but you’ll get used to it with practice and contemplation. This is indicated in the black box diagram shown in Figure 16. This is reasonable in that it could be the case where only one output was required in order to control some other device or circuit. In other words. The synchronous process handles the asynchronous reset and the assignment of a new state upon the arrival of the system clock. Despite the fact that process statements are filled with sequential statements.

arbitrary.Digital McLogic Design Chapter 16 In some FSM designs. To show this situation.make it to these two statement end case. architecture fsm2 of my_fsm2 is type state_type is (ST0. end if.Moore output if (TOG_EN = ‘1’) then NS <= ST0. end my_fsm2. else NS <= ST1. the state variables are provided as outputs.CLR) begin if (CLR = ‘1’) then PS <= ST0. Y. end if.NS. elsif (rising_edge(CLK)) then PS <= NS.NS : state_type.5 shows the black box diagram of this solution and the alternate VHDL model is shown in Figure 16. -.6. begin sync_proc: process(CLK. end if.5: Black box diagram of Example 16-1 including the state variable as an output. Figure 16. when others => -.items regarding state ST1 Z1 <= ‘1’.6: Solution for Example 16-1 including state variable as an output. end process comb_proc. end process sync_proc.the catch-all condition Z1 <= ‘0’. -. else NS <= ST0. 445 . others. entity my_fsm2 is port ( TOG_EN : in std_logic. when ST0 => -. CLK. representing the state variables ST0. it should never NS <= ST0. comb_proc: process(PS. ST1. -.Z1 : out std_logic). signal PS.TOG_EN) begin case PS is Z1 <= ‘0’.assign values with PS select Y <= ‘0’ when ‘1’ when ‘0’ when end fsm2.CLR : in std_logic.ST1). when ST1 => -. Figure 16. -. we’ll provide a solution to Example 16-1 where the state variables are “modeled” as outputs.Moore output if (TOG_EN = ‘1’) then NS <= ST1. Figure 16.items regarding state ST0 Z1 <= ‘0’. -.

7: Black box diagram for the FSM of Example 16-2. since we have declared an enumeration type for the state variables. In reality. The selective signal assignment statement is evaluated each time a change in signal PS is detected. the solution requires at we use at least two signals to model the state variables which is sufficient to handle the three states. And lastly.6 differs in only two areas from the code shown in Figure 16.Digital McLogic Design Chapter 16 Note that the VHDL code in shown in Figure 16.4. Note that the two state variables are handled as a bundled signal. Solution: The state diagram shown in the problem description indicates that this is a three-state FSM with one Mealy-type external output (Z2) and one external input (X). The first area is the modification of the entity declaration to account for the state variable output Y. The selective signal assignment statement in the code of Figure 16. there are methods we can use to control how the state variables are represented and we’ll deal with those soon. Figure 16. Once again.7 shows the black box diagram for this example while Figure 16. be sure to note that there are three concurrent statements in the VHDL code shown in Figure 16. The second area is the inclusion of the selective signal assignment statement which assigns a value of state variable output Y based on the condition of the state variable. Since there are three states. Consider the state variables as outputs of the FSM.6: two process statements and a selective signal assignment statement. 446 . Example 16-2 Write the VHDL code that implements the FSM shown on the right.6 only makes it appear as if one state variable was used to represent the two states shown in the original state diagram. Use a dependent PS/NS coding style in your implementation. we have no way of knowing exactly how the synthesizer has opted to represent the state variable. Figure 16.7 shows the full solution.

ST2). -. you should note the similarities between this solution and the solution to the previous example. “00” when others. end process sync_proc. when ST1 => -.X) begin case PS is Z2 <= ‘0’. end if. else NS <= ST2. end process comb_proc.SET) begin if (SET = ‘1’) then PS <= ST2.items regarding state ST0 Z2 <= ‘0’. end fsm3. begin sync_proc: process(CLK.8: Solution for Example 16-2. Most importantly. else NS <= ST2. Figure 16.items regarding state ST2 -.the catch all condition Z2 <= ‘1’. -. else NS <= ST1.Mealy output handled in the if statement if (X = ‘0’) then NS <= ST0. when others => -.pre-assign FSM outputs when ST0 => -. end case.NS. Y : out std_logic_vector(1 downto 0). architecture fsm3 of my_fsm3 is type state_type is (ST0.items regarding state ST1 Z2 <= ‘0’.faking some state variable outputs with PS select Y <= “00” when ST0. “11” when ST2. when ST2 => -. there are a couple of fun things to note about the solution for Example 16-2. As usual. In the final when clause. end if. NS < ST0. The fact that the Z2 output is different in the context of state ST2 that makes it a Mealy-type output and therefore a Mealy-type FSM. “10” when ST1. elsif (rising_edge(CLK)) then PS <= NS. Z2 : out std_logic).ST1.NS : state_type. • The FSM has one Mealy-type output. -.Mealy output always 0 if (X = ‘0’) then NS <= ST0.SET : in std_logic. comb_proc: process(PS. signal PS.Mealy output always 0 if (X = ‘0’) then NS <= ST0. the Z2 output appears in both sections of the if statement.CLK. Z2 <= ‘0’. Z2 <= ‘1’. 447 . -. end my_fsm3. The solution essentially treats this output as a Moore-type output in the first two when clauses of the case statement. end if.Digital McLogic Design Chapter 16 entity my_fsm3 is port ( X. end if.

10 shows the associated VHDL model.Digital McLogic Design Chapter 16 • This original state diagram has a mysterious state transition arrow. The solution opted to represent these outputs as a bundle which has the effect of slightly changing the form of the selected signal assignment statement appearing at the end of the architecture description.9: Black Box diagram for the FSM of Example 16-3. Use a dependent PS/NS coding style in your model. Therefore the approach used to model the SET signal is nothing new and strange. Example 16-3 Write the VHDL code that models the FSM shown on the right. Figure 16. Figure 16. two signals are required since the state diagram contains more than two states (and less than five states). and two external outputs.9 shows the black box diagram for the solution while Figure 16. This is a hybrid FSM in that the if contains both a Mealy and Moore-type output but in this case. one external input. 448 . the FSM would be considered a Mealy-type FSM. This is the typical symbology used to model asynchronous inputs to FSMs. The SET arrow on the lower right of the state diagram seems to enter the lower state out of nowhere. Modeling the SET signal in the synchronous process uses the same approach as modeling asynchronous inputs in basic storage elements. Consider the listed state variables as output. Solution: The state diagram indicates that the solution contains four states. • When faking the state variable outputs (keeping in mind that the actual state variables are represented with enumeration types). This input is considered to be a “parallel input” as previously described since the SET signal simultaneously acts on all of the storage elements.

-. Z2 <= ‘0’.items regarding state ST2 Z1 <= ‘0’. NS <= ST0. Z2 <= ‘1’. Figure 16.Z2 : out std_logic).Z1: the Moore output. comb_proc: process(PS. architecture fsm4 of my_fsm4 is type state_type is (ST0. ST3. Z2 <= ‘1’. you’ll rarely find yourself having to code VHDL FSM models from scratch. ST0. end if.ST2.Moore output if (X = ‘0’) then NS <= ST2.NS : state_type. It’s actually a cookbook approach it’s so straight-forward. when ST1 => -. end if. else NS <= ST1. Z2 <= ‘1’. end if.CLK. else NS <= ST0. when ST2 => -. end if. end process comb_proc. Keep in mind 9 Particularly useful if you’re a CPE: “cut and paste engineer”.Moore output if (X = ‘0’) then NS <= ST3. implementing FSMs using VHDL behavioral modeling is remarkably straight-forward. Z1. signal PS. So if you’ve haven’t noticed by now.Digital McLogic Design Chapter 16 entity my_fsm4 is port ( X. there is no need to reinvent the wheel when using VHDL to model FSMs: use the cut and paste9 feature of your text editor instead. Z2 <= ‘1’. 449 .NS. others. Z2 <= ‘0’. ST2. else NS <= ST2. -.items regarding state ST0 Z1 <= ‘1’. Z2 <= ‘0’. end my_fsm4. end case.ST1. ST1. -. -. else NS <= ST3.Moore output if (X = ‘0’) then NS <= ST1. The better approach is to grab a previously coded model and use that. Z2 <= ‘0’. Z2: the Mealy output Z1 <= ‘0’.10: Solution for Example 16-3.RESET : in std_logic. Z2 <= ‘0’.pre-assign the outputs case PS is when ST0 => -. when others => -. begin sync_proc: process(CLK. In reality. end if. elsif (rising_edge(CLK)) then PS <= NS. -. In other words.items regarding state ST1 Z1 <= ‘1’. with PS select Y <= “00” when “01” when “10” when “11” when “00” when end fsm4.RESET) begin if (RESET = ‘1’) then PS <= ST0.Moore output if (X = ‘0’) then NS <= ST0.X) begin -. end process sync_proc.items regarding state ST3 Z1 <= ‘1’.the catch all condition Z1 <= ‘1’. Y : out std_logic_vector(1 downto 0). when ST3 => -.ST3). Z2 <= ‘0’.

11: Possibly the ultimate VHDL FSM behavioral modeling cheat sheet. Figure 16. So don’t get too comfortable with behavioral modeling of FSMs.Digital McLogic Design Chapter 16 that real engineering is rarely cookbook and therefore modeling FSM using VHDL is not true engineering. For FSM problems. 450 . the real fun is generating a FSM that solves a given problem which we’ll start doing in the next chapter. the engineering is in the testing and creation of the state diagram.

Use a dependent PS/NS coding style in your implementation. we need to look at the process of explicitly encoding one-hot FSMs. Solution: The state diagram shows four states. The changes required from our previous approach are limited how the VHDL places constraints on the encoding of the state variables. In other words. 451 .13 shows the required modifications to the state variable output assignment in order to move from enumeration types to a special form of assigned types. provide the state variables as outputs to the FSM. two external outputs Z1 and Z2 with the Z2 output being a Mealy output. And since we’re concerned with learning VHDL. You should strongly consider comparing and contrasting these three figures. This is a Mealy machine that indicates that one-hot encoding must be use to encode the state variables.Digital McLogic Design Chapter 16 16. Figure 16.13. Modifications to the binary encoded approach are thus limited to a few lines in the VHDL state variable declaration process. These two lines of code essentially force the VHDL synthesizer to represent each state of the FSM with its own storage element. Figure 16. Forcing the state variables to be truly encoded using one-hot encoding requires these two extra lines of code as is shown in Figure 16. Use one-hot encoding for the state variables. Consider the listed state variables as output. Example 16-4 Write the VHDL code that implements the FSM shown on the right. We’ll approach this solution in pieces.14 shows the total solution for this example. bits and pieces. Figure 16. If you need to provide the state variables as outputs. In this particular example. If you want total control of the process.12 shows the modifications to the entity declaration required to convert the binary encoding used in standard VHDL behavioral modeling to one-hot encoding. you’ll need to grab control away from the synthesizer. the code essentially forces four bits per state remembered by the FSM implementation which essentially requires four flip-flops. each state is represented by the associated “string” modifier as provided in the VHDL code. the entity declaration (you’ll need more variables to represent the states) and the VHDL code controlling the assignment of output variables will also need modification. The modular approach we used to implement FSMs expedites the conversion process from using enumeration types to actually specifying the representation of the state variables.3 VHDL Topics: One-Hot Encoding in FSM Behavioral Modeling The question naturally arises as to how VHDL implements one-hot encoded FSMs. one external input X. This problem is identical to a previous example but one-hot encoding for the state variables in this example. Most synthesis tool vendors provide the ENUM_ENCODING attribute to allow the digital designer to specific the binary encoding to that is used by each object of enumerated types.

ST3). -.ST2.NS : state_type. Y : out std_logic_vector(1 downto 0). end my_fsm. attribute ENUM_ENCODING: STRING.RESET : in std_logic.full encoded approach entity my_fsm is port ( X.CLK. end my_fsm.NS : state_type.ST1.Z2 : out std_logic).13: Modifications to convert state variables to use one-hot encoding.ST1.12: Modifications to convert entity associated with Error! Reference source not found. to one-hot encoding. Figure 16.ST2.ST3).Digital McLogic Design Chapter 16 -.Z2 : out std_logic). -.RESET : in std_logic.CLK. signal PS.one-hot encoding approach entity my_fsm is port ( X. signal PS.the approach to for enumeration types type state_type is (ST0. 452 . attribute ENUM_ENCODING of state_type: type is “1000 0100 0010 0001”. Y : out std_logic_vector(3 downto 0).the approach used for explicitly specifying state bit patterns type state_type is (ST0. Z1. Z1. Figure 16. -.

items regarding state ST2 Z1 <= ‘0’. architecture fsm of my_fsm is type state_type is (ST0.ST1. Z1.Moore output if (X = ‘0’) then NS <= ST3. Figure 16.Moore output if (X = ‘0’) then NS <= ST1.items regarding state ST1 Z1 <= ‘1’. else NS <= ST3. end if. Z2 <= ‘0’. comb_proc: process(PS.NS : state_type. signal PS. Z2: the Mealy output Z1 <= ‘0’. end process sync_proc. when ST1 => -. -. end if. else NS <= ST1. Z2 <= ‘1’.RESET) begin if (RESET = ‘1’) then PS <= ST0.Moore output if (X = ‘0’) then NS <= ST2. Z2 <= ‘0’.Z1: the Moore output. -.X) begin -.4 Shift Registers 453 . -. “0001” when ST3. end fsm.CLK. -. end my_fsm. begin sync_proc: process(CLK. end process comb_proc.items regarding state ST3 Z1 <= ‘1’. Z2 <= ‘1’. when ST3 => -. 16. when others => -.one-hot encoded approach with PS select Y <= “1000” when ST0. “0010” when ST2.pre-assign the outputs case PS is when ST0 => -. Y : out std_logic_vector(3 downto 0). Z2 <= ‘0’. end if. NS <= ST0. Z2 <= ‘0’. Z2 <= ‘1’. elsif (rising_edge(CLK)) then PS <= NS. attribute ENUM_ENCODING: STRING.ST3).Digital McLogic Design Chapter 16 entity my_fsm is port ( X. when ST2 => -.items regarding state ST0 Z1 <= ‘1’. end if. else NS <= ST2.RESET : in std_logic. attribute ENUM_ENCODING of state_type: type is “1000 0100 0010 0001”.ST2. -.Moore output if (X = ‘0’) then NS <= ST0. Z2 <= ‘0’. Z2 <= ‘1’. else NS <= ST0. “0100” when ST1. end case.14: The final solution to Example 16-4.the catch all condition Z1 <= ‘1’. Z2 <= ‘0’. -. end if. “1000” when others.NS.Z2 : out std_logic).

Figure 16: A simple 4-bit shift register. The universal shift register is based on a simple concept. The operation of a SR is simple but can be somewhat tricky when you first look at it. are extremely useful in many digital applications primarily because the things they do can be done really fast. The shift register in Figure 15 is purposely drawn generically (with magic ellipsi). As you would guess. you often saw shifters used as FSMs that acted as controllers. Shift registers don’t really do that much11. Common descriptions of shift register include “a 4-bit shift register” or “an 8-bit shift register”. Figure 15 shows a schematic diagram of a generic shift register. Basic shift register circuitry is not complicated and thus helps the noob understand the basic functioning of sequential circuits. this cell is nothing more than a simple storage element and is usually modeled as a D flip-flop. you should discern the following: • • • The shift register is a sequential circuit: the circuit comprises solely of D flip-flops. • Figure 15: A typical n element shift register. I’ll forever substitute “SR” to mean shift register (not to be confused with a SR latch). Figure 17 shows an example timing diagram associated with the 4-bit SR shown in Figure 16. Shift registers. cyclic redundancy checking. 454 . There is not really a lot to say about Figure 16 as the fun stuff begins when you examine a timing diagram associated with this circuit. All the D flip-flops share the same clock. we can decompose a shift register down to its most basic component which is referred to as a shift register cell. barrel shifters. but they do a few things really well. Your initial inspection of Figure 15 should reveal that there is really not that much to the circuit. Figure 17 has some annotations in it to help with the following description of the SR. Figure 16 shows the schematic diagram of a 4-bit SR. In other words. 10 11 Such as universal shift registers. and their variants10. Shift registers are generally defined by the number of bit storage elements they contain. Upon further inspection.Digital McLogic Design Chapter 16 It turns out that one of the more simple circuits out there in digital-land is also one of the most useful: the friendly shift register. bowling ball polishers… Back in the days before microcontrollers.

Q3 is considered to be the higher order bit while Q0 (or data_out) is the lowest order bit12. the either shift to the left or right. • • The notion of this circuit actually shifting something is somewhat tricky. Shift registers are considered to shift directionally. Figure 17 makes a feeble attempt at showing this shifting by way of a timing diagram. • • • This is a 4-bit shift register. The way the circuit of Figure 16 is drawn makes this a right-shifting SR. particularly in this explanation. 12 Keep in mind that SRs are often used for mathematical operations. All of the storage elements share the same clock signal. meaning that the SR circuitry contains four storage elements. For this example. which is a typical feature of SRs. Here are some fun things to note about the timing diagram in Figure 17. Another way to look at this is that the circuit is passing in 1’s and 0’s from the left side of the circuit and passing them through to the right side.Digital McLogic Design Chapter 16 Figure 17: A typical n element shift register. numbers generally have weights associated with the bit positions (unless you’re a cave-person). The notation of “Qx” is typical of any circuit having flip-flops as storage elements. The “thing” being shifted by the SR of Figure 16 is “data”. 455 . The fun things to note about Figure 16 and Figure 17 are listed below. this circuit cannot shift left. The “Qx” notation used in these figures indicates the bit positions of the storage elements in the SR. that is. Each of the signals in Figure 16 is labeled as they all are important.

the storage elements have a state associated with them. and all you have to work with are 13 Truncation means the lowest order bit is lost. In most SR circuits there are other features such as most of the ones listed below. each of the four D flip-flops can change state or hold their current state based on the value of the D input. If you’re actually unfortunate enough to be forced to use SRs on discrete ICs. the initial state of each storage element is considered to be ‘0’. if you stand back a few paces. On the clock edge labeled ‘1’. Since the storage elements are all D flip-flops. Overall. shift registers are massively powerful.Digital McLogic Design Chapter 16 • Since this is a sequential circuit. specifically. For example. Also keep in mind that the circuit shown in Figure 16 is overly simple. a similar operation is “round-up” where the value of the lowest order bit is “taken into account” and your weeds are killed at the same time. Even SRs that have all the bells and whistles take about zero-time to model if you understand the basics of how VHDL is used to model sequential circuits. The individual signals are shifted versions of each other. For the timing diagram of Figure 17. etc. 14 But I certainly don’t care because I sleep well at night knowing that the VHDL synthesizer is going to take care of the details for me. Q2 is a shifted version of Q3. if you need a 64-bit SR. the VDHL model for this simple SR is very similar to the VHDL model for a D flip-flop (although there is one interesting trick in this model). etc. data_in is latched into the left-most flip-flop. they can only change state in on the active clock edge. another way to look at this is that the data_out signal is a delayed version of the data_in signal. on each active clock edge. In other words. Keep in mind that there are many different ways to model a SR in VHDL. Keep in mind that the right-shift operation (one shift in the right direction) is the same thing as a divide-by-two operation with truncation13. As you can see from Figure 20. Figure 20 shows the VHDL model for the SR of A simple no-feature VHDL model of the SR shown in Figure 16. • • • • • parallel clearing or parallel setting of storage elements parallel loading of values to the storage elements Shifting left or shift right operations Multiple shifts on one clock edge Automatic bowling score feature A few final comments regarding shift registers… SRs are amazingly straight-forward to model in VHDL. you can see the shifting action of the SR. the model shown in Figure 20 is probably not the best way14. the only time the input has an affect is on the active clock edge. In yet another way of looking at this. 456 . all of the flip-flops transfer the value on their inputs to their outputs. And of course. which is of course completely arbitrary. Q3 is a shifted version of data_in. Notice that the data_in input is changing at various times. • • • • Yes. Q3 is latched into the second to the left-most flip-flop. you may have to use a bunch of them to actually obtain the data width that you need. Another issue that usually surrounds SRs is the notion of cascadeabilitly. on the active clock edge.

Once again. 15 16 In this context “cascade” is a fancy way of saying “connect up the part properly”. CLK : in std_logic). -----------------------------------------------------------------. We can only hope. you’ll need to cascade15 eight 8-bit SRs in order to create a 64-bit SR. Most SRs do a lot more stuff such as shift left. it’s rather straight-forward to model in VHDL. shift right. The following quick example hopefully16 shows that. Figure 376: VHDL code for the universal shift register.massively generic 4-bit right-shifting shift register ---------------------------------------------------------------entity my_sr is port ( DATA_IN : in std_logic. parallel load.5 Universal Shift Registers The truth is that shift registers that only shift in one direction are not the useful. end if. end process. 457 . hold (don’t change state) etc. 16. things really used to be done this way.DATA_IN) begin if (rising_edge(CLK)) then tmp_D <= DATA_IN & tmp_D(3 downto 1). DATA_OUT : out std_logic. begin process (CLK. the power of VHDL behavioral modeling is highlighted by the fact that no matter what features your SR needs. Sad as it seems. end my_sr. end my_sr.Digital McLogic Design Chapter 16 ICs containing 8-bit shift registers. DATA_OUT <= tmp_D(0). architecture my_sr of my_sr is signal tmp_D : std_logic_vector(3 downto 0). parallel clear.

• • • • Hold (don’t change state) Shift right Shift left Parallel load Solution: Allow me to blather on about this before I get to the VHDL model. Figure 377 repeats Figure 15 for your viewing convenience which is a generic schematic for a simple right-shifting SR.Digital McLogic Design Chapter 16 Example 16-5 Provide a model for an 8-bit universal shift register (USR) that can perform the following characteristics. The schematic for the single storage element that you’re probably thinking of is shown in Figure 377: A typical n element shift register. In this way. 458 . each storage element is now going to have its own MUX to decide which value is going to be loaded to the storage element. The way you should think about the hardware-based solution to this problem is to imagine that each SR storage element is now going to have to decide upon what value is going to be loaded on the next active clock edge. you should be thinking MUX. When you hear the word decision in digital design-land. Figure 20: A SR element with an attached MUX for data selection.

now that we have our SR element designed. 459 . if you understand how a D flip-flop is generated using VHDL. S1 0 0 1 1 S0 0 1 0 1 D Qm P_load Qm-1 Qm+1 Comment hold parallel load shift right shift left Table 3: Summary of the SR element functionality. The code for the VHDL universal shift register is shown in Figure 380. or to put it another way. It’s not too much more complicated than just a simple D flip-flop. VHDL will save our butts once again on this one. OK. Figure 379: A black box diagram of the universal shift register. how are we going to implement it? But alas. you can effectively implement a shift-left or shiftright functionality. The final functionality of the SR element is summarized in Table 3. By selecting the input that will be loaded to the Qm SR element. All we need to do from here is to put a bunch of these in a row. the Qm+1 SR element is the D flip-flop to the right of the Qm element while the Qm-1 SR element is the D flip-flop to the left of the Qm element.Digital McLogic Design Chapter 16 Figure 20 shows that the all the functionality we need to implement the datapath circuit can be generated by applying the correct signals to the MUX. The design of a universal shift register using VHDL is straight-forward and instructive. The P_load input provides a means to input a value from the outside world that is not currently in any of the SR registers. For the circuit shown in Figure 20. you’ll easily understand the VHDL implementation of a universal shift register.

end if. end process. -. end my_sr. begin process (CLK.datapath for LED bounce display project ---------------------------------------------------------------entity univ_sr is port ( SEL : in std_logic_vector(1 downto 0). P_LOAD : in std_logic_vector(7 downto 0).default case --------------------------------when others => tmp_D <= "00000000". end case. architecture my_sr of univ_sr is signal tmp_D : std_logic_vector(7 downto 0). An overview of the inputs and outputs are provided below.DR_IN.shift left ----------------------------------when "11" => tmp_D <= tmp_D(6 downto 0) & DR_IN.right and left side inputs end univ_sr. This is the concatenation operator in VHDL. • D_LOAD: this input provides the signals that can be loaded into the individual SR elements. Namely. D_OUT <= tmp_D. -. Figure 380: VHDL code for the universal shift register. -. there are a couple of instances of the “&” operator.DL_IN : in std_logic). DR_IN.SEL. • D_OUT: this signal provides outputs from the individual shift register elements. D_OUT : out std_logic_vector(7 downto 0).Digital McLogic Design Chapter 16 -----------------------------------------------------------------. There is some new and cool stuff listed in the VHDL code of Figure 380.do nothing (don't change state) -------------when "00" => tmp_D <= tmp_D. -. CLK : in std_logic.P_LOAD) begin if (rising_edge(CLK)) then case SEL is -. It is used to concatenate two signals (or parts of two signals) together.parallel load -------------------------------when "01" => tmp_D <= P_LOAD. 460 .shift right ---------------------------------when "10" => tmp_D <= DL_IN & tmp_D(7 downto 1).DL_IN. This loading is done “in parallel” which means all SR storage elements are loaded simultaneously. -.

There are four operations included in this USR which can be controlled with these two bits. 461 . DL_IN: These two inputs provided a signal to input from either the left or right. the DL_IN signal is input into the left-most USR element.Digital McLogic Design Chapter 16 • DR_IN. the DR_IN signal is input to the right-most SR element. When the USR is shifting left. • CLK: the clock is a typical clocking signal that synchronizes all the operations of the USR. • SEL: these inputs control the operation of the shift register. if the USR is shifting right. Similarly.

using the attribute approach detail in this section is a simple but viable alternative. There are VHDL constructs available to force the VHDL synthesizer to encode FSM behavioral models using a one-hot code. there are many approaches that can be used to model FSMs using VHDL. The real engineering involved in implementing FSM is in the generation of the state diagram that solves the problem at hand. The process is so straight-forward that it is often considered cookie cutter. Due to the general versatility of VHDL. The approach used in this chapter is referred to as the dependent style of FSM model.Digital McLogic Design Chapter 16 Chapter Summary • Modeling FSMs from a state diagram is a straight-forward process using VHDL behavioral modeling. there are options that can be chosen in the synthesizer toolset that allow the user to indirectly select the exact flavor of state variable encoding. The actual encoding of the FSM’s state variables when enumeration types are used is left up to the synthesis tool. external outputs of FSM can be assigned by including concurrent signal assignment statements in the FSM model. Generally speaking. These constructs allow the digital designer to directly control the state variable encoding. If a preferred method of variable encoding is desired. Although state variables can be simulated using this approach. there are many standard flavors to choose from though only two were discussed in this chapter. • • • • 462 . When enumeration types are used to represent state variables. This approach used two processes to model FSM behavior: one process for the sequential elements of an FSM and one process for the combinatorial elements. the VHDL synthesizer has the ultimate control as to how the state variables are actually assigned.

end fsm. end if. comb_proc: process(PS.NS. if (X = '0') then NS <= A. end process comb_proc. Z1. NS <= A. elsif (rising_edge(CLK)) then PS <= NS. Z2 <= '1'. else NS <= C. end process sync_proc. RESET : in std_logic. when C => Z1 <= '1'. Z2 <= '1'. end if. The state variables should be encoded as listed and also provided as outputs of the FSM.NS : state_type. end if.Digital McLogic Design Chapter 16 Chapter Problems 1) Draw the state diagram associated with the following VHDL code. 463 . end case. when others => Z1 <= '1'. Z2 <= '0'. else NS <= B. Z2 <= '0'. architecture fsm of fsm is type state_type is (A. end if. end fsm. Z2 <= '1'. when A => Z1 <= '0'. else NS <= A. when B => Z1 <= '1'. 2) Write a VHDL behavioral model that could be used to implement the state diagram on shown in the right. begin sync_proc: process(CLK.X) begin case PS is Z1 <= '0'.B.Z2 : out std_logic. Be sure to provide a legend and completely label everything. Z2 <= '0'. if (X = '0') then NS <= B.RESET) begin if (RESET = '0') then PS <= C. Z2 <= '0'.CLK : in std_logic. Z2 <= '0'. entity fsm is port ( X. if (X = '0') then NS <= A.C). signal PS.

NS <= S1. entity fsmx is Port ( BUM1. elsif (BUM1 = '1') then TOUT <= '1'. end if. end if.BUM2) begin case PS is when S1 => CTA <= '0'. when others => end case. architecture my_fsmx of fsmx is type state_type is (S1. when S3 => CTA <= '1'. end process comb_p. if (BUM2 = '1') then NS <= S1. 4) Write a VHDL behavioral model that could be used to implement the state diagram on shown in the right.CTA : out std_logic). 464 . TOUT. signal PS. comb_p: process (CLK. NS <= S2. end my_fsmx. begin sync_p: process (CLK. elsif (BUM2 = '0') then NS <= S2.BUM2 : in std_logic.NS) begin if (rising_edge(CLK)) then PS <= NS. NS <= S3.BUM1. TOUT <= '0'. if (BUM1 = '0') then TOUT <= '0'. NS <= S1. Be sure to provide a legend and completely label everything. end fsmx.NS : state_type. CTA <= '0'.S2. end if.Digital McLogic Design Chapter 16 3) Draw the state diagram associated with the following VHDL code.S3). TOUT <= '0'. when S2 => CTA <= '0'. TOUT <= '0'. end process sync_p. CLK : in std_logic.

end case. attribute ENUM_ENCODING of state_type: type is "001 010 100". end my_fsm. else NS <= A.C). end if. else NS <= C. B. Z2 <= '0'. others. signal PS. end if. Z2 <= '1'. NS <= A. elsif (rising_edge(CLK)) then PS <= NS.X) begin case PS is when A => Z1 <= '0'. begin sync_proc: process(CLK. when C => Z1 <= '1'. 6) Write a VHDL behavioral model that could be used to implement the state diagram on shown in the right. architecture my_fsm of fsm is type state_type is (A. when B => Z1 <= '1'. Be sure to provide a legend. when others => Z1 <= '1'. std_logic_vector(2 downto 0)).CLK RESET Z1.Digital McLogic Design Chapter 16 5) Draw the state diagram associated with the following VHDL code. C. entity fsm is port ( X. : : : : in in out out std_logic.NS : state_type. Z2 <= '0'. end if. std_logic.Z2 Y end fsm. Encode the state variables as listed and also provided them as outputs of the FSM.B. 465 . Z2 <= '0'. if (X = '0') then NS <= A. else NS <= B. std_logic. Consider the outputs Y to be representative of the state variables. if (X = '0') then NS <= A. end if.NS. end process sync_proc. Z2 <= '1'. if (X = '0') then NS <= B. with PS select Y <= "001" when "010" when "100" when "001" when A. Z2 <= '1'. end process comb_proc. comb_proc: process(PS. Z2 <= '0'. attribute ENUM_ENCODING: STRING. Indicate the states with both the state variables and their symbolic equivalents.RESET) begin if (RESET = '0') then PS <= C.

attribute ENUM_ENCODING: STRING. end fsm.NS : state_type. NS <= sC.X2 : in std_logic. Z1. Z2 <= '1'. end process sync_p. NS <= sC. else Z1 <= '1'. architecture my_fsm of fsm is type state_type is (sA. when sD => if ( X1 = '1') then Z1 <= '1'. elsif (rising_edge(CLK)) then PS <= NS. end case. NS <= sA.SET) begin if (CLR = '1' and SET = '0') then PS <= sA. Z2 <= '0'. begin sync_p: process (CLK. end my_fsm. 466 . Z2 <= '0'. Z2 <= '1'. end process comb_p.sC.CLR.X2. Z2 <= '0'. attribute ENUM_ENCODING of state_type: type is "1000 0100 0010 0001". Z2 <= '1'. else Z1 <= '1'. end if.X1. end if.SET. signal PS. Z2 <= '1'.NS. NS <= sD. end if. comb_p: process (X1. else Z1 <= '0'. end if. end if. NS <= sC.Z2 : out std_logic). NS <= sB. elsif (CLR = '0' and SET = '1') then PS <= sD. Be sure to label everything. NS <= sB.sD). else Z1 <= '0'. when sB => if ( X2 = '1') then Z1 <= '1'.PS) begin case PS is when sA => if ( X1 = '1') then Z1 <= '0'. Z2 <= '0'. entity fsm is Port ( CLK. when sC => if ( X2 = '1') then Z1 <= '0'.sB.Digital McLogic Design Chapter 16 7) Draw the state diagram that corresponds to the following VHDL model and state whether the FSM is a Mealy or Moore machine.CLR. NS <= sB.

The state variables should be encoded as listed and also provided as outputs of the FSM. 9) Write a VHDL behavioral model that could be used to implement the state diagram on shown in the right. 467 . The state variables should be encoded as listed and also provided as outputs of the FSM. 10) Write a VHDL behavioral model that could be used to implement the state diagram on shown in the right. The state variables should be encoded as listed and also provided as outputs of the FSM.Digital McLogic Design Chapter 16 8) Write a VHDL behavioral model that could be used to implement the state diagram on shown in the right.

14) Write a VHDL behavioral model that could be used to implement the state diagram on shown in the right. The state variables should be encoded as listed and also provided as outputs of the FSM. 12) Write a VHDL behavioral model that could be used to implement the state diagram on shown in the right. The state variables should be encoded as listed and also provided as outputs of the FSM.Digital McLogic Design Chapter 16 11) Write a VHDL behavioral model that could be used to implement the state diagram on shown in the right. 468 . The state variables should be encoded as listed and also provided as outputs of the FSM. 13) Write a VHDL behavioral model that could be used to implement the state diagram on shown in the right. The state variables should be encoded as listed and also provided as outputs of the FSM.

the cost of digital stuff was such that the average human could not afford to take notice. Main Chapter Topics FSMS MODELS USING VHDL: This chapter presents an intuitive view of the state diagram. • The digital stuff required some circuitry to control it. The main problem with software-based control was that the required software increased the complexity of your program (and thus the length of the program) 1 2 But it was a giant pain in the ass. The key to generating state diagrams is understanding the basic state diagram symbology and terminology and how they relate to designing a solution to solving the problem at hand. In regards to FSMs.1 Chapter Overview Implementing FSMs from a provided state diagram was our initial focus when dealing with FSMs. an overview of the path that has led us to where we are today is listed below (a few details have been left out): • In relatively recent history. but it should still be helpful in solidifying the various concepts associated with FSMs. FSM Problem Solving: This chapter finally introduces the true meaning of FSM with their ability to solve real design problems. The thought here is that maybe you could use a computer to control a computer. Having an intuitive feel for state diagrams and being familiar with the mechanics of implementing FSM. you’ll be ready to handle just about any control problem known to both humans and academic administrators alike. but until relatively recently. It actually started happening a long time ago. A true play on words. we’ve developed a need for lowlevel control of just about everything in our lives. The skills required to implement the FSM with either discrete logic components (gatelevel implementations) or VHDL behavioral models was not overly challenging once you did a few examples1.2 The Big FSM Picture The world progressed really nicely for billions of years without having the concept of finite state machines or any other such important items.17 Chapter Seventeen 17. Now that we have some of the mechanics of FSM implementation down. but. The wait is finally over. Our intent here is to provide an intuitive look at the state diagram and the associated timing diagrams. these were still the days where computers were actually expensive (and big) and had names like “HAL”. we change our focus the generation of the state diagram. FSMs were the logical2 option. digital stuff (computers and things) started happening. 469 . In recent history. particularly control by tiny electronic things. Some of the presented information will seem like review. (Bryan Mealy 2011 ©) 17.

The push here is to choose the smallest/cheapest MCU to get the job done. MCUs can do a lot of tasks (generally at the same time. This means that you could use the PLD to handle logic functions required by your circuit. there were many more ICs out there. but they were now less expensive. There were also ICs dedicated to controlling specific devices which were essentially required because devices were becoming complex and control requirements were also growing in complexity. This meant that hardware devices could now essentially be under software control (what drives the MCU) rather than hardware (what FSMs are constructed from). sort of). In other words. there are most likely quite a few FSMs embedded in the amazingly complex ICs that control everyday devices such as cell phones. Keep in mind that back in these days. More importantly. So the good news is that FSMs are not quite dead. This means a less capable MCU is in charge or more tasks. they are not appropriate for all such tasks. There generally had been many ICs out there. including FSMs in on the IC requires a relatively small amount of real estate which makes them cost effective. The downside of having MCUs do a lot of tasks is that the associated software becomes more complicated and error prone based on the number of tasks it is required to control. In the end. And what the heck. memory was much more expensive than it was today. This gets ugly. Although you probably don’t know it. 4 3 470 . This approach was a pure hardware approach and could be constructed with readily available and relatively inexpensive materials. the development environments (primarily PC-based) and associated CAD tools were significantly less expensive also. Although MCUs nicely handle some control tasks. 5 The thought here is that if you’re going to fabricate an IC. The downside is that using the MCU to control hardware requires processing time from the MCU or dedicating an entire MCU to the control task. MCUs are often limited by the number of pins they have to interface to the outside world. The pin count is generally related to the cost of the MCU also. but all of a sudden. transferring control from the MCU to the FSM would no longer be too costly. • Microcontrollers (MCUs) started becoming prevalent4. This meant that the hardware being controlled by FSM could now be controlled in many circumstances by MCUs. if you could purchase an IC that controlled some other digital device.Digital McLogic Design Chapter 17 and increased the overall memory requirements of your design3. Now days. Discrete components such as gates and flip-flops were used to construct FSMs which could be used to control things. they are still used quite often to avoid some of the hassles created by complicating the software associated with the controlling circuits using MCUs. The advent of relatively inexpensive but powerful PLDs as well as the relatively inexpensive IC fabrication technology5 allows the offloading of control tasks from the system software to some form of external hardware. it makes sense to use that PLD to implement a FSM while you’re at it. MP3 players. As this becomes an intensely complex problem once you have one MCU in charge of controlling many tasks. • Programmable Logic Devices (PLDs) such as FPGAs and CPLDs hit the market and became BIG (in size at least). • Integrated circuits (ICs) started taking over. The upside of this software control is the flexibility in software (re-programmability). And this was good. These new ICs were providing more complex functionality which meant that some of the control functions that had been relegated to FSMs were now being built into the various ICs. The type of errors associated with digital systems such as these are intermittent and hard to reproduce and repair. you would therefore not need to design a FSM that controlled the device. They had actually been around for awhile. Since you may have already been using a PLD. which is good. In other words. you could use the PLD to implement the entire MCU (known as a soft-core MCU).

external outputs.Digital McLogic Design Chapter 17 bowling balls and other such useless devices that we can’t seem to live without. Mealy/Moore machine. output decoding logic.1 shows the general model of the FSM acting as a controller circuit. FSMs are to help reduce the I/O pin count requirements in MCU-based applications. everything beyond that point is straight-forward to the point of being tedious grunt work. next state decoder. Without doubt. the state diagram symbology and the PS/NS table content) Understand how to implement the FSM (either flip-flops and discrete logic or some type of programmable logic device) 3. strike. etc. What a deal! Use them where you can to make your world nicer.3 The FSM: An Intuitive Over-Review The Finite State Machine makes a great little controller circuit. in theory. The toughest part of any FSM design is to generate the state diagram. The question that arises is: How do I use a FSM to control something? The answer to this question is based on whether you understand the following: 1. next state. 2. 471 . The following sections provide an intuitive overview of FSMs and include a few examples where FSMs can be used in somewhat real-world control problems. spare. 4. the fourth point is the least “engineering” related of the four points and amounts to what I refer to as grunt work.) Understand the symbology used to describe the FSM (namely. In other words. 17. This grunt work includes discrete and VHDL behavioral FSM implementations.1. state transitions. And you also generally need a clock signal to keep things synchronized. the external inputs act as the status signals to the circuit your controlling while the external outputs act as the control signals that interface with hardware outside of the FSM. Figure 17. This chapter describes everything you need to know in order to design FSMs that act as controller circuits. The only real stumbling block to designing FSMs is learning to represent your intuition with the standard FSM lingo and symbology. output decoder. next state decoding logic) Understand the various lingo used when dealing with FSM (such as present state. FSMs are actually quite intuitive. the fourth item is relatively straight-forward in comparison. state variables. the first three items require a solid understanding of the various design-related aspects of FSMs. If you think about it. you’ll find that FSMs are actually quite intuitive once you get comfortable with the four items listed above. In other words. the things that are important to a controller circuit are the control signals (to do the actual control) and the status signals (to let you know what’s going on). Also. FSMs are massively useful as well as massively interesting. external inputs. Most of the major issues dealing with the first three points listed above are mapped out in the following sections. FSMs generally simplify required control tasks by off-loading the software-based control requirements to nonsoftware-based circuitry. The point we’re trying to make here is that. Understand how the FSM operates in terms of the underlying hardware (such as the storage elements. excitation logic. In the FSM model shown in Figure 17. namely FSMs.

Digital McLogic Design Chapter 17 Figure 17. • A state needs some way to delineate it from other states which is why the state bubble generally contains some type of identifying information.2: The State Bubble and associated timing diagram. 472 . The state bubble is used to represent a particular “state” in a FSM. In the case of the diagram in Figure 17. For example. Some of the key features regarding this state bubble are listed below. each state has a unique set of bits being stored in the storage elements. Although you could technically provide duplicate symbolic names for states. • • (a) (b) Figure 17. any given state is bounded by the active edges of the underlying storage elements. The boundaries of these time slots are delineated by the associated active edges of the clock as is shown in Figure 17. Generally speaking.3.1 The State Bubble The state bubble is one of the major features of a state diagram-based FSM description. There are generally two types of identifying information which include either a symbolic name. some form of symbolic representation is used in most state diagram except for FSM implementing counter. 17. In other words. Figure 17. The symbolic state names should be unique for any given state diagram to help disambiguate the states on a human level. The states are represented in timing diagram by the time slots representing the possible state values. a state name such as “WAIT_FOR_SIGNAL” conveys a lot more information than “10”. the actual implementation dependent bit representation of the states must be unique.2(b).2(b).1: The general view of a FSM used as a controller circuit.2(a) shows a typical state bubble. In other words. Using symbolic names also delivers more information to the human reader if the state names are chosen such that they describe what is going on in that state. the elements are rising-edge triggered (RET) storage elements in that the state boundaries are being defined relative to the rising edge of the associated clock. or the actual state variable values used to encode the FSM. The states themselves are defined by the current value of the underlying storage elements.

the state diagram is not the best available representation of the FSM if you’re are required to actually implement the FSM using discrete logic. There are three forms of information presented by state diagrams: 1) the various states in the FSM. The relation between the timing diagram shown in Figure 17. and 3) the values of the various outputs associated with the various states (and external inputs in the case of a Mealy-type FSM). you would want to give these more meaningful names such as something to indicate why the state exists (or what is going on in that state). or. they help humans reduce functions with a visual approach. When we talk of state. 7 We’ve dealt with asynchronous inputs in a previous chapter. In real life. you would never consider using a K-map-type approach. The notion of simplicity arises in the fact that these are truly the only possible transitions7 (generally speaking).Digital McLogic Design Chapter 17 17. In reality. there is clocking information present in a state diagram.3(b) and the state diagram in Figure 17.3(a) is the key to understanding state diagrams in general. the state transition arrow can be thought of as representing what happens on each of the associated clock edges. there are only two possible state transitions in a state diagram from a given state: on the associated clock edge.3(a) have unique names. we’re talking about all the time in-between the active edges of the clock. no commitment has been made to assigning unique binary codes to disambiguate the states on a hardware level.3(a) give no indication as to how the states will be represented when the FSM is actually implemented. The transition between states is represented by an arrow directed from the source state to the destination state. There several approaches available to implement FSMs. 2) the input conditions that control the transitions from one state to another state (or back to the same state). in a state diagram relative to a given state.2 The State Diagram The state diagram is one of many methods used to model a FSM. the clock is never shown in the state diagram. Even though the system clock is an integral part of a FSM. This section deals primarily with the transitions associated with a state diagram. The particularly pleasing aspect of the state diagram is that it is designed to convey meaning and understanding to the human viewer (as opposed to facilitating the actual implementation of the FSM as a VHDL model generally does). The state diagram contains no clock signal as you may expect. In other words. • The terminology used to describe how a FSM goes from one state to another is called a state transition or just transition. 473 . but they’re a useless way to perform function reduction in an algorithmic sense6. either the FSM transitions to another state or • • • 6 In other words.3(a) shows a typical (and overly generic) state diagram.3(a)). The only part of the clock signal we’re interested in is the clock edges.3. The state names provided Figure 17. In other words. one of two things must necessarily occur. but it’s only implied as opposed to specifically listed. On each clock edge. The two states shown in Figure 17. Some of the key features of this state diagram are described below. if you had to write a program to reduce Boolean functions. the arrows represent what action occurs on the clock edges. Roughly speaking. On the other hand. 2) the FSM can remain in the same state (indicated by the “no state change” label in Figure 17.3(a)). the state bubble essentially represents all the time between any two active edges of the clock. a transition can occur from 1) one state to another state (indicated by the “state change” label in Figure 17. What we’re interested now is the typical operation of an FSM. It’s sort of like K-maps. The state transitions caused by asynchronous inputs (such as presets and clears) are simple to model and implement due to the fact they represent “special” circumstances in a FSM. Figure 17.

so there must be conditions that decide on which transition will actually occur.3: The state diagram (a). then you can declare the following state as the next state relative to the present state.3. we often listed no conditions. the state transition arrows in Figure 17.3 Conditions Controlling State Transitions As you would guess from examining the state diagram shown in Figure 17. and the associated timing diagram (b). In the global sense. there are two forms of information that will decide on what transitions will be taken from any give state: 1) at least one of the external inputs to the FSM. maybe we should have listed a “don’t care” for those particular transitions. 2) the given state the FSM is currently in (otherwise known as the present state).Digital McLogic Design Chapter 17 the FSM remains in the same state.4 shows the way we indicate these conditions. and. every state transition arrow must have conditions associated with it that describes what governs the transition8. In general. there must be some mechanism that decides on which transition will occur from a given state. Figure 17. Each state has it own set of conditions that govern transitions.3(a) can be thought of as the minute piece of time between two states in the associated timing diagram. As we saw with counters. The second condition is somewhat too general because when we’re talking about state transitions.3(b). Note in Figure 17. • The concept of Present State (PS) and Next State (NS) is somewhat hard to pin down in a timing diagram such as the one shown in Figure 17. A more general way of saying this is that a state transition occurs on every clock edge.3(a) that state1 has two arrows leaving the state.3(a). (a) (b) Figure 17. 17. there are three important things to keep in mind: This is sort of not always true. As you can see from Figure 17. the way the rules governing transitions are listed is by placing the conditions next to the state transition arrows. In reality. so in terms of state diagrams. we’re more so concerned on a state-by-state basis as to what external input conditions control the state transitions from a given state. but sometimes it is a transition back to the same state. The truth here is that the present state and next state concept and accompanying information is better modeled in the PS/NS table as opposed to the timing diagram.4. we talk about them from the context of being in one state and transitioning to another state. 8 474 . This definition of course changes as you traverse the timing diagram. The arrows help us model FSM behavior but have no true significance in the associated hardware. If you declare one state as the present state. when the transitions were unconditional. On this note. The problem is that the present state (and hence the next state) is constantly changing as you travel from left to right on the time axis. So once again.

The external inputs to the FSM can be thought of as status inputs from the circuit that the FSM is controlling. hard to trace error. And if you found yourself issuing the same control signals from different states. 475 . The most likely thing to do in this case is to stay in the same state. Worst of all. the state diagram will have different states and the control signals output from one state are generally not the same as control signals output from other states. The idea here is that. If this condition did exist.3. the FSM will once again not know what to do. One thing to keep in mind here is that the FSM is a piece of hardware that is used to control another piece of hardware. the external inputs control the state transitions while the external outputs are issued based on which state the FSM currently resides in (and on external inputs in the case of Mealy-type FSMs). The thing we haven’t mentioned yet is that there are also some external outputs from the FSM which are used to control inputs to the circuit being controlled by the FSM. the FSM will transition to one state or another. If no conditions are listed with the state transition arrow. 17. But in reality. We’ll see examples of this type of transition later. This means that there can never be a particular set of input conditions that is associated with two different transitions arrows leaving the same state.4 External Outputs from the FSM The external outputs from a FSM are generally used to control other circuits. Once again. Generally speaking.4: How state diagrams indicate the conditions associated with state transitions. The set of conditions associated with a particular state must be complete.Digital McLogic Design Chapter 17 1. there is a chance you have a redundant state (which is only a problem in the sense that a redundant state wastes hardware). the FSM would not be able to decide which state to transition to. this usually means the state transition is unconditional. you may have created an ugly. your state diagram should leave no room for guessing. In that the external input signals are used as status inputs to the FSM. If there is a set of conditions from a given state that is not covered by the associated state transition arrows. 2. This is because in general. the external output signals are used to directly control some other circuit. it is generally a better ideal to provide a “don’t care” of the condition portion of the state diagram. you’ll be performing different control functions based on the different states in the FSM. Sometimes you may not like the tool’s decision. you truly must cover all the cases or else the VHDL synthesizer or some other development tool will decide for you. The conditions associated with the state transition arrows from a given state must be mutually exclusive. The outputs are the next step in the FSM and are covered in the next section. You’re boss will hate you and your modest raise will become even more modest. Figure 17. When you implement FSM using VHDL. 3. depending on the current status of the hardware that is being controlled. Once again. It would be literal FSM anarchy and the digital gods would be unhappy.

Although there are probably a lot of ways to represent these outputs. 476 . The outputs Moore-type outputs are a function of the state variables only while the Mealy-type outputs are a function of both the state variables and the current external inputs. The common terminology used is to describe you FSM as either a Mealy-type FSM. they are represented by placing their values inside of the state bubble. or Moore machine. be sure to provide a detailed legend in order to appease the FSM Gods (as well as whoever is looking at your circuit).6. In this case. make an effort to be as clear as possible. There can be any number of outputs represented inside the bubble. For your viewing pleasure. Figure 17. Figure 17. this type of machine is considered a Mealy-machine since the overall machine contains external outputs that are a function of external inputs. there are FSMs that have both Mealy and Moore-type outputs. a subset of the Mealy-type output. Different outputs are usually delineated by a comma but you can use whatever method you choose9. Since Moore-type outputs are a function of the state variables only. Although these two types of outputs are similar in most aspects. the method that we present here is used by the world’s most intelligent people (so you should use it too). The key to any state diagram is the legend that tells the viewer how to interpret what they’re looking at. Figure 17. Don’t be 9 As always.6: Block diagram of a Moore-type FSM.7 shows a state diagram that uses this approach.5: Block diagram of Mealy-type FSM.5 and Figure 17. or better yet. So if you deviate from the approach for representing state diagrams provided here. What we’re concerned about in this section is how we’re going to represent the Mealy and Moore-type outputs on the state diagram. This is somewhat intuitive in that the Moore-type output could be considered a special case. they have one major difference.Digital McLogic Design Chapter 17 There are two different types of outputs in a FSM: Mealy-type outputs and Moore-type outputs. a block diagram of a Mealy and Moore-type machine is yet again provided in Figure 17. or a Moore-type FSM. particularly in their controlling functions. As you will see soon. or Mealy machine.

8 that can sometimes go without notice.8 if you by chance look close enough. but if you can think of a better approach.8 and Figure 17.8 due to the fact that there are two transitions from state1. To account for these characteristics in a state diagram. knock yourself out. the outputs are listed next to the external inputs associated with the individual state transition arrows and differentiated by the addition of the forward slash. And it should come as not surprise that you can represent both Mealy and Moore-type outputs in the same state diagram. Figure 17. they are represented by placing them next to the particular external inputs and associated with a given state transition arrow. Be sure to note the similarity between the state diagrams of Figure 17. But… the listed condition of the Mealy-type outputs is always associated with the state the arrow is leaving (and not the state the arrow is entering). so be sure to look close enough. Once again. Figure 17. Figure 17. the current Mealy-type outputs are also a function of those same inputs.8: Representing Mealy-type outputs in a state diagram. Clarity and readability takes home the prize when drawing state diagrams. if a particular FSM has multiple Mealy-type outputs. But then again.9 shows an example of a state diagram that contains both Mealy and Moore-type outputs. these should be represented with either a comma separated list or something equally as readable.7: The State Bubble with associated Moore outputs. Since the Mealy-type outputs are a function of the external inputs.9. Although this is not a complex point. Note that there are two sets of Mealy outputs shown in Figure 17. There is a massively important feature shown in Figure 17. This is listed in Figure 17. Figure 17. The arrows are associated with the state transitions which are based exclusively upon the current external inputs. 477 . Mealy-type outputs are not represented inside of the state bubble because they are a function of some combination of the external inputs as well as the state variables. Representing the Mealy-type outputs in this manner may not be the clearest possible way. understanding the symbology that is used to represented the state transition arrows and their association with the Mealy-type outputs generally takes a little getting used to.8 shows an example of this approach.Digital McLogic Design Chapter 17 afraid to increase the size of your bubble on your state diagram in order to include all the outputs.

5 The Final State Diagram Summary Figure 17. The example state diagrams we’ve work with so far seem to indicate the FSM states are somehow limited in the number or transition arrows that can leave (or enter) the state. The key issues to be aware of here are: 1) make sure all of the conditions associated with each state transition are unique (no two arrows can have the same conditions). but not all of the outputs need to be assigned for every state. the general rule with listing outputs is that you only list the “important” outputs for a given state. Figure 17.9: A state diagram that has both Mealy and Moore-type outputs. it is assumed to be a “don’t care”. If in any state a given output is not assigned. your state diagram becomes quite cluttered thus causing the FSM Gods to shudder and look frownly upon your state diagram. The point that the state diagram of Figure 17. but if you have a lot of outputs.10: The State Bubble. In terms of the circuit that is being controlled by the FSM. It is not bad practice to list all the external output for each state. the presence of don’t cares simplifies the output decoding logic but has no negative side-effects on the FSM as was the case when not all external input conditions were accounted for in the state transitions from a given state.10. As a final note in this section.Digital McLogic Design Chapter 17 Figure 17.11 provides a quick overview of the relation between the FSM black box and the example state diagrams we’ve been working with in this section. What you should be gathering from this diagram is that properly designed state diagrams have a particular structure that is 478 .10 is trying to be make is that there is no limit to the number of transition arrows leaving a given state. the outputs that have been omitted from a state will not have any effect on that circuit that is being controlled by the FSM. 17. As you would imagine.3. There are generally many outputs from a FSM. and 2) all possible conditions based on the inputs associated with the state transition arrow leaving the state are represented (don’t assume the FSM will stay in the same state if you don’t explicitly specify all conditions). There is actually no limit as is somewhat shown in the state diagram of Figure 17.

Once final comment is in order here… There always seems to be question of how and where to start problems that require the generation of state diagram. Having something or anything down on