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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO.

6, JUNE 1997

905

A High-Speed Median Circuit


Ion E. Opris and Gregory T. A. Kovacs

Abstract A high-speed analog median circuit is presented using a two-stage architecture to minimize the errors around the transition corners. Prototypes have been designed and built using the Orbit 2-m CMOS process. The design has been optimized for low crossover distortion and fast transient recovery in less than 200 ns. The active area is 0.2 mm2 , and the circuit dissipates 7 mW from a single 5 V supply while being able to drive an external 30 pF capacitor. Index TermsActive lters, analog processing circuits, nonlinear circuits.

I. INTRODUCTION

EDIAN ltering has emerged as one of the most important nonlinear ltering applications due to its properties of rejecting impulse noise while perfectly preserving step changes. Many applications in image and speech processing are discussed in the literature [1], [2]. Most of those applications use digital techniques for nding the median. However, reduced circuit complexity and power dissipation can be achieved in a pure analog implementation [3], [4]. One of the problems associated with analog implementations is the inherent errors in the transition regions (corner errors). In [5] we described an analog median circuit that has a very sharp transfer characteristic, virtually eliminating the errors in the transition region. However, this approach is not suitable for high-speed circuits due to large internal node voltage swings. A two-stage architecture for the median circuit [6] allows a tradeoff between the dc accuracy and a fast transient response. Using cascode error ampliers, the dc accuracy was greatly improved with minimal impact on the transient performance. II. CIRCUIT DESCRIPTION

Fig. 1. Block diagram of the high-speed median circuit.

Fig. 2. Schematic detail of the high-speed median circuit. TABLE I MOS DEVICE SIZES FOR THE HIGH-SPEED MEDIAN EXTRACTOR

The principle of the nonlinear median operation is shown in the block diagram of Fig. 1. The three differential ampliers are in a feedback loop with the median selector circuit implemented with the nMOS transistors . In order for the output voltage to be in the active linear region, the bias current has to ow through at least one of the branches , , or . Therefore, at least two of the nodes , , and have a high potential. The equilibrium condition is reached if one of the amplier outputs

Manuscript received January 11, 1996; revised December 20, 1996. The authors are with the Center for Integrated Systems, Stanford University, Stanford, CA 94305 USA. Publisher Item Identier S 0018-9200(97)03844-4.

is saturated high, one is saturated low, and one is in the active linear region. If the differential gain is high enough, the output is essentially equal to the median of the inputs. This conguration reduces the transition errors in the coarse median by the gain of the differential ampliers extractor .

00189200/97$10.00 1997 IEEE

906

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 6, JUNE 1997

Fig. 3. Experimental dc transfer Vin = 1:5 V and Vin = 3:5 V.

characteristic

with

inputs

set to

Fig. 6. Rejection of the nonmedian input. Measured output voltage variation for Vin = Vin = 2:5 V.

Fig. 4. Experimental dc error from median for Vin = 3:5 V.

Vin

= 1:5 V and

Fig. 7. Transient response to a 3 Vpp /1 MHz sine input with inputs set to Vin = 1:5 V and Vin = 3:5 V.

Fig. 5. Detail of the experimental dc transfer characteristic.

Fig. 8. Transient response to a 200 mVpp /1 MHz square wave input.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 6, JUNE 1997

907

Fig. 9. Microphotograph of the high-speed median circuit. The circuit dimensions are 720

m

2 270 m.

Details of the circuit schematic are presented in Fig. 2. Only one differential amplier and one rank selector branch are shown. Each selector branch was implemented using four nMOS transistors ( and in Fig. 2) to obtain a completely symmetrical structure. The nMOS and pMOS transistors limit the voltage swing of the internal node to several hundreds of mV, therefore reducing the transient nonlinear recovery. Since any of the inputs can be the active input, any of the amplier outputs can be the active driving node in the feedback loop. A frequency compensation network ( - ) is necessary for each internal node , , or . The series resistor moves the right half-plane transmission zero to the left half-plane, improving the phase margin. This circuit has a slew-rate and a small signal bandwidth determined by the bias current of each amplier stage , the transconductance of the input pMOS transistors , and the size of the compensation capacitor . III. EXPERIMENTAL RESULTS The circuit has been fabricated using a 2- m double-poly CMOS process. The transistor sizes are shown in Table I. Since the circuit was not buffered on chip, the output stage was designed to drive at least 30 pF of external capacitance. Using a tail current in the ampliers of A, the small signal bandwidth is about 20 MHz, and the slew-rate is in excess of 25 V/ s. The total power dissipation from a single 5 V supply is 7 mW. All transistors were folded in the layout design to reduce the parasitics. The total active area is 0.2 mm . The dc transfer characteristic for V and V shows very sharp corners, Fig. 3. The total measured dc error from the true median, shown in Fig. 4, is dominated by the input transistors mismatches. All the random offsets measured for the four available samples were less than 5 mV. The linear range in the follower mode ( ) is limited by the pMOS threshold voltage and the saturation of the tail current sources in the differential ampliers and, on the lower end, by the output nMOS transistors entering the

linear region. With a 5 V supply, the measured linear range output was 0.54.0 V. The high gain of the cascodes minimizes both the systematic errors due to a nite loop gain and the corner errors near the transition points. The estimated open-loop gain of the cascode stage from the dc transfer characteristics is greater than 49 dB. The detail of the dc transfer characteristic in Fig. 5 conrms very small dc errors in the transition regions and also experimentally illustrates the effect of input offsets on the transfer characteristic. At higher frequencies, however, due to a lower loop gain, the reduction in the inherent errors in the coarse median extractor is proportionally reduced. Another important dc test is the rejection of the nonmedian input. The output voltage variation when two of the inputs were held at a common constant potential V is less than 7 mV, Fig. 6, and it is essentially determined by the input referred offsets for different input pairs. The horizontal scale also indicates a total linear range of 7 mV, which is consistent with the measured voltage variation and conrms that this variation is essentially determined by the different input offsets and not by the corner errors, which are an order of magnitude smaller. With two of the inputs held to constant potentials, V and V, the limiting function at the output for a 3 V /1 MHz sine wave input can be seen in Fig. 7. The small distortions observed at the crossover transitions are mainly due to the internal cascode nodes without any clamps. An important advantage of this circuit is good transient behavior for both large and small amplitude input signals. Fig. 8 shows the transient response to a 200 mV /1 MHz square wave input crossing a threshold level. The nonlinear recovery occurs in less than 200 ns, and it takes somewhat longer for lower input amplitudes. The slew-rate measured with an input of 3 V /1 MHz square wave was 25 V/ s. This value is actually limited by the output bias current and the total capacitance at the output node of about 50 pF, including the test setup. The measured small signal unity gain bandwidth for the linear operation was about 18 MHz and essentially independent

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 6, JUNE 1997

of the number of active inputs. The bandwidth of the local feedback loops is actually much higher, and no noticeable increase in the corner errors was observed for an input frequency of 1 MHz. IV. CONCLUSION A simple analog circuit technique for nding the median has been described in this paper. The two-stage conguration has the advantage of minimizing the errors in the transition regions by the gain of the rst stage, and also clamping the voltage swing at the internal nodes for high-speed operation. A prototype was designed and fabricated in a 2- m CMOS process. With an active area of only 0.2 mm (Fig. 9) and a power dissipation of 7 mW from a single 5 V supply, the circuit achieved operation speeds suitable for real-time video applications. The same circuit technique can be used

for other nonlinear circuits, such as min/max circuits or other rank extractors, by modifying the rank selector appropriately. REFERENCES
[1] Y. H. Lee and S. A. Kassam, Generalized median ltering and related nonlinear ltering techniques, IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-33, pp. 672683, June 1985. [2] I. Pitas and A. N. Venetsanopoulos, Nonlinear Digital Filters: Principles and Applications. Boston, MA: Kluwer, 1990. [3] T. Jarske, O. Vainio, Y. Neuvo, and S. Long, GaAs MESFET switchedcapacitor linear-median hybrid lter, IEEE Int. Symp. Circuits Syst., 1988, pp. 14611464. [4] P. Dietz and R. Carley, An analog circuit technique for nding the median, in IEEE 1993 Custom Integrated Circuits Conf., San Diego, CA, May 912, 1993, pp. 6.1.16.1.4. [5] I. E. Opris and G. T. A. Kovacs, Analogue median circuit, Electron. Lett., vol. 30, no. 17, pp. 13691370, Aug. 1994. , A videobandwidth median lter, in IEEE 1995 Custom Inte[6] grated Circuits Conf., Santa Clara, CA, May 14, 1995, pp. 555558.