Freescale Semiconductor, Inc.

MC9S12D-FamilyPP Rev 6.1, 23-Oct-02

MC9S12D-Family
Product Brief

16-Bit Microcontroller
Designed for automotive multiplexing applications, members of the MC9S12D-Family of 16 bit Flashbased microcontrollers are fully pin compatible and enable users to choose between different memory and peripheral options for scalable designs. All MC9S12D-Family members are composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 512K bytes of Flash EEPROM, 14K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), IIC-bus, an enhanced capture timer (ECT), two 8-channel 10-bit analog-to-digital converters (ADC), an eight-channel pulse-width modulator (PWM), J1850 interface and up to five CAN 2.0 A, B software compatible modules (MSCAN12). System resource mapping, clock generation, interrupt control and bus interfacing are managed by the system integration module (SIM). The MC9S12D-Family has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 22 I/O ports are available with interrupt capability allowing Wake-Up from STOP or WAIT mode.

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Features
NOTE Not all features listed here are available in all configurations. Additional information about D and B family inter-operability is given in: EB386 HCS12 D-Family Compatibility Considerations and EB388 Using the HCS12 D-Family as a development platform for the HCS12 B family 16-bit CPU12 Upward compatible with M68HC11 instruction set Interrupt stacking and programmers model identical to M68HC11 HCS12 Instruction queue Enhanced indexed addressing Multiplexed bus Single chip or expanded 16 address/16 data wide or 16 address/8 data narrow modes External address space 1MByte for Data and Program space (112 pin package only) Wake-up interrupt inputs depending on the package option 8-bit port H 2-bit port J1:0 2-bit port J7:6 shared with IIC, CAN4 and CAN0 module 8-bit port P shared with PWM or SPI1,2 Memory options 32K, 64K, 128K, 256K, 512K Byte Flash EEPROM 1K, 2K, 4K Byte EEPROM 2K, 4K, 8K, 12K, 14K Byte RAM

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Analog-to-Digital Converters One or two 8-channel modules with 10-bit resolution depending on the package option External conversion trigger capability Up to five 1M bit per second, CAN 2.0 A, B software compatible modules Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Receive, Transmit, Error and Wake-up Low-pass filter wake-up function in STOP mode Loop-back for self test operation Enhanced Capture Timer (ECT) 16-bit main counter with 7-bit prescaler 8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer Input capture filters and buffers, three successive captures on four channels, or two captures on four channels with a capture/compare selectable on the remaining four Four 8-bit or two 16-bit pulse accumulators 16-bit modulus down-counter with 4-bit prescaler Four user-selectable delay counters for signal filtering 8 PWM channels with programmable period and duty cycle (7 channels on 80 Pin Packages) 8-bit, 8-channel or 16-bit, 4-channel Separate control for each pulse width and duty cycle Center- or left-aligned outputs Programmable clock select logic with a wide range of frequencies Serial interfaces Two asynchronous serial communications interfaces (SCI) Up to three synchronous serial peripheral interfaces (SPI) IIC SAE J1850 Compatible Module (BDLC) 10.4 kbps Variable Pulse Width format Byte level receive and transmit 4x receive mode supported SIM (System Integration Module) CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and reset) MEBI (multiplexed external bus interface) INT (interrupt control) Clock generation Phase-locked loop clock frequency multiplier Limp home mode in absence of external clock Clock Monitor Low power 0.5 to 16 MHz crystal oscillator reference clock Operating frequency for ambient temperatures TA -40C <= TA <= 125C 50MHz equivalent to 25MHz Bus Speed for single chip 40MHz equivalent to 20MHz Bus Speed in expanded bus modes. Internal 5V to 2.5V Regulator 112-Pin LQFP or 80-Pin QFP package I/O lines with 5V input and drive capability 5V A/D converter inputs and 5V I/O 2.5V logic supply Development support Single-wire background debug mode (BDM) On-chip hardware breakpoints

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Table 1 List of MC9S12D-Family members

Flash 512K RAM 14K EEPROM Package 4K Device DP512 112LQFP DT512 DJ512 DT256 112LQFP DJ256 256K 12K 4K 80QFP DG256 DJ256 DG256 DT128 112LQFP DJ128 128K 8K 2K 80QFP 112LQFP 64K 4K 1K 80QFP 32K 2K 1K 80QFP DG128 DJ128 DG128 DJ64 D64 DJ64 D64 D32 CAN 5 3 2 3 2 2 2 2 3 2 2 2 2 1 1 1 1 1 J1850 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 SCI 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SPI 3 3 3 3 3 3 3 3 2 2 2 2 2 1 1 1 1 1 IIC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 A/D 2/16 2/16 2/16 2/16 2/16 2/16 1/8 1/8 2/16 2/16 2/16 1/8 1/8 2/16 2/16 1/8 1/8 1/8 PWM 8 8 8 8 8 8 7 7 8 8 8 7 7 8 8 7 7 7 I/O 91 91 91 91 91 91 59 59 91 91 91 59 59 91 91 59 59 59

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Pin out explanations: A/D is the number of modules/total number of A/D channels. I/O is the sum of ports capable to act as digital input or output. 112 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, H = 8, J = 4, K = 7, M = 8, P = 8, S = 8, T = 8, PAD = 16 input only. 22 inputs provide Interrupt capability (H =8, P= 8, J = 4, IRQ, XIRQ) 80 Pin Packages: Port A = 8, B = 8, E = 6 + 2 input only, J = 2, M = 6, P = 7, S = 4, T = 8, PAD = 8 input only. 11 inputs provide Interrupt capability (P= 7, J = 2, IRQ, XIRQ) CAN0 pins are shared between J1850 pins. CAN0 can be routed under software control from PM1:0 to pins PM3:2 or PM5:4 or PJ7:6. CAN4 pins are shared between IIC pins. CAN4 can be routed under software control from PJ7:6 to pins PM5:4 or PM7:6. Versions with 4 CAN modules will have CAN0, CAN1, CAN2 and CAN4. Versions with 3 CANs modules will have CAN0, CAN1 and CAN4. Versions with 2 CAN modules will have CAN0 and CAN4. Versions with one CAN module will have CAN0. Versions with 2 SPI modules will have SPI0 and SPI1. Versions with 1 SPI will have SPI0. SPI0 can be routed to either Ports PS7:4 or PM5:2. SPI2 pins are shared with PWM7:4; In 112 pin versions SPI2 can be routed under software control to PH7:4. In 80 pin packages SS-signal of SPI2 is not bonded out! NOTE CAN and SPI routing features are not available on the 1st PC9S12DP256 mask set 0K36N!

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32K - 512K Byte Flash EEPROM 2K - 14K Byte RAM 1K - 4K Byte EEPROM
VDDR VSSR VREGEN VDD1,2 VSS1,2 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST

ATD0

VRH VRL VDDA VSSA PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07

ATD1

VRH VRL VDDA VSSA

VRH VRL VDDA VSSA PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PK0 PK1 PK2 PK3 PK4 PK5 PK7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19 ECS/ROMONE

Voltage Regulator

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 RXD TXD RXD TXD

AD0

Single-wire Background Debug Module Clock and Reset Generation Module

CPU12

DDRK DDRT DDRS

PPAGE

PLL

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Periodic Interrupt COP Watchdog Clock Monitor Breakpoints

XIRQ IRQ System R/W Integration LSTRB Module ECLK (SIM) MODA MODB NOACC/XCLKS

DDRE

PTE

Enhanced Capture Timer

SCI0 SCI1

PTS

PTT

PTK

AD1

Multiplexed Address/Data Bus SPI0 DDRA PTA

PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

MISO MOSI SCK SS RXB TXB RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN

DDRB PTB
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

CAN0
ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8

Module to Port Routing

BDLC (J1850)

CAN1 CAN2 CAN3

Multiplexed Wide Bus Multiplexed Narrow Bus

CAN4

IIC

SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 MISO MOSI SCK SS MISO MOSI SCK SS

KWJ0 KWJ1 KWJ6 KWJ7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7

PJ0 PJ1 PJ6 PJ7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7

DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

DDRJ

Internal Logic 2.5V

VDD1,2 VSS1,2

I/O Driver 5V
VDDX VSSX

DDRP

PLL 2.5V
VDDPLL VSSPLL

A/D Converter 5V & Voltage Regulator Reference

VDDA VSSA

PWM

Voltage Regulator 5V & I/O

VDDR VSSR

SPI1

DDRH

Not all functionality shown in this Block diagram is available in all Versions!

SPI2

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PTH

PTP

Signals shown in Bold are not available on the 80 Pin Package

DDRM

DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8

DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0

ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0

PTJ

PTM

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Figure 1 Pin assignments 112 LQFP for MC9S12D-Family

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For More Information On This Product, PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02 Go to: www.freescale.com

ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 SS2/KWH7/PH7 SCK2/KWH6/PH6 MOSI2/KWH5/PH5 MISO2/KWH4/PH4 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 XADDR17/PK3 XADDR16/PK2 XADDR15/PK1 XADDR14/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 XADDR19/PK5 XADDR18/PK4 KWJ1/PJ1 KWJ0/PJ0 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85

PP4/KWP4/PWM4/MISO2 PP5/KPW5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7/ECS/ROMONE VDDX VSSX PM0/RXCAN0/RXB PM1/TXCAN0/TXB PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA/RXCAN0 PJ7/KWJ7/TXCAN4/SCL/TXCAN0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN3/RXCAN4 PM7/TXCAN3/TXCAN4 VSSA VRL 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57

MC9S12D-Family
112LQFP

VRH VDDA PAD15/AN15/ETRIG1 PAD07/AN07/ETRIG0 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8

Signals shown in Bold are not available on the 80 Pin Package

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Figure 2 Pin Assignments in 80 QFP for MC9S12D-Family

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80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

PP4/KWP4/PWM4/MISO2 PP5/KWP5/PWM5/MOSI2 PP7/KWP7/PWM7/SCK2 VDDX VSSX PM0/RXCAN0/RXB PM1/TXCAN0/TXB PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA/RXCAN0 PJ7/KWJ7/TXCAN4/SCL/TXCAN0 VREGEN PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VRL SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

MC9S12D-Family
80 QFP

VRH VDDA PAD07/AN07/ETRIG0 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8

ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

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Figure 3 MC9S12Dx512 User Configurable Memory Map

$0000 $0000 $0400 $0800 $03FF $0800 1K Register Space Mappable to any 2K Boundary

14K Bytes RAM Alignable to top ($0800 - $3FFF) or bottom ($0000 - $37FF)

$3FFF $4000 EXT $6FFF $7000 $7000 $8000 $7FFF $8000 $4000

Mappable to any 16K Boundary 0.5K, 1K, 2K or 4K Protected Sector 12K Fixed Flash EEPROM 4K Flash overlapped by EEPROM in this configuration 4K Bytes EEPROM Mappable to any 4K Boundary 16K Page Window thirty two * 16K Flash EEPROM Pages

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$BFFF $C000 EXT $C000 16K Fixed Flash EEPROM

$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF

2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)

The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0800 - $3FFF: 14K RAM $0000 - $0FFF: 4K EEPROM (1k $0400 - $07FF visible, $0000 - $03FF and $0800 - $0FFF are not visible) Various possibilities to make more of the EEPROM fully visible are available, one of them is shown above

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Figure 4 MC9S12Dx256 User Configurable Memory Map

$0000 $0000 $0400 $1000 $03FF $0000 $0FFF $1000 1K Register Space Mappable to any 2K Boundary 4K Bytes EEPROM Initially overlapped by register space Mappable to any 4K Boundary 12K Bytes RAM Alignable to top ($1000 - $3FFF) or bottom ($0000 - $2FFF) $4000 $3FFF $4000 Mappable to any 16K Boundary 0.5K, 1K, 2K or 4K Protected Sector

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$7FFF $8000 $8000 EXT $BFFF $C000 $C000

16K Fixed Flash EEPROM

16K Page Window sixteen * 16K Flash EEPROM Pages

16K Fixed Flash EEPROM

$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF

2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)

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Figure 5 MC9S12Dx128 User Configurable Memory Map

$0000 $0000 $0400 $0800 $1000 $2000 $03FF $0800 $0FFF $2000 $3FFF $4000 $4000 0.5K, 1K, 2K or 4K Protected Sector 1K Register Space Mappable to any 2K Boundary 2K Bytes EEPROM Mappable to any 2K Boundary 8K Bytes RAM Mappable to any 8K Boundary

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$7FFF $8000 $8000 EXT $BFFF $C000 $C000

16K Fixed Flash EEPROM

16K Page Window eight * 16K Flash EEPROM Pages

16K Fixed Flash EEPROM

$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF

2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)

The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $1FFF: 8K RAM $0000 - $07FF: 1K EEPROM (not visible)

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Figure 6 MC9S12Dx64 User Configurable Memory Map

$0000 $0000 $0400 $0800 $1000 $3000 $3000 $3FFF $4000 Mappable to any 4K Boundary 4K Bytes RAM $03FF $0800 $0FFF 1K Register Space Mappable to any 2K Boundary 1K Bytes EEPROM repeated twice in the 2K space Mappable to any 2K Boundary

$4000

0.5K, 1K, 2K or 4K Protected Sector

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$8000

$7FFF $8000 EXT

16K Fixed Flash EEPROM 16K Page Window four * 16K Flash EEPROM Pages

$BFFF $C000 $C000 16K Fixed Flash EEPROM

$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF

2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)

The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0000 - $0FFF: 4K RAM $0000 - $07FF: 1K EEPROM (not visible)

10

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Figure 7 MC9S12Dx32 User Configurable Memory Map

$0000 $0000 $0400 $0800 $1000 $3800 $3800 $4000 $3FFF $03FF $0800 $0FFF

1K Register Space Mappable to any 2K Boundary 1K Bytes EEPROM Repeated twice in the 2K space Mappable to any 2K Boundary 2K Bytes RAM Mappable to any 2K Boundary

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$8000 $8000 EXT 16K Fixed Flash EEPROM $BFFF $C000 $C000 16K Fixed Flash EEPROM 0.5K, 1K, 2K or 4K Protected Sector two * 16K Flash EEPROM Pages

$FFFF $FF00 $FF00 $FFFF VECTORS NORMAL SINGLE CHIP VECTORS EXPANDED VECTORS SPECIAL SINGLE CHIP $FFFF

2K, 4K, 8K or 16K Protected Boot Sector BDM (If Active)

The figure shows a useful map, which is not the map out of reset. After reset the map is: $0000 - $03FF: Register Space $0800 - $0FFF: 2K RAM $0000 - $07FF: 1K EEPROM (not visible)

For More Information On This Product, PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02 Go to: www.freescale.com

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4X PIN 1 IDENT 1 112

0.20 T L-M N

4X 28 TIPS 85 84

0.20 T L-M N

J1 J1 C L

4X

VIEW Y
108X

X X=L, M OR N

VIEW Y B L M B1 V1 V

AA

28

57

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F D 0.13
M

BASE METAL

29

56

L-M N

N A1 S1 A S

SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE

C2 C 0.050

VIEW AB 0.10 T
112X

SEATING PLANE

NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 3 7 13 11 11 13

3
T
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3

R2 0.25
GAGE PLANE

R1

C1 (Y) (Z) VIEW AB

(K) E

Figure 8 112-pin LQFP Mechanical Dimensions (case no. 987)

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L
60 61 41 40

B B P

H A-B

V 0.05 D

C A-B

-A-

-B-

0.20

0.20

-A-,-B-,-DDETAIL A

DETAIL A

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80 1 20

21

-D0.20
M

A H A-B S

0.05 A-B J
S

0.20 E C -CSEATING PLANE

C A-B

M DETAIL C -HH G
DATUM PLANE

D 0.20
M

C A-B

SECTION B-B

VIEW ROTATED 90

0.10 M

U T
DATUM PLANE

-H-

K W X DETAIL C

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.

DIM A B C D E F G H J K L M N P Q R S T U V W X

MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC --0.25 0.13 0.23 0.65 0.95 12.35 REF 5 10 0.13 0.17 0.325 BSC 0 7 0.13 0.30 16.95 17.45 0.13 --0 --16.95 17.45 0.35 0.45 1.6 REF

Figure 9 80-pin QFP Mechanical Dimensions (case no. 841B)

For More Information On This Product, PRODUCT PROPOSAL, Rev 6.1, 23-Oct-02 Go to: www.freescale.com

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