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I2C(Inter-Integrated Circuit) generally referred as a “Two Wire Interface”. It is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, or cell phone or other electronics. Introduction I2C bus = Inter-IC Bus • Simple Bi-directional 2-wire bus- serial data(SDA) & serial clock(SCL) • Originally to interact within small num. of devs(radio/TV tuning....) • Speeds
-100 kbps (standard mode) -400 kbps (fast mode) -3.4 Mbps (high-speed mode)
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Has become a worldwide industry standard and used by all major IC manufacturers. Data transfer: serial, 8-bit oriented, bi-directional. Addressing: 7bit or 10bit address. Multi-master capable bus with arbitration feature. Master-Slave communication. Master can operate as transmitter or receiver Each IC on the bus is identified by its own address code. The slave can be a: –Receiver-only device –transmitter with the capability to both receive and send data.
Design I²C uses only two bidirectional open-drain lines, Serial Data Line (SDA) and Serial Clock (SCL), pulled up with resistors. Typical voltages used are +5 V or +3.3 V although systems with other voltages are permitted. The ‘bus’ wires are named SDA (serial data) and SCL (serial clock). These two bus wires have the same configuration. They are pulled-up to the logic ‘high’ level by resistors connected to a single positive supply, usually +3.3 V or +5 V but designers are now moving to +2.5 V and towards 1.8 V in the near future. All the connected devices have open-collector (open-drain for CMOS - both terms mean only the lower transistor is included) driver stages that can transmit data by pulling the bus low, and high impedance sense amplifiers that monitor the bus voltage to receive data. Unless devices are communicating by turning on the lower transistor to pull the bus low, both bus lines remain ‘high’. To initiate
The start and stop sequences mark the beginning and end of a transaction with the slave device.communication a chip pulls the SDA line low. and is called the bus ‘master’. The I2C Physical Protocol When the master wishes to talk to a it begins by issuing a start sequence on the I2C bus. When data is being transferred. The start sequence and stop sequence are special in that these are the only places where the SDA (data line) is allowed to change while the SCL (clock line) is high. SDA must remain stable and not change whilst SCL is high. It then has the responsibility to drive the SCL line with clock pulses. until it has finished. the other being the stop sequence. A start sequence is one of two special sequences defined for the I2C bus. 2 .
If it sends back a high then it is indicating it cannot accept any further data and the master should terminate the transfer by sending a stop sequence. then it has received the data and is ready to accept another byte.Data is transferred in sequences of 8 bits. For every 8 bits transferred. Masters and Slaves 3 . the device receiving the data sends back an acknowledge bit. The bits are placed on the SDA line starting with the MSB (Most Significant Bit). then low. If the receiving device sends back a low ACK bit. it simply "lets go" of it and the resistor actually pulls it high. The SCL line is then pulsed high. The I2C Software Protocol ➢ Send a start sequence ➢ Send the I2C address of the slave with the R/W bit low (even address) ➢ Send the internal register number you want to write to ➢ Send the data byte ➢ Send the stop sequence. Remember that the chip cannot really drive the line high. so there are actually 9 SCL clock pulses to transfer each 8 bit byte of data.
multiple slaves on the I2C bus.The devices on the I2C bus are either masters or slaves. Slaves will never initiate a transfer. The slaves are the devices that respond to the master. Reading from the Slave ➢ Send a start sequence ➢ Send 0xC0 ( I2C address of the CMPS03 with the R/W bit low (even address) ➢ Send 0x01 (Internal address of the bearing register) ➢ Send a start sequence again (repeated start) ➢ Send 0xC1 ( I2C address of the CMPS03 with the R/W bit high (odd address) ➢ Read data byte from CMPS03 ➢ Send the stop sequence. It is possible to have multiple masters. Devices communicate in master4 . only a master can do that. The bit sequence will look like this: SPI PROTOCOL The SPI (Serial Peripheral Interface Bus) bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. but it is unusual and not covered here. A slave cannot initiate a transfer over the I2C bus. however there is normally only one master. but that transfer is always controlled by the master. There can be. and usually are. The master is always the device that drives the SCL clock line. Both master and slave can transfer data over the I2C bus.
l The Master device controls the clock (SCK) l No data is transferred unless a clock signal is present l All slaves are controlled by the master clock l The slave devices may not manipulate the clock Communication between the two processors is handled via the serial peripheral interface (SPI). Sometimes SPI is called a "four-wire" serial bus. SOMI: Master Input. ➢ Clock speed is in MHz (1-70MHz). ➢ At most one "unique" bus signal per device (chip select). Slave Output (output from slave) ➢ SS: Slave Select (Active low output from master). ➢ Complete protocol flexibility for the bits transferred. SIMO: Master Output. and don't need precision oscillators. ➢ Full Duplex Communication. much less than parallel interfaces. ➢ SPI is a Master-Slave protocol. and a slave is any integrated circuit that receives the SPI clock from the master. 5 . ➢ Uses only four pins on IC packages. Multiple slave devices are allowed with individual slave select lines. ➢ Higher Throughput then I2C. but there can only be one master at any given time.slave mode where the master device initiates the data frame. ➢ Slaves use the master's clock. The SPI bus specifies four logic signals: ➢ SCLK: Serial Clock (output from master) ➢ MOSI. Every SPI system consists of one master and one or more slaves. Slave Input (output from master) ➢ MISO. Introduction ➢ SPI – Serial Peripheral Interface. It is possible to have a system where more than one IC can be master. all others are shared. where a master is defined as the microcomputer that provides the SPI clock. and wires in board layouts or connectors.
Timing Diagrams- 6 .
Master-Slave Communication- 7 .
USART. even in the "3-Wire" variant ➢ No in-band addressing. digital potentiometers. touchscreens.Applications➢ ➢ ➢ ➢ ➢ ➢ ➢ ➢ Sensors: temperature. sometimes even for managing image data Any MMC or SD card. CAN. ADC. video game controllers Control devices: Audio Codec. out-of-band chip select signals are required on shared buses ➢ No hardware flow control by the slave (but the master can delay the next clock edge to slow the transfer rate) ➢ No hardware slave acknowledgment (the master could be "talking" to nothing and not know it) ➢ Supports only one master device ➢ No error-checking protocol is defined 8 . USB.4. pressure. handheld video games Memory: Flash and EEPROM Real-time clocks LCD displays.IEEE 802.11. Disadvantages➢ SPI doesn’t have acknowledge mechanism to confirm receipt of data. ➢ Requires more pins on IC packages than I²C. DAC Camera lenses: Canon EF lens mount Communications: Ethernet.IEEE 802.15.
or CAN-bus ➢ Many existing variations.➢ Generally prone to noise spikes causing faulty communication ➢ Without a formal standard. RS-485. validating conformance is not possible ➢ Only handles short distances compared to RS-232. making it difficult to find development tools like host adapters that support those variations 9 .
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