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It was said previously that the synthesis process is the inverse of the analysis process. The general formulation of the synthesise procedure is: given a description or a specification of a digital system it is requested its implementation under certain constrains like: technology, cost, timing, power description a.s.o.. It was said that the synthesis has not a unique solution as there can be used several implementing techniques, both at the logical design phase and the technique phase. The adopted methods depends on the technological bases, which is available. Up to now, we have presented the classical implementation based on SSI modules, but the implementation methods are enhanced according to new technology like MSI, LSI. Each technology has its own specific methodologies of implementing digital networks. Always, after a synthesis is completed a careful timing verification is recommended. Sometimes the whole process is reconsidered due to some timing defects detected. The general methods of synthesise are: - standard or conventional, based on SSI technology. - methods based on utilisation of functional blocks modules - the MSI technology. This is subdivided as follows: - multiplexor implementation. - decoder implementation. - dedicated universal logic modules implementation. - methods based on LSI technology. This is subdivided in: - implementing with ROMs. - implementing with RAMs. - implementing with PLDs. (Programmable Logic Devices) like:PLA, GFLA, BLA. - methods based on VLSI technology. This class correspond toimplementation of digital networks with microprocessor. In this case the hardware function are replaced by software function and the complexity of CLN is reduced in the expense of the speed reduction.

2.5.1 The implementation of CLNs by the cascading method This method is based on taking advantage of a dedicated module pertaining to the universal logic modules (ULM). This method is based on realising successively the Shannon’s expansion theorem as follows: f (x1 ... x i ... x n ) = x i ⋅ f (x1 ...0... x n ) + x i ⋅ f (x1 ...1... x n ) = x i ⋅ f i 0 + x i ⋅ f i 1 , where f i 0 , f i 1 are sub-functions depending on n-1 variables. Further we expand each sub-function with respect to another variable: f i1 = x j ⋅ f ij10 + x j ⋅ f ij11

The main advantage of the procedure is that any switching function can be implemented having a regular structure being a balanced tree. because each subfunction is implemented by a dedicated universal module and both structure is a tree. It may be proved that by further analysis they may be found cases when the number of layers is reduced.In a similar way the new sub-functions are expended with respect to another variable. Reassembling the whole process it is constructed the function f. Each level introduces its own delay. Fig. since the order of applying Shannon’s . This is accomplished with computer assistant synthesis. This tree consist of n-1 layers. The disadvantage of this method is the input/output propagation time as the numbers of level is up to n-1. because the last sub-functions are faster becoming constants or variables. These common branches should be discovered also by computer added design methods. 2. This method is very useful in the particular case of implementing logic multiples.7 The order of using the variables for expansion procedure is not fixed. This method is named the cascade method. The inputs in the last layers are constants 0.1 or one variable. The advantage offered by this implementation is that common branches may be used in realising two or more function. So that the total delay is important. The process continues until the sub-functions became logical constants 0 or 1 or a variable. In each layer it is inserted a variable x j .

.8 Example: It is given a Boolean form depending on four variables and it is required it’s implementation with DUMs based on Shannon’s theorem. (The Cascading Method ).theorem is arbitrary. The basic sale is implementing the following function: f = x⋅f + x⋅f S S 0 S1 . Fig. 2. X * i X *i i X *i where X* is a subset of X and S represents binary vector corresponding to the assigning of variables of vector X*.

. xn ) = x1 ⋅ f 1 1 + x1 ⋅ f 01 1 f f f f f f f f f f f f f f f 1 1 0 1 1 = 1 ⋅ x2 x3 + 1 ⋅ x3 x4 + x2 x3 x4 + 0 ⋅ x2 x4 + x2 x3 x4 = x2 x3 + x2 x3 x4 + x3 x4 + x2 x3 x4 = 0 ⋅ x2 x3 + x2 x3 x4 + 0 ⋅ x3 x4 + x2 x3 x4 + 0 ⋅ x2 x4 = x2 x3 x4 + x1 x3 x4 + x2 x4 = x2 ⋅ 1 11 12 10 12 0 f 11 + x2 ⋅ 12 f 10 12 = 1 ⋅ x3 + 1 ⋅ x3 x 4 + x3 x 4 + 0 ⋅ x3 x4 = x3 + x3 x4 + x3 x4 = 0 ⋅ x3 + 0 ⋅ x3 x4 + x3 x4 + 1 ⋅ x3 x4 = x3 x4 + x3 x 4 = x2 ⋅ 1 01 12 00 12 11 f + x2 ⋅ 12 01 f 00 12 = 1 ⋅ x3 x4 + 0 ⋅ x 3 x4 + 0 ⋅ x4 = x3 x4 = 0 ⋅ x3 x4 + 1 ⋅ x3 x4 + 1 ⋅ x4 = x3 x4 + x4 = x3 ⋅ 12 111 123 110 123 10 f 111 + x3 ⋅ 123 f 110 123 = 0 + 1 ⋅ x4 + 0 ⋅ x4 = x4 = 1 + 0 ⋅ x4 + 1 ⋅ x4 = 1 = x3 ⋅ 12 101 123 100 123 01 f 101 + x3 ⋅ 123 f 100 123 = 0 ⋅ x4 + 0 ⋅ x4 = 0 = 1 ⋅ x4 + 1 ⋅ x4 = 1 = x3 ⋅ 12 f + x3 ⋅ 123 010 f 011 123 f f f f f 010 123 010 123 00 12 = 0 ⋅ x4 = 0 = 1⋅ x4 = x4 = x3 ⋅ f + x3 123 001 f 000 123 001 123 000 123 = 0 ⋅ x4 + x4 = x4 = 1⋅ x4 + x4 = 1 . xn ) = x1 x2 x3 + x2 x3 x4 + x1 x3 x4 + x1 x2 x4 + x2 x3 x4 f ( x1 ..f ( x1 ...

OR.9(2-5.5. NOT]. It is known that each electronic gate has its own FAN-IN. Taking into account the FAN-IN factor of all used gates.Fig. the associatively postulates and the pseudo associatively theorem. As it is known the . He must adjust his equations too conform to the values of the imposed FAN-Ins. Initially when dealing with logical equations we are neglected this major factor. The major impact of the FAN-IN adaptation on the implementations is the increasing of the number of the levels in the CLN. the designer learns that values of the FAN-IN are different from those expected. namely the FAN-IN of the gate but later when the technological basis is specified.2 Synthesise of CLNs With Input Constrains An essential problem linked to the CLN synthesis is the implementation of logical equations. 2. Usually this action is carried out with tools offered by the Boolean algebra. Definition: The synthesise of the CLN with input constrains correspond to the implementation process of the CLN.) 2. this represents the more general product which is extensively treated in the literature. the number of inputs which are available. We focus only on the case of the natural base [AND.

M is the maximum number of levels for implementing the product terms. We restrict the values of Ki and Km to the limit value: Km=r and Ki=r-1. Proof: Let us assume that there exists a product term with the lengths L.10 Since the variable in the first level are not available in a complemented form too. the minimal number of implementing levels is E=M+2 under the following restrictions: Kn<=r. are sum of products or product of sums which corresponds to a second level implementation. Theorem NICKS-BERNSTEIN This theorem referees to a method of CLNs implementation in the natural base AND-OR-NOT with the following construction. we have to had an additional level designated 0 for complemented input . The FAN-IN in AND gate is d and in OR gate is r.M]. Ki<=r-1 where I is the number of levels required for implementing a product term. Then the following structure is proposed for the implementation of the given normal disjunctive form: Fig. For every i<m and i>M it results that Ki=0. Km is the number of product terms requiring m levels for implementing. Obviously the FAN-IN constrains imposed a factoring process increasing implicitly the number of levels of implementation. Ki is the number of product terms requiring i levels for implementation. m is a minimal number of levels for implementing the product terms. To realise this term with a given AND gates with a FAN-IN d will need i=[log2L] levels.minimal form which are obtained after the minimisation algorithm are used are used. We admit that I belongs to [m. 2. Given a noble disjunctive form (a sum of products form) a set of AND gates with FAN-IN d and set of OR gates with FAN-IN r.

Both the AND or OR gates have the FAN-IN 2.variables.> K1=2 x 3 x 4 x 5 = (x 3 x 4 )x 5 − −− > K 2 = 1 x 3 x 4 x 5 x 6 x 7 = (x 3 )( x 4 x 5 )( x 6 x 7 ) − − > K 3 = 1 − − > M = 3 E = M +2=5 Fig. Then the total number of levels covers the interval 0…M+1 which gives a total E=M+2. By applying the previous theorem we must determine the total number of variables under the assumption that we have no access to complemented. 2. Then the whole structure of the CLN is repeated. Example: It is given a Boolean F depending on 7 variables which has to be complemented in the natural base [AND-OR-NOT]. F = x1 x 2 + x1 x 2 + x 3 x 4 x 5 + x 3 x 4 x 5 x 6 x 7 K1 d=2 and r=2 (x1 x 2 ) − − > 1 (x1 x 2 ) − − > 1 K1 K2 K3 --. Conclusion: This structure will contain M+2 levels under the hypothesis that a dedicated level is assigned for complementing variables.11 . We determine M=3 it results E=5.

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