COMPARISON BETWEEN TWO MODULATION TECHNIQUES FOR THREE PHASE INVERTERS FROM A HARDWARE IMPLEMENTATION POINT OF VIEW

BY BOGDAN ALECSA* and ALEXANDRU ONEA*

Abstract. This paper presents a comparison between two modern modulation techniques applied to three phase inverters from a hardware implementation point of view. The considered techniques are the sinusoidal pulse width modulation with zero sequence injection and the space vector modulation. Both these techniques conduct to the same result regarding supply voltage usage efficiency and harmonic content of the resulted signals. However, they are based on different approaches and, in consequence, need different algorithms for implementation. Both the modulation algorithms were implemented in hardware on FPGA, and the resulted designs are compared for resource usage efficiency, obtained speed and ease of integration within a complex AC drive control system. Key words: Sinusoidal PWM, ZSS, SVM, FPGA, System Generator 2000 Mathematics Subject Classification: 93C83

1. Introduction The modern FPGA (Field Programmable Gate Array) devices are not only configurable arrays of logic elements, as they were at their invention. They incorporate RAM (Random Access Memory) blocks, hardware multipliers (or even multiply-accumulate units), digital clock managers, making them target platforms for very complex digital systems [1]. The FPGAs usage in industrial control applications is an area of intensive research [2], mainly because they offer the possibility to execute control algorithms in hardware, making use of the parallelism of the algorithm in the implementation. In three phases AC drives control, a whole range of FPGA based systems have been developed. A common feature of these systems is that

they all use some kind of pulse width modulation (PWM) technique for producing the three phase voltages using a three phase inverter bridge (VSI Voltage Source Inverter). The simplest of these techniques is the sinusoidal PWM (SPWM), which consists of generating a pulse train of fixed frequency characterized by the fact that the duty cycle follows a sinusoidal function. An independent modulator is used for each phase. The disadvantages of this technique are the non-ideal usage of the supply voltage and the independent treatment of the three phases, which leads to superfluous changes in the switches states and, thus, to increased switching losses and harmonic content in the output signals. These disadvantages can be faded by a technique called zero sequence signal (ZSS) injection. It consists of adding a certain signal to all three reference signals, thus modifying their sinusoidal waveforms. The injected signal can be observed in the load neutral point (star point or zero point), hence the name ZSS. The ZSS is chosen so as to decrease the amplitude of the reference signal, thus improving the usage of the supply voltage: with the same supply voltage, a higher amplitude signal can be modulated. The ZSS injection exploits the fact that usually the star point of the load is unconnected and the three phase voltages dont need to be sinusoidal. Only the phase to phase voltage must be sinusoidal, so the ZSS must modify the phase voltages without changing the phase to phase voltages. One example of ZSS is the third harmonic of the sinusoidal reference signals. While this introduces the lowest level of harmonics in the resulted signals, it is not used in practice due to its high complexity in implementation [3]. The most widely used ZSS is the triangular signal containing all the third order harmonics of the sinusoidal signals. This is because it has been obtained independently through space vector modulation (SVM), a digital modulation technique developed as the microprocessor systems became industry standard. This paper proposes a comparison between the implementation requirements of these two modulation techniques when targeting FPGA devices: SPWM with triangular ZSS injection versus SVM. For this purpose, both modulation algorithms were designed in MATLAB Simulink, using System Generator, validated by simulation and then implemented into FPGA hardware. They were experimentally tested, proving they provide the same results. Then, the resources usage and execution time were compared, providing a valuable result regarding which algorithm to choose when implementing an FPGA based AC drive control system. 2. SPWM with triangular ZSS injection As already stated, SPWM is the simplest method of generating three phase sinusoidal voltages of variable frequency and amplitude using a three phase

inverter bridge. The bridge consists of six power transistors (MOSFETs Metal-Oxide-Semiconductor Field Effect Transistor or IGBTs Insulated Gate Bipolar Transistor), connected in series in pairs between the positive and negative supply points of the bridge. Each pair is called a bridge leg, and from between the transistors of the same leg a phase of the load is supplied. Obviously, the transistors of the same leg can not be in conduction simultaneously, or they would short-circuit the power supply. The transistors on the same leg can be considered as having opposite states. Thus, the inverter bridge state is fully determined by the states of the high side transistors. It can be described as 3 bi-positional switches. In practice, a short delay should be inserted between the blocking command of one transistor and the saturation command of the other, to cover the response delay (switching time of the power transistor) and prevent unwanted high transitional currents. Although this dead time can be inserted by hardware by the driving circuit of the power transistors, it is common practice for the modulator to take care of it. SPWM is accomplished by determining the intersections between a carrier signal, usually of triangular or saw-tooth waveform, and a modulator sinusoidal signal, of much lower frequency. The intersection points give the moments when the switches states change. With three phase inverter bridges, an independent sinusoidal modulator is used for each phase. This is one of the weaknesses of SPWM, because each phase is treated independently. This problem is solved by ZSS injection, as the ZSS is usually derived from the signals of all the three phases. This way, a measure of the interaction between the three phases is injected in the modulator signals. The ZSS injection also improves the supply voltage usage. For triangular ZSS injection, the ZSS is determined from the three phase sinusoidal voltages by a minimum magnitude rule [3]:

(1)

vZSS

va , if min( va , vb , vc ) = va ; = vb , if min( va , vb , vc ) = vb ; . v , if min( v , v , v ) = v . a b c c c

This can be also implemented with analog components, using diode rectifier circuits to collect the minimum magnitude signal from the three phase signals. When implementing Eq. (1) digitally, in order to make a decision on which signal has lower magnitude, first the absolute values of the signals must be found, and then they must be compared. Digital comparisons allow only two terms, so Eq. (1) must be rewritten as:

(2)

vZSS

va , if min(min( va , vb ), min( va , vc )) = va ; = vb , if min(min( va , vb ), min( va , vc )) = vb ; v , if min(min( v , v ), min( v , v )) = v . a b a c c c

The usual way to compare two numbers digitally is to subtract them and examine the sign bit of the result. The direct hardware implementation of Eq. (2) would then consist of three subtractions: first between va and vb and between va and vc , and then between the resulted two minimum values. This approach needs two computation steps, as the third subtraction can only be performed after the first two have completed. A better approach is to make all the subtractions between va , vb and vc , namely va vb , va vc and vb vc in parallel and decide the minimum by using all three sign bits. The advantage of this approach is that all three subtractions can be performed in parallel, and the minimum value can be determined in only one step. It must be noted that this advantage is specific to hardware (FPGA) implementations, because in a processor the operations would be done sequentially. The ZSS computation hardware, designed in Simulink using System Generator blocks, is presented in Fig. 1.

Fig.1 The ZSS computation circuit, designed using System Generator blocks.

In the computation path, registers with enable input were inserted. All the 1 registers (denoted by z ) are synchronous to the same global clock signal, which is not represented for readability. They have the role of preventing long combinational paths and so increasing the working frequency of the system. The registers are enabled by a finite state machine (FSM) which controls the data flow through the system. So the hardware was designed following the datapath-controller paradigm [4]. It can be seen in Fig. 1 that there are 4 sets of registers in the datapath. So the ZSS computation needs 4 clock cycles. The 4 computational steps correspond to the following operations: the input values are saved, the absolute values of the sinusoidal signals are computed and saved, the 3 differences are

computed and the multiplexer selection value is derived from the sign bits and saved, the selected sinusoidal signal is scaled by 0.5 and saved. The SPWM modulator consists of 3 modules: a controlled sinusoidal waveform generator module, a threshold computation module and a carrier generator and gating signals control module. The ZSS computation circuit is part of the threshold computation module. The modulator is presented in greater detail in [5]. Here, only a short description will be made, to enable the comparison with the space vector modulator. The ZSS computation circuit has been modified from the one presented in [5] to implement a more general equation. The sinusoidal waveform generator is based on a read only memory (ROM) look-up table (LUT) containing the sampled image of a sine period. This memory is accessed 3 times, to get the current samples of the three phases sinusoidal waveforms. The generator is driven also by a FSM, and it needs 10 clock cycles to prepare the data. The threshold computation module is the most computationally intensive part of the modulator. Its block diagram is presented in Fig. 2. It contains the ZSS computation circuit from Fig. 1. It performs the following operations: first, the ZSS is computed, then it is added to the three sinusoidal signals; the resulted modulator signals are then normalized by multiplication by 2 / Vdc . This operation brings them to the [-1;+1] interval. The signals are then reverted, biased to 1 and scaled by 0.5, getting to the [0;1] interval. A final multiply operation brings them to the same interval as the carrier signal, making the comparisons for intersection point detection possible. The last step in Fig. 2 shifts the threshold values to introduce a dead time the necessity of which has been discussed. The thresholds for the high side transistors are shifted upwards, while the thresholds for the low side transistors are shifted downwards. The usage of different shifting constants allows maximum flexibility when setting the dead time, enabling the compensation of asymmetries in transistors response.

Fig.2 The thresholds computation module.

The rectangles in Fig. 2 represent registers, while the dotted arrows represent enabling signals for the registers. All registers aligned vertically are enabled by the same signal, constituting a step in the computation. The module needs 9 clock cycles to complete the computation, including the 4 in the ZSS computation. The third module in the modulator has the role of generating the carrier signal. This is a triangular periodic signal and is obtained digitally by the classical approach of a bi-directional counter. The counter upper limit is given by the ratio between the system clock and the desired PWM frequency. For the experiments, a 50MHz system clock was used and a PWM frequency of 20kHz was set, so the counter limit was set to 1250. This value was also used for the last multiplication in the thresholds computation module. It must be noted that if a power of 2 counter limit is used, this multiplication is reduced to a shifting operation, costing nothing in hardware. However, the multiplication approach allows the highest flexibility. The carrier signal generation module is also responsible with activating the transistors gating signals. For this purpose, equality comparators are used to detect the match between the counter output value and the corresponding threshold value (the intersection between the carrier signal and the modulator signal). The comparator outputs are used together with counter direction signals to set or reset output flip-flops (FF) memorizing the transistor state. The outputs of the FFs are used for gating the transistors. The whole modulator needs 20 clock cycles to execute all operations, meaning only 400ns at a 50MHz clock rate. A discussion about used FPGA resources will be presented in the last section. 3. Space vector modulation

The SVM technique processes the complex voltage space vector as a whole and thus exploits the interaction between the three phases. This improves the supply voltage usage efficiency and minimizes the harmonic content of the output signals. The SVM is based on the complex space vector representation of electrical variables [6]: (3)
V = v + jv = V m e j ,

where v, v are the voltage components in the two phases stationary / plane. When using a three phase inverter bridge, the space vector must be derived by a combination of the bridge possible states. As already mentioned, the bridge is fully described by the states of three transistors, so it has 8 possible states. When representing the voltages obtained by each of the states in the / plane, 8 space vectors result. Two of them are null vectors, while the other 6 define a hexagon and split it into 6 sectors. By SVM, a given reference vector is reconstructed from the base vectors. In practice, only 3 base vectors must be combined to obtain the reference vector: the two base vectors defining the sector in which the vector is found and one null vector. Usually, both null vectors are used, for symmetric usage of high side and low side bridge transistors. The base vectors are combined by PWM. An example of vector reconstruction using PWM can be seen in Fig. 4, for the reference vector having the magnitude and orientation in Fig. 3. Two base vectors are used, and each is applied for a period proportional with the magnitude of the vector projection on it. The rest of the PWM period is allotted equally to the null vectors.

Fig.3 Example of reference vector decomposition into base vectors.

Fig.4 PWM reconstruction of the reference vector by using base vectors.

The SVM algorithm must do the following: determine the sector in which the reference vector is situated, and so the base vectors used; determine the duty cycles for the base vectors application; find the switching order; generate the PWM carrier and apply the modulation. These tasks have been reduced to simple plane geometry comparisons and segment computations, without the need of trigonometric functions. The relations leading to the algorithm implementation have been presented in [7], being derived from various forms found in the literature [8, 9, 10]. There are 3 sets of formulae for duty cycle computation, and they are applied in relation with the sector in which the vector is found. The novelty of the FPGA implementation consists in the fact that the operations leading to the sector decision also lead to the duty cycle computations and they are made in parallel. All the formulae are computed and when the sector is found, the right result is routed to the output using multiplexers. This shortens the computation significantly compared to a microprocessor or digital signal processor (DSP) implementation, where the computations are made sequentially. The block diagram of the algorithm is presented in Fig. 5, with the same notations as in Fig. 2. All computations are performed with 18 bit resolution. The algorithm execution is controlled also by a FSM, and it needs 8 clock cycles to complete.

Fig.5 The SVM algorithm implementation.

In order to test the algorithm, it was integrated together with a sinusoidal waveform generator, used as input, and a triangular waveform generator, used as PWM carrier. These two modules are similar to those used in the sinusoidal PWM modulator, so they were reused with only slight modifications. The modular design and components reuse is a basic principle in FPGA-based design. Experimental results are presented in the next section. It must be noted that the SVM algorithm uses the / representation of the three phase sinusoidal signals. So an a/b/c to / transform was included into the sinusoidal waveform generator, whose operation needs thus 12 clock cycles. The three phases to two phases transform is given by:

(4)

1 v [ k ] = (2v a [k ] vb [ k ] v c [ k ]); 3 3 v [k ] = (vb [k ] v c [ k ]). 3

4. FPGA based experimental results

Both the presented algorithms were implemented into a Spartan-3E XC3S500E device. Then they were tested using a Technosoft PM50 three phase inverter bridge. The bridge outputs were filtered by passive RC low pass filters. The three phases were star connected by resistors, and the star point signal, also low pass filtered, was observed. As expected, both modulation techniques have the same results: the three phases signals are modified, with around 15% decreased amplitude; the phase to phase signal remains sinusoidal; and the neutral point signal has a triangular waveform with a frequency three times higher than the phase signal. Fig. 6 presents an oscilloscope capture of the output signals, showing the enumerated characteristics.

Fig.6 Oscilloscope capture of SVM filtered output signals. Table 1 FPGA resources used by each algorithm Used resources Algorithm SPWM-ZSS SVM 4 input LUTs 833 (8%) 957 (10%) D type FFs 548 (5%) 585 (6%) Logic slices 560 (12%) 605 (12%) Hardware 8 (40%) 9 (45%) multipliers RAM blocks 4 (20%) 4 (20%) Maximum 90 MHz 124 MHz frequency

Table 1 presents the FPGA resources occupied by each design. It can be seen that the SPWM with ZSS system is consuming slightly less resources. So it may seem the most appropriate for usage in an FPGA based AC motor control system, as it is done in [11]. However, at a closer look, the SVM is in fact more advantageous, for the following reasons: It takes less steps to perform the computation; It starts from the / representation of the voltages, which is usually available in a digital controller, as it is modelled in / or d/q frames. So the SVM would in fact need 2 less multipliers than in Table I, while the SPWMZSS algorithm would need 2 more for the transform. It would also need at least one more clock cycle for the / to a/b/c transform. It works at a slightly higher frequency. The SPWM-ZSS algorithm frequency could be improved by inserting more registers, but this would increase the number of steps needed for computation. 5. Conclusion

A comparative analysis of two of the most well known and used modulation algorithms for three phase inverters control was presented. Both the sinusoidal PWM with zero sequence injection and the space vector modulation algorithm have the same results in power supply usage and harmonic content of the output signals. However, they come with different approaches and are very different. The implementation of these algorithms in hardware on FPGA, shortly presented here, is very fast, taking advantage of parallel computations and fast embedded multipliers, capable to perform an 18x18 bit multiplication in less than 5ns [12]. The paper offers a comparison between the algorithms in terms of used resources and speed. It thus proves the SVM algorithm to be the better choice in implementing FPGA based AC drives controllers. For the future, a similar design approach, based on Simulink and System Generator, will be used for the entire AC drive control system implementation in FPGA.
Submitted: Accepted: *Gheorghe Asachi Technical University of Iasi Automatic Control and Applied Informatics Department Iasi, Romania e-mail: balecsa@ac.tuiasi.ro, aonea@ac.tuiasi.ro REFERENCES 1. R o d r i g u e z A n d i n a J. J., M o u r e M. J., V a l d e s M. D., Features, Design Tools, and Application Domains of FPGAs, IEEE Transactions on Industrial Electronics, vol. 54, no. 4, August 2007. 2. M o n m a s s o n E., C i r s t e a M. N., FPGA Design Methodology for Industrial Control Systems - a Review, IEEE Transactions on Industrial Electronics, vol. 54, no. 4, August 2007. 3. H a v a A., K e r k m a n R., L i p o T., Simple Analytical and Graphical Methods for Carrierbased PWM-VSI Drives, IEEE Transactions on Power Electronics, vol. 14, no. 1, January 1999. 4. C h u P. P., FPGA Prototyping by Verilog Examples, John Wiley and Sons, 2008. 5. A l e c s a B., I o a n A., FPGA Implementation of a Sinusoidal PWM Generator with Zero Sequence Insertion, Proceedings of The 7th International Symposium on Advanced Topics in Electrical Engineering, May 2011. 6. B o s e B. K., Modern Power Electronics and AC Drives, Upper Saddle River: Prentice Hall, 2002. 7. A l e c s a B., O n e a A., C i r s t e a M., An Efficient FPGA Implementation of the Space Vector Modulation Algorithm, Proceedings of International Symposium on Signals, Circuits and Systems, ISSCS2011, June-July 2011. 8. T e r o e r d e G., Electrical Drives and Control Techniques, Leuven: Academische Cooperative Vennootschap, 2004. 9. Q u a n g N. P., D i t t r i c h J.-A. (Editors), Vector Control of Three-Phase AC Machines, Springer, 2008.

10. F i l h o N. P., P i n t o J. O. P., S i l v a L.E B., B o s e B. K., A Simple and Ultra-fast DSPbased Space Vector PWM Algorithm and its Implementation on a Two-level Inverter Covering Undermodulation and Overmodulation, Proc. 30th Annual Conf. of IEEE IES, IECON 2004. 11. I d k h a j i n e L., M o n m a s s o n E., M a a l o u f A., Extended Kalman Filter for AC Drive Sensorless Speed Controller - FPGA-based Solution or DSP-based Solution, Proceedings of the 2010 International Symposium on Industrial Electronics, ISIE 2010, July 2010. 12. *** Spartan-3E FPGA Family: Complete Data Sheet, Xilinx Inc., 2008.

COMPARAIE NTRE DOU TEHNICI DE MODULAIE PENTRU INVERTOARE TRIFAZICE DIN PUNCTUL DE VEDERE AL IMPLEMENTRII N HARDWARE (Rezumat) n aceast lucrare este realizat o comparaie din punctul de vedere al implementrii n hardware pe FPGA a dou modulatoare pentru controlul invertoarelor trifazice. Este vorba despre un modulator PWM sinusoidal cu injecie de semnal la punctul neutru i despre un modulator bazat pe vectori spaiali. Ambele modulatoare au fost prezentate detaliat n lucrri anterioare i n consecin sunt descrise aici doar succint, pentru a permite compararea arhitecturilor lor. Modulatorul sinusoidal PWM a fost mbuntit fa de versiunea prezentat anterior prin implementarea ecuaiei mai generale de determinare a semnalului injectat la punctul neutru. Modulatoarele au fost proiectate modular, fiind alctuite din 3 module. Modulele generator de semnal de intrare i cel generator de semnal purttor sunt folosite, cu schimbri minime, de ambele modulatoare. Modulele de calculare a valorilor de prag, ce conin de fapt algoritmii de modulaie, reprezint diferena ntre cele dou modulatoare. Implementarea lor s-a fcut dup paradigma controler cu cale de date, n mediul Simulink, folosind software-ul System Generator (o unealt de proiectare special pentru FPGA). Implementrile beneficiaz din plin de paralelismul posibil n FPGA: modulatorul sinusoidal PWM prelucreaz simultan semnalele pentru cele 3 faze, iar modulatorul bazat pe vectori spaiali realizeaz n paralel calculul mai multor formule pentru factorii de umplere i procesul de selecie a formulelor valide. Ambele modulatoare au fost realizate practic i testate experimental. Comparnd resursele ocupate n FPGA de cele 2 modulatoare, se constat c modulatorul sinusoidal PWM utilizeaz ceva mai puine resurse logice. El are totui cteva dezavantaje: folosete mai multe multiplicatoare integrate (resurse critice n FPGA); lucreaz cu reprezentarea trifazat a semnalelor (modulatorul bazat pe vectori spaiali utilizeaz reprezentarea n sistemul de coordonate /), mai ndeprtat de reprezentarea intern a mrimilor ntr-un sistem de control pentru un motor de curent alternativ (aplicaia final a modulatoarelor); are nevoie de mai muli pai de calcul i lucreaz la o frecven ceva mai mic. Se poate concluziona deci c modulatorul bazat pe vectori spaiali este mai potrivit din punct de vedere practic pentru integrarea n aplicaii de control, n ciuda concepiei foarte rspndite c modulaia sinusoidal este cea mai simpl metod de modulaie. Singurul avantaj major al modulatorului sinusoidal este adaptabilitatea sa mai uoar: dac se dorete injectarea unui alt semnal la punctul neutru, acest lucru se obine relativ uor, reproiectnd doar o mic parte din circuit. n cazul modulatorului bazat pe vectori spaiali, o astfel de modificare implic reproiectarea total a cii de date, deoarece se modific formulele de calcul.