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ASU ID: 1203112308 Email ID: vrayapr1@asu.

edu

Systematic and Random Mismatches in Analog Integrated Circuits


Vamsi Pavan Rayaprolu ASU ID: 1203112308, MSE in EE, Ira A. Fulton Schools of Engineering, ASU, Tempe.
Abstract Systematic and random mismatches in analog integrated are one of the most complex challenged faced by a modern design engineer. These are primary causes for redesigns and limitations in circuit design. Therefore it is extremely important to measure, analyze, interpret, model and document parametric mismatch mechanisms. This paper briefly defines systematic and random mismatches, their impact on design and yield and the remedies involved in minimizing them. Index Terms Analog integrated circuits, Circuit modeling, Matching, Mismatch, Random parametric mismatch, Simulation, Systematic mismatch.

I. INTRODUCTION Analog integrated systems require perfectly symmetrical and ideally similar characteristic components for reliable and optimal performance. The introduction deals with the definitions and classifications of symmetrical and random mismatches. Section II is an overview of the impact of these effects on yield and design of Analog ICs and section III illustrates remedies to these problems in sections of design methods, calibration and layout methods. A. Mismatches A mismatch is defined as the variation of parameters which were meant to be equally designed. This is a serious constraint and a source of problems in performance and functionality of analog circuits. Mismatches are classified into two categories according to their generation mechanisms: fabricated-related mismatch and ambient-related mismatch[1]. In this paper we will mainly discuss the fabricated related mismatches, namely: systematic mismatch and Random mismatch. B. Measurement of mismatches The most common method used to gather mismatch data is obtained by juxtaposing two devices of similar geometry or layout configuration on a test chip. Both the devices are
Manuscript received September 1, 2010. This work was supported by the Course of EEE591, Ira A. Fulton Schools of Engineering. Vamsi Pavan Rayaprolu is with the Arizona State University, Tempe, AZ 82581 USA (corresponding author to provide phone: 303-555-5555; e-mail: vrayapr1@asu.edu).

subject to electrical probing and the results are recorded either in absolute or relative terms. This procedure is repeated for many dice across lots and wafers. The general median is used as the expected values of the results and the dispersion is estimated by the standard deviation (denoted by ). In probability theory and statistics, the standard deviation of a statistical population, a data set, or a probability distribution is the square root of its variance. Where variance is the difference of the value of the part to the mean value defined previously. On each iteration, data points beyond the +/-3 limits are removed and the distribution is recalculated [2]. A plot of standard deviation is made from which the devices in the one sigma range are kept into consideration.

Fig. 1. A typical example of device mismatches dependence on geometry. Here, the standard deviation in mismatch for the zero-bias resistance of a diffused p-type resistor is plotted against the resistor length and width.

One standard deviation (sometimes expressed as "one sigma") away from the mean in either direction on the horizontal axis accounts for somewhere around 68 percent of the data points. C. Systematic and random mismatches Random mismatch is mainly due to microscopic device architecture fluctuations, such as random dopant fluctuations, lithographic edge roughness, or grain boundary effects[3].

ASU ID: 1203112308 Email ID: vrayapr1@asu.edu The underlying physical disturbance mechanisms are ignored if they are small as compared to the device dimensions. Then the mismatch fluctuation standard deviation P maps inversely proportional to the square root of the device area: P = AP / WxL (1) in which W and L are the effective dimensions of the active part of the device. AP (the A-factor)[4] is the proportionality constant related to the nature and effectiveness of the microscopic device architecture fluctuation cause and hence fundamentally related to the IC-process flow (recipe). Systematic mismatches are generally arise when there are imperfections in circuit design and/or layout. Hence it is highly recommended that in design of analog components, a large amount of attention is to be given to the consistency and symmetry of the layout of matched circuit elements. Apart from the basic design errors, such as asymmetrical biasing and uncontrolled voltage drops in source and ground lines, a whole range of process technology errors known as layout environment effects, can give rise to systematic mismatches. Such effects are usually related to, often incompletely modeled or characterized, litho and etch (loading) effects, topography differences, well-proximity effects[5], and local stress asymmetries. It was reported that mechanical stress and litho effects can affect the electrical performance of devices over distances of up to tens of microns.

2 Device composability is greatly reduced, which implies that it will be difficult to compose a complex circuit function out of individual simple functions. Wherein each component or logic gate will have to individually defined. Hence there is an increasing need to model keeping in mind the manufacturing and not just by simple emphasis on design. B. Impact on yield It has been reported that in analog signal processing systems the precision of signal processing is dependent on the magnitude of the random mismatch of a certain device type, hence the yield will be directly dependent on the ability to characterize and control device matching performance. As the magnitude of random mismatch is inversely proportional to the area of the component, high precision in analog design is achieved by balancing between device area, power consumption and speed.

II. IMPACT OF MISMATCHES IN ANALOG DESIGN A. Difficulties faced by designers Until relatively recently (say in the 1990s) the definition of the layout features which determine the performance of a fabricated MOSFET were relatively simple. The intersection between the diffusion and polysilicon mask shapes determined the dimensions of the MOSFET, and those dimensions sufficed to characterize the behavior of the transistor. In spite of miraculous advances in manufacturing technology and CAD, it remains a fact that there is an ever growing gap between device layout as viewed by a designer, and final manufactured shapes as rendered in Silicon. At the 65nm node and below, the radius of influence that defines the neighborhood of shapes that play a part in determining the characteristics of a MOSFET is expected to increase from the current "nearest feature" to include oneremoved features, auxiliary features, corners, vias, and other second order phenomena. This increase in the radius of influence will impact a number of areas[7]: It will make modeling of a device difficult as there can be no precise reference component design which can be used in computations and simulations. Due to the increased amount of constraints and variables the circuit extraction phase will be highly complex.

Fig. 2.

Random mismatch of different size in 0.7 technology

Systematic mismatches are brought about by imprecise design faults, such flaws can bring about heavy nonlinearities in high precision analog systems[6]. These are generally corrected by redesigns, i.e. by adding missing parasitics to the signal, source and ground lines, fixing the layout asymmetry. Sometimes even the dimensions of critical components are varied minutely to remove and symmetrical mismatches. The effects of this mismatch are so high that sometimes up to tens of microns of around the most critical devices in the systems can be of high influence, in such cases entire system topologies have to be changed.

III. REMEDIES FOR MISMATCHES Almost all systematic mismatches arise at the design-end and can be avoided to a great extent with proper layout. Different patterns are available, that can reduce linear to n-th order polynomial systematic mismatches. It is almost

ASU ID: 1203112308 Email ID: vrayapr1@asu.edu impossible to completely eliminate random mismatches, although it is possible to minimize its effects with better process control and larger transistor areas. As the transistor area reduces new effects come in play and complex equations are used to calculate the standard deviation representing random mismatch. A. Layout methods Systematic mismatches are avoided by making two devices as similar as possible with their side in parallel. There are three layout methods: (1) central symmetry pattern (Fig. 3 ab) (2) circular symmetry pattern (Fig. 3 c) (3) hexagonal tessellation (Fig. 3 d). parameters.

C. Calibration and external compensation On chip compensation techniques are becoming popular to reduce the random mismatch effects on the system. These techniques have been mostly incorporated in ADC convertors, filters and differentiators. In the case of systematic mismatch, designers are involving in the introduction of the small of parasitics, whose magnitude and location are determined by calibration and mismatch simulation.

IV. CONCLUSION Symmetrical mismatches can almost be eliminated in most cases, whereas random mismatches prevail after a large amount of detailed design and compensation. Although there are general techniques to minimize mismatches, there exist individual methods to reduce mismatch effects in different systems. As transistor size reduces the equations relating to random mismatch standard deviation will become further more complex with the introduction of more device parameters and variables. Large of amount of research being conducted by small and large semiconductor companies to pave a way for a future of sub 20nm technologies.
Fig. 3. Pattern to reduce systematic mismatch. 1 and 2 denote the smaller devices that constitute transistors 1 and 2.

ACKNOWLEDGMENT The author is indebted to the course of EEE591: Analog IC design and Dr. Ahmed Helmy for his guidance and support. REFERENCES
[1] Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He1 Satoshi Goto and Jiayi Liu, Symmetry constraint based on mismatch analysis for analog layout in SOI technology, IEEE, Analog/RF/mixed signal CADs, pp. 772-775, 2008. [2] Patrick G. Drennan , Integrated Circuit Device Mismatch Modeling and Characterization for Analog Circuit Design(Dissertation), Arizona State University, May 1999. [3] Peter A. Stolk, Frans P. Widdershoven and D.B.M. Klaassen, "Modeling Statistical Dopant Fluctuations in MOS Transistors", IEEE Transactions on Electron Devices Vol. 45, No, 9, pp. 1960-1971, 1998. [4] Marcel. J. M. Pelgrom, Aad C.J. Duinmaijer and Anton P.G. Welbers, "Matching Properties of MOS Transistors", IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, pp. 1433-1439, 1989. [5] Richard W. Gregor, "On the Relationship Between Topography and Transistor Matching in Analog CMOS Technology", IEEE Transactions on Electron Devices Vol. 39, No. 2, pp. 275-282, 1992.. [6] Tuinhout, H.; Wils, N., Parametric mismatch characterization for mixedsignal technologies IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp. 107-114, Oct 2009. [7] S. R. Nassif, B Model to hardware matching for nano-meter scale technologies, in Proc.IEEE Int. Symp. Low-Power Electron. Design,2006, pp. 203206. [8] C. He, X. Dai, H. Xing, and D. Chen. "New layout strategies with improved matching performance" , Analog Integrated Circuits and Signal Processing,49:281289, 2006. [9] M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G.Welbers, "Matching properties of MOS transistors",IEEE Journal of Solid-State Circuits, 24:14331989, 1989. [10] J. Bastos, M. Steyaert, A. Pergoot, andW. Sansen, "Mismatch characterization of submicron MOS transistors", Analog Integrated Circuits and Signal Processing, 12:95106, 1997.

The n-th order central symmetry and n-th order circular symmetry can cancel mismatch from linear to the n-th order polynomial between two devices by using 2n unit cells for each one[8]. The hexagonal tessellation has a higher areaefficiency because it removes quadratic gradient with only 3 units per device. B. Design methods Random mismatches are minimized by the designer by using complex equations and optimizing the mismatch parameters to obtain the least possible random mismatch. The most commonly used transistor mismatch parameters are threshold voltage (Vt) and current factor (). One of the most commonly used basic equations for sub micron devices is given by:

In equations (2)[9] and (3)[10], AVt/ and SVt/ are technology-dependent parameters, W and L are channel dimensions, and D is the distance between two transistors. It is to be noted that some designers introduce other mismatch